CN101290607B - Chip debugging interface device - Google Patents

Abstract

The invention relates to a chip debugging interface device. The device comprises a USB port for connecting information processing equipment, an I<2>C port for connecting a chip and a main processing unit for respectively supporting the data transmission of the USB port and the I<2>C port; the I<2>C port and the USB port are controlled with each other by the main processing unit; the main processing unit comprises a first universal control interface and a second universal control interface; the I<2>C port comprises a data transmission port and a clock control port; the first universal control interface is connected with the data transmission port for transmitting and receiving data; the second universal control interface is connected with the clock control port for transmitting and receiving clock information; the USB port comprises a differential signal interface; the main processing unit also comprises a differential signal output interface; and the differential signal interface is connected with the differential signal output interface for transmitting and receiving a differential signal.

Description

A kind of chip debugging interface device

Technical field

The present invention relates to interface debugging device that chip is programmed and/or debugged.

Background technology

At present chip is programmed and/or debugging technique mostly adopts a kind of background debug mode interface is provided in computing machine, utilize the commissioning device of the described background debug mode interface of coupling to connect CPU and chip, and chip is programmed or performance test accordingly.General this commissioning device be divided into special-purpose debugging head and simple and easy debugging first two.Special-purpose debugging head reception and sending function can only carry out serial and carry out communication, and can not realize simultaneously receiving and sending function, and cost an arm and a leg.Easy debugging head is similar to a cable, and one section is carried out communication by parallel interface cable and computing machine, and the other end is connected with chip.Simple and easy debugging head like this uses simple, but its processing speed is very slow, for example to the programming of chip, and very slow of speed, approximately the file of 512k size approximately needs at least 5 minutes time.

All the time, the technician has taked diversified technology to solve above problem, for example Chinese patent CN200510078460.7 discloses a kind of fast programming/commissioning device, programming/the debugging interface that comprises the parallel port that is connected with computing machine and be used for being connected with chip, it adopts the transmission first in first out module that is connected with described parallel port and receives the first in first out module, and the displacement transmitter that is connected with programming/debugging interface, receiver and be used to produce the tranmitting data register occurrence logic of receiving and dispatching synchronizing signal and be used for the clock signal input port that external clock reference is connected is shifted.Advantage such as that though this patented technology has is simple to operate, programming/debugging speed is fast.But now increasing ordinary PC and notebook computer have all removed the design of parallel port, make that utilizing common PC and notebook computer to carry out the chip debugging immediately becomes very inconvenient.And need to use the computing machine of proprietary parallel interface to carry out debugging work.

Summary of the invention

An object of the present invention is to provide a kind of chip debugging interface device easily.

For addressing the above problem, the present invention by the following technical solutions:

A kind of chip debugging interface device comprises: USB port is used for the link information treatment facility; I²The C port is used for connecting chip; Primary processing unit is used for supporting respectively USB port and I²The data transmission of C port, described I²C port, USB port are controlled mutually by primary processing unit; Describedly be controlled to be mutually: described I²The C port can be controlled USB port by primary processing unit, and described USB port can be controlled I by primary processing unit²The C port; Described primary processing unit comprises the first general controls interface, the second general controls interface; Described I²The C port comprises data transmission mouth, and clock control mouth, the described first general controls interface linking number reportedly send mouth to carry out data and transmit reception, and described second general controls interface connection clock control mouth carries out the clock information transmission and receives; Described USB port comprises the differential signal interface, and described primary processing unit also comprises the differential signal output interface, and described differential signal interface connects the differential signal output interface, is used for carrying out differential signal and transmits reception.

Above-mentioned first general controls interface and data transmit and also connect first protective device that adopts metal-oxide-semiconductor between the mouth, are used for carrying out the data isolation protection; Also connect second protective device that adopts metal-oxide-semiconductor between the second general controls interface and the clock control mouth, be used for carrying out the data isolation protection.

Described metal-oxide-semiconductor one end is connected to power supply, and the other end is connected with ground by an electric capacity.

The said chip debugging interface device also comprises: the 3rd power interface, ground connection interface and power supply, and described the 3rd power interface is connected with power supply, ground connection interface ground connection; Described the 3rd power interface is independently-powered, described the 3rd power interface comprises first power supply interface and second power supply interface, first power supply interface directly connects power supply, connect by a parallel circuit between second power supply interface and the ground connection interface, described parallel circuit is 1 decoupling capacitor and 1 filter capacitor parallel connection.

Above-mentioned I²The data of C port transmit mouth, clock control mouth and are connected with power supply by a pull-up resistor respectively.

Connect a USB coupling and protective resistance between above-mentioned differential signal interface and the differential signal output interface, be used for carrying out coupling and the protection of USB.

Above-mentioned USB port also comprises first power interface, and the parallel circuit that composes in parallel by 1 decoupling capacitor and 1 filter capacitor is connected with power supply.

Connect a USB coupling and protective resistance between above-mentioned differential signal interface and the differential signal output interface, be used for carrying out coupling and the protection of USB.

Above-mentioned power supply is+3.3V or+5V.

The present invention mainly is a kind of chip debugging interface device, and main mentality of designing is that chip debugging interface device comprises: USB port is used for the link information treatment facility; I²The C port is used for connecting chip; Primary processing unit is used for supporting respectively USB port and I²The data transmission of C port, described I²C port, USB port are controlled mutually by primary processing unit.Type and chip interface according to chip to be measured can connect chip easily like this.Type and interface according to messaging device comes the link information treatment facility again.And the I of chip debugging interface device of the present invention²C port and USB port be control signal output input mutually.The debugging work of the programmable chip that such design greatly facilitates.The present invention is described in detail below in conjunction with accompanying drawing, and these and other purpose of the present invention, feature, aspect and advantage will become more obvious.

Description of drawings

Fig. 1 is the structural representation of chip debugging interface device embodiment of the present invention;

Fig. 2 is the physical circuit block diagram of chip debugging interface device embodiment of the present invention.

Embodiment

In order to make those skilled in the art person understand the present invention program better, and above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the present invention is further detailed explanation below in conjunction with embodiment and embodiment accompanying drawing.

Chip debugging interface device of the present invention comprises: first port is used for the link information treatment facility.Described messaging device can be a computing machine, the televisor of breath treatment facility of taking a message, POD or other messaging devices.With the computing machine is example, and first port carries out respective design according to the characteristics of computing machine connectivity port.As the computing machine connectivity port is USB port, and the described first port respective design is a USB interface, is connected with the computing machine of USB port, guarantees interface debugging device of the present invention and computing machine normal communication.In like manner, be example with the televisor of the breath treatment facility of taking a message, the information processing interface of televisor is the HDMI terminal, the first port respective design of described interface debugging device of the present invention is the HDMI Interface Terminal, is connected with televisor.

Second port is used for connecting chip.Present chip mostly adopts I²C interface is so the second port respective design is I²C interface is connected with chip.

Primary processing unit is used for supporting respectively the data transmission of first port and second port, and described first port, second port are controlled mutually by primary processing unit.

Fig. 1 is the physical circuit figure of chip debugging interface device embodiment of the present invention, and chip debugging interface device of the present invention specifically comprises:primary processing unit 1 is specially chip.First port 2, physical circuit is designed to chip,second port 3, physical circuit is designed to chip.

First port 2 specifically is a usb socket, is connected with USB interface of computer by the USB line.Comprise:first power interface 10, differential interface 29.First power interface 10 is connected withpower supply 7 by a parallel circuit, and described parallel circuit is composed in parallel by adecoupling capacitor 13 andfilter capacitor 14 respectively.The power supply that describeddecoupling capacitor 13 andfilter capacitor 14 can make first power interface receive is cleaner.Describedpower supply 7 is+3.3V or+5V.

Differential interface 29 receives and transmits differential signal.And the connection differentialsignal output interface 28 ofconnection chip 1, be used for carrying out the transmission and the reception of differential signal.Also connected aprotective device 30 between differential interface 29 and the differential signal output interface 28.Protective device mainly is USB coupling and protective resistance.The input of described differential interface 29 is inputs of two signals, and the difference of these two signals is effective input signal, and the output of these two signals is the amplifications to the difference of these two input signals.There is undesired signal in the ifs circuit, can produces identical interference these two input signals, by the input and output of differential signal, the two poor, effective input of undesired signal just is zero.Thereby reach the purpose of anti-common mode interference.So differential interface 29 comprises minus tolerance and divides interface 11, positive differential interface 12.The connection differential signal output interface ofchip 1 comprises that minus tolerance divides output interface 15 and positive differential output interface 16.The minus tolerance that minus tolerance divides interface 11, positive differential interface 12 to connectchip 1 respectively divides output interface 15, positive differential output interface 16 to connect; for the signal of further protecting minus tolerance to divide interface 11, positive differential interface 12 to receive; minus tolerance divides a connected protective device such as resistance 17 of interface 11 to divide output interface 15 to be connected with minus tolerance, and a connected protective device such as resistance 18 of positive differential interface 12 is connected with positive differential output interface 16.Protective device (resistance 17 and resistance 18) is respectively USB coupling and the protective resistance that minus tolerance is divided interface 11 and positive differential interface 12.

Second port 3 specifically is I²The C socket is connected with waiting the chip of debugging and/or detecting by the interface line.The interface ofchip 3 comprises:second source interface 4, data transmitmouth 5, clock control mouth 6.Second source interface 4, data transmitmouthfuls 5,clock control mouth 6 and joiningpower 7, describedpower supply 7 is+3.3V or+5V.In this parallel circuit, wherein data transmitmouthfuls 5 pull-up resistors 8 of also connecting,clock control mouth 6 pull-up resistor 9 of also connecting.Pull-up circuit 8 and pull-upresistor 9 respectively protected data transmitmouthfuls 5 andclock control mouth 6 be not subjected to electric current too high and be damaged, and because I²The C socket all is open collector output, so need upper resistance to connect.Data transmitmouthfuls 5 and are connected with second general-purpose interface 21 with first general-purpose interface 20 ofchip 1 respectively withclock control mouth 6.

Primary processing unit 1 comprises: the 3rd power interface 19, the first general controls interface 20, the second general controls interface 21.The 3rd power interface 19 connectspower supplys 7, and described the 3rd power interface can be concentrated and obtain power supply, and it is independently-powered also can be divided into several sections separately.When the 3rd power interface 19 is divided into several sections separately when independently-powered, comprising: first power supply interface part isconnection power supply 7 directly.1decoupling capacitor 26 in parallel and 1 filter capacitor 27 between the ground connection interface 24 of the ground connection of second power supply interface part and chip 1.Describedpower supply 7 is+3.3V or+5V.The first general controls interface 20 is connected by thedata transmission mouth 5 of one firstprotective device 22 of series connection and chip 3.The secondgeneral controls interface 21 also is connected by theclock control mouth 6 of one secondprotective device 23 of series connection and chip 3.Described first protective device and second protective device play the effect of data isolation protection, prevent that exterior static from plugging the pulse of moment in addition chip is caused damage.Described first protective device and second protective device specifically all can adopt metal-oxide-semiconductor.Described metal-oxide-semiconductor 22, metal-oxide-semiconductor 23 are connected topower supply 7 simultaneously.Connect by adecoupling capacitor 25 between metal-oxide-semiconductor 22, metal-oxide-semiconductor 23 and the ground connection interface 24.

The above; be the specific embodiment of the present invention only, protection scope of the present invention is not limited thereto, and anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Protection scope of the present invention should be as the criterion with the protection domain that claim was defined.

Claims (9)

1. chip debugging interface device comprises:

USB port is used for the link information treatment facility;

I²The C port is used for connecting chip;

Primary processing unit is used for supporting respectively USB port and I²The data transmission of C port, described I²C port, USB port are controlled mutually by primary processing unit, describedly are controlled to be mutually: described I²The C port can be controlled USB port by primary processing unit, and described USB port can be controlled I by primary processing unit²The C port;

Described primary processing unit comprises the first general controls interface, the second general controls interface; Described I²The C port comprises data transmission mouth, and clock control mouth, the described first general controls interface linking number reportedly send mouth to carry out data and transmit reception, and described second general controls interface connection clock control mouth carries out the clock information transmission and receives;

Described USB port comprises the differential signal interface, and described primary processing unit also comprises the differential signal output interface, and described differential signal interface connects the differential signal output interface, is used for carrying out differential signal and transmits reception.

2. chip debugging interface device according to claim 1 is characterized in that: described first general controls interface and data transmit and also connect first protective device that adopts metal-oxide-semiconductor between the mouth, are used for carrying out the data isolation protection; Also connect second protective device that adopts metal-oxide-semiconductor between the second general controls interface and the clock control mouth, be used for carrying out the data isolation protection.

3. chip debugging interface device according to claim 2 is characterized in that: described metal-oxide-semiconductor one end is connected to power supply, and the other end is connected with ground by an electric capacity.

4. chip debugging interface device according to claim 3 is characterized in that: described chip debugging interface device also comprises: the 3rd power interface, ground connection interface and power supply, and described the 3rd power interface is connected with power supply, ground connection interface ground connection; Described the 3rd power interface is independently-powered, described the 3rd power interface comprises first power supply interface and second power supply interface, first power supply interface directly connects power supply, connect by a parallel circuit between second power supply interface and the ground connection interface, described parallel circuit is 1 decoupling capacitor and 1 filter capacitor parallel connection.

5. chip debugging interface device according to claim 4 is characterized in that: described I²The data of C port transmit mouth, clock control mouth and are connected with power supply by a pull-up resistor respectively.

6. according to the arbitrary described chip debugging interface device of claim 1 to 5, it is characterized in that: connect a USB coupling and protective resistance between described differential signal interface and the differential signal output interface, be used for carrying out coupling and the protection of USB.

7. according to claim 4 or 5 described chip debugging interface devices, it is characterized in that: described USB port also comprises first power interface, and the parallel circuit that composes in parallel by 1 decoupling capacitor and 1 filter capacitor is connected with power supply.

8. chip debugging interface device according to claim 7 is characterized in that: connect a USB coupling and protective resistance between described differential signal interface and the differential signal output interface, be used for carrying out coupling and the protection of USB.

9. chip debugging interface device according to claim 8 is characterized in that: described power supply for+3.3V or+5V.

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