Five, embodiment
5.1 low power consumption high-precision radar liquid level instrument system implementation
Native system is used for petroleum industry and water conservancy field, because system will be installed in the oil tank, in order to reach the industrial standard of essential safety, harsh requirement has been proposed for the power consumption of system, the power consumption of system must be less than 40mW, and the precision that simultaneity factor need reach is very high.In order to satisfy this two requirements, adopted following measure: the device of as far as possible selecting low-power consumption for use; Adopt special system's control and signal Processing mechanism.To make introductions all round below.The total of low power consumption high-precision radar liquid level instrument system as shown in Figure 1, this system is divided into three parts:HART plate 1, measureplate 2 and slottedline 3, wherein the HART plate is finished the communicating by letter of MSP430F449 controller andhost computer 4, the generation of 4-20mA electric current, the conversion of power source voltage; Measure plate and finish the measurement of distance, and carry out data communication by the HART plate with host computer in real time, measure plate and form byprimary controller 30, precision clock generation 17 (seeing Fig. 6 for details), pulse generation and shaping 18 (seeing Figure 10 for details),annular device 31,analogue multiplier 13, filtering amplification 27 (seeing Figure 12 for details), direct current correction and negative pulse paraphase 28 (seeing Figure 15 for details) andAD circuit 29; Slotted line comprises and measures mechanical interface, flange or cable between the plate.System's each several part implementation will be done concrete introduction in the back.
Systematic technical indicator is:
1, maximum measuring distance scope: 40m
Upper limit dead band:<250mm
Lower limit dead band:<150mm
2, resolution: 1mm
3, measuring error :≤± 5mm
4, repeatability: ± 1mm
5, communication: RS-485/RS-232 and HART communications protocol
6, electric current output: 2 line system 4-20mA, isolate load, maximum to 750 Ω
7, power supply: DC18V to 36V
8, damping time: 0~40S
9, environment temperature :-40~60 ℃
10, ambient humidity: 100%RH
11, dielectric property
Specific inductive capacity: 1.4~100
Temperature :≤200 ℃
Pressure :≤4Mpa
Can adapt to foam, steam, dust
12, antenna, rod-type or cable formula, guide cable maximum tension 5KN
13, mechanical property
Shell: cast aluminium
Be connected with the process jar: G3/2 " screw thread or DN50, PN40 sends out orchid
Cable outlet: M20 * 1.5
Protection: IP67
14, explosive-proof grade: iaIICT3-T6 or dIICT3-T6
15, modification zero-bit, range, capacity, the upper limit, lower limit, damping, website, password etc. can be set at the scene
16, has automatic control function, low-cost below 7000/
5.2HART communication implementation
HART (Highway Addressable Remote Transducer), the open communication agreement of highway addressable remote transducer is a kind of communication protocol that is used between field intelligent instrument and the pulpit equipment.The HART agreement adopts the audio digital signals that superposes on the 4-20mA simulating signal to carry out the bi-directional digital communication, and does not influence the size that sends the control system simulating signal to, has guaranteed the compatibility with existing simulation system.
The HART agreement has adopted its simplification three layer model structure, i.e. ground floor Physical layer, second layer data link layer and layer 7 application layer with reference to ISO/OSI (Open Systems Interconnection).
Physical layer specifies the transmission method of signal, transmission medium, carry out simultaneously and do not disturb mutually in order to realize analogue communication and digital communication, the HART agreement adopts shift keying technique FSK, i.e. frequency signal of superposition on the 4-20mA simulating signal, frequency signal adopts the Be11202 international standard, and the transmission baud rate of digital signal is set at 1200bps, 1200Hz represents logical zero, 2200Hz represents logical one, signal amplitude 0.5A, as shown in Figure 2.In a signal period, the fsk signal average is 0, does not influence the 4-20mA simulating signal so carry out digital communication.Because fsk signal mean value is zero, can not produce any influence to simulating signal.
The selection of communication media is decided on transmission range length.When adopting the multiple twin concentric cable as transmission medium usually, maximum transmission distance can reach 1500m.The circuit resulting impedance should be between 230-1100 Ω.Data link layer has been set up the HART information format according to the HART agreement.Application layer is used to realize the HART instruction.
Data link layer has been stipulated the form of HART frame, the link communication function realizes setting up, safeguards, terminates, the HART agreement is according to redundant error-detecging code information, adopt automatic repetitive requests transmit mechanism, eliminate because the data communication that line noise or other interference cause is made mistakes, realize that the communication data zero defect transmits.
The HART protocol section of intelligence radar level gauge is mainly finished the conversion of numeral to electric current, by the setting of electric current in the single-chip microcomputer and liquid level corresponding relation, realizes the last output of liquid level.Fig. 3 is intelligent radar level gauge HART protocol section theory diagram, and the control line between MSP430F449 and the A5191HRT comprises that Data Receiving 5, data sendinterruption 6 and data transmission 7.
The HART communications portion is mainly realized by D/A conversion and Bell202 MODEM and accessory circuit thereof.The HART communication unit detects after the FSK frequency shift keyed signals that is superimposed upon on the 4-20mA loop, by Bell202 MODEM the signal of 1200Hz is demodulated into " 1 ", and the 2200Hz signal is demodulated into " 0 ", transfers to microprocessor processes.Equally, the digital communication signal that microprocessor sends is superimposed upon on the loop and is sent by the FSK frequency shift keyed signals that MODEM is modulated into corresponding 1200Hz and 2200Hz.What HART communication was adopted is semiduplex mode.The key of hardware design is to solve the low-power consumption problem, and system all adopts low energy-consumption electronic device.
Because the requirement of HART digital communication has the sine-wave current signal of 0.5mA to be superimposed upon on the 4mA electric current, therefore must guarantee can also operate as normal below 3.5mA for whole hardware circuit.Therefore microprocessor need adopt the single-chip microcomputer (MSP430F449) of low-power consumption to realize, and powers with minimum voltage.
AD421 is adopted in the D/A conversion, and it is a kind of monolithic high-performance digital to analog converter that U.S. ADI company releases, and by loop service, 16 position digital signals are imported with serial mode, the output of 4-20mA electric current.The solution that it provides high precision, fully integrated, low-power consumption adopts 16 pin DIP, TSSOP, SOIC encapsulation, can realize long-distance intelligent Industry Control cheaply.AD421 comprises 16 D/A of serial input (numeral/electric current) conversion, except that self electricity consumption, also provides selectable (5V, 3.3V or 3V) voltage stabilizing output for the electricity consumption of transmitter other parts.
The HT2015 that HART MODEM adopts Amis company to produce realizes the coding or the decoding of the digital communication of HART agreement regulation.This chip aims at the HART instruments design, and chip integration has become to meet modulator, detuner, clock and timing circuit, the detection control circuit of BELL202 standard.Cost performance is higher, 16 pin DIP encapsulation ,+working current 80 μ A when 5V powers.A5191HRT and microcontroller exchange digital signal are made analog signal interface with AD421.The process flow diagram of software section as shown in Figure 4.
Compare with traditional scheme, this system has advantages such as reliability is higher, real-time is strong, cost is lower.
5.3 measure firm and hard existing scheme
Measure plate finish the measurement of distance, system control and with the control of host computer, the area of PCB is 114cm * 7cm, principle as shown in Figure 5, whereinanalog multiplier 13 is used the HMC207S8 of Hittite companies.
Measure plate by the power supply of HART plate, in order to save electric current, system's supply voltage be 3v and-3v, under the prerequisite that can reach system performance, the device of measuring in the plate is all selected the device of low-power consumption for use, some are arranged is the super low-power consumption device.As having selected the MCU:MSP430F449 of super low-power consumption in the system for use, under the work clock of 1MHz, electric current is 280uA during the power supply of 2.2v power supply, and under the work clock of 5MHz, electric current is 1mA during the power supply of 2.2v power supply, and minimum operating voltage is 1.8v.That the positive supply module in the system is selected for use is the LT1763 LDO of Linear Technology company, its static working current is 20uA, maximum output current is 500mA, what the negative supply module was selected for use is the LT1617 switch modulator of Linear Technology company, its static working current is 20uA, and maximum output current is 300mA.That the clock generating device is selected for use is the low-power consumption AD9834 of AD company, and electric current is 4mA under the work clock of this chip 25MHz, and electric current is 10uA under dormant state.Operational amplifier also is the series of the lowest power consumption selected for use in the system.The basic circuit that system has drawn in Fig. 6, in order to reduce power consumption, must work in the system gap, promptly system in a measuring period, the sub-fraction that accounts for measuring period of working time, MSP430F449 closes other devices in the remaining time.Next with the duty of partial circuit in the introducing system and system.
5.3.1 realize that with two AD9834 difference on the frequency is 100Hz and 4Hz two-way clock
DDS has very high frequency resolution, realizes that with DDS difference on the frequency is that the two-way clock of 100Hz and 4Hz is only method.Require the difference on the frequency of two-way clock to be strict 100Hz and 4Hz in the system, the degree of accuracy of 100Hz and 4Hz difference on the frequency directly influences the precision of measurement, and in order to realize this index, two-way DDS adopts identical reference clock 5MHz, guarantee the difference on the frequency of 4Hz and 100Hz, realize block diagram as shown in Figure 6.
Frequency, phase differential and the reference clock of MCU control two-way DDS.When AD9834 can close clock and DDS in idle time period, thereby saved power consumption.The relative phase of two-way DDS output frequency also can be achieved by reference clock and the DDS of control two-way DDS, and this provides strong assurance for the intellectuality control and the low-power consumption solution of system.
Block diagram design frequency difference according to Fig. 6 is the two-way clock of 4Hz and 100Hz, and frequency control word and mode control word are by being defeated by AD9834 after the MSP430F449R ESET.Wave filter among the figure adopts low pass Chebyshev form.Index is as follows: 1 passband, 0~1.2MHz; 2 band attenuations are less than 0.3dB; The decay of 3 frequencies during greater than 2MHz is greater than 60dB.
In target search stage: MSP430F449 control two-way AD9834 output frequency difference is the two-way clock signal of 100Hz, the frequency spectrum of theclock signal 9 thatAD9834#2 produces as shown in Figure 7, the frequency spectrum of theclock signal 8 thatAD9834#1 produces is as shown in Figure 8.
Distance accurately measuring phases: MSP430F449 control two-way AD9834 output frequency difference is being the two-way clock signal of 4Hz, the frequency spectrum of theclock signal 9 thatAD9834#2 produces as shown in Figure 7, the frequency spectrum of theclock signal 8 thatAD9834#1 produces is as shown in Figure 9.
5.3.2 pulse-generating circuit and pulse shaping circuit
Square wave amplification and pulse-generating circuit are as shown in figure 10, triple-pole type transistor 2SC3356 will import square wave and amplify, SRD selects the mp4023 of M-Pulse company for use in the circuit, SRD is the Primary Component that produces ultra wideband narrow-pulse, SRD has very strong nonlinear capacitance characteristic, SRD is when forward conduction, can store a large amount of few sons in the n type layer, when SRD enters reverse-conducting, SRD does not end at once, but enters cut-off state after the electric charge in the n layer all is drawn out of, and inverse current falls lowly especially suddenly, make diode end, so just formed step voltage.Very crucial element is L in circuit1And L2, these two inductance play the effect of resonance and excitation, according to author's experience, will change the amplitude of Dc bias or driving pulse accordingly when changing inductance value, can have influence on the width and the amplitude of pulse simultaneously, find in simulation process, when increasing L1, then must reduce dc offset voltage, the amplitude of the pulse that produces can increase, and pulse width broadens; When increasing L2Value then must increase dc offset voltage, and the amplitude of the pulse that produces increases, and pulse width broadens.So, must reduce L if make the narrowed width of pulse1And L2Value, but under same pulse situation, reduce L1And L2Can make the amplitude of output pulse reduce, this is a contradiction, this problem of the consideration that will compromise in circuit design.
Thepumping signal 11 of pulse-generating circuit is the clock signal of 3.3V, this clock signal is that the clock signal that AD9834 produces produces through shaping circuit, butnarrow pulse waveform 18 rings that step-recovery diode (SRD) produces are bigger, adopted schottky diode that narrow pulse signal is carried out shaping in the circuit, thesignal 12 of shaping output is relatively more carefully and neatly done, improved the signal to noise ratio (S/N ratio) of received signal, schottky diode is selected the hsms2820 of Avago company for use, thesignal 12 of shaping output as shown in figure 11, pulse width is 400ps, and pulse height is 1.5V.
5.3.3 filter amplification circuit
The output signal 14 of system simulation multiplier 13 has high-frequency information and low-frequency information, in order to extract the envelope information of analogue multiplier output, the signal that needs the filtering HFS, simultaneously because the low frequency signal power of analogue multiplier output 14 is very little, so also need low frequency signal is amplified,, selected the mode of active power filtering for use in order to reach this two purposes simultaneously, OPA selects the super low-power consumption operational amplifier OP90 of AD, its input off-set voltage (V for useOs) be 50uV, input drift current (IOs) be 0.4nA, operating voltage range is 1.6-36v, exports maximum drive current greater than 5mA, open-loop gain 700V/mV, common mode inhibition (CMR) 110dB, input noise voltage 3 μ VP-p, power supply inhibiting rate (PSRR) 10 μ V/V.Artificial circuit as shown in figure 12, the bandwidth that is provided with source filter is 6KHz, gain in the passband is 30dB (S21), at first calculate each component value, change the component value that calculates into standard value then, the tolerance of each element is set, and carries out software debugging, up to each element in certain range of tolerable variance wave filter family curve constant substantially.The S21 curve of simulation result as shown in figure 13, in the vicinity of 1MHz and harmonic wave thereof bigger component is arranged in the signal spectrum of analogue multiplier output, we look at the inhibition degree at this low-pass filter 1MHz frequency place, the 42dB that decays at frequency 1MHz place wave filter, add the gain of 30dB in passband, inhibition degree at 1MHz place wave filter is 72dB, and wave filter increases along with the increase of frequency at the inhibition degree that the 1MHz harmonic wave removes.OP90 is under ± 3V power drives, and the input range scope is-1.5V~1.5V that the output amplitude scope is-2.5V~2.5V to satisfy the requirement of signal amplitude.Simulation is multiplied each other its output signal through after two-stage amplification and the filtering, and the amplitude of envelope signal 15 will reach 3V, has reached the requirement of AD input full scale basically, and the envelope negative pulse need be carried out paraphase, and will carry out suitable amplification according to the amplitude of negative pulse.
5.3.4 direct current is proofreaied and correct and the negative pulse phase inverter
The output signal of wave filter is before carrying out paraphase and amplifying, need proofread and correct direct current, phase inverter will be born the signal paraphase of semiaxis to positive axis, if the filter output signal direct current component is non-vanishing, paraphase will lead to errors so, two kinds of situations as shown in figure 14, wherein dotted line is the waveform after the negative semiaxis paraphase, left side figure is that direct current is greater than zero situation, through a phase inverter paraphase partial pulse, the right-hand component of Figure 14 is the minus situation of direct current, through negative pulse behind the phase inverter and part positive pulse all by paraphase, both of these case all can cause the mistake of paraphase, so the DC voltage of signal will be proofreaied and correct to zero before the negative pulse paraphase.The circuit that direct current is proofreaied and correct as shown in figure 15, operational amplifier is selected the OP90 of AD company for use in the correcting circuit, can obtain following equation for desirable operational amplifier,
V wherein1For direct current is proofreaied and correct signal before, by two impulse sources (SRC3 and SRC4) simulation, V19For direct current is proofreaied and correct output, R8, R9For resistance shown in the figure, work as R8=25K, R9During=100K, V19=1.25V15-0.25VDc, i.e. R8Voltage passed through direct current offset, side-play amount is-0.25VDcSo, can be in circuit by adjusting VDcValue adjust the direct current of input signal.For adjusting dc offset that can be real-time in software, select for use the DA chip that V is providedDc, system controls the output valve of DA according to the data of tested curve, thereby changes DC quantity.Direct current correctingcircuit input signal 15 as shown in figure 16; Direct current correctingcircuit output signal 19 as shown in figure 17; Negative pulseparaphase output signal 16 as shown in figure 18.V among the figure15Proofread and correct preceding signal for direct current, DC component is 1V, works as VDcDuring=5.1V, output signal V19Direct current be 0.
As the V among the figure16, the amplitude and the waveform shape of positive pulse all do not change, and amplitude is 1.5V, and to positive axis, the shape of waveform does not change negative pulse yet by paraphase, and just variation has taken place in amplitude, in Figure 15, R13The amplitude amplification multiple of decision negative pulse, R13The more little negative pulse amplification multiple of value big more, so can be by changing R13Value different negative pulse gain coefficients is set.In order to control the gain coefficient of negative pulse amplitude in real time, selected the MAX5429 digital regulation resistance of MAXIM company in the system for use, MSP430F449 is according to the value of the amplitude real-time regulated digital regulation resistance of echoed signal, thus with the amplitude adjusted of echoed signal to suitable value.The MAX5429 maximum resistance is 10K, and 32 different resistance values can be set, and 32 different negative pulse gain coefficients are arranged accordingly.
5.3.5 system low-power consumption, done with high accuracy scheme
The workflow of system is controlled by MSP430F449, the MSP430F449 low-power scm adopts 16 RISC (reduced instruction set computer) structure, instruction cycle can reach 125ns, 5 kinds of low-power consumption modes are provided, the built-in 64KByte flash program space and 2K Byte ram space, the maximum clock that system can work is 7.5MHz, in order to leave surplus for system's operate as normal, the work clock that system is set is 5MHz, as shown in the table, working current when system clock is 1MHz is 420uA, and the electric current during system hibernates is 0.1uA, and working current only is 1mA when system clock is 5MHz after tested.
After the system reset, MSP430F449 at first carries out initialization to circuit, comprises the setting of two counters and the setting of interruption, the setting of two-way DDS, the setting of AD, the setting of HART plate.There is counter A sum counter B MSP430F449 inside, and counter A is set to the sampling clock of clock AD, and the clock of counter A is 200KHz, and counter B is used for the state of control system, and the clock of counter B is 25KHz.Finish once complete measurement and need carry out two step branch processes:
Target search:
After initialization is provided with, open counter B, counter B has 7 comparers, so can provide the periodic signal that 7 cycles are identical, pulse width is adjustable at most, system has used 4 comparers, one of them comparer is used to be provided with interrupt source, the sequential of these four comparer outputs as shown in figure 19, the repetition period of system works is 40ms, TB1 is used for producing the interruption sequential among Figure 19, produce an interruption constantly at t1, this interruption wakes MSP430F449 up from dormancy, do following work after MSP430F449 is waken up in succession:
It is 0 that a is provided with the phase place that produces reference clock AD9834 and generation burst pulse clock AD9834, and the frequency that reference clock AD9834 is set is 1MHz, and it is 1MHz+100Hz that the frequency that produces burst pulse clock AD9834 is set, and activates two-way AD9834.
B activates TA.
C closes HART and interrupts allowing.
D opens TB1 and interrupts allowing.
The clock that counter TA produces is as the sampling clock of AD7813.The sequential of TA as shown in Figure 19.The BUSY position of MSP430F449 cyclic query AD7813, when the BUSY position of AD7813 when low, show that the AD sampling of last time has finished, then MSP430F449 withdraws from circulation, reads the AD sampled data and is saved in earlier in the internal RAM of MSP430F449.MSP430F449 reads the AD sampled data continuously, interrupts 2 up to t2 TB1 generation constantly, and in commission disconnected 2 service routines, MSP430F449 finishes following task:
A closes AD9834
B closes TA
C revises stack pointer, and stack pointer is shifted to an earlier date one, and the value of return pointer correspondence is pointed to master routine.Because interrupt 1 service routine also do not withdraw from this moment, originally interrupt 2 return address and point to the address of interrupting in 1 service routine.
D opens TB1 and interrupts allowing
Turn back in the master routine after program is finished four work as listed above, in master routine, MSP430F449 writes down this progress of work, and service routine decides next time the progress of work according to the progress of work of this record when interrupt producing next time.MSP430F449 will enter dormant state, open the HART plate and interrupt allowing before entering dormant state.Illustrate that some the mimic channel in the system, burst pulse produce activation and the dormant state of circuit, AD9834 clock circuit and AD7813 and controlled by the TB2 among Figure 19, TB3 and TB4, do not need software control.Finishing target search needs two TB cycles, the same substantially with first TB cycle before the program of second TB in the cycle interrupting 2, and the phase place that different is will be provided with generation reference clock AD9834 is 36 °.The AD sampled data is saved in after the AD sampled data first time.To write down executive process equally when in commission breaking 2 service routines.In conjunction with the AD sampled data of a last TB in the cycle, search the position of target roughly.Exomonental frequency is 1MHz+100Hz, the frequency of reference pulse is 1MHz, analysis according to a last chapter, time scale amplification coefficient k=10001, the maximum measuring distance of system is 30m, then transponder pulse and received pulse maximum time are spaced apart 200ns, after the elapsed time ratio is amplified, maximum time is spaced apart 2.0001ms, just can all note the position that target may occur so need only two sampling periods, as shown in figure 20.Judge that according to the data of twice record driftlessness is arranged, and the position of target appearance, two kinds of possibilities write down: driftlessness; Target is arranged, and the position that record object occurs, the amplitude of target echo are converted into phase place with the target and the exomonental time interval.In the next TB cycle, MSP430F449 judges that driftlessness is arranged, if target is arranged then enter accurate measurement, if do not have target then the target approach search.MSP430F449 enters the interruption permission of opening the HART plate before the dormancy.
Accurately measure:
Target search can be determined the Position Approximate of echo target, the time scale enlargement factor is 10001 times, because the speed of AD sampling only is 200KHz, resolution in this following time of sampling rate is 250ps, corresponding range resolution is 7.5cm, then far do not reach the index of system, so will carry out further more accurate measurement.After system enters accurate measuring phases, the target phase value that MSP430F449 writes down in the stage according to target search, the phase theta that produces reference clock AD9834 is set, it is 1MHz+4Hz that the frequency that produces reference clock AD9834 is set, it is 1MHz that the frequency that produces pulse clock AD9834 is set, and according to the amplitude of the target echo of target search stage record the negative pulse amplification coefficient is set.This moment time scale amplification coefficient k=250001.The program of other program and target search is the same.Time difference between echo-pulse and the transponder pulse is two parts, and as shown in figure 21, first is t1, this part is directly related in the initial phase of reference clock AD9834, t1Obtain by following formula.
In the formula, f1Be exomonental clock frequency, k is the time scale amplification coefficient.
Position in target search stage echo target is definite substantially, this can guarantee accurately comprising the echo target as shown in figure 21 in the sampling interval of measuring phases at 1ms, the second portion of mistiming between echo-pulse and the transponder pulse is Δ t, and Δ t is obtained by the data that 1ms sampled in the time.Transponder pulse and the echo-pulse time interval after time scale is amplified is t1+ Δ t, the time interval between transponder pulse and the echo-pulse is
Under accurate measuring phases, k=250001, under the 200KHz sampling clock, the resolution of time is 20ps, corresponding range resolution is 3mm.MSP430F449 finishes after the calculating of distance, gives HART plate distance value, and this value of HART plate is provided with corresponding current value, preserves measured value, preserves the measurement process, so that enter the measurement of next round in the next TB cycle.MSP430F449 opens the HART plate before entering dormant state interruption allows.So far once complete measurement finishes.When next TB search of target approach again in the cycle, circulate with this, the measured value of system can be followed the tracks of the variation at a slow speed of liquid level.The program flow diagram of system as shown in figure 22.
5.4 upper computer software explanation
The operation upper computer software at first enters the serial port setting interface, as shown in figure 23.From the pull-down submenu, select thestring slogan 20 of gateway.The hit OK button enters intelligent radar liquid level instrument system master interface, clicks the Cancel button and withdraws from radar intelligent liquid level instrument system.
5.4.1 intelligent radar liquid level instrument system master interface
After setting up the string slogan, the hit OK button enters intelligent radar liquid level instrument system master interface, as shown in figure 24.Main interface mainly is made up of following several sections:menu item 21; 4-20mA electriccurrent output area 22; Outage liquidlevel viewing area 25; Outage levelvalue viewing area 23; Enter thebutton 24 at other interfaces; Information shows 26.Can enter from Figure 24 interface, waveform display interface and history curve interface are set.Click button is set enters the interface is set of the setting (X) of Figure 24 master menu or Figure 24 lower left corner.
5.4.2 upper computer software process flow diagram
The flow process of upper computer software as shown in figure 25.