CN101278352B - Daisy chain cascade device and method - Google Patents

Abstract

The present invention provides a technique for serially coupling devices in a daisy chain cascade arrangement. The devices are coupled in a daisy chain cascade arrangement such that an output of a first device is coupled to an input of a second device in the daisy chain to provide for the transfer of information, such as data, address and command information, and control signals from the first device to the second device. Devices coupled in a daisy chain cascade include a Serial Input and a Serial Output (SO). Information is input to the device via the SI. The information is output from the device via the SO. The SO of a preceding device in the daisy chain cascade is coupled to the SI of a succeeding device in the daisy chain cascade. Information input to a preceding device via the SI of the device is transmitted via the device and output from the device via the SO of the device. The information is then transferred to the SI of the following device via the connection between the SO of the preceding device and the SI of the following device.

Description

Translated fromChinese

菊花链级联设备和方法Daisy chain cascade device and method

背景技术Background technique

以计算机为基础的系统在当前已经随处可见，并成功进入到日常生活中所使用的许多设备中，如手机、手提电脑、汽车、医疗装置，个人电脑等等。普遍地，社会在处理日常工作时已经大量依赖于以计算机为基础的系统，如从平衡帐单的简单工作到诸如预报天气等相对复杂的工作。随着技术的发展，越来越多的工作被转移到以计算机为基础的系统。这也使得社会越来越依赖于这些系统。 Computer-based systems are ubiquitous today and have successfully entered many devices used in daily life, such as cell phones, laptops, cars, medical devices, personal computers, and more. In general, society has relied heavily on computer-based systems for everyday tasks ranging from the simple task of balancing bills to relatively complex tasks such as forecasting the weather. As technology develops, more and more jobs are being transferred to computer-based systems. This also makes society more and more dependent on these systems. the

典型的以计算机为基础的系统包括系统板和可选的一个或多个外围设备，如显示单元，存储单元等。系统主板可以包含一个或多个处理器，存储子系统以及其它逻辑，如串行设备接口，网络设备控制器，硬盘控制器等。 A typical computer-based system includes a system board and optionally one or more peripheral devices such as a display unit, memory unit, etc. A system motherboard can contain one or more processors, storage subsystems, and other logic such as serial device interfaces, network device controllers, hard disk controllers, and more. the

在特定系统板上使用的处理器的类型通常取决于系统上所执行的工作的类型。例如，执行限定的一组工作的系统，如监控由汽车引擎所产生的排放物并调整空气/燃料混合物以保证引擎完全燃烧燃料，可以采用简单的专用处理器，专门用来执行这些工作。另一方面，执行许多不同工作的系统，如管理许多用户以及运行许多不同的应用，可以采用一个或多个更为复杂的处理器，这些处理器其本质上是通用的，通过配置以执行高速计算和处理数据，从而将服务用户请求的响应时间降低到最小。 The type of processor used on a particular system board usually depends on the type of work being performed on the system. For example, a system that performs a defined set of jobs, such as monitoring the emissions produced by a car engine and adjusting the air/fuel mixture to ensure that the engine burns the fuel completely, could employ a simple dedicated processor dedicated to those jobs. On the other hand, systems that perform many different jobs, such as managing many users and running many different Compute and process data so that the response time to service user requests is minimized. the

存储子系统是用于保存处理器所使用信息(如指令、数据值)的存储器。存储子系统典型包含控制逻辑以及一个或多个存储设备。控制逻辑被典型地配置成存储设备与处理器间的接口，以使得处理器能够存储信息到存储设备并从存储设备取回信息。存储设备保存了实际的信息。 The storage subsystem is the memory used to hold information (eg, instructions, data values) used by the processor. A storage subsystem typically contains control logic and one or more storage devices. Control logic is typically configured to interface between the storage device and the processor to enable the processor to store information to and retrieve information from the storage device. Storage devices hold the actual information. the

与处理器相类似，在存储子系统上所使用设备的类型通常由计算机系统所执行任务的类型决定。例如，计算机系统可能具有在没有磁盘驱动器的帮助下开机以及执行一组不常改变的软件例程的工作。此时，存储子系统可以采用非易失性的设备，例如闪存设备，来存储软件例程。其它的计算机系统可能执行非常复杂的工作，需要大量的高速数据存储器以保存大量的信息。此时，存储子系统可以采用高速高密度动态随机存储器 (DRAM)装置以保存大量的信息。 Like processors, the type of devices used on a storage subsystem is generally determined by the type of tasks the computer system is performing. For example, a computer system may have the job of booting up without the aid of a disk drive and executing a set of software routines that change infrequently. At this time, the storage subsystem may use a non-volatile device, such as a flash memory device, to store software routines. Other computer systems may perform very complex tasks requiring large amounts of high-speed data storage to hold large amounts of information. At this time, the storage subsystem can use high-speed high-density dynamic random access memory (DRAM) devices to store large amounts of information. the

目前，硬盘驱动器具有可存储20到40G字节数据的高密度，但体积相对庞大。然而，闪存(flash memory)，也被称为固态驱动器，由于它的高密度、非易失性、以及相对于硬盘驱动器的小尺寸而受到欢迎。闪存技术是基于EPROM以及EEPROM技术的。选择“闪”一词是因为在一次操作中擦除大量的存储单元，有别于EEPROM中一次操作擦除一个字节。相对于单层式存储单元，多层式存储单元(MLC)的出现进一步增加了闪存的密度。本领域技术人员将会了解，闪存可以被配置成NOR闪存或NAND闪存，其中的NAND闪存由于其较紧密的存储排列结构而在每个给定面积具有更高的密度。为了后续说明的目的，所提到的闪存可以被认为是NOR或NAND或其它类型的闪存。 Currently, hard disk drives have high densities that can store 20 to 40 gigabytes of data, but are relatively bulky. However, flash memory, also known as a solid-state drive, has gained popularity due to its high density, non-volatility, and small size relative to hard drives. Flash memory technology is based on EPROM and EEPROM technology. The term "flash" was chosen because a large number of memory cells are erased in one operation, as opposed to erasing one byte at a time in EEPROM. Compared with single-level memory cells, the emergence of multi-level memory cells (MLC) further increases the density of flash memory. Those skilled in the art will understand that the flash memory can be configured as NOR flash memory or NAND flash memory, where NAND flash memory has a higher density per given area due to its denser memory arrangement. For purposes of subsequent descriptions, references to flash memory may be considered to be NOR or NAND or other types of flash memory. the

存储子系统中的设备通常采用平行互连机制互连。该机制涉及到以这样的方式连接到设备上：地址和数据信息以及控制信号以并行的方式耦合到设备上。每个设备可包括多个输入/输出，以便于并行传送数据和地址信息以及控制信号到设备。 Devices in a storage subsystem are usually interconnected using a parallel interconnect mechanism. The mechanism involves connecting to a device in such a way that address and data information and control signals are coupled to the device in parallel. Each device may include multiple inputs/outputs to facilitate parallel transfer of data and address information as well as control signals to the device. the

发明内容Contents of the invention

与在存储子系统中采用并行连接相关的缺点为设备间往往需要大量的互连以在设备间并行地传送信息和信号。这就增加了采用这些存储子系统的板的复杂度。此外，与大量互连相关的不良效果，如串扰(crosstalk)，往往会限制这些子系统的性能。并且，包含在这些子系统中的设备的数量可能会因为互连带来的信号传输延迟而受到限制。 A disadvantage associated with employing parallel connections in storage subsystems is that a large number of interconnections between devices are often required to transfer information and signals between devices in parallel. This adds to the complexity of the boards that employ these memory subsystems. Additionally, undesirable effects associated with large numbers of interconnects, such as crosstalk, tend to limit the performance of these subsystems. Also, the number of devices included in these subsystems may be limited due to signal transmission delays caused by interconnections. the

此处所描述的技术通过提供将设备用菊花链级联排列耦合的技术克服了上述缺陷，其中的菊花链级联排列与并行互连实现相比采用了较少和较短的连接。因为采用了较少和较短的互连可使得整个实施很少受不良效果的影响，如传输延迟以及串扰，所以以菊花链级联排列的方式配置设备可允许设备在操作时较并行互连实现具有更快的速度。另外，较少和较短的连接往往减少了实现的复杂性。所降低的复杂性进一步使得包含该设备的子系统能在更小的面积上实施，因此允许子系统占用较小的面积。 The techniques described herein overcome the aforementioned drawbacks by providing techniques for coupling devices in a daisy-chain cascade arrangement that employs fewer and shorter connections than a parallel interconnection implementation. Configuring devices in a daisy-chain cascade arrangement allows devices to operate more parallel to each other because fewer and shorter interconnects make the overall implementation less susceptible to undesirable effects such as propagation delay and crosstalk Implementation has greater speed. Additionally, fewer and shorter connections tend to reduce implementation complexity. The reduced complexity further enables the subsystems incorporating the device to be implemented on a smaller area, thus allowing the subsystems to occupy a smaller area. the

根据在此所述技术的一些方面，设备以菊花链级联排列耦合，以使得菊花链级联中的在先设备的输出被耦合到菊花链级联中的在后设备的输入，以提供从在先设备到在后设备的信息(如，数据、地址和命令信息) 和控制信号(如，使能信号)的传输。 According to some aspects of the technology described herein, devices are coupled in a daisy-chain cascade arrangement such that the output of an earlier device in the daisy-chain cascade is coupled to the input of a subsequent device in the daisy-chain cascade to provide Transmission of information (such as data, address, and command information) and control signals (such as enable signals) from the previous device to the subsequent device. the

在本技术的一个实施例中，菊花链级联中的每个设备包括串行输入(SI)和串行输出(SO)。信息通过设备的SI输入到设备中。类似的，信息通过设备的SO设备输出。菊花链级联中设备的SO被耦合到菊花链级联中下一个设备的SI。在设备中设置电路以使得通过设备的SI输入到菊花链级联中的一个在先设备的信息通过该设备传送，并通过设备的SO从该设备输出。然后信息通过在先设备的SO和下一个设备的SI之间的连接，被传送到菊花链级联中下一个设备的SI。被传送的信息可通过下一个设备的SI被输入到下一个设备中。 In one embodiment of the present technology, each device in the daisy chain cascade includes a serial input (SI) and a serial output (SO). Information is entered into the device through the device's SI. Similarly, information is output through the device's SO device. The SO of a device in a daisy-chain cascade is coupled to the SI of the next device in the daisy-chain cascade. Circuitry is arranged in the device so that information input to a previous device in the daisy-chain cascade via the device's SI is transmitted through the device and output from the device through the device's SO. The information is then passed to the SI of the next device in the daisy-chain cascade through the connection between the SO of the previous device and the SI of the next device. The transmitted information can be input to the next device through the SI of the next device. the

此外，时钟信号耦合到菊花链级联中的设备。该时钟信号被设备使用以提供信息从菊花链级联中的一个设备到下一个设备间的传送。 Additionally, a clock signal is coupled to the devices in the daisy-chain cascade. This clock signal is used by devices to provide the transfer of information from one device to the next in a daisy chain cascade. the

根据在此所述技术的其它方面，为设备所用(例如使数据通过SI输入到设备以及通过SO将数据从设备中输出)的控制信号(如使能信号)在如前所述的菊花链级联的设备间传送。此处，设置电路以使能输入到菊花链级联中的在先设备的控制信号传播通过该设备，并通过一个输出从该设备传送到菊花链级联中的下一个设备的输入。然后所传送的控制信号通过该输入而输入到下一个设备。 According to other aspects of the technology described herein, control signals (such as enable signals) used by devices (such as enabling data input to the device through SI and output data from the device through SO) are at the daisy chain level as previously described transfer between connected devices. Here, the circuitry is arranged to enable a control signal input to a previous device in the daisy chain cascade to propagate through the device and pass from that device via an output to the input of the next device in the daisy chain cascade. The transmitted control signal is then input to the next device through this input. the

根据本发明的原理，闪存系统可拥有多个串行连接的闪存设备。该系统中的闪存设备可包括具有串行输入数据端口和串行数据输出端口的串行数据链接接口，用于接收第一输入使能信号的控制输入端口，以及用于发送第二输入使能信号的控制输出端口。输入使能信号在电路中被使用，以控制数据在串行数据链接接口和存储体间的传送。闪存设备被配置为从外部源接收串行输入数据和控制信号以及向外部设备提供数据和控制信号。外部源和外部设备可以是系统中的其它闪存设备。在本发明的实施例中，当设备在系统中串行级联时，这些设备可进一步输出控制端口，这些控制端口将所接收到的IPE和OPE信号“传回(echo)”到外部设备。这允许系统具有点对点连接的信号端口，以形成菊花链级联机制(相对于广播/多点级联机制)。 In accordance with the principles of the present invention, a flash memory system may have multiple serially connected flash memory devices. The flash memory device in the system may include a serial data link interface having a serial input data port and a serial data output port, a control input port for receiving a first input enable signal, and a control input port for sending a second input enable signal. Signal control output port. The input enable signal is used in the circuit to control the transfer of data between the serial data link interface and the memory bank. The flash memory device is configured to receive serial input data and control signals from an external source and to provide data and control signals to the external device. External sources and external devices can be other flash devices in the system. In an embodiment of the present invention, when devices are cascaded serially in a system, the devices may further output control ports that "echo" received IPE and OPE signals to external devices. This allows systems to have point-to-point connected signal ports to form a daisy chain cascading mechanism (as opposed to a broadcast/multipoint cascading mechanism). the

这些系统可采用特有的设备识别符以及目标设备选择地址机制，而不使用有限的硬件物理设备选择插脚，因此整个系统很容易在存储密度方面尽可能地扩展，而无需牺牲系统的整体性能。在本发明的一些实施例中，每个闪存设备可包含一个特有的设备识别符。该设备可被配置为解析在串行输入数据中的目标设备信息域，以将目标地址信息和设备的特有设备识别码相关联，以确定该设备是否是目标设备。该设备可在处理所接收到的任何其它输入数据前，先分析目标设备信息域。如果存储设备并非目标设备，则可忽略串行输入数据，从而节省了额外的处理时间和资源。 These systems can use a unique device identifier and target device selection address mechanism instead of using limited hardware physical device selection pins, so the entire system is easy to expand as much as possible in terms of storage density without sacrificing overall system performance. In some embodiments of the invention, each flash memory device may contain a unique device identifier. The device may be configured to parse a target device information field in the serial input data to correlate target address information with the device's unique device identification code to determine whether the device is the target device. The device may analyze the target device information field before processing any other input data received. If the storage device is not the target device, the serial input data can be ignored, saving additional processing time and resources. the

附图说明Description of drawings

参照附图描述，通过下面的对本发明的示例性实施例的更详细说明，使得前述内容更为清楚。附图中，相同标记是指遍及不同图中的相同部分。这些图并非按比例绘制，而是将重点放在说明本发明的实施例。 The foregoing will be made apparent by the following more detailed description of exemplary embodiments of the present invention, described with reference to the accompanying drawings. In the drawings, the same reference numerals refer to the same parts throughout the different drawings. The figures are not drawn to scale, emphasis instead being placed upon illustrating embodiments of the invention. the

图1为示例性设备的结构框图，其包括以串行的菊花链级联排列配置的多个单端口设备； Figure 1 is a block diagram of an exemplary device comprising a plurality of single-port devices configured in a serial daisy-chain cascade arrangement;

图2为示例性设备的结构框图，其包括以具有级联时钟的串行菊花链级联排列配置的多个单端口设备； 2 is a block diagram of an exemplary device comprising a plurality of single-port devices configured in a serial daisy-chain cascade arrangement with cascaded clocks;

图3为示例性设备的结构框图，其包括以串行菊花链级联排列配置的多个双端口设备； Figure 3 is a block diagram of an exemplary device comprising a plurality of dual-port devices configured in a serial daisy chain cascaded arrangement;

图4为示例性设备的结构框图，其包括以串行菊花链级联排列配置的多个单端口设备，该串行菊花链级联排列为各种使能信号提供输入和输出； 4 is a block diagram of an exemplary device including a plurality of single-port devices configured in a serial daisy-chain cascade arrangement that provides inputs and outputs for various enable signals;

图5为示例性设备的结构框图，其包括以串行菊花链级联排列配置的双端口设备，该串行菊花链级联排列为各种使能信号提供输入和输出； 5 is a block diagram of an exemplary device including a dual-port device configured in a serial daisy-chain cascade arrangement that provides inputs and outputs for various enable signals;

图6为示例性设备的结构框图，其包括以串行菊花链级联排列配置的多个设备，该设备具有多个串行输入端以及多个串行输出端； 6 is a block diagram of an exemplary device comprising a plurality of devices configured in a serial daisy chain cascaded arrangement, the device having a plurality of serial inputs and a plurality of serial outputs;

图7为描述在以串行菊花链级联排列配置的单独设备上和配置的多个设备上执行读操作时的相关时序的时序图； Figure 7 is a timing diagram depicting the relevant timing when performing a read operation on a single device configured in a serial daisy chain cascaded arrangement and on multiple devices configured;

图8为描述与以串行菊花链级联排列所配置的设备间传送信息相关的时序的时序图； Figure 8 is a timing diagram describing the timing associated with transferring information between devices configured in a serial daisy chain cascade arrangement;

图9为单端口设备的示例性串行输出控制逻辑的高级框图； Figure 9 is a high-level block diagram of exemplary serial output control logic for a single-port device;

图10为双端口设备的示例性串行输出控制逻辑的高级框图； Figure 10 is a high-level block diagram of exemplary serial output control logic for a dual-port device;

图11为用于设备的示例性串行输出控制逻辑的详细框图； Figure 11 is a detailed block diagram of an exemplary serial output control logic for the device;

图12为以串行菊花链级联排列配置以及包括示例性的串行输出控制逻辑的设备的示例性结构框图； 12 is an exemplary structural block diagram of a device configured in a serial daisy chain cascade arrangement and including exemplary serial output control logic;

图13为描述与包含有示例性串行输出控制逻辑的设备的输入和输出相关时序的时序图。 Figure 13 is a timing diagram depicting the timing associated with input and output of a device incorporating exemplary serial output control logic. the

图14为示例性串行输出控制逻辑的框图，该控制逻辑可用于将菊花链级联中的第一设备中的存储器所存储的数据传送到菊花链级联中的第二设备； 14 is a block diagram of exemplary serial output control logic that may be used to transfer data stored in a memory in a first device in a daisy-chain cascade to a second device in the daisy-chain cascade;

图15为描述采用示例性串行输出控制逻辑将包含在菊花链级联中的第一设备的存储器中的数据传送到菊花链级联中的第二设备的相关时序的时序图。 15 is a timing diagram depicting the timing associated with transferring data contained in the memory of a first device in a daisy-chain cascade to a second device in the daisy-chain cascade using exemplary serial output control logic. the

具体实施方式Detailed ways

以下对本发明的较佳实施例进行描述： Preferred embodiments of the present invention are described below:

图1为示例性设备的结构框图，其包括以串行的菊花链级联排列配置的多个单端口设备110a-e。设备110a-e为示例性的存储设备，各包含有存储器(未在图中示出)，该存储器可以包含动态随机存取存储器(DRAM)单元，静态随机存取存储器(SRAM)单元，闪存单元等等。每个设备110包含有串行输入(SI)、串行输出(SO)，时钟(SCLK)输入以及片选择(CS#)输入。 FIG. 1 is a block diagram of an exemplary device including a plurality of single-port devices 110a-e configured in a serial daisy-chain cascaded arrangement.Devices 110a-e are exemplary storage devices, each containing a memory (not shown in the figure), which may include dynamic random access memory (DRAM) cells, static random access memory (SRAM) cells, flash memory cells etc. Each device 110 includes a serial input (SI), serial output (SO), clock (SCLK) input, and chip select (CS#) input. the

串行输入被用于传送信息(如命令，地址和数据信息)到设备110。串行输出被用于从设备110传出信息。SCLK输入用于向设备110提供外部的时钟信号，以及CS#输入用于向设备110提供片选信号。可与此处所述的技术一起使用的设备的一个范例是在美国专利申请第11/324,023号中的多独立串行链接(MISL)存储设备。 The serial input is used to communicate information (such as commands, addresses, and data information) to device 110 . Serial output is used to transfer information from device 110 . The SCLK input is used to provide an external clock signal to the device 110 , and the CS# input is used to provide a chip select signal to the device 110 . One example of a device that may be used with the techniques described herein is the Multiple Independent Serial Link (MISL) storage device in US Patent Application Serial No. 11/324,023. the

菊花链级联排列的设备110间的SI和SO彼此连接，以使得在菊花链级联中较前的设备110中的SO耦合到菊花链级联中下一个设备110的SI。例如，设备110a的SO连接到设备110b的SI。每个设备110的SCLK输入馈送以来自例如存储控制器(未在图中示出)的时钟信号。该时钟信号通过共同的连接分配到各个设备110。如下所述，SCLK特别被用于将输入到设备110的信息锁存到包含的各种寄存器中。 The SI and SO among devices 110 arranged in a daisy-chain cascade are connected to each other such that the SO in a device 110 earlier in the daisy-chain cascade is coupled to the SI of the next device 110 in the daisy-chain cascade. For example, the SO ofdevice 110a is connected to the SI ofdevice 110b. The SCLK input of each device 110 is fed with a clock signal from, for example, a memory controller (not shown in the figure). This clock signal is distributed to the individual devices 110 via a common connection. SCLK is used, inter alia, to latch information input to device 110 into the various registers included, as described below. the

输入到设备110的信息可以在提供至SCLK输入的时钟信号的不同时刻被锁存。例如，在单数据率(SDR)实现中，通过SI输入到设备110的信息可以在SCLK时钟信号的上升沿或下降沿被锁存。可替换的，在双数据率(DDR)实现中，通过SI输入到设备110的信息在SCLK时钟信号的上升沿和下降沿都可被锁存。 Information input to device 110 may be latched at different times of the clock signal provided to the SCLK input. For example, in a single data rate (SDR) implementation, information input to device 110 via SI may be latched on either the rising or falling edge of the SCLK clock signal. Alternatively, in a double data rate (DDR) implementation, information input to device 110 via SI may be latched on both rising and falling edges of the SCLK clock signal. the

各个设备的用于选择设备的CS#输入为传统的片选择。该输入被耦合到公用链接以使得片选择信号被并行确立(assert)到所有的设备110，因而同时对所有设备110进行选择。 The CS# input of each device used to select the device is a traditional slice selection. This input is coupled to a common link so that the chip select signal is asserted to all devices 110 in parallel, thus selecting all devices 110 at the same time. the

图2为示例性设备的结构示意图，其包括以具有级联时钟的串行菊花链级联排列配置的多个单端口设备210a-e。每个设备210包括如上所述的SI，SO，SCLK输入以及CS#输入。此外，每个设备210包含时钟输出(SCLKO)。该SCLKO为将输入到设备210的SCLK信号输出的输出端。 FIG. 2 is a block diagram of an exemplary device including multiple single-port devices 210a-e configured in a serial daisy-chain cascaded arrangement with cascaded clocks. Each device 210 includes SI, SO, SCLK inputs and a CS# input as described above. Additionally, each device 210 includes a clock output (SCLKO). The SCLKO is an output terminal to which the SCLK signal input to the device 210 is output. the

参考图2，如前所述，设备210的SI和SO以串行的菊花链级联被耦合。另外，设备的SCLK输入和SCLKO输出也以串行的菊花链级联排列被耦合，使得在菊花链级联中较前的设备210中的SCLKO耦合到菊花链级联中下一个设备210的SCLK输入。因此，例如，设备210a的SCLKO耦合到设备210b的SCLK输入。 Referring to FIG. 2, as previously described, the SI and SO of device 210 are coupled in a serial daisy-chain cascade. Additionally, the SCLK input and SCLKO output of the devices are also coupled in a serial daisy-chain cascade arrangement such that SCLKO in a device 210 earlier in the daisy-chain cascade is coupled to the SCLK of the next device 210 in the daisy-chain cascade. enter. Thus, for example, SCLKO ofdevice 210a is coupled to the SCLK input ofdevice 210b. the

注意，时钟信号在通过菊花链级联的装置传播时会产生延迟。可采用内部延迟补偿电路，如延迟锁定环(DLL)电路，来排除该延迟。 Note that the clock signal is delayed as it propagates through the daisy-chained devices. Internal delay compensation circuits, such as delay locked loop (DLL) circuits, can be used to remove this delay. the

图3为示例性设备的结构示意图，其包括以串行菊花链级联排列配置的多个双端口设备310a-e。每个设备310在每个端口各包括一个SI和SO，还包括如前所述的SCLK输入和CS#输入。参考图3，设备310上第一端口的SI被标记为“SI0”，第二断口的SI被标记为“SI1”。类似的，第一端口的SO被标记为“SO0”，第二端口的SO被标记为“SO1”。每个端口的SO和SI如前所述连接于设备310之间。因此，例如，设备310a上的端口0的SO馈送到设备310b上的端口0的SI，如此等等。类似的，设备310a上的端口1的SO馈送到设备310b上的端口1的SI，如此等等。 FIG. 3 is a block diagram of an exemplary device including multiple dual-port devices 310a-e configured in a serial daisy-chain cascaded arrangement. Each device 310 includes an SI and SO on each port, as well as an SCLK input and a CS# input as previously described. Referring to FIG. 3, the SI of the first port on device 310 is labeled "SI0" and the SI of the second port is labeled "SI1". Similarly, the SO of the first port is marked as "SO0" and the SO of the second port is marked as "SO1". The SO and SI of each port are connected between devices 310 as previously described. So, for example, the SO ofport 0 ondevice 310a feeds the SI ofport 0 ondevice 310b, and so on. Similarly, the SO ofport 1 ondevice 310a feeds the SI ofport 1 ondevice 310b, and so on. the

图4为示例性设备的结构示意图，其包括以串行菊花链级联排列配置的多个单端口设备，该串行菊花链级联排列具有用于各种使能信号的输入和输出。每个设备410包含如前所述的SI、SO、CS#输入、SCLK输入。此外，每个设备410还包括输入端口使能(IPE)输入、输出端口使能(OPE)输入、输入端口使能输出(IPEQ)以及输出端口使能输出(OPEQ)。IPE输入用于向设备输入IPE信号。IPE信号由设备用来使能SI，使得IPE被确立时，信息可通过SI串行输入到设备410。类似的，OPE输入用于向设备输入OPE信号。OPE信号由设备用来使能SO，使得OPE被确立时，信息可通过SO从设备410串行输出。IPEQ和OPEQ为分别从设备输出IPE和OPE信号的输出端。IPEQ信号可以为延迟的IPE信号，或IPE信 号的变型。类似的，OPEQ信号可能为延迟的OPE信号，或OPE信号的变型。CS#输入和SCLK输入耦合到不同的链接，该链接分别分配CS#和SCLK信号到如前所述的设备410a-d。 4 is a block diagram of an exemplary device including multiple single-port devices configured in a serial daisy-chain cascade arrangement with inputs and outputs for various enable signals. Each device 410 contains SI, SO, CS# inputs, SCLK inputs as previously described. In addition, each device 410 also includes an input port enable (IPE) input, an output port enable (OPE) input, an input port enable output (IPEQ), and an output port enable output (OPEQ). The IPE input is used to input the IPE signal to the device. The IPE signal is used by the device to enable SI so that when IPE is asserted, information can be serially input to device 410 via SI. Similarly, the OPE input is used to input the OPE signal to the device. The OPE signal is used by the device to enable the SO so that when OPE is asserted, information can be serially output from the device 410 through the SO. IPEQ and OPEQ are output terminals for outputting IPE and OPE signals from the device, respectively. The IPEQ signal may be a delayed IPE signal, or a variant of the IPE signal. Similarly, the OPEQ signal may be a delayed OPE signal, or a variant of the OPE signal. The CS# input and the SCLK input are coupled to different links that distribute the CS# and SCLK signals, respectively, todevices 410a-d as previously described. the

如前所述，SI以及SO从菊花链级联排列的一个设备耦合到下一个设备。此外，菊花链级联排列中的一个在前的设备410的IPEQ和OPEQ被分别耦合到菊花链级联中的下一个设备410的IPE输入和OPE输入。这种排列允许IPE和OPE信号从菊花链级联的一个设备410传送到下一个设备。 As previously mentioned, SI and SO are coupled from one device to the next in a daisy-chain cascade arrangement. Furthermore, the IPEQ and OPEQ of a preceding device 410 in the daisy-chain cascade arrangement are respectively coupled to the IPE input and OPE input of the next device 410 in the daisy-chain cascade. This arrangement allows IPE and OPE signals to be passed from one device 410 to the next in a daisy chain cascade. the

图5为示例性设备的结构示意图，其包括以串行菊花链级联排列配置的双端口设备510a-d，该串行菊花链级联排列包括用于各种使能信号的输入和输出。每个设备510包括如前所述的CS#输入、SCLK输入，以及在每个端口上包括SI、SO、IPE、OPE、IPEQ和OPEQ。端口1和端口2中的SI、SO、IPE、OPE、IPEQ和OPEQ被分别表示为SI1、SO1、IPE1、OPE1、IPEQ1和OPEQ1，以及SI2、SO2、IPE2、OPE2、IPEQ2和OPEQ2。 5 is a block diagram of an exemplary device including two-port devices 510a-d configured in a serial daisy-chain cascade arrangement including inputs and outputs for various enable signals. Each device 510 includes a CS# input, a SCLK input as previously described, and on each port SI, SO, IPE, OPE, IPEQ, and OPEQ. SI, SO, IPE, OPE, IPEQ, and OPEQ inport 1 andport 2 are denoted as SI1, SO1, IPE1, OPE1, IPEQ1, and OPEQ1, and SI2, SO2, IPE2, OPE2, IPEQ2, and OPEQ2, respectively. the

如上所述，各个设备510的CS#输入被耦合到单个链路以同时选择所有设备510。类似的，如上所述，各个设备510的SCLK被耦合到单个链路，以配置成同时分配时钟信号到所有设备510。并且，如上所述，SI、SO、IPE、OPE、IPEQ和OPEQ在设备间耦合，以使得菊花链级联中的一个在前设备的SO、IPEQ和OPEQ被耦合到菊花链级联中的一个在后设备的SI、IPE和OPE。例如，设备510a的SO1、SO2、IPEQ1、IPEQ2、OPEQ1和OPEQ2被分别耦合到设备510b中的SI1、SI2、IPE1、IPE2、OPE1和OPE2。 As described above, the CS# input of each device 510 is coupled to a single link to select all devices 510 simultaneously. Similarly, as described above, the SCLK of each device 510 is coupled to a single link configured to distribute the clock signal to all devices 510 simultaneously. And, as described above, SI, SO, IPE, OPE, IPEQ, and OPEQ are coupled between devices such that the SO, IPEQ, and OPEQ of a preceding device in the daisy-chain cascade are coupled to one SI, IPE, and OPE of the device behind. For example, SO1, SO2, IPEQ1, IPEQ2, OPEQ1, and OPEQ2 of device 510a are coupled to SI1, SI2, IPE1, IPE2, OPE1, and OPE2 of device 510b, respectively. the

分别输入到设备510a的SI、IPE和OPE输入端的SI、IPE和OPE信号在例如存储器控制器(未示出)的控制下，被提供给设备510a。设备510d通过设备510d中的SO、IPEQ以及OPEQ输出端向存储器控制器返回数据和控制信号。 The SI, IPE, and OPE signals respectively input to the SI, IPE, and OPE inputs of the device 510a are provided to the device 510a under the control of, for example, a memory controller (not shown). Device 510d returns data and control signals to the memory controller through the SO, IPEQ, and OPEQ outputs in device 510d. the

图6为示例性设备的结构示意图，其包括以串行菊花链级联排列配置的多个设备610a-d，该设备具有多个串行输入端(SI0到SIn)以及多个串行输出端(SO0到SOn)。此外，每个设备610具有如上所述的SCLK输入和CS#输入。 6 is a block diagram of an exemplary device including multiple devices 610a-d configured in a serial daisy-chain cascaded arrangement, the devices having multiple serial inputs (SI0 through SIn) and multiple serial outputs (SO0 to SOn). In addition, each device 610 has a SCLK input and a CS# input as described above. the

各个设备610所使用的串行输入端(SI0到SIn)以及串行输出端(SO0到SOn)使得信息以串行的方式分别输入和输出设备610。每个输入被分 配特定的角色以输入某种类型的数据(如地址，命令，数据)和/或信号(如使能信号)到设备610。类似的，每个输出被分配特定的角色以从设备610输出某种类型的数据和信号。例如，一个或多个输入可以被分配一个能将地址信息输入到设备610的角色。类似的，例如，一个或多个输出可以被分配一个将地址信息从设备610输出的角色。 The serial inputs (SI0 to SIn) and serial outputs (SO0 to SOn) used by each device 610 allow information to be input and output to and from the device 610, respectively, in a serial manner. Each input is assigned a specific role to input a certain type of data (e.g. address, command, data) and/or signal (e.g. enable signal) to device 610. Similarly, each output is assigned a specific role to output certain types of data and signals from device 610 . For example, one or more inputs may be assigned a role capable of inputting address information into device 610 . Similarly, one or more outputs may be assigned a role to output address information from device 610, for example. the

每个设备610上的串行输入端和串行输出端的数量通常取决于某些因素，例如地址线的数量，命令大小和数据宽度大小。这些因素会受到设备在特定系统应用中如何使用的影响。例如，与需要对大量信息进行数据存储的系统应用相比，需要对少量信息进行数据存储的系统应用可以采用具有较少地址线和数据线的设备，而且因此有较少的输入/输出端。 The number of serial inputs and serial outputs on each device 610 generally depends on certain factors, such as the number of address lines, command size and data width size. These factors are affected by how the device is used in a particular system application. For example, a system application requiring data storage of a small amount of information may employ a device having fewer address and data lines, and thus fewer input/output ports, than a system application requiring data storage of a large amount of information. the

图7为描述在以串行菊花链级联排列配置的单独设备上和配置的的多个设备上执行读操作时相关的时序的时序图。参考图7，CS#被确立以选择所有的设备。通过确立IPE和将与读操作相关的时钟信息通过SI按时钟节拍输入进设备以开始读操作。示例性地，这些信息包括指示执行读操作的命令(CMD)以及指示从哪里读取数据的存储器起始地址的列地址(Col ADD)和行地址(Row ADD)。 FIG. 7 is a timing diagram depicting the timing associated with performing a read operation on a single device configured in a serial daisy chain cascade arrangement and on multiple devices configured. Referring to Figure 7, CS# is asserted to select all devices. The read operation is started by establishing the IPE and inputting the clock information related to the read operation into the device according to the clock beat through the SI. Exemplarily, such information includes a command (CMD) indicating to perform a read operation, and a column address (Col ADD) and a row address (Row ADD) indicating a memory start address from where to read data. the

在时间“tR”，从存储器读取所请求的数据并将之存放在包含在设备中的特定内部数据缓存器中。tR的长度通常由包含存储器的单元的特性决定。在时间tR后，OPE被确立以使得数据从内部数据缓存器通过SO串行传输到菊花链级联的下一个设备。示例性地，在SLCK的上升沿，数据从位于SO输出端的内部缓存中串行输出。将从位于菊花链级联的设备所输出的数据延迟一个时钟周期那么长以控制例如与传播控制信号(如IPE以及OPE)相关的延迟时间(latency)。正如将要描述的，采用时钟同步锁存器执行延迟时间控制。 At time "tR", the requested data is read from memory and stored in a specific internal data buffer included in the device. The length of tR is generally determined by the characteristics of the cell containing the memory. After time tR, OPE is asserted so that data is transferred serially from the internal data buffer through SO to the next device in the daisy-chain cascade. Exemplarily, at the rising edge of SLCK, data is serially output from the internal buffer at the SO output. Delaying data output from devices located in the daisy-chain cascade by as long as one clock cycle controls, for example, the latency associated with propagating control signals such as IPE and OPE. As will be described, delay time control is performed using clocked latches. the

闪存核心架构实施中的级联存储设备的一些操作实例显示在下列表1中。表1列出了目标设备地址(TDA)，可能的操作(OP)码以及列地址，行/体地址的对应状态，以及输入数据。 Some operational examples of cascaded storage devices in a flash core architecture implementation are shown in Table 1 below. Table 1 lists the target device address (TDA), possible operation (OP) codes and column addresses, corresponding states of row/body addresses, and input data. the

  操作 operate  目标设备  地址  (1字节)target device address (1 byte)  OP码  (1字  节)OP code (1 byte)  列地址  (2字  节)column address (2 bytes)  行/体  地址  (3字  节)line/body address (3 bytes)  输入数据  (1字节到2112  字节)input data (1 byte to 2112 bytes)  页读取page read  tdatda  00h00h  有效 efficient  有效 efficient  --  随机数据读取Random data read  tdatda  05h05h  有效 efficient  --  --  用于复制的页读取Page reads for replication  tdatda  35h35h  --  有效 efficient  --  用于复制的目标地址  输入Destination Address for Copy Input  tdatda  8Fh8Fh  --  有效 efficient  --  串行数据输入Serial data input  tdatda  80h80h  有效 efficient  有效 efficient  有效 efficient  随机数据输入Random data input  tdatda  85h85h  有效 efficient  --  有效 efficient  页编程page programming  tdatda  10h10h  --  --  --  块擦除block erase  tdatda  60h60h  --  有效 efficient  --  读取状态read status  tdatda  70h70h  --  --  --  读取识别码(ID)Read the identification code (ID)  tdatda  90h90h  --  --  --  写配置寄存器Write configuration register  tdatda  A0hA0h  --  --  有效(1字节)valid (1 byte)  写装置名称(DN)条  目Write Device Name (DN) entry  00h00h  B0hB0h  --  --  --  重置Reset  tdatda  FFhFFh  --  --  --  体选择body selection  tdatda  20h20h  --  有效  (体)effective (body)  --

                            表1 命令集 Table 1 command set

在本发明的一些实施例中，在图1-6中所显示的系统的各个设备可拥有特有的设备识别符，以用作串行输入数据中的目标设备地址(tda)。在接收串行输入数据时，闪存设备分析串行输入数据中的目标设备地址，并通过关联目标设备地址与设备的特有的设备识别号来判断设备是否是目标设备。 In some embodiments of the present invention, each device of the system shown in FIGS. 1-6 may have a unique device identifier for use as a target device address (tda) in the serial input data. When receiving the serial input data, the flash memory device analyzes the target device address in the serial input data, and determines whether the device is the target device by associating the target device address with the unique device identification number of the device. the

表2显示了根据本发明的实施例(包括结合图1-6所描述的系统)的输入数据流的较佳输入顺序。命令、地址，以及数据，从最高有效位开始串行地移进或移出每个存储设备。 Table 2 shows the preferred input order of the input data streams according to embodiments of the present invention, including the system described in connection with FIGS. 1-6. Commands, addresses, and data are shifted in and out of each memory device serially, starting with the most significant bit. the

参考图4，设备410a-d可以在输入端口使能(IPE)为高时利用在串行时钟(SCLK)上升沿所采样的串行输入信号(SIP)进行操作。命令序列以单字节的目标设备地址(“tda”)和单字节的操作码(也可替换地称为命令码(表1中的“cmd”))开始。通过在串行输入信号的最高有效位中采用单字节目标设备地址作为起始，设备可在处理所收到的任何额外的输入数据前，先分析目标地址域。如果存储设备并非目标设备，则可在处理前传送该串行输入数据到另一个设备，从而节省额外的处理时间和资源。 Referring to FIG. 4,devices 410a-d may operate with the serial input signal (SIP) sampled on the rising edge of the serial clock (SCLK) while the input port enable (IPE) is high. A command sequence begins with a one-byte target device address ("tda") and a one-byte opcode (also referred to alternatively as a command code ("cmd" in Table 1)). By starting with the single-byte target device address in the most significant bit of the serial input signal, the device can parse the target address field before processing any additional input data it receives. If the storage device is not the target device, the serial input data can be passed to another device before processing, saving additional processing time and resources. the

  操作 operate  第1  个  字   节1st Word Section  第2  个  字   节2nd Word Section  第3  个  字   节3rd Word Section  第4  个  字   节4th Word Section  第5  个  字   节5th Word Section  第6  个  字   节6th Word Section  第7  个  字   节7th Word Section  第8  个  字   节8th Word Section……  第  2116  个字   节Section 2116 Characters……  第  2119  个字   节Section 2119 Characters  页读  取page read  tdatda  cmdcmd  caca  caca  rara  rara  rara  ----  ----  --  随机  数据  读取random data read  tdatda  cmdcmd  caca  caca  --  --  --  ----  ----  --  用于  复制  的页  读取Page read for replication  tdatda  cmdcmd  rara  rara  rara  --  --  ----  ----  --  用于  复制  的目  标地  址输  入Destination address input for copying  tdatda  cmdcmd  rara  rara  rara  --  --  ----  ----  --  串行  数据  输入serial data input  tdatda  cmdcmd  caca  caca  rara  rara  rara  datadata……  datadata……  datadata  随机randomly  tdatda  cmdcmd  caca  caca  datadata  datadata  datadata  datadata……  datadata--  --

  数据  输入 data input the the the the the the the the the the the the  页编  程page programming  tdatda  cmdcmd  --  --  ----------------  块擦  除block erase  tdatda  cmdcmd  rara  rara  rara--------------  读取  状态read status  tdatda  cmdcmd  --  --  ----------------  读取  IDread ID  tdatda  cmdcmd  --  --  ----------------  写配  置寄  存器Write configuration register  tdatda  cmdcmd  datadata  --  ----------------  写DN  条目Write DN entry  tdatda  cmdcmd  --  --  ----------------  重置Reset  tdatda  cmdcmd  --  --  ----------------

                    表2字节模式下的输入序列 Table 2 Input sequence in byte mode

在单字节的cmd码之后，将单字节TDA移位到设备中。最高有效位(MSB)从SIP开始并于串行时钟(SCLK)的上升沿锁存各个位。取决于命令，单字节命令码之后可跟随列地址字节、行地址字节、体地址字节，数据字节，和/或组合或空白。 After the single-byte cmd code, the single-byte TDA is shifted into the device. The most significant bit (MSB) starts with the SIP and latches each bit on the rising edge of the serial clock (SCLK). Depending on the command, the single byte command code may be followed by a column address byte, a row address byte, a bank address byte, a data byte, and/or a combination or blank. the

图8为描述与在串行菊花链级联排列中所配置的设备间传送的数据有关的时序的时序图。如上所述，确立CS#以选择设备。通过确立IPE以及在连续的SCLK的上升沿将时钟数据按时钟节拍送入设备，信息被输入到串行菊花链级联排列中的第一个设备。IPE在不到一个周期的时间内通过第一设备传播到第二设备。这使得信息在按时钟节拍进入第一设备后的一个周期内从第一设备的SO按时钟节拍进入第二设备的SI。这一过程在串行菊花链级联的连续设备中重复进行。因此，例如，在从数据在第一设备的锁存点算起的SCLK的第三个上升沿时，将信息输入到串行菊花链级联中的第三设备。 8 is a timing diagram depicting the timing associated with data transfer between devices configured in a serial daisy chain cascaded arrangement. As above, CS# is asserted to select the device. Information is input to the first device in a serial daisy-chain cascade arrangement by asserting IPE and clocking data into the device on successive rising edges of SCLK. The IPE propagates through the first device to the second device in less than one cycle. This allows information to be clocked from the SO of the first device into the SI of the second device within one cycle of clocking into the first device. This process is repeated in successive devices in a serial daisy chain cascade. So, for example, information is input to a third device in a serial daisy chain cascade on the third rising edge of SCLK counting from the point at which data is latched at the first device. the

图9为单端口设备中的示例性串行输出控制逻辑900的框图。逻辑900包括用于IPE的输入缓存器902、用于SI(SIP)的输入缓存器904、用于 OPE的输入缓存器906、输入锁存控制器908、串行至并行寄存器910、输出锁存控制器912、数据寄存器914、地址寄存器916、命令解释器918、选择器920、页缓存器924、逻辑或(OR)门926、输出缓存器928、选择器930以及存储器950。 FIG. 9 is a block diagram of exemplary serialoutput control logic 900 in a single port device.Logic 900 includesinput buffer 902 for IPE,input buffer 904 for SI (SIP),input buffer 906 for OPE,input latch controller 908, serial toparallel register 910,output latch Controller 912 , data register 914 ,address register 916 ,command interpreter 918 ,selector 920 ,page buffer 924 , logical OR (OR)gate 926 ,output buffer 928 ,selector 930 andmemory 950 . the

输入缓存器902是一种传统的低电压晶体管到晶体管逻辑(LVTTL)缓存器，它被配置成缓存馈送给设备位于缓存器902的输入端的IPE信号的状态。缓存器902的输出提供给输入锁存控制器908，它锁存IPE信号的状态并向输入缓存器904和选择器920提供IPE信号的锁存的状态。输入缓存器904是一种LVTTL缓存器，它被配置成缓存通过SI输入提供给设备的信息。输入缓存器904由输入锁存控制器908使能。当被使能时，提供给SI输入的信息由缓存器908传送到串行至并行寄存器910以及选择器930的一个输入。当由输入锁存控制器908所提供的IPE信号的锁存的状态显示IPE信号被确立时，输入缓存器904被使能。提供给串行至并行寄存器910的信息由寄存器910从串行形式转换为并行形式。串行至并行寄存器910的输出提供给数据寄存器914，地址寄存器916以及命令解释器918。 Theinput buffer 902 is a conventional low voltage transistor-to-transistor logic (LVTTL) buffer configured to buffer the state of the IPE signal fed to the device at the input of thebuffer 902 . The output ofbuffer 902 is provided to inputlatch controller 908 which latches the state of the IPE signal and provides the latched state of the IPE signal to inputbuffer 904 andselector 920 . Theinput buffer 904 is an LVTTL buffer configured to buffer information provided to the device through the SI input. Theinput buffer 904 is enabled by theinput latch controller 908 . When enabled, the information provided to the SI input is transferred by thebuffer 908 to the serial-to-parallel register 910 and one input of theselector 930 . Theinput buffer 904 is enabled when the status of the latch of the IPE signal provided by theinput latch controller 908 indicates that the IPE signal is asserted. Information provided to serial-to-parallel register 910 is converted byregister 910 from serial to parallel form. The output of serial-to-parallel register 910 is provided to data register 914 ,address register 916 andcommand interpreter 918 . the

数据寄存器914以及地址寄存器916分别保存通过SI提供给设备的数据以及地址信息。命令解释器918被配置成解释通过SI输入到设备的命令。这些命令用于进一步控制设备的操作。例如，“写存储器”命令可被用于令设备将包含于数据寄存器914的数据写入位于设备中经由地址寄存器916所指定地址的存储器950。 The data register 914 and theaddress register 916 respectively store the data and address information provided to the device through the SI. Thecommand interpreter 918 is configured to interpret commands input to the device through the SI. These commands are used to further control the operation of the device. For example, a "write memory" command may be used to cause the device to write the data contained in data register 914 tomemory 950 located in the device at an address specified viaaddress register 916 . the

输入缓存器906为LVTTL缓存器，它被配置成缓存提供给设备的OPE输入的OPE信号。缓存器906的输出被传送到用于锁存OPE信号的状态的输出锁存控制器912。输出锁存控制器输出锁存的OPE信号状态到或门926。或门926为传统的逻辑或门，其输出被用于使能/禁止输出缓存器928的输出。 Theinput buffer 906 is an LVTTL buffer configured to buffer the OPE signal provided to the OPE input of the device. The output ofbuffer 906 is passed tooutput latch controller 912 for latching the state of the OPE signal. The output latch controller outputs the latched OPE signal state to ORgate 926 . The ORgate 926 is a conventional logical OR gate, and its output is used to enable/disable the output of theoutput register 928 . the

选择器920为传统的2选1多路复用器，它通过信号DAISY_CHAIN从两个输入中选择其一作为输出。如前所述，这些输入之一为从输入锁存控制器908所得到的IPE信号的锁存状态。另一个输入被设定为逻辑低状态。信号DAISY_CHAIN显示设备是否以串行菊花链级联排列连接到一个或多个其它设备。示例性地，如果设备以串行菊花链级联排列连接到一个或多个其它设备，该信号被确立。确立DAISY_CHAIN信号使得提供给选 择器920的IPE信号的锁存状态从选择器920输出。当DAISY_CHAIN信号未被确立时，输入到选择器920的逻辑低状态从选择器920被输出。 Theselector 920 is a traditional 2-to-1 multiplexer, which selects one of the two inputs as an output through the signal DAISY_CHAIN. One of these inputs is the latch state of the IPE signal derived from theinput latch controller 908, as previously described. The other input is set to a logic low state. The signal DAISY_CHAIN indicates whether a device is connected to one or more other devices in a serial daisy-chain cascade arrangement. Illustratively, this signal is asserted if the device is connected to one or more other devices in a serial daisy-chain cascade arrangement. Asserting the DAISY_CHAIN signal causes the latch state of the IPE signal supplied to theselector 920 to be output from theselector 920. When the DAISY_CHAIN signal is not asserted, a logic low state input to theselector 920 is output from theselector 920 . the

页缓存器924为传统的数据缓存器，它被配置为保存从存储器950读得的信息。选择器930为传统的2选1多路复用器，通过信号ID_MATCH从两个输入中选择一个作为输出。选择器930的一个输入由页缓存器924的输出提供，另一个输入由SI输入缓存器904的输出提供。选择器930的输出提供给输出缓存器928。信号ID_MATCH指示通过SI传送到设备的特定命令是否寻址(addressed)到该设备。如果该命令寻址到设备，ID_MATCH被确立以使得页缓存器924的输出从选择器930输出。如果ID_MATCH未被确立，则从SI缓存器904得到的输出(即，输入到设备的SI信号的状态)从选择器930输出。 Page buffer 924 is a conventional data buffer configured to hold information read frommemory 950 . Theselector 930 is a traditional 2-to-1 multiplexer, which selects one of the two inputs as an output through the signal ID_MATCH. One input ofselector 930 is provided by the output ofpage buffer 924 and the other input is provided by the output ofSI input buffer 904 . The output of theselector 930 is provided to theoutput buffer 928 . The signal ID_MATCH indicates whether a particular command transmitted to a device via SI is addressed to that device. If the command addresses a device, ID_MATCH is asserted so that the output ofpage buffer 924 is output fromselector 930 . If ID_MATCH is not asserted, the output from the SI buffer 904 (ie, the state of the SI signal input to the device) is output from theselector 930 . the

存储器950为传统的寄存器，它被配置成保存数据。存储器950可以是包含多个单元的随机存取存储器(RAM)，如静态RAM(SRAM)，动态RAM(DRAM)或闪存单元，其可使用通过SI输入到设备的地址进行寻址。 Memory 950 is a conventional register configured to hold data.Memory 950 may be random access memory (RAM) comprising multiple cells, such as static RAM (SRAM), dynamic RAM (DRAM), or flash memory cells, which are addressable using addresses entered into the device via SI. the

在操作时方面，一个确立的IPE信号由输入缓存器902进行缓存并被传送到输入锁存控制器908，该控制器锁存所确立的IPE的状态。这一锁存状态提供给选择器920以及输入缓存器904，以使能该缓存器904。输入至输入缓存器904的命令、地址以及数据信息然后被传送到用于将信息从串行形式转换到并行形式的串行至并行寄存器910，并分别将命令、地址以及数据信息提供给命令解释器918、地址寄存器916和数据寄存器914。缓存器904的输出也被提供给选择器930。如果ID_MATCH未被确立，缓存器904的输出会出现在选择器930的输出，该输出被提供给输出缓存器928的输入。如果DAISY_CHAIN被确立，IPE的锁存状态会出现在选择器920的输出，并提供给或门926的第一输入。或门926传递IPE的状态到输出缓存器928以使能输出缓存器928。这又将允许输入到SI输入端的信息从设备的SO输出。 In operation, an asserted IPE signal is buffered by theinput buffer 902 and sent to theinput latch controller 908, which latches the state of the asserted IPE. This latched state is provided to theselector 920 and theinput register 904 to enable theregister 904 . The command, address, and data information input to theinput buffer 904 is then transferred to the serial-to-parallel register 910, which converts the information from serial to parallel form, and provides the command, address, and data information, respectively, to thecommand interpreter register 918,address register 916 and data register 914. The output ofbuffer 904 is also provided toselector 930 . If ID_MATCH is not asserted, the output ofbuffer 904 appears at the output ofselector 930 , which is provided to the input ofoutput buffer 928 . If DAISY_CHAIN is asserted, the latched state of IPE appears at the output ofselector 920 and is provided to the first input of ORgate 926 . The ORgate 926 passes the state of the IPE to theoutput register 928 to enable theoutput register 928 . This in turn will allow information input to the SI input to be output from the SO of the device. the

通过确立OPE以及ID_MATCH，将来自页缓存器924的数据从设备输出。详细的说，所确立的OPE的状态提供给输入缓存器906，该缓存器又提供该状态到用于锁存该状态的输出锁存控制器912。锁存的所确立的状态被提供给或门926的第二输入，或门926输出信号以使能输出缓存器928。确立ID_MATCH使能页缓存器924的输出出现在选择器930的输出。选择器930的输出被提供给所使能的输出缓存器928，该缓存器从设备的SO输出端将数据输出该设备。 By asserting OPE and ID_MATCH, data from thepage buffer 924 is output from the device. In detail, the asserted state of the OPE is provided to theinput buffer 906, which in turn provides the state to theoutput latch controller 912 for latching the state. The asserted state of the latch is provided to a second input of ORgate 926 , which outputs a signal to enableoutput buffer 928 . Asserting ID_MATCH enables the output ofpage buffer 924 to appear at the output ofselector 930 . The output ofselector 930 is provided to enabledoutput buffer 928, which outputs data from the device's SO output to the device. the

注意，如果DAISY_CHAIN未被确立，输出缓存器928仅被OPE使能。这将允许该设备在非菊花链串行级联结构中使用。 Note thatoutput buffer 928 is only enabled by OPE if DAISY_CHAIN is not asserted. This will allow the device to be used in non-daisy-chained serial cascade configurations. the

图10为双端口设备中的示例性串行输出控制逻辑1000的框图。对于每个端口，该串行输出控制逻辑1000包括IPE输入缓存器1002、SI输入缓存器1004、OPE输入缓存器1006、输入锁存控制器1008、串行到并行寄存器1010、输出锁存控制器1012、数据寄存器1014、地址寄存器1016、命令解释器1018、选择器1020、页缓存器1024、逻辑或门1026、输出缓存器1028和选择器1030，它们分别与上述的IPE输入缓存器902、SIP输入缓存器904、OPE输入缓存器906、输入锁存控制器908、串行至并行寄存器910、输出锁存控制器912、数据寄存器914、地址寄存器916、命令解释器918、选择器920、页缓存器924、逻辑或门926、输出缓存器928和选择器930相同。 FIG. 10 is a block diagram of exemplary serial output control logic 1000 in a dual port device. For each port, the serial output control logic 1000 includes IPE input buffer 1002, SI input buffer 1004, OPE input buffer 1006, input latch controller 1008, serial to parallel register 1010, output latch controller 1012, data register 1014, address register 1016, command interpreter 1018, selector 1020, page buffer 1024, logical OR gate 1026, output buffer 1028 and selector 1030, which are respectively connected with the above-mentionedIPE input buffer 902,SIP Input buffer 904,OPE input buffer 906,input latch controller 908, serial toparallel register 910,output latch controller 912, data register 914,address register 916,command interpreter 918,selector 920, page Theregister 924, the logic ORgate 926, theoutput register 928 and theselector 930 are the same. the

图11为与此处所描述的技术一同使用的串行输出控制逻辑1100的另一个实施例的详细框图。逻辑1100包括SI输入缓存器1104、IPE输入缓存器1106、OPE输入缓存器1108、SCLK输入缓存器1110、逻辑与(AND)门1112和1114、锁存器1116、1118、1120和1122、选择器1124和1130、逻辑或门1126和SO输出缓存器1128。缓存器1104、1106、1108和1110为传统的LVTTL缓存器，分别配置为缓存被输入到设备中的SI、IPE、OPE和SCLK信号。 FIG. 11 is a detailed block diagram of another embodiment of serialoutput control logic 1100 for use with the techniques described herein.Logic 1100 includesSI input buffer 1104,IPE input buffer 1106,OPE input buffer 1108,SCLK input buffer 1110, logic AND (AND)gates 1112 and 1114, latches 1116, 1118, 1120 and 1122,selector 1124 and 1130 , logic ORgate 1126 and SOoutput buffer 1128 . Thebuffers 1104, 1106, 1108 and 1110 are conventional LVTTL buffers, respectively configured to buffer the SI, IPE, OPE and SCLK signals input into the device. the

与门1112被配置为当IPE被确立时，将输入到SI的信息输出到锁存器1116。锁存器1116被配置为当缓存器1110提供时钟信号(SCLK)时，锁存该信息。DATA_OUT表示从包含在设备内存储器(未示出)所读取的数据的状态。与门1114被配置为当OPE被确立时，输出DATA_OUT的状态。与门1114的输出提供给锁存器1118，所述的锁存器1118被配置为当缓存器1110提供时钟信号时锁存DATA_OUT的状态。缓存器1106被配置为缓存提供给设备的IPE信号。缓存器1106的输出被锁存器1120锁存。类似的，缓存器1108被配置为缓存提供给设备的OPE信号。锁存器1122被配置为锁存由缓存器1108所输出的OPE的状态。选择器1124和1130为传统的2选1多路复用器，各包含两个输入。选择器1124的输入通过上述的ID_MATCH信号被选择从选择器1124作为输出。一个输入被 提供由锁存器1118所维持的DATA_OUT的锁存状态。当ID_MATCH被确立时，这一输入被选择从选择器1124输出。另一输入被提供由锁存器1116所维持的SI的锁存状态。当ID_MATCH未被确立时，这一输入被选择从选择器1124输出。 ANDgate 1112 is configured to output information input to SI to latch 1116 when IPE is asserted. Thelatch 1116 is configured to latch the information when thebuffer 1110 provides a clock signal (SCLK). DATA_OUT represents the status of data read from memory (not shown) contained in the device. The ANDgate 1114 is configured to output the state of DATA_OUT when OPE is asserted. The output of the ANDgate 1114 is provided to alatch 1118 configured to latch the state of DATA_OUT when thebuffer 1110 provides a clock signal.Buffer 1106 is configured to buffer IPE signals provided to the device. The output ofbuffer 1106 is latched by latch 1120 . Similarly, thebuffer 1108 is configured to buffer the OPE signal provided to the device. Thelatch 1122 is configured to latch the state of the OPE output by thebuffer 1108 .Selectors 1124 and 1130 are conventional 2-to-1 multiplexers, each containing two inputs. The input of theselector 1124 is selected as an output from theselector 1124 by the above-mentioned ID_MATCH signal. One input is provided the latched state of DATA_OUT maintained bylatch 1118. This input is selected for output fromselector 1124 when ID_MATCH is asserted. Another input is provided the latched state of SI maintained bylatch 1116 . This input is selected for output fromselector 1124 when ID_MATCH is not asserted. the

选择器1130的输入通过上述的DAISY_CHAIN信号被选择从选择器1130输出。选择器1130的一个输入被提供由锁存器1120所维持的IPE的锁存状态，而另一个输入连接到逻辑0。当DAISY_CHAIN被确立时，IPE的锁存状态被选择作为选择器1130的输出。类似的，当DAISY_CHAIN未被确立时，逻辑0被选择从选择器1130的输出。 The input of theselector 1130 is selected and output from theselector 1130 by the above-mentioned DAISY_CHAIN signal. One input ofselector 1130 is provided with the latched state of the IPE maintained by latch 1120, while the other input is connected to logic zero. When DAISY_CHAIN is asserted, the latched state of the IPE is selected as the output of theselector 1130 . Similarly,logic 0 is selected from the output ofselector 1130 when DAISY_CHAIN is not asserted. the

或门1126为传统的逻辑或门，它被配置为向输出缓存器1128提供使能/禁止信号。或门1126被提供选择器1130的输出，以及由锁存器1122所维持的OPE的锁存状态。这两个输出的任一个可被用于向缓存器1128提供时能信号以使能该缓存器的输出。缓存器1128为传统的缓存器，它用来缓存输出信号SO。如上所述，缓存器1128通过或门1126的输出被使能/禁止。 TheOR gate 1126 is a conventional logical OR gate configured to provide an enable/disable signal to theoutput buffer 1128 . ORgate 1126 is provided with the output ofselector 1130 and the latched state of OPE maintained bylatch 1122 . Either of these two outputs may be used to provide an enable signal to buffer 1128 to enable the output of the buffer. Thebuffer 1128 is a conventional buffer, which is used to buffer the output signal SO. Thebuffer 1128 is enabled/disabled through the output of theOR gate 1126 as described above. the

在操作方面，当IPE被确立时，通过SI被输入到设备的信息被提供给锁存器1116。示例性地，锁存器1116在IPE被确立后的SCLK的第一向上转变时锁存该信息。类似的，锁存器1120在这次SCLK转变时锁存IPE的状态。假设ID_MATCH未被确立，锁存器1116的输出通过选择器1124被提供给缓存器1128。类似的，确立的IPE从缓存器1106被传送到锁存器1120，在锁存器1120中也示例性地在SCLK的第一向上转变时进行锁存。假设DAISY_CHAIN被确立时，IPE的锁存状态被提供到选择器1130的输出，并被传送到或门1126以向缓存器1128提供使能信号。接着，SI的锁存状态通过缓存器1128从设备传出作为输出SO。 In terms of operation, when IPE is asserted, information that is input to the device via SI is provided to latch 1116 . Illustratively,latch 1116 latches this information on the first upward transition of SCLK after IPE is asserted. Similarly, latch 1120 latches the state of IPE at this SCLK transition. Assuming ID_MATCH is not asserted, the output oflatch 1116 is provided to buffer 1128 throughselector 1124 . Similarly, asserted IPE is transferred frombuffer 1106 to latch 1120 where it is also latched, illustratively on the first up transition of SCLK. Assuming DAISY_CHAIN is asserted, the latched state of the IPE is provided to the output ofselector 1130 and sent toOR gate 1126 to provide an enable signal to buffer 1128 . Next, the latched state of SI is output from the device throughbuffer 1128 as output SO. the

当DAISY_CHAIN未被确立时，选择输入到选择器1130的逻辑0，从选择器1130输出逻辑0。这有效地禁止了IPE使能缓存器1128。 When DAISY_CHAIN is not asserted,logic 0 input toselector 1130 is selected, andlogic 0 is output fromselector 1130 . This effectively disables the IPE enableregister 1128. the

示例性地，在OPE被确立后的SCLK的下一个向上转变时，OPE的所确立的状态被锁存在锁存器1122，以及DATA_OUT的状态被锁存在锁存器1118。假设ID_MATCH被确立，DATA_OUT的锁存状态被选择器1124选择并被加到缓存器1128的输入。同时，从锁存器1122得到的OPE的锁存的所确立的状态通过或门1126传送到使能缓存器1128，这使得DATA_OUT的锁存状态从设备输出作为输出SO。 Illustratively, on the next up transition of SCLK after OPE is asserted, the asserted state of OPE is latched inlatch 1122 and the state of DATA_OUT is latched inlatch 1118 . Assuming ID_MATCH is asserted, the latch state of DATA_OUT is selected byselector 1124 and added to the input ofregister 1128 . Simultaneously, the latched asserted state of OPE obtained fromlatch 1122 is transferred to enablebuffer 1128 through ORgate 1126, which causes the latched state of DATA_OUT to be output from the device as output SO. the

图12为以串行菊花链级联排列配置以及包括示例性的串行输出控制逻辑的设备的示例性结构框图。该排列包括三个设备1210，其如前所述被配置成菊花链级联中的一个在先设备的输出端与菊花链级联中的下一个设备的输入端相耦合。信息和数据从一个设备到下一个设备的传送过程参考下面的图13进行描述。 12 is an exemplary block diagram of a device configured in a serial daisy-chain cascade arrangement and including exemplary serial output control logic. The arrangement includes three devices 1210 configured as previously described such that the output of a previous device in the daisy-chain cascade is coupled to the input of the next device in the daisy-chain cascade. The transfer of information and data from one device to the next is described with reference to Figure 13 below. the

图13为用于说明在图12中所描述设备的输入和输出相关时序的示例性时序图。具体来说，关于将在每个设备1210的SI输入端所输入的信息传送到设备1210的SO输出端，该图描述了各设备中的串行输出控制逻辑1100的操作。 FIG. 13 is an exemplary timing diagram for explaining input and output related timing of the device described in FIG. 12 . Specifically, the figure depicts the operation of the serialoutput control logic 1100 in each device with respect to passing information input at the SI input of each device 1210 to the SO output of the device 1210 . the

参考图11、12和13，假设DAISY_CHAIN被确立。当在设备1210a确立IPE时，如前所述在设备SI输入端的数据通过设备的串行输出控制逻辑1100传送到设备1210a的SO输出端。详细的，在IPE被确立后的每个SCLK上升沿，数据被示例性地按时钟节拍输入进设备1210a中。如前所述IPE的信息和状态通过逻辑1100传播，并分别在设备的SO和IPEQ输出端离开设备1210a。这些输出在图中分别用S1和P1表示。如前所述，这些输出被提供给设备1210b的SI和IPE输入，通过设备1210b的串行输出控制逻辑1100，并在一个时钟周期后自设备1210b的SO和IPEQ输出端从设备1210b输出。这些输出在图中分别用S2和P2表示。类似的，设备1210b的SO和IPEQ输出分别被提供给设备1210c的SI和IPE输入，通过设备1210c的串行输出控制逻辑1100，并在一个时钟周期后分别从设备的SO和IPEQ输出端从设备1210c输出。这些输出在图中分别用S3和P3表示。 Referring to Figures 11, 12 and 13, it is assumed that DAISY_CHAIN is established. When IPE is asserted atdevice 1210a, the data at the SI input ofdevice 1210a is passed through the device's serialoutput control logic 1100 to the SO output ofdevice 1210a as previously described. In detail, at each rising edge of SCLK after IPE is asserted, data is exemplarily input into thedevice 1210a in clock ticks. The information and status of the IPE propagates through thelogic 1100 as previously described and exits thedevice 1210a at the device's SO and IPEQ outputs, respectively. These outputs are denoted S1 and P1 respectively in the figure. As before, these outputs are provided to the SI and IPE inputs of device 1210b,control logic 1100 through the serial output of device 1210b, and output from device 1210b one clock cycle later from the SO and IPEQ outputs of device 1210b. These outputs are denoted S2 and P2 respectively in the figure. Similarly, the SO and IPEQ outputs of device 1210b are provided to the SI and IPE inputs of device 1210c respectively,control logic 1100 through the serial output of device 1210c, and are slaved to the SO and IPEQ outputs of device 1210c, respectively, one clock cycle later. 1210c output. These outputs are denoted S3 and P3 respectively in the figure. the

在如上所述的菊花链级联排列中，对于SDR操作在菊花链级联中的信号输出延迟时间(latency)可以采用下面的公式确定： In the above-mentioned daisy-chain cascade arrangement, the signal output delay time (latency) of the SDR operation in the daisy-chain cascade can be determined by the following formula:

             output_latency＝N*clock_cycle_time      output_latency＝N*clock_cycle_time 

其中： in:

“output_latency”是数据的输出延迟时间， "output_latency" is the output delay time of the data,

“N”是菊花链级联排列中的设备的数量，以及 "N" is the number of devices in the daisy-chain cascaded arrangement, and

“clock_cycle_time”是时钟操作的时钟周期时间。 "clock_cycle_time" is the clock cycle time of the clock operation. the

例如，假设图12中所描述的菊花链级联的clock_cycle_time为10纳秒。对于在设备1210c中的SO的数据，总输出延迟时间为3*10纳秒或30纳秒。 For example, assume that the clock_cycle_time of the daisy-chain cascade depicted in Figure 12 is 10 nanoseconds. For the data of the SO in device 1210c, the total output delay time is 3*10 ns or 30 ns. the

在DDR操作的例子中，输出延迟时间可以通过如下方式决定： In the example of DDR operation, the output delay time can be determined as follows:

          output_latency＝N*(clock_cycle_time/2)    output_latency＝N*(clock_cycle_time/2) 

在DDR操作中，时钟的两沿都可作为输入数据的锁存点和输出数据的改变点。因此，总的延迟时间是SDR操作中延迟时间的一半。 In DDR operation, both edges of the clock can be used as the latch point of input data and the change point of output data. Therefore, the total delay time is half of the delay time in SDR operation. the

注意，在上述的说明中，对于SDR操作输入到设备1210中的信息在一个时钟周期后输出，对于DDR操作在半个周期后输出。引入此类延迟以提供启动输出缓存器1128所需的时间。 Note that in the above description, the information input into the device 1210 is output after one clock cycle for SDR operation, and after half a cycle for DDR operation. Such a delay is introduced to provide the time required for theoutput buffer 1128 to start. the

图14为用于将菊花链级联中的第一设备1450a的存储器所存储的数据传送到菊花链级联中的第二设备1450b的逻辑1400的框图。逻辑1400包括数据输出寄存器1402，OPE输入缓存器1404，SCLK输入缓存器1406，与门1408，数据输出锁存器1410，OPE状态锁存器1412，选择器1414，SO输出缓存器1416以及OPEQ输出缓存器1418。 14 is a block diagram oflogic 1400 for transferring data stored in the memory of afirst device 1450a in a daisy-chain cascade to asecond device 1450b in the daisy-chain cascade.Logic 1400 includesdata output register 1402,OPE input buffer 1404,SCLK input buffer 1406, ANDgate 1408,data output latch 1410, OPE status latch 1412,selector 1414, SOoutput buffer 1416 andOPEQ output Buffer 1418 . the

数据输出寄存器1402为传统的寄存器，它被配置为存储自包含于设备1450中的存储器所读取的数据。寄存器1402示例性地为并行至串行数据寄存器，它以并行方式从存储器加载数据并将数据串行传输到门1408的输入端。SCLK提供了寄存器1402用来传送数据到门1408时所采用的时钟信号。如所示，数据寄存器1402被配置为保存包括位D0到D7的字节数据，其中D0为字节中的最低有效位(LSB)，而位D7为字节中的最高有效位(MSB)。寄存器1402以并行方式从存储器加载一字节宽度的数据。该数据从最高有效位开始从寄存器移出并以串行方式逐位地提供给门1408的输入。 Data output registers 1402 are conventional registers configured to store data read from memory contained in device 1450 .Register 1402 is illustratively a parallel-to-serial data register that loads data from memory in parallel and transfers the data serially to the input ofgate 1408 . SCLK provides the clock signal that register 1402 uses to transfer data togate 1408 . As shown, data register 1402 is configured to hold byte data including bits D0 through D7, where D0 is the least significant bit (LSB) in the byte and bit D7 is the most significant bit (MSB) in the byte.Registers 1402 are loaded with one byte wide data from memory in parallel. The data is shifted out of the registers starting with the most significant bit and provided to the input ofgate 1408 bit by bit in a serial fashion. the

缓存器1404和1406为传统的LVTTL缓存器，分别用于缓存输入信号OPE和SCLK。OPE信号从缓存器1404的输出(OPEI)传送到门1408。将SCLK信号从缓存器1406的输出传送到数据输出寄存器1402，以及锁存器1410和1412，以向这些组件提供时钟。 Theregisters 1404 and 1406 are conventional LVTTL registers, which are respectively used to buffer the input signals OPE and SCLK. The OPE signal is passed from the output (OPEI) ofbuffer 1404 togate 1408 . The SCLK signal is passed from the output ofbuffer 1406 todata output register 1402, and latches 1410 and 1412 to clock these components. the

门1408为传统的逻辑与门，它被配置为当OPE被确立时传送数据输出寄存器1402的输出(DATA_OUT)到锁存器1410。门1408的输出被表示为“DBIT”。锁存器1410和1412为传统的锁存器，它被配置为分别锁存DBIT和OPE信号的状态。选择器1414为传统的2选1多路复用器，它由信号ID_MATCH控制。其中一个数据输入为DBIT的锁存状态。当ID_MATCH被确立时，这一状态从选择器1414输出。另一输入为通过设备1450a的SI传输到该设备的串行数据(SI0)。当ID_MATCH未被确立 时，这一信息从选择器1414中输出。 Gate 1408 is a conventional logic AND gate configured to transfer the output (DATA_OUT) ofdata output register 1402 to latch 1410 when OPE is asserted. The output ofgate 1408 is denoted "DBIT".Latches 1410 and 1412 are conventional latches configured to latch the states of the DBIT and OPE signals, respectively. Theselector 1414 is a traditional 2-to-1 multiplexer, which is controlled by the signal ID_MATCH. One of the data inputs is the latch state of DBIT. This status is output fromselector 1414 when ID_MATCH is asserted. The other input is the serial data (SI0) transmitted to the device via the SI ofdevice 1450a. This information is output fromselector 1414 when ID_MATCH is not asserted. the

缓存器1416和1418为传统的缓存器，它们被配置为分别缓存选择器1414和锁存器1406的输出。缓存器1416的输出作为SO(SO0)离开设备1450a以及缓存器1418的输出作为OPEQ(OPEQ0)离开设备1450a。 Buffers 1416 and 1418 are conventional buffers configured to buffer the outputs ofselector 1414 andlatch 1406, respectively. The output ofbuffer 1416 leavesdevice 1450a as SO (SO0) and the output ofbuffer 1418 leavesdevice 1450a as OPEQ (OPEQ0). the

图15为与采用逻辑1400将一字节宽度的数据从包含在设备1450a的存储器传送到设备1450b的示例性时序相关的时序图。参考图14和15，在OPE于输入缓存器1404提供给设备1450a后不久，OPEI被确立。OPEI被提供给门1408以使能当前位于数据输出寄存器1402的D7的数据在SCLK的下一个上升沿在锁存器1410中被锁存。此外，该SCLK的下一个上升沿令数据右移进数据输出寄存器，以使得D6的数据移动到D7，D5的数据移动到D6，依此类推。锁存器1410的输出出现在选择器1414，假设ID_MATCH被确立，选择器1414输出数据的锁存状态到缓存器1416。缓存器1416将这一锁存状态作为SO0从设备1450a输出，SO0被提供给菊花链级联中的下一个设备的SI输入(SI1)。同时，同样在OPE被确立后的第一时钟的上升沿，OPE的状态在锁存器1412中被锁存。锁存器1412的输出被传送到缓存器1418，该缓存器将OPE的锁存状态作为OPEQ(OPEQ0)从设备1450a输出，该OPEQ被提供给菊花链级联中的下一个设备1450b的OPE输入(OPE1)。对比特位D6到D0重复上述过程。 15 is a timing diagram related to an exemplary timing of transferring one byte wide data from memory contained indevice 1450a todevice1450b using logic 1400 . 14 and 15, OPEI is asserted shortly after OPE is provided todevice 1450a ininput buffer 1404. OPEI is provided togate 1408 to enable the data currently at D7 ofdata output register 1402 to be latched inlatch 1410 on the next rising edge of SCLK. In addition, the next rising edge of this SCLK shifts data right into the data output register, so that data from D6 is shifted to D7, data from D5 is shifted to D6, and so on. The output of thelatch 1410 appears at theselector 1414 , and assuming ID_MATCH is asserted, theselector 1414 outputs the latch state of the data to thebuffer 1416 .Buffer 1416 outputs this latched state as SO0 fromdevice 1450a, which is provided to the SI input (SI1) of the next device in the daisy-chain cascade. At the same time, also at the rising edge of the first clock after OPE is asserted, the state of OPE is latched in the latch 1412 . The output of latch 1412 is passed to buffer 1418, which outputs the latched state of the OPE as an OPEQ (OPEQ0) fromdevice 1450a, which is provided to the OPE input of the next device in the daisy-chain cascade, 1450b (OPE1). Repeat the above process for bits D6 to D0. the

虽然已经参照本发明的较佳实施例特别显示与描述本发明，但本领域的技术人员应当了解到在形式与细节上可以进行的各种变化，而不脱离所附权利要求所要保护的范围。 While the invention has been particularly shown and described with reference to preferred embodiments thereof, those skilled in the art will recognize that various changes may be made in form and detail without departing from the scope of the appended claims. the

Claims (28)

Translated fromChinese

1.一种具有多个串行连接设备的装置，至少包括第一和第二设备，1. An apparatus having a plurality of serially connected devices, comprising at least a first and a second device,第一设备具有：The first device has:存储器；memory;第一输入，被配置为接收数据；以及a first input configured to receive data; and第一输出，被配置为输出在所述第一设备的所述第一输入中输入的数据或包括在所述存储器中的数据；a first output configured to output data input in said first input of said first device or data included in said memory;第一控制输入，被配置为接收第一输入使能信号使能所述第一设备的所述第一输入以输入数据；以及a first control input configured to receive a first input enable signal to enable said first input of said first device to input data; and第二控制输入，被配置为接收第一输出使能信号使能所述第一设备的所述第一输入上的数据输入或者包括在所述存储器中的数据在所述第一设备的所述第一输出上输出，A second control input configured to receive a first output enable signal to enable input of data on said first input of said first device or data included in said memory on said first input of said first device output on the first output,所述第二设备具有：The second device has:第一输入，被配置为输入从所述第一设备所输出数据。The first input is configured to input data output from the first device.2.根据权利要求1所述的装置，其特征在于，2. The device according to claim 1, characterized in that,所述第一输入被配置为接收与存储器中存储位置相关的地址信息；以及the first input is configured to receive address information associated with a storage location in memory; and所述第一输出被配置为输出包含在存储位置中的数据。The first output is configured to output data contained in a storage location.3.根据权利要求1或2所述的装置，其特征在于，数据与时钟信号同步地从第一设备的第一输出被传输到第二设备的第一输入。3. The arrangement as claimed in claim 1 or 2, characterized in that data is transferred from the first output of the first device to the first input of the second device synchronously with the clock signal.4.根据权利要求3所述的装置，其特征在于，响应时钟信号边沿执行数据传送的同步。4. The apparatus of claim 3, wherein the synchronization of the data transfer is performed in response to a clock signal edge.5.根据权利要求4所述的装置，其特征在于，所述的时钟信号边沿包括时钟周期的上升沿和下降沿中的任意一个或全部。5 . The device according to claim 4 , wherein the clock signal edge includes any one or all of a rising edge and a falling edge of a clock cycle.6.根据权利要求1所述的装置，其特征在于，由第二设备的第一输入接收的数据包括设备地址信息，所述的设备地址信息与第二设备相关。6. The apparatus of claim 1, wherein the data received by the first input of the second device includes device address information, the device address information being associated with the second device.7.根据权利要求6所述的装置，其特征在于，所述由第二设备的第一输入接收的数据还包括命令和数据信息。7. The apparatus of claim 6, wherein the data received by the first input of the second device further comprises command and data information.8.根据权利要求1所述的装置，其特征在于，所述的第一设备还包括：8. The apparatus according to claim 1, wherein said first device further comprises:被配置为输出第二输入使能信号的第一控制输出。A first control output configured to output a second input enable signal.9.根据权利要求8所述的装置，其特征在于，所述的第一设备还包括：9. The apparatus according to claim 8, wherein said first device further comprises:被配置为输出第二输出使能信号的第二控制输出。A second control output configured to output a second output enable signal.10.根据权利要求8所述的装置，其特征在于，所述的第一设备的第二输入使能信号源于所述第一设备的第一输入使能信号。10. The apparatus according to claim 8, wherein the second input enable signal of the first device is derived from the first input enable signal of the first device.11.根据权利要求8-10之一所述的装置，其特征在于，所述的第二设备还包括第一控制输入，被配置为从第一设备输入第二输入使能信号。11. The apparatus according to any one of claims 8-10, wherein the second device further comprises a first control input configured to input a second input enabling signal from the first device.12.根据权利要求1所述的装置，其特征在于，所述的第一设备还包括：12. The apparatus according to claim 1, wherein said first device further comprises:第二输出，被配置为从第一设备输出第二输出使能信号。The second output is configured to output a second output enable signal from the first device.13.根据权利要求12所述的装置，其特征在于，所述的第二设备还包括与第一设备的第二输出相耦合的第二输入，被配置为从第一设备接收第二输出使能信号。13. The apparatus of claim 12, wherein the second device further comprises a second input coupled to the second output of the first device, configured to receive the second output from the first device so that can signal.14.根据权利要求1所述的装置，其特征在于，所述的第一设备和第二设备各自还包括被配置为接收时钟信号的时钟输入，以同步所述数据从第一设备的第一输出向第二设备的第一输入的传送。14. The apparatus of claim 1, wherein each of the first device and the second device further comprises a clock input configured to receive a clock signal to synchronize the data from the first device to the first device of the first device. A transfer of the output to the first input of the second device.15.根据权利要求1所述的装置，其特征在于，所述的第一设备和第二设备各自还被配置为在时钟输入接收公共时钟信号。15. The apparatus according to claim 1, wherein each of the first device and the second device is further configured to receive a common clock signal at a clock input.16.根据权利要求1所述的装置，其特征在于，所述的第一设备还包括与第二设备的时钟输入相耦合的时钟输出，被配置为从第一设备向第二设备传送时钟信号。16. The apparatus of claim 1, wherein the first device further comprises a clock output coupled to a clock input of the second device, configured to transmit a clock signal from the first device to the second device .17.根据权利要求1所述的装置，其特征在于，所述的输入数据包括串行输入数据，第一设备和第二设备各自被配置为：17. The apparatus of claim 1, wherein the input data comprises serial input data, and the first device and the second device are each configured to:将串行输入数据转换成并行数据，并将并行数据传送到存储器；或convert serial input data to parallel data and transfer the parallel data to memory; or将来自存储器的并行数据转换成串行输出数据。Converts parallel data from memory to serial output data.18.根据权利要求14所述的装置，其特征在于，所述的第一设备还包括：18. The apparatus according to claim 14, wherein said first device further comprises:被配置为响应时钟信号闭锁所接收到数据的数据闭锁电路；以及a data blocking circuit configured to block received data in response to a clock signal; and被配置为在数据闭锁电路中的闭锁数据和来自存储器的数据中选择一个的选择电路，所选择的一个被传送到第二设备。A selection circuit configured to select one of the latch data in the data latch circuit and the data from the memory, the selected one is transmitted to the second device.19.根据权利要求1所述的装置，其特征在于，所述的存储器包括非易失性的存储器。19. The device according to claim 1, wherein the memory comprises a non-volatile memory.20.根据权利要求19所述的装置，其特征在于，所述的非易失性的存储器包括闪存器。20. The device according to claim 19, wherein the non-volatile memory comprises a flash memory.21.一种在至少包含有第一设备和第二设备的多个串行连接设备中访问存储器的方法，该方法包括：21. A method of accessing memory in a plurality of serially connected devices comprising at least a first device and a second device, the method comprising:向第一设备的第一输入输入包括地址信息的输入数据，该地址信息与包含在第一设备中的存储器的存储位置相关；a first input to the first device inputs input data comprising address information associated with a storage location of a memory contained in the first device;向第一设备的第一控制输入输入第一输入使能信号，使能输入数据被输入到第一设备的第一输入；inputting a first input enable signal to a first control input of the first device, enabling input data to be input to the first input of the first device;访问包含于第一设备的存储器中在所述存储位置的数据；accessing data contained in the memory of the first device at the memory location;向第一设备的第二控制输入输入第一输出使能信号，使能所访问的数据从第一设备输出；inputting a first output enable signal to a second control input of the first device, enabling the accessed data to be output from the first device;从第一设备的第一输出输出所访问的数据以及Outputting the accessed data from the first output of the first device and向第二设备的第一输入输入由第一设备输出的所访问的数据，以将所访问的数据从第一设备传送到第二设备。The accessed data output by the first device is input to a first input of the second device to transfer the accessed data from the first device to the second device.22.根据权利要求21所述的方法，其特征在于，还包括：向第一设备和第二设备的时钟输入输入时钟信号，以同步所访问的数据从第一设备的第一输出向第二设备的第一输入的传送。22. The method according to claim 21, further comprising: inputting a clock signal to the clock inputs of the first device and the second device to synchronize the accessed data from the first output of the first device to the second Transmission of the first input of the device.23.根据权利要求22所述的方法，其特征在于，还包括：从第一设备的时钟输出向第二设备的时钟输入传输由第一设备所接收的时钟信号。23. The method of claim 22, further comprising: transmitting the clock signal received by the first device from the clock output of the first device to the clock input of the second device.24.根据权利要求21所述的方法，其特征在于，还包括：24. The method of claim 21, further comprising:从第一设备的第一控制输出输出第二输入使能信号；以及outputting a second input enable signal from the first control output of the first device; and向第二设备的第一控制输入输入第一输入使能信号，使能所访问的数据从第一设备的第一输出传送到第二设备的第一输入。Inputting a first input enable signal to the first control input of the second device enables transfer of the accessed data from the first output of the first device to the first input of the second device.25.根据权利要求24所述的方法，其特征在于，所述第一设备的第二输入使能信号源于所述第一设备的第一输入使能信号。25. The method of claim 24, wherein the second input enable signal of the first device is derived from the first input enable signal of the first device.26.根据权利要求21所述的方法，其特征在于，还包括：26. The method of claim 21, further comprising:从第一设备的第一控制输出输出第二输出使能信号；以及outputting a second output enable signal from the first control output of the first device; and向第二设备的第二控制输入输入第二输出使能信号，使能第二设备的第一输出输出来自第一设备的所访问的数据。A second output enable signal is input to the second control input of the second device, enabling the first output of the second device to output the accessed data from the first device.27.根据权利要求26所述的方法，其特征在于，所述第一设备的第二输出使能信号源于所述第一设备的第一输出使能信号。27. The method of claim 26, wherein the second output enable signal of the first device is derived from the first output enable signal of the first device.28.根据权利要求22或权利要求23所述的方法，其特征在于，响应时钟信号边沿执行数据传输的同步。28. A method as claimed in claim 22 or claim 23, characterized in that the synchronization of the data transmission is performed in response to a clock signal edge.

Images