CN101246438A

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Info

Publication number: CN101246438A
Application number: CNA2008100077328A
Authority: CN
Inventors: 尹旭全
Original assignee: ZTE Corp
Current assignee: ZTE Corp
Priority date: 2008-03-07
Filing date: 2008-03-07
Publication date: 2008-08-20

Abstract

The invention discloses a disposal for process and interruption in a SMP system. The method adapts separation interrupt handling and process handling on processor grade, processes specially the interruption by using one or a group processors, furthermore, monitors the process and the interruption handling, and dynamic adjusts the number of processors in two group processors according to the load index of the process and the interruption handling. The invention also discloses a handling device for process and interruption in a SMP system. The device comprises interrupted handling module, a process processing module, a process and interruption monitor module. The device ensures the process handling and interruption handling mutual noninterference to improve the hit rate of cache and to ensure the stabilizing ability and actual time character of the system.

Description

Method and device for processing processes and interrupts in symmetric multiprocessing system

Technical Field

The present invention relates to the field of symmetric multiprocessor systems, and in particular, to a method and apparatus for processing processes and interrupts in a symmetric multiprocessor system.

Background

With the rapid development of multiprocessor technology, multiprocessor platforms are increasingly being used in various fields such as industrial automation, electronic communications, and home appliances. Meanwhile, the multi-processor platform is also more and more complex to process various process scheduling and interrupt sources. Under the circumstance, in order to ensure the system stability and the real-time performance of the multiprocessor platform in the process scheduling and interrupt processing process, the original process scheduling and interrupt processing technology is continuously developed.

Multiprocessing systems include symmetric multiprocessing systems and asymmetric multiprocessing systems. The interrupt processing method currently used in the symmetric multiprocessing system mainly includes the following procedures: (1) as shown in fig. 1, a hardware device generates an external IRQs (interrupt request) signal, and reports the signal to an I/O APIC (I/O advanced programmable interrupt controller), after the I/O APIC performs interrupt priority determination and mask control, the external IRQs are dynamically distributed to a local APIC (advanced programmable interrupt controller) of a certain CPU through an interrupt controller communication bus according to a programming logic in the I/O APIC, and the received external IRQs and its local IRQs are processed by the CPU; (2) FIG. 2 is a flow chart of software processing after an interrupt is distributed to a specific CPU according to an interrupt processing principle, the CPU obtaining an external IRQs searches an interrupt vector table according to an interrupt vector corresponding to the IRQs, determines an interrupt type, then jumps to an ISR (interrupt service routine), and executes an interrupt response code set by a user to perform interrupt processing; and calling a callback function registered in the upper layer in an interrupt service routine of the bottom layer, processing the interrupt service or the distribution service of the upper layer, and interrupting and returning after the upper layer codes are executed in the interrupt context of the bottom layer.

The process scheduling method in the current symmetric multiprocessing system mainly comprises a scheduling algorithm based on priority, a scheduling algorithm based on proportion sharing, a process scheduling algorithm based on time and the like, but the most common scheduling algorithm is the scheduling algorithm based on priority. The process scheduling in the symmetric multiprocessing system mainly comprises the following procedures: (1) a user creates a process, which initially starts running on a certain processor a; (2) the multiple processors independently carry out process scheduling, and when the processor A schedules the process next time, the process is distributed to the processor B with light load according to the load balancing principle; (3) and so on, the process will rotate execution across multiple processors.

However, as the number of devices to which interrupts are hooked increases and the number of user processes increases, the process scheduling and interrupt processing methods of the existing multiprocessor system face various challenges in terms of stability and real-time performance. Firstly, each processor processes interrupt and runs a user process, if a certain device is interrupted too frequently, the processor needs to enter interrupt continuously when executing the process, and switches back to the process after the interrupt processing is finished, and the process is repeated in a round, so that for a preemptive operating system, the CPU occupancy rate maintains a high level, the process processing is delayed, the input response of the operating system to a user is slow intuitively, and the real-time performance of the system is influenced. Secondly, as the processes and the interrupts are distributed to each processor in a balanced manner, the processes frequently generating interrupts and scheduling more processes can be frequently switched on the processors; since the cache always stores therein data with a high access rate or data to be called next by the running program, if the job is frequently switched, it is necessary for the processor cache to frequently switch between the call-in of the relevant data to be involved in the running interrupt and the call-in of the relevant data to be involved in the running process, which is a disaster for the processor cache, a high hit rate cannot be guaranteed, and the stability and real-time performance of the system are seriously affected in some cases.

In the existing chinese patent application with application number CN200710066924, "process scheduling method for heterogeneous multi-core system", because the application processes interrupt and process are processed on the same core, it is impossible to avoid system overhead caused by frequent switching under the condition of large number of processes and frequent interrupts, which affects the real-time performance of the system to a certain extent.

Although the patent of US20050246461 entitled Scheduling threads in an amulti-processor computer (Scheduling threads among multiple processors) distributes processes and interrupts evenly among multiple cores, it cannot fundamentally solve the system overhead caused by frequent switching of the processes and interrupts on the same core; therefore, under the conditions of various interrupt devices, complex interrupt processing and more processes, the real-time performance of the system for responding to the interrupt and processing the processes can be influenced.

Disclosure of Invention

In view of the above, the main objective of the present invention is to provide a method and an apparatus for processing processes and interrupts in a symmetric multiprocessing system, so as to prevent the processing delay and the system stability from decreasing when there are many processes and frequent interrupts in the system.

In order to achieve the purpose, the technical scheme of the invention is realized as follows:

the invention discloses a process and interrupt processing method in a symmetric multiprocessing system, which adopts a method of separating interrupt processing and process processing on a processor level, wherein one or a group of processors are used for specially processing interrupt, and the other processors are used for specially processing process; and further, the process and interrupt processing is monitored and the number of processors in the two groups of processors is dynamically adjusted. The method comprises the following steps:

a. after an interrupt signal is generated, binding an interrupt to an interrupt handler group, and processing the interrupt by the interrupt handler group;

b. and binding the generated process to a process processor group, wherein the process processor group processes the process, and a processor in the process processor group is different from a processor in an interrupt processor group.

c. And monitoring the interrupt processor group and the process processor group, calculating the load index of each group of processors, and dynamically adjusting the number of the processors in the two groups of processors according to the load index.

Further, in step a, the interrupt handler group processes an interrupt, and includes: and dynamically distributing the interrupt among the CPUs in the interrupt handling group in a balanced manner according to the load condition of the CPUs in the interrupt handling group, and enabling the same CPU to handle the same type of interrupt according to the interrupt affinity principle.

In step c, said calculating the load index of the processor of the interrupt handler group is: a ═ intLoad1+ intLoad2+. + intLoad)/n, where intLoad1 to intLoad are the load index of each CPU in the interrupt handler group, and n indicates the current number of CPUs in the interrupt handler group; or, in step c, the load index of the processor of the process processor set is calculated as: b ═ process load1+ process load2+. + process load m)/m, where process load1 to process load are the load indices of each CPU in the process processor group, and m indicates the current number of CPUs in the process processor group. In step c, dynamically adjusting the number of processors in the two groups of processors according to the load index includes: if the load index of the interrupt processor group is monitored to be larger than the load index of the process processor group, the processor with the minimum load index in the process processor group is bound to the interrupt processor group; and if the load index of the interrupt processing unit group is smaller than the load index of the process processor group, the processor with the minimum load index in the interrupt processing unit group is bound to the process processor group.

The invention also discloses a device for processing the process and the interrupt in the symmetric multiprocessing system, which comprises the following steps:

the interrupt processing module is used for carrying out interrupt binding distribution processing according to system requirements after an interrupt signal is generated, and the interrupt binding distribution processing comprises I/O APIC configuration and binding interrupt to an interrupt processing unit group;

the process processing module is used for binding the generated process to the process processor group and scheduling the process among the CPUs of the process processor group;

the interrupt processing unit group is used for processing the interrupt;

and the process processor group is used for processing the process, and a processor contained in the process processor group is different from a processor contained in the interrupt processing group.

The device also includes: and the process and interrupt monitoring module is used for counting the process processor group and the interrupt processor group, calculating the load capacity of each group of processors and dynamically adjusting the number of the processors in the two groups of processors according to the load index.

Compared with the prior art, the method and the device for processing the process and the interrupt in the symmetric multiprocessing system have the advantages and characteristics that:

because the method that the process processing and the interrupt processing are separated at the processor level is adopted, on one hand, the process processing and the interrupt processing are ensured not to be interfered with each other, the process processing and the interrupt processing can be ensured to be responded in time, and the real-time requirement of the system is ensured; on the other hand, if an interrupt or a process is bound to one (or a group of) processors, the CPU cache stores the data to be called next by the currently running program or the data with high access rate, and frequent and large-amount reading or removing is not needed, so that the cache problem caused by distribution on a plurality of processors can be avoided or reduced, and the cache is ensured to always keep high hit rate.

In addition, the invention also provides a process and interrupt monitoring module, which is used for counting the related information of the two groups of processors and re-binding the interrupt processing and the process processing according to the counting result, so that the multiprocessor system can automatically start a load balancing mechanism even under the condition that the equipment is interrupted too frequently or the processes are increased sharply (such as in the field of electronic communication), thereby avoiding the delay of the process or the interrupt processing and obviously improving the stability and the real-time property of the system when the process and the interrupt are processed.

Drawings

FIG. 1 is a block diagram of a conventional interrupt and process handling flow for a symmetric multiprocessor system;

FIG. 2 is a flow chart of software processing of interrupts on a CPU;

FIG. 3 is a schematic diagram of the interrupt and process separation of the symmetric multiprocessor system according to the present invention;

FIG. 4 is a flow chart of the main processes of the symmetric multiprocessor process and interrupt of the present invention.

Detailed Description

The invention uses the symmetrical multi-processing system process and interrupt processing device to process and interrupt, which comprises the following steps:

step A, in the starting process of the multi-processing system, calling an interrupt processing module interface by an operating system kernel, starting the interrupt processing module, and then carrying out interrupt binding distribution processing by the interrupt processing module, wherein the interrupt binding distribution processing comprises configuring I/OAPIC and binding interrupt to one or a group of processors, the group of processors become an interrupt processing group, and the rest processors without binding interrupt become a process processor group;

b, in the starting process of the multi-processing system, calling a process and an interrupt monitoring module interface by an operating system kernel to start a monitoring program, and monitoring the load conditions of an interrupt processor group and a process processor group in real time;

step C, after the multi-processing system is started, a user program calls a process processing module interface, and after the process processing module is started, all the generated processes are bound to a process processor group;

and D, dynamically reconfiguring the two groups of processors by the process and interrupt monitoring module according to the monitored load condition of each group of processors, wherein the reconfiguration comprises the following steps: if the load index of the process processor group is detected to be larger than that of the interrupt processor group, the processor with the minimum load index in the interrupt processor group is bound to the process processor group, otherwise, if the load index of the process processor group is smaller than that of the interrupt processor group, the processor with the minimum load index in the process processor group is bound to the interrupt processor group.

The interrupt and process processing method and device for the symmetric multiprocessor system of the present invention are described in detail below with reference to the accompanying drawings.

As shown in fig. 3, the structure of the interrupt and process handling apparatus of the symmetric multiprocessor system of the present invention includes:

and aninterrupt processing module 302, which is responsible for performing interrupt binding distribution processing according to system requirements after the interrupt signal is generated, including configuring the I/O APIC and binding the interrupt to one or a group of interrupt processors. The interrupt processing of the part is completed by the CPUs of the interruptprocessing unit group 304, for various interrupt types, the same CPU is made to process the same type of interrupt as much as possible according to the interrupt affinity principle, and the interrupt is dynamically distributed among the CPUs of the group in a balanced manner according to the load condition of the CPUs in the group;

in theinterrupt processing module 302, the method for dynamically distributing interrupts among the CPUs in the group includes: firstly, the software programs the I/O APIC, converts the load index of the CPU into a priority value to be written into an interrupt redirection table of the I/O APPIC, so that the I/O APIC sends the interrupt to the CPU with the lowest priority according to the interrupt redirection table, and the interrupt redirection table is dynamically adjusted in the running process, so that the interrupt can be dynamically distributed to each CPU;

theprocess handling module 303 is responsible for binding processes to the correspondingprocess processor group 305 after the processes are created, and scheduling the processes among the CPUs in theprocess processor group 305, and employs a general process scheduling method, such as a priority-based scheduling algorithm, a proportional sharing-based scheduling algorithm, a time-based process scheduling algorithm, and the like.

As shown in fig. 4, the main processing flow of the present invention:

step 401: starting a multiprocessor;

step 402: the interrupt handling module is called and started by the kernel of the operating system, and thenstep 405 is executed;

step 403: the process and the interrupt monitoring module are called and started by the kernel of the operating system, and thenstep 409 andstep 414 are respectively executed;

step 404: the process processing module is called and started by the user program, and thenstep 407 is executed;

step 405: the interrupt processing module binds an interrupt to an interrupt processing unit group;

step 406: the interrupt of the interrupt processing module in the interrupt processing unit group is dynamically distributed according to the load condition of the CPU in the group, and the interrupt processing is carried out;

step 407: the process processing module binds the process to the process processor group;

step 408: the process processing module adopts a general process scheduling method to schedule processes among CPUs in the process processor group;

step 409: the process and interrupt monitoring module starts an interrupt monitoring task;

step 410: timing, such as 1S polling each CPU in the interrupt group;

step 411: detecting the number IntNum of processing interrupts and the CPU occupancy CpuPercent of each CPU in the group within 1S;

step 412: according to the formula: calculating the load index intLoad of each CPU in the group;

step 413: and (3) calculating the average load index A of the group of CPUs according to the load index of each CPU in the group of CPUs:

a ═ intLoad1+ intLoad2+. + intLoad/n, where n denotes the current number of CPUs in the interrupt handler group; step 419 is then performed;

step 414: simultaneously with thestep 409, the process and interrupt monitoring module starts a process monitoring task;

step 415: timing, such as 1S polling each CPU in the process processor group;

step 416: detecting the number of processing processes processed by each CPU in the group in 1S and the CPU occupancy CpuPercent;

step 417: according to the formula: calculating the load index processLoad of each CPU in the group by processLoad (processNum) CpuPercent;

step 418: and solving the average load index B of the group of CPUs according to the load index of each CPU in the group:

b ═ process load1+ process load2+. + process load m)/m, where m refers to the current number of CPUs in the process group;

step 419: comparing the values of A and B, if A is greater than B, it shows that the load of CPU in the interrupt processing unit is too heavy, so executingstep 421, binding the CPU with the minimum load index in the CPU in the process processor unit to the interrupt processing unit, and transferring the original task on the CPU bound to the interrupt processing unit to the CPU with the minimum load index in the process processor unit;

step 420: if A is less than B, it shows that the load of the CPU in the process processor group is too heavy, the CPU with the minimum load index of the CPU in the interrupt processor group is bound to the process processor group, and the original task of the CPU bound to the process processor group is transferred to the CPU with the minimum load index in the interrupt processor group; if A equals B, no treatment is done.

Then, starting from

steps

409 and 414, each group of CPUs is continuously polled, and after long-time running, the loads of the two groups of CPUs are generally in a balanced level, and processes and interrupts are effectively processed in time.

In fig. 4,step 402,step 405 and step 406 are related interrupt processing flows,step 404,step 407 and step 408 are related process processing flows, and steps 403 andsteps 409 to 421 are process and interrupt monitoring module processing flows.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.

Claims

1. A method for processing processes and interrupts in a symmetric multiprocessing system, the method comprising:

2. The method of claim 1, further comprising:

3. The method of claim 1, wherein the interrupt handler group processes interrupts in step a by: and dynamically distributing the interrupt among the CPUs in the interrupt handling group in a balanced manner according to the load condition of the CPUs in the interrupt handling group, and enabling the same CPU to handle the same type of interrupt according to the interrupt affinity principle.

4. The method of claim 2,

in step c, said calculating the load index of the processor of the interrupt handler group is: a ═ intLoad1+ intLoad2+. + intLoad)/n, where intLoad1 to intLoad are the load index of each CPU in the interrupt handler group, and n indicates the current number of CPUs in the interrupt handler group;

or,

in step c, the load index of the processor of the process processor group is calculated as: b ═ process load1+ process load2+. + process load m)/m, where process load1 to process load are the load indices of each CPU in the process processor group, and m indicates the current number of CPUs in the process processor group.

5. The method of claim 2, wherein the dynamically adjusting the number of processors in the two groups of processors in step c according to the load index is: if the load index of the interrupt processor group is monitored to be larger than the load index of the process processor group, the processor with the minimum load index in the process processor group is bound to the interrupt processor group; and if the load index of the interrupt processing unit group is smaller than the load index of the process processor group, the processor with the minimum load index in the interrupt processing unit group is bound to the process processor group.

6. A device for processing processes and interrupts in a symmetric multiprocessing system, the device comprising:

the interrupt processing unit group is used for processing the interrupt;

7. The apparatus of claim 6, further comprising:

and the process and interrupt monitoring module is used for counting the process processor group and the interrupt processor group, calculating the load capacity of each group of processors and dynamically adjusting the number of the processors in the two groups of processors according to the load index.