CN101221961B - Pixel structure and manufacturing method thereof - Google Patents

Abstract

The invention provides a pixel structure and a manufacturing method thereof, wherein the pixel structure comprises: a substrate, a floating shading pattern on the substrate, an insulating layer on the substrate and the shading pattern, a data line above the shading pattern and corresponding to the shading pattern, a dielectric layer on the data line and the insulating layer, and a third layer of conductive pattern on the dielectric layer. The third layer of conductive pattern comprises a common line and a common pattern, wherein the common pattern has two branch lines, a gap is arranged between the two branch lines, and the gap is positioned above the data line. The pixel structure utilizes the shading pattern of the first conductive pattern to shield light leakage which is easy to generate at two sides of the data line of the second layer of conductive pattern, and utilizes the common pattern of the third layer of conductive pattern to shield the pixel electrode and the data line so as to avoid generating parasitic capacitance between the pixel electrode and the data line.

Description

Translated fromChinese

像素结构及其制作方法Pixel structure and manufacturing method thereof

技术领域technical field

本发明系关于一种像素结构及其制作方法，尤指一种具有超高开口率的像素结构及其制作方法。The present invention relates to a pixel structure and a manufacturing method thereof, in particular to a pixel structure with an ultra-high aperture ratio and a manufacturing method thereof.

背景技术Background technique

在液晶显示器的制造上，像素开口率的大小直接影响到背光源的利用率，也影响到面板的显示亮度。影响开口率大小的主要因素，即是透明像素电极与数据线之间的距离，若欲追求较大的开口率，在布局时必须缩短透明像素电极与数据线之间的距离。然而，当透明像素电极与数据线过于接近时，其所受到的寄生电容(Cpd，capacitance between pixel and data line)会变大，导致像素电极(pixel electrode)上充饱的电荷在下个画面(frame)转换前，会因数据线传送不同电压，而产生串音效应(cross talk)。另外，共通电极与数据线之间的距离过于接近时，其所受到的寄生电容会变大，而亦会产生串音效应。In the manufacture of liquid crystal displays, the size of the pixel aperture ratio directly affects the utilization rate of the backlight source, and also affects the display brightness of the panel. The main factor affecting the aperture ratio is the distance between the transparent pixel electrode and the data line. To pursue a larger aperture ratio, the distance between the transparent pixel electrode and the data line must be shortened during layout. However, when the transparent pixel electrode is too close to the data line, the parasitic capacitance (Cpd, capacitance between pixel and data line) it receives will become larger, causing the fully charged charge on the pixel electrode to be lost in the next frame. ) before conversion, there will be a crosstalk effect (cross talk) due to the different voltages transmitted by the data lines. In addition, when the distance between the common electrode and the data line is too close, the parasitic capacitance received by it will increase, and a crosstalk effect will also occur.

为减少寄生电容的效应，已有许多方式被研究，例如增加储存电容的大小，其可降低寄生电容占影响一个子像素单元(sub-pixel)所有电容的比率，然而若以增大面积的方式增加储存电容，会影响像素开口率。In order to reduce the effect of parasitic capacitance, many methods have been studied, such as increasing the size of the storage capacitor, which can reduce the ratio of parasitic capacitance to all capacitance affecting a sub-pixel unit (sub-pixel). However, if the area is increased Increasing the storage capacitance will affect the pixel aperture ratio.

发明内容Contents of the invention

本发明的目的之一在于提供一种像素结构及其制作方法，以提升开口率并减少寄生电容。One of the objectives of the present invention is to provide a pixel structure and a manufacturing method thereof, so as to increase aperture ratio and reduce parasitic capacitance.

为达上述目的，本发明首先提出一种像素结构，该像素结构包括：In order to achieve the above purpose, the present invention first proposes a pixel structure, which includes:

一基板；a substrate;

一第一层导电图案，设置于基板上，该第一层导电图案包括一栅极、一扫描线与一遮光图案，其中栅极电连接至该扫描线；A first-layer conductive pattern disposed on the substrate, the first-layer conductive pattern includes a grid, a scanning line and a light-shielding pattern, wherein the grid is electrically connected to the scanning line;

一绝缘层，设置于第一层导电图案与基板上；an insulating layer, disposed on the first layer of conductive patterns and the substrate;

一第二层导电图案，设置于绝缘层上，该第二层导电图案包括一数据线、一源极与一漏极，其中数据线设置于遮光图案的上方且数据线电性连接至源极；A second-layer conductive pattern is disposed on the insulating layer, the second-layer conductive pattern includes a data line, a source and a drain, wherein the data line is arranged above the light-shielding pattern and the data line is electrically connected to the source ;

一介电层，设置于第二层导电图案与绝缘层上；以及a dielectric layer disposed on the second conductive pattern and the insulating layer; and

一第三层导电图案，设置于介电层上，第三层导电图案包含一共通线及一共通图案，共通图案具有两支线，两支线之间具有一间隙，且间隙位于该数据线上方。A third-layer conductive pattern is arranged on the dielectric layer. The third-layer conductive pattern includes a common line and a common pattern. The common pattern has two branch lines with a gap between the two branch lines, and the gap is located above the data line.

本发明另提供一种制作像素结构的方法，包括下列步骤：The present invention also provides a method for manufacturing a pixel structure, comprising the following steps:

提供一基板；providing a substrate;

于基板上形成一第一层导电图案，该第一层导电图案包括一栅极、一扫描线与一遮光图案，其中栅极电连接至扫描线；forming a first-layer conductive pattern on the substrate, the first-layer conductive pattern includes a gate, a scanning line and a light-shielding pattern, wherein the gate is electrically connected to the scanning line;

于第一层导电图案与基板上形成一绝缘层；forming an insulating layer on the first conductive pattern and the substrate;

于绝缘层上形成一第二层导电图案，第二层导电图案包括一数据线、一源极与一漏极，其中数据线设置于遮光图案的上方，且数据线电连接至源极；forming a second-layer conductive pattern on the insulating layer, the second-layer conductive pattern includes a data line, a source and a drain, wherein the data line is arranged above the light-shielding pattern, and the data line is electrically connected to the source;

于第二层导电图案与绝缘层上形成一介电层；以及forming a dielectric layer on the second conductive pattern and the insulating layer; and

于该介电层上形成一第三层导电图案，其中第三层导电图案包含一共通线及一共通图案，共通图案具有两支线，两支线之间具有一间隙，且间隙位于数据线上方。A third layer of conductive pattern is formed on the dielectric layer, wherein the third layer of conductive pattern includes a common line and a common pattern, the common pattern has two branch lines with a gap between the two branch lines, and the gap is located above the data line.

本发明还提出另一种像素结构，该像素结构包含有一有源元件区与一周边区，包括：The present invention also proposes another pixel structure, which includes an active device area and a peripheral area, including:

一第一层导电图案，设置于该基板上，该第一层导电图案包括一栅极与一遮光图案，其中该栅极位于该有源元件区，该遮光图案位于该周边区；A first-layer conductive pattern is disposed on the substrate, the first-layer conductive pattern includes a gate and a light-shielding pattern, wherein the gate is located in the active element area, and the light-shielding pattern is located in the peripheral area;

一绝缘层，设置于该第一层导电图案与该基板上；an insulating layer disposed on the first conductive pattern and the substrate;

一第二层导电图案，设置于该绝缘层上，该第二层导电图案包括一数据线、一源极与一漏极，其中该数据线设置于该周边区的该遮光图案的上方，该源极与该漏极设置于该有源元件区，并且分置于该栅极两侧的上方而与该栅极部分重叠；A second-layer conductive pattern is disposed on the insulating layer, the second-layer conductive pattern includes a data line, a source and a drain, wherein the data line is disposed above the light-shielding pattern in the peripheral region, the The source and the drain are arranged in the active element area, and are separated above the two sides of the gate to partially overlap with the gate;

一介电层，设置于该第二层导电图案与该绝缘层上，并暴露出该有源元件区的该漏极；以及a dielectric layer, disposed on the second-layer conductive pattern and the insulating layer, and exposing the drain of the active device region; and

一第三层导电图案，设置于该周边区的该介电层上，并分置于该数据线两侧的上方并与该遮光图案重叠。A third-layer conductive pattern is arranged on the dielectric layer in the peripheral area, and is separated above the two sides of the data line and overlapped with the light-shielding pattern.

本发明的特点和优点是：本发明的像素结构利用第一导电图案的遮光图案遮蔽第二层导电图案的数据线两侧容易产生的漏光，并利用第三层导电图案的共通图案屏蔽像素电极与数据线，以避免像素电极与数据线之间产生寄生电容。此外，共通图案本身具有两支线且两支线之间具有间隙，因此两支线虽具有屏蔽像素电极与数据线的作用，但却不会与数据线产生过大的寄生电容而可减少串音效应。另外共通图案的支线、像素电极与位于其间保护层亦可形成的储存电容，使得像素结构不需另行于显示区内设置过大的储存电容，使得本发明的像素结构具有高开口率的优点。The features and advantages of the present invention are: the pixel structure of the present invention uses the light-shielding pattern of the first conductive pattern to shield the light leakage that is likely to occur on both sides of the data line of the second layer of conductive pattern, and uses the common pattern of the third layer of conductive pattern to shield the pixel electrode and the data line to avoid parasitic capacitance between the pixel electrode and the data line. In addition, the common pattern itself has two branch lines and there is a gap between the two branch lines. Therefore, although the two branch lines have the function of shielding the pixel electrodes and the data lines, they do not generate excessive parasitic capacitance with the data lines to reduce the crosstalk effect. In addition, the branch lines of the common pattern, the pixel electrodes and the protection layer located therebetween can also form storage capacitors, so that the pixel structure does not need to set too large storage capacitors in the display area, so that the pixel structure of the present invention has the advantage of high aperture ratio.

附图说明Description of drawings

图1为本发明较佳实施例的像素结构的示意图。FIG. 1 is a schematic diagram of a pixel structure in a preferred embodiment of the present invention.

图2至图7为本发明较佳实施例的制作像素结构的方法示意图。2 to 7 are schematic diagrams of a method for fabricating a pixel structure according to a preferred embodiment of the present invention.

图8为本发明另一较佳实施例的像素结构的剖面示意图。FIG. 8 is a schematic cross-sectional view of a pixel structure according to another preferred embodiment of the present invention.

图9为本发明又一较佳实施例的像素结构的剖面示意图。FIG. 9 is a schematic cross-sectional view of a pixel structure in another preferred embodiment of the present invention.

图10为本发明又一较佳实施例的像素结构的剖面示意图。FIG. 10 is a schematic cross-sectional view of a pixel structure in another preferred embodiment of the present invention.

【主要组件符号说明】[Description of main component symbols]

10    基板      12    薄膜晶体管区10Substrate 12 Thin Film Transistor Area

14    周边区    20    扫描线14peripheral area 20 scan lines

22    栅极      24    遮光图案22grid 24 shading pattern

30    绝缘层    32    半导体层30insulating layer 32 semiconductor layer

34    重掺杂半导体层    40    数据线34 heavily dopedsemiconductor layer 40 data line

42    源极              44    漏极42Source 44 Drain

50    介电层            60    共通图案50dielectric layer 60 common pattern

60a   共通图案的支线    61    共通线60a Branch line ofcommon pattern 61 Common line

62    间隙              70    保护层62Clearance 70 Protective layer

80    像素电极80 pixel electrodes

具体实施方式Detailed ways

为使审查员与熟习该项技艺者能更进一步了解本发明，下文特列举本发明的较佳实施例，并配合附图、组件符号等，详细说明本发明的构成内容及所欲达成的功效。In order to enable examiners and those familiar with the art to further understand the present invention, the preferred embodiments of the present invention are listed below, together with the accompanying drawings, component symbols, etc., to describe in detail the composition of the present invention and the desired effects .

本实施例是以非晶硅薄膜晶体管液晶显示装置的像素结构为例说明本发明，但本发明的像素结构应用不局限于此，而可应用于其它型式液晶显示装置的像素结构上，请参考图1至图7。图1为本发明一较佳实施例的像素结构的示意图，图2至图7为制作图1的像素结构的剖面示意图，其中图1绘示出像素结构的俯视示意图，图2至图7为像素结构沿图1的切线AA’绘示的剖面示意图。如图2所示，首先提供一基板10，基板10为透明基板，例如玻璃基板、石英基板或塑料基板。基板10上定义有数个像素结构，且每单一像素结构包含有一薄膜晶体管区12与一周边区14。如接着进行一沉积制程于基板10上形成一导电层，例如一金属层，并利用微影暨蚀刻技术定义此导电层，以形成一第一层导电图案。第一层导电图案为金属材料但亦可为其它导电材质，其包括一扫描线20、一栅极22以及一遮光图案24。扫描线20可为一直线位于像素结构的一边，如图1所示。栅极22设置于薄膜晶体管区12，并与扫描线20电连接，其电连接方式请参考图1所示。遮光图案24则设置于周边区14，其中遮光图案24为一浮置(floating)金属，而未与扫描线20与栅极22电连接，其作用为遮蔽光线防止漏光。This embodiment illustrates the present invention by taking the pixel structure of an amorphous silicon thin film transistor liquid crystal display device as an example, but the application of the pixel structure of the present invention is not limited thereto, and can be applied to the pixel structure of other types of liquid crystal display devices. Please refer to Figures 1 to 7. Figure 1 is a schematic diagram of a pixel structure in a preferred embodiment of the present invention, and Figures 2 to 7 are schematic cross-sectional views of manufacturing the pixel structure in Figure 1, wherein Figure 1 shows a schematic top view of the pixel structure, and Figures 2 to 7 are A schematic cross-sectional view of the pixel structure along the tangent line AA' in FIG. 1 . As shown in FIG. 2 , firstly, asubstrate 10 is provided, and thesubstrate 10 is a transparent substrate, such as a glass substrate, a quartz substrate or a plastic substrate. Several pixel structures are defined on thesubstrate 10 , and each single pixel structure includes aTFT region 12 and aperipheral region 14 . For example, a deposition process is then performed to form a conductive layer, such as a metal layer, on thesubstrate 10, and the conductive layer is defined by lithography and etching techniques to form a first layer conductive pattern. The first layer of conductive pattern is metal material but can also be other conductive material, which includes ascan line 20 , agrid 22 and a light-shieldingpattern 24 . Thescan line 20 can be a straight line located on one side of the pixel structure, as shown in FIG. 1 . Thegate 22 is disposed in the thinfilm transistor region 12 and is electrically connected to thescan line 20 , the electrical connection method is shown in FIG. 1 . The light-shieldingpattern 24 is disposed on theperipheral region 14 , wherein the light-shieldingpattern 24 is a floating metal, which is not electrically connected to thescan line 20 and thegate 22 , and functions to shield light and prevent light leakage.

如图3所示，于基板10与第一层导电图案上形成一绝缘层30。绝缘层30是作为栅极绝缘层，其材质可为氧化硅或其它适合的介电材料。再于薄膜晶体管区12的绝缘层30上另形成一半导体层32与一重掺杂半导体层34。半导体层32作为通道，其材质可为硅(例如非晶硅)，而重掺杂半导体层34则用来提高后续形成的源极与漏极与半导体层之间的奥姆式接触。As shown in FIG. 3 , an insulatinglayer 30 is formed on thesubstrate 10 and the first conductive pattern. The insulatinglayer 30 is used as a gate insulating layer, and its material can be silicon oxide or other suitable dielectric materials. Asemiconductor layer 32 and a heavily dopedsemiconductor layer 34 are further formed on the insulatinglayer 30 of theTFT region 12 . Thesemiconductor layer 32 is used as a channel, and its material can be silicon (such as amorphous silicon), and the heavily dopedsemiconductor layer 34 is used to improve the ohmic contact between the source and drain formed later and the semiconductor layer.

如图4所示，接着于绝缘层30上沉积一导电层，例如一金属层，并利用微影暨蚀刻技术定义此导电层以形成一第二层导电图案。第二层导电图案为金属材料，但亦可为其它导电材质，其包括一数据线40、一源极42与一漏极44。数据线40亦可为一直线，与扫描线20垂直交错并位于像素结构的另一边(如图1所示)。数据线40设置于遮光图案24的上方并对应遮光图案24，其中遮光图案24的宽度会略大于数据线40的宽度，用以遮蔽光线防止漏光，但遮光图案24的宽度与数据线40的宽度可视遮光需要作适度调整。源极42与漏极44亦设置于薄膜晶体管区12，且分别设置于栅极22二侧的上方并对应重掺杂半导体层34，并且源极42电连接至数据线40。As shown in FIG. 4 , a conductive layer, such as a metal layer, is then deposited on the insulatinglayer 30 , and the conductive layer is defined by lithography and etching techniques to form a second layer conductive pattern. The second layer of conductive pattern is made of metal material, but can also be other conductive material, which includes adata line 40 , asource 42 and adrain 44 . Thedata line 40 can also be a straight line, perpendicular to thescan line 20 and located on the other side of the pixel structure (as shown in FIG. 1 ). Thedata line 40 is arranged above the light-shieldingpattern 24 and corresponds to the light-shieldingpattern 24, wherein the width of the light-shieldingpattern 24 is slightly larger than the width of thedata line 40 to shield light from light leakage, but the width of the light-shieldingpattern 24 is the same as the width of thedata line 40 Visible shading needs to be adjusted appropriately. Thesource 42 and thedrain 44 are also disposed in the thinfilm transistor region 12 , and are respectively disposed above two sides of thegate 22 and correspond to the heavily dopedsemiconductor layer 34 , and thesource 42 is electrically connected to thedata line 40 .

如图5所示，随后于绝缘层30与第二层导电图案上形成一介电层50，再于介电层50上沉积一导电层(例如一金属层)，并利用微影暨蚀刻技术定义此导电层以形成一第三层导电图案。介电层50的材质可为无机材质如氧化硅、氮化硅等，或是有机材质。第三层导电图案为金属材料，但亦可为其它导电材质，如氧化铟锡，其包含一贯穿像素结构的共通线61与一共通图案60，其共通图案60连接于共通线61，如图1所示。共通图案60含包两支线60a，此两支线60a位于像素结构的周边区14，并且两支线60a具有一间隙62，此两平行的支线60a亦可为两平行的直条。两支线60a分置于数据线40的两侧，其间隙62则位于数据线40的上方并且其间隙62至少大于或等于数据线40的宽度。As shown in FIG. 5, adielectric layer 50 is then formed on the insulatinglayer 30 and the second layer of conductive patterns, and then a conductive layer (such as a metal layer) is deposited on thedielectric layer 50, and the lithography and etching technology is used to The conductive layer is defined to form a third layer conductive pattern. The material of thedielectric layer 50 can be an inorganic material such as silicon oxide, silicon nitride, etc., or an organic material. The third conductive pattern is a metal material, but it can also be other conductive materials, such as indium tin oxide, which includes acommon line 61 that runs through the pixel structure and acommon pattern 60, and thecommon pattern 60 is connected to thecommon line 61, as shown in the figure 1. Thecommon pattern 60 includes twobranch lines 60 a located in theperipheral area 14 of the pixel structure, and the twobranch lines 60 a have agap 62 , and the twoparallel branch lines 60 a can also be two parallel straight lines. The twobranch lines 60 a are located on two sides of thedata line 40 , and thegap 62 is located above thedata line 40 and thegap 62 is at least greater than or equal to the width of thedata line 40 .

如图6所示，接着于介电层50与第三层导电图案上形成至少一保护层70，并去除部分保护层70与介电层50，以曝露出漏极44。如图7所示，随后于保护层70上形成一像素电极80，并使像素电极80与曝露出的漏极44电连接。As shown in FIG. 6 , at least onepassivation layer 70 is then formed on thedielectric layer 50 and the third conductive pattern, and part of thepassivation layer 70 and thedielectric layer 50 are removed to expose thedrain 44 . As shown in FIG. 7 , apixel electrode 80 is then formed on thepassivation layer 70 , and thepixel electrode 80 is electrically connected to the exposeddrain electrode 44 .

本发明的像素结构具有三层金属层，其中第一导电图案的遮光图案24的作用在于遮蔽第二层导电图案的数据线40两侧容易产生的漏光，特别是斜向漏光，而第三层导电图案的作用在于利用共通图案60及部分共通线61屏蔽像素电极80与数据线40，以避免像素电极80与数据线40之间产生寄生电容，藉此可减少串音效应。值得注意的是，共通图案60本身为一具有一间隙62的两支线60a，而数据线40位于两支线60a之间，因此共通图案60本身却不会与数据线40产生过大的寄生电容。另外，共通图案60、像素电极80与位于其间保护层70亦可形成储存电容，使得像素结构不需另行于显示区内设置过大的储存电容，而可大幅提升开口率。The pixel structure of the present invention has three layers of metal layers, wherein the function of the light-shieldingpattern 24 of the first conductive pattern is to shield the light leakage easily generated on both sides of thedata line 40 of the second layer conductive pattern, especially the light leakage in an oblique direction, and the third layer The function of the conductive pattern is to use thecommon pattern 60 and part of thecommon lines 61 to shield thepixel electrodes 80 and the data lines 40 to avoid the generation of parasitic capacitance between thepixel electrodes 80 and the data lines 40 , thereby reducing the crosstalk effect. It should be noted that thecommon pattern 60 itself is twobranch lines 60 a with agap 62 , and thedata line 40 is located between the twobranch lines 60 a, so thecommon pattern 60 itself and thedata line 40 will not generate excessive parasitic capacitance. In addition, thecommon pattern 60 , thepixel electrode 80 and theprotection layer 70 therebetween can also form a storage capacitor, so that the pixel structure does not need to provide an excessive storage capacitor in the display area, and the aperture ratio can be greatly increased.

于本实施例的像素结构中，共通图案60的两支线60a大体上与数据线40的两侧切齐，且由于遮光图案24的宽度大于数据线40的宽度，因此共通图案60与遮光图案24部分重叠，如图7所示，亦可形成储存电容。在综合考虑共通图案60的屏蔽效果、共通图案60与像素电极80之间的寄生电容值等因素下，本发明的像素结构亦可具有其它不同的实施方式，请参考相关的附图并配合下文说明，其中为彰显各实施例的特征，以下各附图仅绘示出周边区的剖面示意图，且各实施例相同组件使用相同组件符号标示并不再赘述。In the pixel structure of this embodiment, the twobranch lines 60a of thecommon pattern 60 are substantially aligned with the two sides of thedata line 40, and since the width of the light-shieldingpattern 24 is greater than the width of thedata line 40, thecommon pattern 60 and the light-shieldingpattern 24 part Overlapping, as shown in Figure 7, can also form a storage capacitor. Considering the shielding effect of thecommon pattern 60, the parasitic capacitance between thecommon pattern 60 and thepixel electrode 80, and other factors, the pixel structure of the present invention can also have other different implementation modes, please refer to the relevant drawings and cooperate with the following To illustrate, in order to highlight the features of each embodiment, the following figures only show a schematic cross-sectional view of the peripheral area, and the same components in each embodiment are marked with the same component symbols and will not be described again.

请参考图8。图8为本发明另一较佳实施例的像素结构的剖面示意图。如图8所示，在本实施例中，共通图案60的两支线60a其中之一与数据线40的一侧部分重叠，而另一者则与数据线40的一侧切齐，而未与数据线40重叠。Please refer to Figure 8. FIG. 8 is a schematic cross-sectional view of a pixel structure according to another preferred embodiment of the present invention. As shown in FIG. 8 , in this embodiment, one of the twobranch lines 60 a of thecommon pattern 60 partially overlaps with one side of thedata line 40 , while the other is aligned with one side of thedata line 40 without being aligned with thedata line 40 .Lines 40 overlap.

请参考图9。图9为本发明又一较佳实施例的像素结构的剖面示意图。如图9所示，在本实施例中，共通图案60的两支线60a分别与数据线40相对应的一侧部分重叠。Please refer to Figure 9. FIG. 9 is a schematic cross-sectional view of a pixel structure in another preferred embodiment of the present invention. As shown in FIG. 9 , in this embodiment, the twobranch lines 60 a of thecommon pattern 60 partially overlap with one side corresponding to thedata line 40 .

请参考图10。图10为本发明又一较佳实施例的像素结构的剖面示意图。如图5所示，在本实施例中，共通图案60的两支线60a均未与数据线40的两侧重叠，且各支线60a与数据线40对应的一侧间距有一距离。Please refer to Figure 10. FIG. 10 is a schematic cross-sectional view of a pixel structure in another preferred embodiment of the present invention. As shown in FIG. 5 , in this embodiment, neither of the twobranch lines 60 a of thecommon pattern 60 overlaps the two sides of thedata line 40 , and there is a distance between eachbranch line 60 a and the corresponding side of thedata line 40 .

上述实施例仅为本发明的不同实施方式，本发明的像素结构并不限于上述实施例所教导而可有其它变化，举例来说，遮光图案24、数据线40、共通图案60与像素电极80的相对位置可视需要作适度的变化。The above-mentioned embodiments are only different implementations of the present invention, and the pixel structure of the present invention is not limited to the teachings of the above-mentioned embodiments, and other changes are possible, for example, the light-shieldingpattern 24, thedata line 40, thecommon pattern 60 and thepixel electrode 80 The relative position of can be moderately changed as needed.

综上所述，本发明的像素结构利用第一导电图案的遮光图案遮蔽第二层导电图案的数据线两侧容易产生的漏光，并利用第三层导电图案的共通图案屏蔽像素电极与数据线，以避免像素电极与数据线之间产生寄生电容。同时共通图案本身具有两平行的直条，且两直条之间具有对应于数据线之间隙，因此共通图案的两支线虽具有屏蔽像素电极与数据线的作用，但却不会与数据线产生过大的寄生电容，而可减少串音效应。再者，共通图案的两支线、像素电极与位于其间保护层亦可形成的储存电容，使得像素结构不需另行于显示区内设置过大的储存电容，使得本发明的像素结构具有超高开口率。In summary, the pixel structure of the present invention uses the light-shielding pattern of the first conductive pattern to shield the light leakage that is likely to occur on both sides of the data line of the second layer of conductive pattern, and uses the common pattern of the third layer of conductive pattern to shield the pixel electrode and the data line. to avoid parasitic capacitance between the pixel electrode and the data line. At the same time, the common pattern itself has two parallel straight bars, and there is a gap corresponding to the data line between the two straight bars. Therefore, although the two branch lines of the common pattern have the effect of shielding the pixel electrode and the data line, they will not interfere with the data line. Excessive parasitic capacitance can reduce crosstalk effects. Furthermore, the two branch lines of the common pattern, the pixel electrode and the protective layer in between can also form a storage capacitor, so that the pixel structure does not need to be additionally provided with an excessively large storage capacitor in the display area, so that the pixel structure of the present invention has an ultra-high opening. Rate.

以上所述仅为本发明的较佳实施例，凡依本发明申请专利范围所做的均等变化与修饰，皆应属本发明的涵盖范围。The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

Claims (16)

1. a dot structure is characterized in that, described dot structure comprises:

One substrate;

One ground floor conductive pattern is arranged on this substrate, and this ground floor conductive pattern comprises a grid, one scan line and a light-shielding pattern, and wherein this grid is electrically connected to this scan line;

One insulating barrier is arranged on this ground floor conductive pattern and this substrate;

One second layer conductive pattern is arranged on this insulating barrier, and this second layer conductive pattern comprises a data wire, one source pole and a drain electrode, and wherein this data wire is arranged at the top of this light-shielding pattern, and this data wire is electrically connected to this source electrode;

One dielectric layer is arranged on this second layer conductive pattern and this insulating barrier; And

One the 3rd layer of conductive pattern is arranged on this dielectric layer, and the 3rd layer of conductive pattern comprises a common line and a common pattern, and this common pattern has two branch lines, has a gap between this two branch line, and this gap is positioned at this data wire top.

2. dot structure as claimed in claim 1 is characterized in that, this light-shielding pattern is the metal of floating.

3. dot structure as claimed in claim 1 is characterized in that the width of this light-shielding pattern is greater than the width of this data wire.

4. dot structure as claimed in claim 1 is characterized in that, this of this common pattern two branch lines are two parallel vertical bars.

5. dot structure as claimed in claim 1 is characterized in that, this gap width of this two branch line is at least more than or equal to the width of data wire.

6. dot structure as claimed in claim 1 is characterized in that, this ground floor conductive pattern, this second layer conductive pattern, the 3rd layer of conductive pattern are constituted by metal level.

7. dot structure as claimed in claim 1; it is characterized in that; described dot structure includes at least one protective layer in addition and is arranged on the 3rd layer of conductive pattern and this dielectric layer, and a pixel electrode is arranged on this protective layer, and wherein this pixel electrode is electrically connected to this drain electrode.

8. dot structure as claimed in claim 7 is characterized in that, this pixel electrode flushes with this two branch line of this common pattern substantially.

9. method of making dot structure, this method comprises:

One substrate is provided;

Form a ground floor conductive pattern on this substrate, this ground floor conductive pattern comprises a grid, one scan line and a light-shielding pattern, and wherein this grid is electrically connected to this scan line;

On this ground floor conductive pattern and this substrate, form an insulating barrier;

Form a second layer conductive pattern on this insulating barrier, this second layer conductive pattern comprises a data wire, one source pole and a drain electrode, and wherein this data wire is arranged at the top of this light-shielding pattern, and this data wire is electrically connected to this source electrode;

On this second layer conductive pattern and this insulating barrier, form a dielectric layer; And

Form one the 3rd layer of conductive pattern on this dielectric layer, wherein the 3rd layer of conductive pattern comprises a common line and a common pattern, and this common pattern has two branch lines, has a gap between this two branch line, and this gap is positioned at this data wire top.

10. method as claimed in claim 9 is characterized in that the width of this light-shielding pattern is greater than the width of this data wire.

11. method as claimed in claim 9 is characterized in that, this light-shielding pattern is the metal of floating.

12. method as claimed in claim 9; it is characterized in that; this method is included in addition and forms after the 3rd layer of conductive pattern; on the 3rd layer of conductive pattern and this dielectric layer, form at least one protective layer; and on this protective layer, form a pixel electrode, wherein this pixel electrode is electrically connected to this drain electrode.

13. a dot structure is disposed on the substrate, this dot structure includes an active element district and a surrounding zone, it is characterized in that, this dot structure comprises:

One ground floor conductive pattern is arranged on this substrate, and this ground floor conductive pattern comprises a grid and a light-shielding pattern, and wherein this grid is positioned at this active element district, and this light-shielding pattern is positioned at this surrounding zone;

One insulating barrier is arranged on this ground floor conductive pattern and this substrate;

One second layer conductive pattern, be arranged on this insulating barrier, this second layer conductive pattern comprises a data wire, one source pole and a drain electrode, wherein this data wire is arranged at the top of this light-shielding pattern of this surrounding zone, this source electrode and this drain electrode are arranged at this active element district, and the top of these grid both sides that are placed in and overlapping with this grid part;

One dielectric layer is arranged on this second layer conductive pattern and this insulating barrier, and exposes this drain electrode in this active element district; And

One the 3rd layer of conductive pattern is arranged on this dielectric layer of this surrounding zone, and the top of these data wire both sides that are placed in and overlapping with this light-shielding pattern.

14. dot structure as claimed in claim 13 is characterized in that, this light-shielding pattern is the metal of floating.

15. dot structure as claimed in claim 13 is characterized in that, the width of this light-shielding pattern is greater than the width of this data wire.

16. dot structure as claimed in claim 13 is characterized in that, the 3rd layer of conductive pattern and this data wire two side portions are overlapping.

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