CN101217124B - A low temperature flip chip welding method of macromolecule electric conducting material of template printing - Google Patents
A low temperature flip chip welding method of macromolecule electric conducting material of template printingDownload PDFInfo
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Abstract
Description
Translated fromChinese技术领域technical field
本发明属于集成电路和微机电系统(MEMS)器件封装中倒装焊领域，特别适合不能进行高温处理的器件。The invention belongs to the field of flip-chip welding in the packaging of integrated circuits and micro-electromechanical systems (MEMS), and is particularly suitable for devices that cannot be processed at high temperatures.
背景技术Background technique
IC设计、芯片制造和封装测试并称为半导体工业的三大产业。统计数据显示，中国将成为世界的IC封装基地之一。因此对于封装技术的研究，对中国的半导体工业的发展具有重要的意义。封装的作用就是给管芯(芯片)和印刷电路板(PCB)之间提供电互连、机械支撑、机械和环境保护及散热通道。随着集成电路特征尺寸的减小，要求封装密度越来越高，从而对封装的可靠性提出更高的要求。同时，随着集成电路芯片成本的不断降低，导致封装的成本在元器件成本中的比例不断上升。因此，半导体产业对于低成本高可靠性的封装技术提出了更高的要求。IC design, chip manufacturing and packaging testing are called the three major industries of the semiconductor industry. Statistics show that China will become one of the world's IC packaging bases. Therefore, the research on packaging technology is of great significance to the development of China's semiconductor industry. The role of the package is to provide electrical interconnection, mechanical support, mechanical and environmental protection, and heat dissipation channels between the die (chip) and the printed circuit board (PCB). With the reduction of the characteristic size of the integrated circuit, the packaging density is required to be higher and higher, thus putting forward higher requirements on the reliability of the packaging. At the same time, as the cost of integrated circuit chips continues to decrease, the proportion of packaging costs in component costs continues to rise. Therefore, the semiconductor industry has put forward higher requirements for low-cost and high-reliability packaging technology.
传统上，用细小的金、铜或铝键合引线进行芯片的连接，该键合引线从半导体芯片表面周边附近设置的接触焊盘引到塑料或陶瓷封装的引线键合焊盘上，实现芯片与外界的电连接。由于引线键合成本低、效率高，目前在工业界仍然广泛应用。然而，随着集成电路特征尺寸的缩小，芯片的引出端越来越多，只能使用周边焊盘的引线键合技术受到挑战。同时，即使在相对短的距离上，细键合引线也必然会将不需要的电感和电容引入互连中，并由此减小电子器件的带宽和操作速率。随着更快的微处理器和更高频率的信号处理和通信装置的发展，引线键合的缺陷变得越来越明显。Traditionally, chip connections are made with tiny gold, copper or aluminum bonding wires that lead from contact pads located near the periphery of the semiconductor chip surface to wire bonding pads in plastic or ceramic packages to achieve chip bonding. electrical connection to the outside world. Due to the low cost and high efficiency of wire bonding, it is still widely used in the industry. However, as the feature size of integrated circuits shrinks, there are more and more terminals on the chip, and the wire bonding technology that can only use peripheral pads is challenged. At the same time, thin bond wires necessarily introduce unwanted inductance and capacitance into the interconnection, even over relatively short distances, and thereby reduce the bandwidth and operating speed of the electronic device. With the development of faster microprocessors and higher frequency signal processing and communication devices, the disadvantages of wire bonding have become more and more obvious.
倒装焊技术就是为了解决芯片引出端数越来越多、工作频率越来越高等问题而发展起来的一种互连技术。相对于传统的引线键合技术，倒装焊技术使用焊球阵列实现芯片之间或芯片与衬底之间的互连。倒装焊技术密度高、节距小且是面阵列，大大增加引出端数，并且具有短的互连通路(大约50到100微米)，可以大大减小互连电感和电容，在高频率的器件里有较好的应用。Flip-chip welding technology is an interconnection technology developed to solve the problems of increasing number of chip leads and higher operating frequency. Compared with traditional wire bonding technology, flip chip bonding technology uses an array of solder balls to realize the interconnection between chips or between chips and substrates. Flip-chip welding technology has high density, small pitch and is an area array, which greatly increases the number of terminals and has a short interconnection path (about 50 to 100 microns), which can greatly reduce the interconnection inductance and capacitance. In high-frequency devices There are better applications.
倒装焊常规的工艺过程是这样的。首先，在芯片的焊盘上制作凸点下金属化层。其次，在芯片的焊盘或制备了凸点下金属化层的焊盘上制备凸点。最后，实现芯片之间或芯片与衬底之间的倒装互连。The conventional process of flip chip welding is like this. First, an under-bump metallization layer is formed on the pads of the chip. Second, bumps are prepared on the pads of the chip or the pads on which the UBM layer is prepared. Finally, flip-chip interconnection between chips or between chips and substrates is realized.
芯片的焊盘通常是铝、铜或其他的金属材料，按照一定的规律分布在芯片的表面。凸点材料通常为各种导电材料，如金、焊料等。一般凸点材料不能直接制作在焊盘上，并且为了防止凸点材料和焊盘之间发生扩散、反应生成金属间化合物从而降低凸点和焊盘金属连接的可靠性，需要制作一层凸点下金属化层。常见凸点下金属化层有Cr-CuCr-Cu、TiW-Cu、Al-NiV-Au、TiW-Au、Ni(P)-Au等，其相应的制作方法包括蒸发、溅射、化学镀镍加浸金等。Chip pads are usually made of aluminum, copper or other metal materials, which are distributed on the surface of the chip according to certain rules. Bump materials are usually various conductive materials, such as gold, solder, and the like. Generally, the bump material cannot be made directly on the pad, and in order to prevent the diffusion and reaction between the bump material and the pad to form intermetallic compounds, thereby reducing the reliability of the metal connection between the bump and the pad, it is necessary to make a layer of bumps lower metallization layer. Common under-bump metallization layers include Cr-CuCr-Cu, TiW-Cu, Al-NiV-Au, TiW-Au, Ni(P)-Au, etc., and the corresponding production methods include evaporation, sputtering, and electroless nickel plating Add immersion gold, etc.
凸点制备技术已经开发出很多种，如蒸发、SBB(Stud Bump Bonding)技术、电镀、印刷等。蒸发工艺需采用金属掩模，成本高，工艺复杂，应用限制较多。SBB技术采用已有的引线键合设备和技术实现单个键合区的凸点，以金凸点为主，但是生产效率相对较低。电镀技术制备的凸点质量较好，可以实现窄节距的凸点制备，但由于需要蒸发或溅射工艺制备凸点下金属化层，而且需要厚胶光刻工艺形成电镀掩模和电镀图形，导致成本高、工艺复杂等问题。模板印刷技术制备倒装凸点，由于和现有的表面贴装技术具有较好的工艺兼容性，因此生产效率高，成本较低。但是由于目前对模板印刷过程中众多工艺参数的研究还不成熟，导致模板印刷制备的凸点存在各种缺陷，如均一性较差、出现孔洞或桥接、可靠性较差等问题，使得模板印刷在倒装焊特别是窄节距的倒装焊技术中的应用受到限制。A variety of bump preparation technologies have been developed, such as evaporation, SBB (Stud Bump Bonding) technology, electroplating, printing, etc. The evaporation process needs to use a metal mask, which has high cost, complicated process and many application restrictions. SBB technology uses existing wire bonding equipment and technology to realize the bumps of a single bonding area, mainly gold bumps, but the production efficiency is relatively low. The quality of bumps prepared by electroplating technology is good, and narrow-pitch bump preparation can be realized. However, due to the need for evaporation or sputtering to prepare the under-bump metallization layer, and the need for thick resist photolithography to form plating masks and plating patterns , leading to problems such as high cost and complicated process. Stencil printing technology prepares flip-chip bumps, because it has better process compatibility with existing surface mount technology, so the production efficiency is high and the cost is low. However, due to the immature research on many process parameters in the stencil printing process, there are various defects in the bumps prepared by stencil printing, such as poor uniformity, holes or bridges, and poor reliability. The application in flip-chip technology, especially narrow-pitch flip-chip technology, is limited.
目前在工业界应用较为广泛、研究比较多的是使用焊膏的模板印刷。常用的焊膏通常又可以分为有铅焊膏(如铅锡共晶焊膏)和无铅焊膏(如Sn4％Ag0.5％Cu、Sn3.5％Ag)。由于欧盟及其他国家已经出台相关规定要求电子器件实现无铅化，因此使用模板印刷技术实现无铅凸点的制备，得到广泛的研究和应用。授予陈正豪等人的“铅/锡及无铅焊料的小间距倒装焊凸点模板印刷制备技术”的中国专利03142416.3中叙述了使用模板印刷制备倒装凸点的工艺。该工艺包括如下步骤：采用镍-钒合金和浮脱工艺制备凸点下金属层和回流引导金属层；根据焊球尺寸和工艺要求，设计制备印刷模板；使用印刷机印制焊膏在晶片上；根据焊膏材料要求，在一定温度下回流形成焊球。由于焊膏回流成球，因此凸点的均一性较好，可靠性较高，并且通过优化工艺参数可以实现小节距的凸点制备。在Dionysios Manessis等人在2004年出版的IMAPS 2004Long Beach的会议论文集的题目为“Accomplishments in Lead-FreeFlip Chip Wafer Bumping using Stencil Printing Technology”论文中披露了使用化学镀镍和模板印刷制备了节距为120微米面阵列的无铅凸点，其高度分布为41.6±2.8微米，达到了较好的均一性。同时，剪切力实验显示Sn4％Ag0.5％Cu凸点的剪切强度为4.26g/mil2，Sn3.5％Ag凸点剪切强度为3.07g/mil2，可靠性较好。但是由于无铅焊膏的熔点较高，如Indium公司SAC系列无铅焊膏熔点约为217～218℃，给无铅焊膏的应用带来限制。At present, the stencil printing using solder paste is widely used and studied more in the industry. Commonly used solder pastes can usually be divided into leaded solder pastes (such as lead-tin eutectic solder paste) and lead-free solder pastes (such as Sn4%Ag0.5%Cu, Sn3.5%Ag). Since the European Union and other countries have issued relevant regulations requiring electronic devices to be lead-free, the preparation of lead-free bumps using stencil printing technology has been extensively researched and applied. The Chinese patent No. 03142416.3 of "Stencil Printing Preparation Technology for Small Pitch Flip-Chip Bumps of Lead/Tin and Lead-free Solder" granted to Chen Zhenghao et al. described the process of preparing flip-chip bumps by stencil printing. The process includes the following steps: using nickel-vanadium alloy and lift-off process to prepare UBM layer and reflow guide metal layer; design and prepare printing template according to solder ball size and process requirements; use printing machine to print solder paste on wafer ; According to the requirements of the solder paste material, reflow at a certain temperature to form solder balls. Since the solder paste is reflowed into balls, the uniformity of the bumps is better and the reliability is higher, and the preparation of bumps with small pitches can be realized by optimizing the process parameters. The title of "Accomplishments in Lead-FreeFlip Chip Wafer Bumping using Stencil Printing Technology" in the conference proceedings of IMAPS 2004Long Beach published in 2004 by Dionysios Manessis et al. The height distribution of the lead-free bumps of the 120-micron area array is 41.6±2.8 microns, which achieves better uniformity. At the same time, the shear force test shows that the shear strength of the Sn4%Ag0.5%Cu bumps is 4.26g/mil2 , and the shear strength of the Sn3.5%Ag bumps is 3.07g/mil2 , showing good reliability. However, due to the high melting point of lead-free solder paste, for example, the melting point of Indium's SAC series lead-free solder paste is about 217-218°C, which limits the application of lead-free solder paste.
发明内容Contents of the invention
本发明的目的是采用模版印刷技术和高分子导电材料实现低温的倒装焊。The purpose of the invention is to realize low-temperature flip-chip welding by adopting stencil printing technology and polymer conductive material.
本发明的特征在于所述方法依次含有以下步骤：The present invention is characterized in that said method comprises the following steps in sequence:
步骤(1)制作开孔的印刷模板；Step (1) making the printing template of perforation;
开孔的位置和芯片上的焊盘、以及衬底上的焊盘的位置要逐个分别对应，The positions of the openings and the pads on the chip and the pads on the substrate should correspond to each other one by one.
开孔的面积比大于0.6，所述面积比＝S/S侧，S是开孔的面积，S侧是开孔的侧壁面积，The area ratio of the opening is greater than 0.6, the area ratio=S/Sside , S is the area of the opening, and the Sside is the side wall area of the opening,
开孔的宽度比W/t要大于1.5，对于方孔，W是开孔的边长，对于圆孔，W是开孔的直径，t是模板的厚度，The width ratio of the hole is greater than 1.5 W/t. For square holes, W is the side length of the hole. For round holes, W is the diameter of the hole, and t is the thickness of the template.
开孔的面积小于焊盘的面积；The area of the opening is smaller than the area of the pad;
步骤(2)清洗所述需要倒装的芯片和衬底，去除所述芯片和衬底焊盘表面的有机污染物；Step (2) cleaning the chip and the substrate that need to be flipped, and removing the organic pollutants on the surface of the chip and the substrate pad;
步骤(3)使用所述模板在所述芯片表面的焊盘上印刷高分子导电材料，形成凸点，所述高分子导电材料是由热塑性或热固性的树脂混合导电颗粒组成的各向同性导电材料，导电颗粒可以是银粉颗粒；Step (3) using the template to print a conductive polymer material on the pad on the surface of the chip to form bumps, the conductive polymer material is an isotropic conductive material composed of thermoplastic or thermosetting resin mixed conductive particles , the conductive particles can be silver powder particles;
步骤(4)把印刷有所述高分子导电材料的芯片放入保温炉中固化，固化温度小于150℃；Step (4) putting the chip printed with the polymer conductive material into a holding furnace for curing, and the curing temperature is less than 150°C;
步骤(5)使用所述模板在所述衬底上印刷所述高分子导电材料形成凸点；Step (5) using the template to print the conductive polymer material on the substrate to form bumps;
步骤(6)把经过步骤(4)固化后的芯片和步骤(5)印刷有所述高分子导电材料但尚未固化的衬底对准后组装在一起；Step (6) aligning and assembling together the cured chip in step (4) and the uncured substrate printed with the conductive polymer material in step (5);
步骤(7)把经过步骤(6)倒装后的芯片和衬底放入所述保温炉中固化，固化温度＜150℃；Step (7) putting the chips and substrate flipped in step (6) into the holding furnace for curing, and the curing temperature is <150°C;
步骤(8)使用不导电的高分子材料从底部去填充已经通过步骤(7)固化的倒装芯片；Step (8) uses a non-conductive polymer material to fill the flip chip that has been solidified through step (7) from the bottom;
步骤(9)把步骤(8)中底部填充后的倒装芯片放入所述保温炉中固化，固化温度小于150℃，形成最后的系统。Step (9) putting the underfilled flip chip in step (8) into the holding furnace for curing, and the curing temperature is less than 150° C. to form the final system.
在模板印刷时所述模版的印刷速度在7mm/s至25mm/s之间。During stencil printing, the printing speed of the stencil is between 7mm/s and 25mm/s.
在模板印刷时所述模板的底部和被印刷凸点的芯片面，或者衬底的上表面的距离为零。During template printing, the distance between the bottom of the template and the surface of the chip on which bumps are printed, or the upper surface of the substrate, is zero.
所述模板的形状是方形、圆形之中的任何一种。The shape of the template is any one of square and circle.
所述模板上开孔的面积小于焊盘的面积。The area of the hole on the template is smaller than the area of the pad.
相对于使用焊膏的模板印刷技术来说，使用高分子导电材料的模板印刷技术具有如下优点：Compared with the stencil printing technology using solder paste, the stencil printing technology using polymer conductive materials has the following advantages:
无须制作凸点下金属化层。高分子导电材料和大多数焊盘金属如铝、铜、金等有较好的浸润性，结合较好，不需要象印刷焊膏一样先制备凸点下金属化层，因而简化工艺过程，降低成本。No UBM layer is required. Polymer conductive materials and most pad metals such as aluminum, copper, gold, etc. have good wettability and good combination. It is not necessary to prepare the under-bump metallization layer like printing solder paste, thus simplifying the process and reducing cost.
固化温度低。对于大多数的高分子导电材料，固化温度＜150℃，可以减少高温对半导体芯片带来的损伤，特别适用于一些半导体探测器的封装。由于整个工艺温度较低，产生的热应力相对较小，提高了系统的可靠性。Curing temperature is low. For most polymer conductive materials, the curing temperature is less than 150°C, which can reduce the damage caused by high temperature to semiconductor chips, and is especially suitable for the packaging of some semiconductor detectors. Due to the low temperature of the whole process, the generated thermal stress is relatively small, which improves the reliability of the system.
机械性能好。高分子导电材料通常由热塑性或热固性树脂和导电金属颗粒如银粉混合制成。由于树脂材料韧性较好，抗热应力、机械应力较好，疲劳寿命高。Good mechanical properties. Polymer conductive materials are usually made by mixing thermoplastic or thermosetting resin and conductive metal particles such as silver powder. Because the resin material has good toughness, good resistance to thermal stress and mechanical stress, and high fatigue life.
对于由热固性树脂组成的高分子导电材料，印刷固化后不能流动，后处理过程可靠性更好，同时也可以减少或取消后处理的清洗残留物设备。For polymer conductive materials composed of thermosetting resins, they cannot flow after printing and curing, and the reliability of the post-processing process is better. At the same time, the cleaning residue equipment for post-processing can also be reduced or eliminated.
无铅等有害金属，可以更好的保护环境。Lead-free and other harmful metals can better protect the environment.
随着模板制作技术的进步，使用高分子导电材料的模板印刷技术可以实现窄节距凸点阵列，满足芯片引出端数越来越多的要求。With the advancement of stencil manufacturing technology, stencil printing technology using polymer conductive materials can realize narrow-pitch bump arrays to meet the increasing number of chip terminals.
附图说明Description of drawings
图1是实施例中要倒装在一起的芯片和衬底的剖面图。Fig. 1 is a cross-sectional view of a chip and a substrate to be flip-chiped together in the embodiment.
图2是印刷模板的俯视图。Figure 2 is a top view of the printing template.
图3是使用图2中的模板在图1中芯片上印刷高分子导电材料时的剖面图。FIG. 3 is a cross-sectional view of printing a conductive polymer material on the chip in FIG. 1 using the template in FIG. 2 .
图4是取走模板后的印刷有高分子导电材料并固化后的芯片剖面图。FIG. 4 is a cross-sectional view of a chip printed with a polymer conductive material and cured after the template is removed.
图5是图1中的衬底印刷了高分子导电材料后的剖面图。FIG. 5 is a cross-sectional view of the substrate in FIG. 1 after printing polymer conductive material.
图6是图4和图5对准后准备组装在一起的示意图。Fig. 6 is a schematic diagram of Fig. 4 and Fig. 5 after being aligned and ready to be assembled together.
图7是对准后的芯片和衬底组装在一起并固化后的剖面图。Fig. 7 is a cross-sectional view of the aligned chips and substrate assembled and cured.
图8是固化后的芯片和衬底使用高分子非导电材料底部填充后的剖面图。FIG. 8 is a cross-sectional view of the cured chip and substrate underfilled with a polymer non-conductive material.
其中，图中各个数字标识所代表的含义为：Among them, the meanings represented by the numbers in the figure are as follows:
1：半导体芯片， 2：半导体芯片正表面的焊盘1: Semiconductor chip, 2: The pad on the front surface of the semiconductor chip
3：半导体芯片正表面的钝化层，4：衬底3: Passivation layer on the front surface of the semiconductor chip, 4: Substrate
5：衬底正表面上的钝化层， 6：衬底正表面上制作的焊盘5: Passivation layer on the front surface of the substrate, 6: Pads made on the front surface of the substrate
7：高分子导电材料， 8：底部填充使用的高分子非导电材料7: Polymer conductive material, 8: Polymer non-conductive material used for underfill
9：印刷用的模板， 10：模板上的开孔9: Template for printing, 10: Holes on the template
具体实施方式Detailed ways
本特选实施例具体工艺实施步骤为：The specific process implementation steps of this selected embodiment are:
1，设计制造印刷模板9；1. Design and manufacture
2，清洗需要倒装的芯片1和衬底4，去除焊盘2、6表面上有机物等沾污；2. Clean the
3，使用模板9在芯片1表面的焊盘2上印刷高分子导电材料7，形成凸点；3. Use the
4，将印刷有高分子导电材料的芯片1放入保温炉中固化；4. Put the
5，使用模板9在衬底4上印刷高分子导电材料7，形成凸点；5. Use the
6，将固化后的芯片1和印刷有高分子导电材料但没有固化的衬底4倒装在一起；6. Flip-chip the cured
7，将倒装后的芯片1和衬底4放入保温炉中固化；7. Put the flip-
8，使用不导电的高分子材料8底部填充已经固化的倒装芯片；8. Use
9，底部填充后的倒装芯片放入保温炉中固化，形成最后的系统；9. Put the underfilled flip chip into the holding furnace to solidify to form the final system;
芯片1是一种电子器件，特别是不能承受高温处理工艺的电子器件，如特殊的半导体探测器。在芯片1的正表面制作有多个焊盘2，焊盘2以外的位置可以覆盖有一层钝化层3。衬底4可以是FR-4、陶瓷、硅衬底或是其他的半导体芯片，同时在其正表面与芯片1上焊盘2对应位置制作有接触焊盘6，接触焊盘6以外的地方也可以覆盖有钝化层5。芯片1和衬底4上的焊盘通常为铝、铜、金或银等金属。在开始倒装前，须将芯片1和衬底4清洗干净，去除焊盘2、6表面的有机物等沾污，提高倒装芯片的机械性能和电学性能。
模板9是本发明中的关键，模板9的设计和印刷的高分子导电凸点的质量有密切联系。同时模板9的设计也受到高分子导电材料的物理性能的影响。一般的，由于高分子导电材料固化时不能象焊膏一样回流成球，所以模板的开孔10尺寸通常比接触焊盘2、6小，以防止出现桥接等缺陷。但是，当芯片1和衬底4上的接触焊盘2、6节距比较大时，也可以采用模板开孔10比接触焊盘2、6大，以改善机械性能和电学性能。The
模板9上的开孔10形状可以采用圆形、椭圆形或带有圆角的矩形等。通常圆形开孔，脱模性能较好；带有圆角的矩形印刷的凸点体积大；椭圆形开孔则适合于节距较小的凸点阵列的印刷。假设模板9上的开孔10宽为W，长度为L，面积为S，开孔侧壁面积为S侧，模板9厚为t，则可以定义如下两个参数：宽厚比＝W/t，面积比＝S/S侧。模板设计时要求宽厚比＞1.5，面积比＞0.6。模板加工方法主要有三种：电化学腐蚀、激光加工和电铸加工。电化学腐蚀成本最低，一般使用铜板作为模板，开孔质量较差，对于节距比较大(＞1毫米)的情况比较适合。激光加工使用钢板作为模板，开孔质量较好，适用于节距大于150微米的倒装焊技术。当模板开孔数量较多，激光加工成本较高。当开孔节距小于150微米时，开孔侧壁质量较差导致印刷效果较差，因此需要采用电铸加工模板技术。电铸加工模板开孔侧壁陡直，质量最好。根据印刷凸点阵列的要求，选择合适的模板加工技术，设计合理的模板开孔参数，从而获得高质量的印刷凸点阵列。The shape of the
高分子导电材料，通常是由热塑性或热固性的树脂混合导电颗粒组成的各向同性导电材料。导电颗粒通常是银粉颗粒，质量分数最高达80％。Polymer conductive materials are usually isotropic conductive materials composed of thermoplastic or thermosetting resin mixed with conductive particles. The conductive particles are usually silver powder particles with a mass fraction of up to 80%.
在印刷高分子导电材料时，需要选择合理的印刷参数来获得均一性较好、可靠性较高的凸点阵列。常见的印刷参数包括印刷速度、印刷压力、离板高度、脱模速度等。印刷速度不能过快，否则导致模板开孔无法完全填充，印刷速度通常为7mm/s到25mm/s。印刷刮刀的压力不能太大，否则造成刮刀和模板的磨损，并且导致印刷材料的向四周流动而造成桥接等缺陷；印刷刮刀的压力不能太小，否则刮刀刮动时，印刷材料残存在模板上。离板高度定义为印刷时模板的底部和被印刷凸点的芯片或衬底的上表面的距离。印刷高分子导电材料时，离板高度通常为0。脱模速度影响高分子导电凸点的质量，过快脱模速度降低高分子导电凸点均一性。为了获得均一性较好的印刷凸点，尽量减小脱模速度。When printing polymer conductive materials, it is necessary to select reasonable printing parameters to obtain a bump array with good uniformity and high reliability. Common printing parameters include printing speed, printing pressure, height from plate, demoulding speed, etc. The printing speed should not be too fast, otherwise the opening of the stencil cannot be completely filled. The printing speed is usually 7mm/s to 25mm/s. The pressure of the printing squeegee should not be too high, otherwise it will cause wear of the squeegee and the stencil, and cause the printing material to flow around and cause bridging and other defects; the pressure of the printing squeegee should not be too small, otherwise the printing material will remain on the stencil when the squeegee scrapes . The off-board height is defined as the distance between the bottom of the stencil and the top surface of the chip or substrate on which the bumps are printed. When printing polymer conductive materials, the height from the board is usually 0. The demoulding speed affects the quality of the polymer conductive bumps, and the demoulding speed is too fast to reduce the uniformity of the polymer conductive bumps. In order to obtain better uniformity of printed bumps, the demoulding speed should be reduced as much as possible.
凸点在芯片和衬底印刷完成后，需要进行组装，即将芯片和衬底倒装在一起。由于高分子导电材料固化以后不能再流动，所以组装时需要保证较高的对准精度，需要采用的专用的组装设备。After the chip and the substrate are printed, the bump needs to be assembled, that is, the chip and the substrate are flipped together. Since the polymer conductive material can no longer flow after solidification, it is necessary to ensure high alignment accuracy during assembly, and special assembly equipment is required.
芯片和衬底采用高分子导电材料倒装以后，为了增强倒装的机械性能，采用非导电性的高分子材料进行底部填充。由于本发明要求工艺温度不能超过150℃，因此用于底部填充的高分子材料固化温度不能超过150℃。After the chip and the substrate are flipped using polymer conductive materials, in order to enhance the mechanical properties of the flip chip, non-conductive polymer materials are used for bottom filling. Since the present invention requires that the process temperature cannot exceed 150°C, the curing temperature of the polymer material used for underfilling cannot exceed 150°C.
本发明的特征在于使用模板印刷高分子导电材料实现低温倒装焊技术，而不是使用焊膏尤其无铅焊膏的倒装焊技术。使用焊膏尤其是无铅焊膏的倒装焊技术，工艺过程最高温度不低于240℃，而本发明整个工艺过程温度不高于150℃，适应于一些对于温度比较敏感的半导体器件，如特殊的半导体探测器等。The present invention is characterized in that the low-temperature flip-chip soldering technology is realized by using stencil printing polymer conductive material instead of the flip-chip soldering technology using solder paste, especially lead-free solder paste. Using solder paste, especially lead-free solder paste flip chip technology, the highest process temperature is not lower than 240°C, while the temperature of the entire process of the present invention is not higher than 150°C, which is suitable for some semiconductor devices that are sensitive to temperature, such as Special semiconductor detectors, etc.
为了更好地介绍本发明，结合一特定实施例来说明。需要注意的是，这个实施例并不构成对发明的限制，其原理和特征可用于各种实施例而不脱离本发明的范围和实质。In order to better introduce the present invention, it is described in conjunction with a specific embodiment. It should be noted that this embodiment does not constitute a limitation to the invention, and its principles and features can be used in various embodiments without departing from the scope and spirit of the present invention.
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