CN101198208A - Substrate with multilayer plated through hole and method for forming multilayer plated through hole - Google Patents

Abstract

A substrate with multi-layer plated through hole is prepared as forming at least one dielectric layer and an electroplated layer in plated through hole of substrate body by deposition mode. The dielectric layer partially covers the circuit layer of the substrate and electrically isolates the electroplated layer from the plated through hole, so that the plated through hole arrangement space of the substrate is saved, and the effect of multilayer plated through holes can be achieved. Preferably, the dielectric layer is formed by electrophoretic deposition to control the deposition thickness of the dielectric layer to be uniform and thin, without drilling alignment, and to improve electrical performance and reduce crosstalk effect.

Description

Translated fromChinese

具有多层镀通孔的基板及其多层镀通孔的形成方法Substrate with multilayer plated through hole and method for forming multilayer plated through hole

【技术领域】【Technical field】

本发明是有关于多层电路板(multi-layercircuit board)，特别是指一种具有多层镀通孔的基板及其制造方法。The present invention relates to a multi-layer circuit board (multi-layer circuit board), in particular to a substrate with multi-layer plated through holes and a manufacturing method thereof.

【背景技术】【Background technique】

在各类电子产品中一般会使用到多层电路板作为电性讯号传导、电源供应、接地的连接。随着电子产品的多功能与复杂化发展，多层电路板的线路层层数与纵向电连接处会增加，因此需要数量众多的镀通孔(Plated Through Hole，PTH)作为不同层之间线路层的相互电性导通。In various electronic products, multilayer circuit boards are generally used as electrical signal transmission, power supply, and ground connections. With the multi-functional and complex development of electronic products, the number of circuit layers and vertical electrical connections of multilayer circuit boards will increase, so a large number of plated through holes (Plated Through Holes, PTH) are required as circuits between different layers. Layers are electrically connected to each other.

台湾专利公告第589729号「具有屏蔽式镀通孔结构之基板及其形成方法」，揭示一种基板，其镀通孔的孔壁先形成有管状金属屏蔽层，再覆盖上一介电层，另将一讯号传递线路配置于该介电层所包围的洞口中。其中，该介电层以填塞方式先充满于管状金属屏蔽层内，再以钻孔方法形成一洞口，最后再形成该讯号传递线路于洞口内。然而钻孔对位并无法控制在相当准确的范围内，该介电层的覆盖厚度会有厚薄差异，导致讯号传递线路与管状金属屏蔽层之间会有间隔的大小变化，甚至有短路的风险，不适用于多层镀通孔的结构。Taiwan Patent Publication No. 589729 "Substrate with Shielded Plated Through Hole Structure and Formation Method thereof" discloses a substrate in which a tubular metal shielding layer is first formed on the wall of the plated through hole, and then covered with a dielectric layer. A signal transmission line is arranged in the hole surrounded by the dielectric layer. Wherein, the dielectric layer is firstly filled in the tubular metal shielding layer by means of filling, and then a hole is formed by drilling, and finally the signal transmission line is formed in the hole. However, the drilling alignment cannot be controlled within a fairly accurate range. The thickness of the dielectric layer will vary in thickness, resulting in a change in the size of the gap between the signal transmission line and the tubular metal shielding layer, and even the risk of short circuits. , not applicable to the structure of multilayer plated through holes.

台湾专利证号I242783号「孔柱分割式连通孔结构及其制造方法」，揭示一种孔柱分割式连通孔结构，包含至少两分离式导体，以组成一孔柱状结构，且在该两分离式导体之间为纵切或是斜切的间隙。简而言之，就是将一镀通孔切割成两半，或是切割成多片，并个别与至少一上方线路或是下方线路相连接，然这样的导体分离，无论是切割当时或是最终基板产品的应用，皆会有镀通孔的结构弱化的现象，易于断裂，无法抵抗基板的热应力发生。此外，该前案所述以往同轴线式的子母贯通孔结构会有阻抗值高与产生电感效应，皆是由于在介电层的形成过程中以介电物质塞孔方式填满镀通孔再钻孔形成内贯穿孔，之后方形成内层导电组件于内贯穿孔内，导致镀通孔内形成的介电层厚度为厚薄不一所引起。Taiwan Patent No. I242783 "Pillar Segmented Connecting Hole Structure and Its Manufacturing Method" discloses a hole column split communicating hole structure, which includes at least two separated conductors to form a columnar structure, and the two separated There are longitudinal or chamfered gaps between the conductors. In short, it is to cut a plated through hole into two halves, or cut it into multiple pieces, and individually connect to at least one upper line or lower line, but such conductors are separated, whether it is cut at the time or at the end In the application of substrate products, there will always be a phenomenon that the structure of the plated through hole is weakened, which is easy to break and cannot resist the thermal stress of the substrate. In addition, the conventional coaxial through-hole structure of the previous coaxial line has high impedance value and inductive effect, both of which are due to filling the plated-through hole with a dielectric substance during the formation of the dielectric layer. The hole is drilled again to form an inner through hole, and then the inner layer conductive component is formed in the inner through hole, resulting in the thickness of the dielectric layer formed in the plated through hole being caused by different thicknesses.

【发明内容】【Content of invention】

本发明的主要目的在于提供一种具有多层镀通孔的基板及其多层镀通孔的形成方法，其在一基板的一镀通孔内以沉积方式形成的介电层以及一电镀层，该介电层形成于该镀通孔内并局部覆盖该基板的线路层，并且电性隔离该电镀层与该基板的该镀通孔，以节省基板的镀通孔设置空间，达到多层镀通孔的功效，以降低基板尺寸或是可供高密度线路设计。The main object of the present invention is to provide a substrate with multilayer plated through holes and a method for forming the multilayer plated through holes, wherein a dielectric layer and an electroplating layer formed by deposition in a plated through hole of a substrate , the dielectric layer is formed in the plated through hole and partially covers the circuit layer of the substrate, and electrically isolates the electroplating layer from the plated through hole of the substrate, so as to save the space for setting the plated through hole of the substrate and achieve multi-layer The effect of plated through holes to reduce the size of the substrate or for high-density circuit design.

本发明的次一目的在于提供一种具有多层镀通孔的基板及其多层镀通孔的形成方法，其中用以电性隔离该镀通孔与该电镀层的该介电层由电泳沉积(electrophoretic deposition)所形成，其可控制该介电层的沉积厚度为均匀且相当薄，无需再钻孔对位，能提升电性效能与降低串音(cross-talk)效应。Another object of the present invention is to provide a substrate with multilayer plated through holes and a method for forming the same, wherein the dielectric layer used to electrically isolate the plated through holes and the electroplating layer is formed by electrophoresis It is formed by electrophoretic deposition, which can control the deposition thickness of the dielectric layer to be uniform and relatively thin, without the need for drilling alignment, and can improve electrical performance and reduce cross-talk effects.

依据本发明，一种具有多层镀通孔的基板主要包含一具有一镀通孔的基板主体、一介电层以及一电镀层。该基板主体更具有一第一线路层与一第二线路层，该镀通孔电性导接该第一线路层与该第二线路层。该介电层以沉积方式形成于该镀通孔内，并局部覆盖该第一线路层与该第二线路层。该电镀层形成于该介电层，该介电层电性隔离该电镀层与该镀通孔。因此可在该镀通孔内再设置由该介电层与该电镀层组成的另一镀通孔，以达到多层镀通孔的功效，其可节省基板的镀通孔设置空间，有效利用基板空间，以降低基板尺寸或是可供高密度线路设计。According to the present invention, a substrate with multilayer plated through holes mainly includes a substrate body with a plated through hole, a dielectric layer and an electroplating layer. The substrate body further has a first circuit layer and a second circuit layer, and the plated through hole electrically connects the first circuit layer and the second circuit layer. The dielectric layer is deposited in the plated through hole and partially covers the first circuit layer and the second circuit layer. The electroplating layer is formed on the dielectric layer, and the dielectric layer electrically isolates the electroplating layer from the plated through hole. Therefore, another plated through hole composed of the dielectric layer and the electroplating layer can be set in the plated through hole to achieve the effect of multilayer plated through holes, which can save the plated through hole setting space of the substrate and effectively utilize Substrate space to reduce the size of the substrate or for high-density circuit design.

【附图说明】【Description of drawings】

本案指定代表图为：图1The designated representative in this case is: Figure 1

本代表图的组件符号说明：Explanation of component symbols in this representative diagram:

100 基板100 substrates

110 基板主体        111 上表面110 Substratemain body 111 Upper surface

112 下表面112 lower surface

113 第一线路层      114 第二线路层113First line layer 114 Second line layer

115 镀通孔115 plated through holes

116 第一电镀层      117 第一环形垫116 The firstelectroplating layer 117 The first ring pad

118 第二环形垫118 second ring gasket

120 介电层          130 第二电镀层120dielectric layer 130 second electroplating layer

131 无电电镀层131 Electroless plating

132 延伸部132 extension

图1：依据本发明的第一具体实施例，一种基板的多层镀通孔的立体局部剖切示意图。Fig. 1: According to the first specific embodiment of the present invention, a three-dimensional partial cross-sectional schematic diagram of a multilayer plated through hole of a substrate.

图2：依据本发明的第一具体实施例，该具有多层镀通孔的基板的截面示意图。FIG. 2 is a schematic cross-sectional view of the substrate with multilayer plated through holes according to the first embodiment of the present invention.

图3A至3E：依据本发明的第一具体实施例，该基板于其多层镀通孔形成过程中的截面示意图。3A to 3E : schematic cross-sectional views of the substrate during the formation of multi-layer plated through holes according to the first embodiment of the present invention.

图4：依据本发明的第二具体实施例，另一种具有多层镀通孔的基板的截面示意图。FIG. 4 is a schematic cross-sectional view of another substrate with multilayer plated through holes according to the second embodiment of the present invention.

图5：依据本发明的第一具体实施例，电泳沉积以形成该基板的介电层的反应机构。Figure 5: Reaction mechanism for electrophoretic deposition to form the dielectric layer of the substrate according to the first embodiment of the present invention.

主要组件符号说明Explanation of main component symbols

11 干膜   12 干膜11Dry film 12 Dry film

21  干膜          22   干膜21dry film 22 dry film

100 基板100 substrates

110 基板主体      111  上表面110 Substratemain body 111 Upper surface

112 下表面112 lower surface

113 第一线路层    114  第二线路层113First line layer 114 Second line layer

115 镀通孔        115A 无电电镀层115 Plated throughhole 115A Electroless plating

116 第一电镀层    117  第一环形垫116 The firstelectroplating layer 117 The first ring pad

118 第二环形垫118 second ring gasket

119 贯穿孔119 through hole

120 介电层        130  第二电镀层120dielectric layer 130 second electroplating layer

131 无电电镀层131 Electroless plating

132 延伸部132 extension

200 基板200 substrates

210 基板主体      211  上表面210 Substratemain body 211 Upper surface

212 下表面212 lower surface

213 第一线路层    214  第二线路层213First line layer 214 Second line layer

215 镀通孔215 plated through hole

216 第一电镀层216 The first electroplating layer

220 第一介电层    230  第二电镀层220 firstdielectric layer 230 second electroplating layer

240 第二介电层    250  第三电镀层240 seconddielectric layer 250 third electroplating layer

【具体实施方式】【Detailed ways】

本发明的一实施例说明如下，如图1与图2所示，一种具有多层镀通孔的基板100包含一基板主体110，该基板主体110具有一上表面111与一下表面112，其可为多层印刷电路板。该基板主体110具有一第一线路层113、一第二线路层114以及一镀通孔115。该第一线路层113形成于该基板主体110的该上表面111；该第二线路层114形成于该基板主体110的该下表面112；该镀通孔115由该上表面111贯穿至该下表面112。该镀通孔115可包含有一无电电镀层115A及一第一电镀层116，以电性导接在该上表面111之该第一线路层113与在该下表面112的该第二线路层114。在本实施例中，该第一线路层113具有一第一环形垫117，且该第二线路层114具有一第二环形垫118，该第一电镀层116连接该第一环形垫117与该第二环形垫118。An embodiment of the present invention is described as follows, as shown in FIG. 1 and FIG. 2 , asubstrate 100 with multilayer plated through holes includes asubstrate body 110, and thesubstrate body 110 has anupper surface 111 and alower surface 112. Can be a multi-layer printed circuit board. Thesubstrate body 110 has afirst circuit layer 113 , asecond circuit layer 114 and a plated throughhole 115 . Thefirst circuit layer 113 is formed on theupper surface 111 of the substratemain body 110; thesecond circuit layer 114 is formed on thelower surface 112 of the substratemain body 110; the plated throughhole 115 penetrates from theupper surface 111 to the lower surface.Surface 112. The plated throughhole 115 may include anelectroless plating layer 115A and afirst electroplating layer 116 to electrically connect thefirst circuit layer 113 on theupper surface 111 with the second circuit layer on thelower surface 112 114. In this embodiment, thefirst circuit layer 113 has afirst ring pad 117, and thesecond circuit layer 114 has asecond ring pad 118, and thefirst electroplating layer 116 connects thefirst ring pad 117 and the The secondannular pad 118 .

在该镀通孔115内形成至少一另一镀通孔，其由一介电层120与一第二电镀层130所构成。At least one other plated through hole is formed in the plated throughhole 115 , which is composed of adielectric layer 120 and asecond electroplating layer 130 .

其中，该介电层120以沉积方式形成于该镀通孔115内，并且局部覆盖该第一线路层113与该第二线路层114。较佳地，该介电层120由电泳沉积(electrophoretic deposition)所形成，以使在该镀通孔115内形成的该介电层120具有厚度薄、厚度均匀且覆盖性佳的优点。该介电层120的沉积厚度介于10～50微米，不会有厚薄差异导致阻塞该镀通孔115的问题，此外，该介电层120的电泳沉积方式具有良好选择性，仅覆盖于裸露的金属表面，不会有使镀通孔内产生电性短路与塞孔的问题。而该第二电镀层130形成于该介电层120，并且由该介电层120电性隔离该第二电镀层130与该镀通孔115的该第一电镀层116。此外，在本实施例中，该介电层120能完全覆盖该第一环形垫117、该第二环形垫118与该第一电镀层116，该介电层120具有概呈「工」字且中心中空的截面，以达到良好的孔内电性隔离且中空孔径一致以利电镀该第二电镀层130的功效。Wherein, thedielectric layer 120 is deposited in the plated throughhole 115 and partially covers thefirst wiring layer 113 and thesecond wiring layer 114 . Preferably, thedielectric layer 120 is formed by electrophoretic deposition, so that thedielectric layer 120 formed in the plated throughhole 115 has the advantages of thin thickness, uniform thickness and good coverage. The deposition thickness of thedielectric layer 120 is between 10-50 microns, and there will be no problem of blocking the plated throughhole 115 due to thickness differences. In addition, the electrophoretic deposition method of thedielectric layer 120 has good selectivity, covering only the exposed metal surface, there will be no electrical short circuit and plug hole problems in the plated through hole. Thesecond electroplating layer 130 is formed on thedielectric layer 120 , and thesecond electroplating layer 130 is electrically isolated from thefirst electroplating layer 116 of the plated throughhole 115 by thedielectric layer 120 . In addition, in this embodiment, thedielectric layer 120 can completely cover thefirst ring pad 117, thesecond ring pad 118 and thefirst electroplating layer 116. The cross-section is hollow in the center to achieve good electrical isolation in the holes and the hollow holes have a uniform diameter to facilitate the effect of electroplating thesecond electroplating layer 130 .

如图2所示，该第二电镀层130形成于在该介电层120，并具有一延伸部132，其延伸至该基板主体110的该上表面111，该延伸部132并可连接至该第一线路层113的其它线路。此外，在该镀通孔115内可形成至少一第二电镀层130并由介电层120电性隔离不同层之该第二电镀层130，以使该第一电镀层116与该第二电镀层130可个别传递不同的电子讯号，以大幅减少基板100之镀通孔设置空间或是可供高密度基板100的应用。As shown in FIG. 2 , thesecond electroplating layer 130 is formed on thedielectric layer 120 and has anextension 132 extending to theupper surface 111 of thesubstrate body 110, and theextension 132 can be connected to the other lines of thefirst line layer 113 . In addition, at least onesecond electroplating layer 130 can be formed in the plated throughhole 115 and thesecond electroplating layer 130 of different layers can be electrically isolated by thedielectric layer 120, so that thefirst electroplating layer 116 and the second electroplating layer Thelayers 130 can individually transmit different electronic signals, so as to greatly reduce the space for setting the plated through holes of thesubstrate 100 or provide for the application of the high-density substrate 100 .

请参阅图3A至图3E绘示该基板100的多层镀通孔一种具体可实施的形成过程。首先，如图3A所示，提供一基板主体110，该基板主体110具有该第一线路层113与该第二线路层114，并利用机械或镭射钻孔方式形成一贯穿孔119，该贯穿孔119由该基板主体110的该上表面111贯穿至该基板100的该下表面112。在图3B中，利用无电电镀与电镀技术将铜层沉积于该贯穿孔119内，以形成包含有该无电电镀层115A与该第一电镀层116的该镀通孔115，并且该镀通孔115电性导接该第一线路层113与该第二线路层114。在本步骤中，该镀通孔115应为中空且不被填满，其中该第一电镀层116显露于该镀通孔115中。Please refer to FIG. 3A to FIG. 3E to illustrate a specific and practicable forming process of the multi-layer plated through hole of thesubstrate 100 . First, as shown in FIG. 3A , a substratemain body 110 is provided, the substratemain body 110 has thefirst circuit layer 113 and thesecond circuit layer 114, and a throughhole 119 is formed by mechanical or laser drilling, the throughhole 119 Theupper surface 111 of thesubstrate body 110 penetrates to thelower surface 112 of thesubstrate 100 . In FIG. 3B, a copper layer is deposited in the throughhole 119 using electroless plating and electroplating techniques to form the plated throughhole 115 including theelectroless plating layer 115A and thefirst electroplating layer 116, and the plating The viahole 115 electrically connects thefirst circuit layer 113 and thesecond circuit layer 114 . In this step, the plated throughhole 115 should be hollow and not filled, wherein thefirst electroplating layer 116 is exposed in the plated throughhole 115 .

接着，如图3C所示，在该基板主体110的该上表面111与该下表面112各形成一干膜11、12，经曝光显影，以局部覆盖该第一线路层113与该第二线路层114，该干膜11、12显露该第一电镀层116、该第一环形垫117与该第二环形垫118。之后，利用电泳沉积技术将该介电层120形成于该第一电镀层116、该第一环形垫117与该第二环形垫118。在本实施例中，该介电层120之材质可为聚醯亚胺(polymide，PI)，先将聚醯亚胺的前驱物以电泳沉积方式形成于金属表面，再烘烤以聚合成聚醯亚胺。而该介电层120电泳沉积的反应机构如图5的化学式所示。Next, as shown in FIG. 3C , adry film 11 and 12 are respectively formed on theupper surface 111 and thelower surface 112 of thesubstrate body 110 , exposed and developed to partially cover thefirst circuit layer 113 and the second circuit layer. 114 , thedry film 11 , 12 exposes thefirst electroplating layer 116 , the firstannular pad 117 and the secondannular pad 118 . Afterwards, thedielectric layer 120 is formed on thefirst electroplating layer 116 , thefirst ring pad 117 and thesecond ring pad 118 by electrophoretic deposition technology. In this embodiment, the material of thedielectric layer 120 can be polyimide (polymide, PI). Firstly, the precursor of polyimide is formed on the metal surface by electrophoretic deposition, and then baked to polymerize into polyimide. imide. The reaction mechanism of the electrophoretic deposition of thedielectric layer 120 is shown in the chemical formula of FIG. 5 .

在移除该些干膜11、12之后，如图3D所示，再形成一干膜21、22于该基板主体110的该上表面111与该下表面112。在本实施例中，经曝光显影之后，该干膜21、22局部显露该介电层120以及局部显露该基板主体110的该上表面111与该下表面112。之后，一无电电镀层131(electroless plating layer)形成于该介电层120及该基板主体110的该上表面111与该下表面112的显露部位。接着，如图3E所示，利用电镀技术可将该第二电镀层130形成于该无电电镀层131，该第二电镀层130可电性连接该第一线路层113与该第二线路层114，并与该第一电镀层116为电性隔离。最后，移除该些干膜21、22并进行后制程的加工，例如热层合、电镀等等，以形成该具有多层镀通孔的基板100。After removing thedry films 11 , 12 , as shown in FIG. 3D , adry film 21 , 22 is formed on theupper surface 111 and thelower surface 112 of the substratemain body 110 . In this embodiment, after exposure and development, thedry films 21 and 22 partially expose thedielectric layer 120 and partially expose theupper surface 111 and thelower surface 112 of thesubstrate body 110 . Afterwards, anelectroless plating layer 131 is formed on thedielectric layer 120 and exposed portions of theupper surface 111 and thelower surface 112 of thesubstrate body 110 . Next, as shown in FIG. 3E , thesecond electroplating layer 130 can be formed on theelectroless plating layer 131 by electroplating technology, and thesecond electroplating layer 130 can electrically connect thefirst circuit layer 113 and the second circuit layer. 114, and is electrically isolated from thefirst electroplating layer 116. Finally, thedry films 21 , 22 are removed and post-process processing is performed, such as thermal lamination, electroplating, etc., to form thesubstrate 100 with multi-layer plated through holes.

本发明的另一实施例说明如下，如图4所示，另一种具有多层镀通孔的基板200，其包含一基板主体210，该基板主体210具有一上表面211与一下表面212，且该基板主体210具有一第一线路层213、一第二线路层214以及一镀通孔215，在该镀通孔215内依续间隔形成一电镀层及一介电层。该镀通孔215具有一第一电镀层216，以电性导接该第一线路层213与该第二线路层214，一第一介电层220以沉积方式形成于该镀通孔215内并局部覆盖该第一线路层213与该第二线路层214，一第二电镀层230形成于该第一介电层220，并由该第一介电层220电性隔离该第一电镀层216与该第二电镀层230，在本实施例中，该第二电镀层230为一金属屏蔽层，其为电性独立或是仅连接至该基板200的接地结构。一第二介电层240形成于该镀通孔215内且亦以沉积方式形成于该第二电镀层230，一第三电镀层250形成于该镀通孔215内且形成于该第二介电层240，且该第二介电层240电性隔离该第二电镀层230与该第三电镀层250。该第三电镀层250电性连接该第一线路层213与该第二线路层214，或者可电性连接其它线路层。由该第二电镀层230的金属屏蔽效果，有效防止该第一电镀层216与该第三电镀层250间产生串音或讯号干扰的现象，以提升高密度基板200内多层镀通孔215的电性效能。Another embodiment of the present invention is described as follows. As shown in FIG. 4 , anothersubstrate 200 with multilayer plated through holes includes asubstrate body 210 , thesubstrate body 210 has anupper surface 211 and alower surface 212 , And the substratemain body 210 has afirst circuit layer 213 , asecond circuit layer 214 and a plated throughhole 215 , and an electroplating layer and a dielectric layer are sequentially formed in the plated throughhole 215 . The plated throughhole 215 has afirst electroplating layer 216 to electrically connect thefirst circuit layer 213 and thesecond circuit layer 214, and a firstdielectric layer 220 is formed in the plated throughhole 215 by deposition. and partially cover thefirst circuit layer 213 and thesecond circuit layer 214, asecond electroplating layer 230 is formed on thefirst dielectric layer 220, and the first electroplating layer is electrically isolated by thefirst dielectric layer 220 216 and thesecond electroplating layer 230 , in this embodiment, thesecond electroplating layer 230 is a metal shielding layer, which is electrically independent or only connected to the ground structure of thesubstrate 200 . Asecond dielectric layer 240 is formed in the plated throughhole 215 and is also deposited on thesecond electroplating layer 230, and athird electroplating layer 250 is formed in the plated throughhole 215 and formed on the second dielectric layer. Theelectrical layer 240 , and thesecond dielectric layer 240 electrically isolates thesecond electroplating layer 230 from thethird electroplating layer 250 . Thethird electroplating layer 250 is electrically connected to thefirst circuit layer 213 and thesecond circuit layer 214 , or can be electrically connected to other circuit layers. The metal shielding effect of thesecond electroplating layer 230 can effectively prevent crosstalk or signal interference between thefirst electroplating layer 216 and thethird electroplating layer 250, so as to improve the multilayer plated throughhole 215 in the high-density substrate 200. electrical performance.

本发明的保护范围当视后附的权利要求书所界定者为准，任何熟知此项技艺者，在不脱离本发明的精神和范围内所作的任何变化与修改，均属于本发明的保护范围.The scope of protection of the present invention should be defined by the appended claims as the criterion. Any changes and modifications made by anyone who is familiar with the art without departing from the spirit and scope of the present invention all belong to the scope of protection of the present invention. .

Claims (10)

1. the substrate with multilayer plated-through-hole is characterized in that, comprises:

One base main body, it has one first line layer, one second line layer and a plated-through-hole, and this plated-through-hole includes one first electrodeposited coating, to be electrically conducted this first line layer and this second line layer;

One dielectric layer, it is formed in this plated-through-hole and local this first line layer and this second line layer of covering with depositional mode; And

One second electrodeposited coating, it is formed at this dielectric layer, and by this first electrodeposited coating of this second electrodeposited coating of this dielectric layer electrical isolation and this plated-through-hole.

2. the substrate with multilayer plated-through-hole as claimed in claim 1 is characterized in that wherein this dielectric layer has generally the cross section that is " worker " word and center hollow.

3. the substrate with multilayer plated-through-hole as claimed in claim 1, it is characterized in that, wherein this first line layer has one first air ring, and this second line layer has one second air ring, this first electrodeposited coating connects this first air ring and this second air ring, and this dielectric layer covers this first air ring, this second air ring and this first electrodeposited coating fully.

4. the substrate with multilayer plated-through-hole as claimed in claim 1 is characterized in that, wherein this second electrodeposited coating extends on this base main body, and is connected to this first line layer.

5. the substrate with multilayer plated-through-hole as claimed in claim 1 is characterized in that, other includes one second dielectric layer and one the 3rd electrodeposited coating, and it is formed at this plated-through-hole, and this this second electrodeposited coating of second dielectric layer electrical isolation and the 3rd electrodeposited coating.

6. the substrate with multilayer plated-through-hole as claimed in claim 1 is characterized in that, wherein is formed with an electroless-plating layer (electroless plating layer) between this dielectric layer and this second electrodeposited coating in addition.

7. the formation method of the multilayer plated-through-hole of a substrate is characterized in that, comprises:

One base main body is provided, and it has one first line layer, one second line layer and a plated-through-hole, and this plated-through-hole includes one first electrodeposited coating, to be electrically conducted this first line layer and this second line layer;

Form a dielectric layer also local this first line layer and this second line layer of covering in this plated-through-hole with depositional mode; And

Form one second electrodeposited coating, it is formed at this dielectric layer, and by this first electrodeposited coating of this second electrodeposited coating of this dielectric layer electrical isolation and this plated-through-hole.

8. the formation method of the multilayer plated-through-hole of substrate as claimed in claim 7 is characterized in that, wherein this dielectric layer is formed at this first electrodeposited coating in electrophoretic deposition (electrophoretic deposition) mode.

9. the formation method of the multilayer plated-through-hole of substrate as claimed in claim 7, it is characterized in that, wherein this first line layer has one first air ring, and this second line layer has one second air ring, this first electrodeposited coating connects this first air ring and this second air ring, and this dielectric layer covers this first air ring, this second air ring and this first electrodeposited coating fully;

Wherein this second electrodeposited coating extends on this base main body, and is connected to this first line layer.

10. the formation method of the multilayer plated-through-hole of substrate as claimed in claim 7, it is characterized in that, other includes: form one second dielectric layer and one the 3rd electrodeposited coating in this plated-through-hole, and this this second electrodeposited coating of second dielectric layer electrical isolation and the 3rd electrodeposited coating;

Before forming this second electrodeposited coating, be formed with an electroless-plating layer (electroless plating layer) in this dielectric layer.

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