CN101149630A - DDS Signal Source Amplitude-Frequency Compensation Method and Corresponding DDS Signal Source - Google Patents

Abstract

Translated fromChinese

本发明提供了一种通过数字滤波对DDS信号源进行幅频特性补偿的方法及相应的DDS信号源，在现有DDS信号源的RAM查找表和数模转换器(DAC)之间增设一个数字滤波模块和一个选择开关。在该DDS信号源投入实际应用前，设置选择开关使RAM查找表输出的数据直接送到DAC进行数模转换，通过测试输出信号获取信号源的幅频特性函数，对该函数取倒数，利用频率抽样法计算得到数字滤波模块的抽头系数，将抽头系数填入数字滤波模块的抽头系数查找表，再设置选择开关，让RAM查找表输出的数据通过数字滤波模块后再输出到DAC进行数模转换，从而实现DDS信号源的幅频特性校正。

The invention provides a method for compensating the amplitude-frequency characteristics of a DDS signal source through digital filtering and the corresponding DDS signal source. A digital filter is added between the RAM lookup table and the digital-to-analog converter (DAC) of the existing DDS signal source. filter module and a selector switch. Before the DDS signal source is put into practical application, set the selection switch so that the data output by the RAM lookup table is directly sent to the DAC for digital-to-analog conversion. The amplitude-frequency characteristic function of the signal source is obtained by testing the output signal, and the reciprocal of this function is taken. The sampling method calculates the tap coefficient of the digital filter module, fills the tap coefficient into the tap coefficient lookup table of the digital filter module, and then sets the selection switch to let the data output by the RAM lookup table pass through the digital filter module and then output to the DAC for digital-to-analog conversion , so as to realize the amplitude-frequency characteristic correction of the DDS signal source.

Description

Translated fromChinese

DDS信号源幅频特性补偿方法及相应的DDS信号源DDS Signal Source Amplitude-Frequency Compensation Method and Corresponding DDS Signal Source

技术领域technical field

本发明涉及DDS信号发生器领域，特别涉及一种能够有效的改善因DAC保持特性以及椭圆滤波器通带内纹波起伏所引起的信号幅频特性不平坦的方法及其装置。The invention relates to the field of DDS signal generators, in particular to a method and device capable of effectively improving the unevenness of signal amplitude-frequency characteristics caused by DAC retention characteristics and ripple fluctuations in the passband of an elliptic filter.

背景技术Background technique

DDS(直接数字合成)是继直接频率合成技术和锁相环式频率合成技术之后的第三代频率合成技术，它凭借其相对带宽宽、转换时间短、分辨率高、输出相位连续、可产生宽带正交信号及其它多种调制信号、可编程、全数字化以及控制灵活方便等特性，近年来在信号发生器领域得到普遍应用。DDS信号源基本结构主要由相位累加器、波形RAM、数模转换器(DAC)以及低通滤波器等组成。相位累加器在取样时钟控制下与频率控制字所决定的相位增量相加；相位累加器的高位输出作为波形RAM的地址，实现波形相位到幅值的转换；波形数据经DAC转换成模拟量，通过低通滤波器输出相对平滑的波形。DDS (Direct Digital Synthesis) is the third-generation frequency synthesis technology after direct frequency synthesis technology and phase-locked loop frequency synthesis technology. It relies on its relatively wide bandwidth, short conversion time, high resolution, continuous output phase, and can generate Broadband quadrature signals and other modulation signals, programmable, fully digital, and flexible and convenient control have been widely used in the field of signal generators in recent years. The basic structure of the DDS signal source is mainly composed of a phase accumulator, a waveform RAM, a digital-to-analog converter (DAC) and a low-pass filter. The phase accumulator is added to the phase increment determined by the frequency control word under the control of the sampling clock; the high-order output of the phase accumulator is used as the address of the waveform RAM to realize the conversion of the waveform phase to the amplitude; the waveform data is converted into an analog quantity by DAC , a relatively smooth waveform is output through a low-pass filter.

低通滤波器在DDS中起着保持有效分量、抑制杂波的作用，对输出波形质量的好坏起着至关重要的作用。对于正弦信号，根据奈奎斯特采样理论，输出信号的谐波分量将出现在kf_S±f₀处，其中f_S是采样时钟的频率，f₀是输出信号的频率。在DDS信号源中常选用过渡特性陡峭的椭圆滤波器完成对正弦信号的滤波，保证正弦信号的谐波抑制，但椭圆滤波器的幅频特性在通带和阻带内都具有纹波起伏。此外，由于目前DAC实现的并非是理想的单位冲击采样，而是采用零阶保持技术，其传递函数具有sinx/x的包络特性。因此，基于DDS的信号源其通带幅频特性不平坦。The low-pass filter plays a role in maintaining effective components and suppressing clutter in DDS, and plays a vital role in the quality of the output waveform. For a sinusoidal signal, according to the Nyquist sampling theory, the harmonic components of the output signal will appear at kf_S ± f₀ , where f_S is the frequency of the sampling clock and f₀ is the frequency of the output signal. In the DDS signal source, an elliptic filter with steep transition characteristics is often used to filter the sinusoidal signal to ensure harmonic suppression of the sinusoidal signal, but the amplitude-frequency characteristics of the elliptic filter have ripple fluctuations in both the passband and the stopband. In addition, because the current DAC is not an ideal unit impact sampling, but uses a zero-order hold technology, its transfer function has a sinx/x envelope characteristic. Therefore, the signal source based on DDS has uneven passband amplitude-frequency characteristics.

目前，DDS信号源常采用LC谐振电路并结合软件的方法来进行幅频特性的校正，但由于电感、电容数值的偏差以及电路板寄生电容与寄生电感的影响，所实现的LC谐振电路与理论计算值具有一定的偏差，且每次需要专业设计人员进行调节，费时费力。而软件校正的方法只能实现点频上的校正，无法实现扫频、调频等波形的幅度校正。At present, DDS signal sources often use LC resonant circuits combined with software methods to correct the amplitude-frequency characteristics, but due to the deviation of inductance and capacitance values and the influence of circuit board parasitic capacitance and parasitic inductance, the realized LC resonant circuit and theory The calculated value has a certain deviation, and professional designers need to adjust each time, which is time-consuming and labor-intensive. However, the method of software correction can only realize the correction on point frequency, and cannot realize the amplitude correction of waveforms such as frequency sweep and frequency modulation.

发明内容Contents of the invention

本发明的目的是为DDS信号发生器(又称DDS信号源)提供一种通过数字滤波进行幅频特性补偿的技术。The purpose of the present invention is to provide a technique for compensating the amplitude-frequency characteristics through digital filtering for a DDS signal generator (also known as a DDS signal source).

本发明是在现有DDS信号源的RAM查找表和数模转换器(DAC)之间增设一个数字滤波模块和一个选择开关(参见图1)，RAM查找表输出的幅度信息由选择开关进行切换，选择是将幅度信息经过数字滤波模块进行幅度预校正后再进行数模转换，还是直接将幅度信息送到DAC进行数模转换。DDS信号源在投入实际应用前，通过数字滤波进行幅频特性补偿(即校正)，具体的校正步骤如下：The present invention is to set up a digital filtering module and a selector switch (referring to Fig. 1) between the RAM lookup table of existing DDS signal source and the digital-to-analog converter (DAC), and the amplitude information output by the RAM lookup table is switched by the selector switch , choose whether to pre-correct the amplitude information through the digital filter module before performing digital-to-analog conversion, or directly send the amplitude information to the DAC for digital-to-analog conversion. Before the DDS signal source is put into practical application, the amplitude-frequency characteristic is compensated (that is, corrected) through digital filtering. The specific correction steps are as follows:

1)设置选择开关，选择将RAM查找表输出的数据直接送到DAC进行数模转换：1) Set the selector switch, choose to send the data output by the RAM lookup table directly to the DAC for digital-to-analog conversion:

2)通过测试DDS信号源的输出信号获取该信号源的幅频特性函数；2) Obtain the amplitude-frequency characteristic function of the signal source by testing the output signal of the DDS signal source;

3)对所获取的幅频特性函数取倒数；3) taking the reciprocal of the obtained amplitude-frequency characteristic function;

4)根据幅频特性函数的倒数利用频率抽样法计算数字滤波模块的抽头系数；4) Utilize the frequency sampling method to calculate the tap coefficient of the digital filtering module according to the reciprocal of the amplitude-frequency characteristic function;

5)将抽头系数填入数字滤波模块的抽头系数查找表；5) fill in the tap coefficient look-up table of the digital filtering module with the tap coefficient;

6)设置选择开关，让RAM查找表输出的数据通过数字滤波模块后输出到DAC。6) Set the selection switch so that the data output by the RAM lookup table is output to the DAC after passing through the digital filtering module.

本发明的另一个目的是提供一种实现上述进行幅频特性补偿方法的DDS信号源。本发明的DDS信号源主要由波形数据合成模块、数字滤波模块、选择开关、DAC及信号调理模块、中央处理模块(CPU)几部分及与之相对应的处理软件组成，分述如下：Another object of the present invention is to provide a DDS signal source for realizing the above-mentioned amplitude-frequency characteristic compensation method. DDS signal source of the present invention is mainly made up of waveform data synthesis module, digital filtering module, selector switch, DAC and signal conditioning module, central processing module (CPU) several parts and corresponding processing software, is described as follows:

1)波形数据合成模块主要由相位累加器、RAM查找表、采样时钟并辅以相应的逻辑控制电路组成，负责在采样时钟信号同步的情况下完成所需频率的高速波形数据产生功能。1) The waveform data synthesis module is mainly composed of a phase accumulator, a RAM lookup table, a sampling clock and a corresponding logic control circuit. It is responsible for completing the high-speed waveform data generation function of the required frequency under the synchronization of the sampling clock signal.

2)数字滤波模块是本发明的核心，如图2，它包括数据存储单元、抽头系数查找表、乘法器、累加器、状态控制逻辑单元：波形数据合成模块中的采样时钟分别与状态控制逻辑单元和累加器连接；状态控制逻辑单元输出控制信号对数据存储单元、抽头系数查找表和累加器进行控制；数据存储单元的输出与抽头系数查找表的输出送到乘法器完成相乘操作，其输出又送到累加器，由累加器输出校正后的幅度信息。2) digital filtering module is the core of the present invention, as Fig. 2, it comprises data storage unit, tap coefficient look-up table, multiplier, accumulator, state control logic unit: the sampling clock in the waveform data synthesis module is connected with state control logic respectively The unit is connected to the accumulator; the state control logic unit outputs control signals to control the data storage unit, the tap coefficient look-up table and the accumulator; the output of the data storage unit and the output of the tap coefficient look-up table are sent to the multiplier to complete the multiplication operation. The output is sent to the accumulator again, and the corrected amplitude information is output from the accumulator.

3)选择开关同时连接RAM查找表和数字滤波模块的累加器，由其选择是将幅度信息直接还是经过数字滤波模块进行幅度预校正后送到DAC进行数模转换。3) The selection switch is connected to the RAM look-up table and the accumulator of the digital filter module at the same time, and it is selected whether to send the amplitude information directly or to the DAC for digital-to-analog conversion after being pre-corrected by the digital filter module.

4)DAC及信号调理模块负责完成预校正后的幅度信息的数字一模拟转换，并对模拟信号进行滤波、调节信号的幅度与偏移。4) The DAC and signal conditioning module are responsible for completing the digital-to-analog conversion of the pre-corrected amplitude information, filtering the analog signal, and adjusting the amplitude and offset of the signal.

5)中央处理模块主要由一片高性能的DSP(数字信号处理器)组成，对整个系统进行总体控制，主要负责波形数据传送、相位累加器控制、数字滤波模块参数设定等工作，并对选择开关进行控制。5) The central processing module is mainly composed of a high-performance DSP (Digital Signal Processor), which controls the entire system and is mainly responsible for waveform data transmission, phase accumulator control, digital filter module parameter setting, etc. switch to control.

本发明DDS信号源的工作原理如图1所示，根据CPU设置的频率控制字，相位累加器在采样时钟的控制下产生地址信号对RAM查找表进行寻址，RAM查找表将波形的相位信息转换为幅度信息，其中，输出信号频率f_o与频率控制字f_REG、采样时钟频率f_clk和相位累加器的位数N之间的关系为：The working principle of the DDS signal source of the present invention is shown in Figure 1. According to the frequency control word set by the CPU, the phase accumulator generates an address signal under the control of the sampling clock to address the RAM lookup table, and the RAM lookup table converts the phase information of the waveform Converted to amplitude information, where the relationship between the output signal frequency f_o and the frequency control word f_REG , the sampling clock frequency f_clk and the number of bits N of the phase accumulator is:

${\mathrm{<span><span>f</span>f</span>}}_{\mathrm{<span><span>O</span>o</span>}}<span><span>=</span>=</span>\frac{{\mathrm{<span><span>f</span>f</span>}}_{\mathrm{<span><span>REG</span>REG</span>}}}{{\mathrm{<span><span>2</span>2</span>}}^{\mathrm{<span><span>N</span>N</span>}}}{\mathrm{<span><span>f</span>f</span>}}_{\mathrm{<span><span>clk</span>clk</span>}}<span><span>-</span>-</span><span><span>-</span>-</span><span><span>-</span>-</span><span><span>(</span>(</span>\mathrm{<span><span>1</span>1</span>}<span><span>)</span>)</span>$

RAM查找表输出的幅度信息由选择开关进行切换，选择是将幅度信息经过数字滤波模块进行幅度预校正后进行数模转换还是直接将幅度信息送到DAC进行数模转换。The amplitude information output by the RAM lookup table is switched by the selector switch, and it is selected whether to perform digital-to-analog conversion after the amplitude information is pre-corrected by the digital filter module or to directly send the amplitude information to the DAC for digital-to-analog conversion.

在数字滤波模块中(参见图2)，状态控制逻辑单元在采样时钟的控制下进行状态的改变，根据当前状态的不同输出控制信息给数据存储单元、抽头系数查找表和累加器单元。数据存储单元在状态逻辑控制单元的控制下将RAM查找表输出的幅度信息存放在相应的存储位置并选择相应的幅度信息输出给乘法器，抽头系数查找表也在状态逻辑控制单元的控制之下将相应的抽头系数传送给乘法器，抽头系数由上述校正方法步骤1)-4)得到。乘法器完成幅度信息与抽头系数的相乘后将结果送到累加器单元进行累加操作。这一过程所实现的数字滤波模块的传递函数$H\left(e^{\mathrm{j\&omega;}}\right)=\underset{n=0}{\overset{N-1}{\mathrm{\&Sigma;}}}h\left(n\right)e^{-\mathrm{j\&omega;n}},$其中：H(e^jw)是数字滤波模块的频率响应，ω是角频率，h(n)是抽头系数，N为正整数，代表所截取的点数。整个幅频预校正数字滤波模块均可在一个FPGA(现场可编程逻辑阵列)内部实现。In the digital filter module (see Figure 2), the state control logic unit changes the state under the control of the sampling clock, and outputs control information to the data storage unit, tap coefficient lookup table and accumulator unit according to the current state. Under the control of the state logic control unit, the data storage unit stores the amplitude information output by the RAM lookup table in the corresponding storage location and selects the corresponding amplitude information to output to the multiplier. The tap coefficient lookup table is also under the control of the state logic control unit. The corresponding tap coefficients are sent to the multiplier, and the tap coefficients are obtained from steps 1)-4) of the correction method above. After the multiplier completes the multiplication of the amplitude information and the tap coefficient, the result is sent to the accumulator unit for accumulation operation. The transfer function of the digital filter module realized by this process is$h\left(e^{\mathrm{j\&omega;}}\right)=\underset{\mathrm{no}=0}{\overset{N-1}{\mathrm{\&Sigma;}}}h\left(\mathrm{no}\right)e^{-\mathrm{j\&omega;n}},$ Among them: H(e^jw ) is the frequency response of the digital filter module, ω is the angular frequency, h(n) is the tap coefficient, N is a positive integer, representing the number of intercepted points. The entire amplitude-frequency pre-correction digital filtering module can be realized inside an FPGA (Field Programmable Logic Array).

预校正以后的波形数据送DAC实现数字信号到模拟信号的转换。DAC输出的信号经过信号调理通道处理后得到最终的波形输出。The waveform data after pre-calibration is sent to DAC to realize the conversion from digital signal to analog signal. The signal output by the DAC is processed by the signal conditioning channel to obtain the final waveform output.

本发明的DDS信号源中，相位累加器、数字滤波模块与选择开关均可集成在一款高性能的FPGA内部实现。In the DDS signal source of the present invention, the phase accumulator, the digital filter module and the selection switch can be integrated in a high-performance FPGA for internal realization.

本发明为基于DDS的信号源(函数发生器或任意波形发生器)提供了一种全数字化的幅频特性校正功能。其实现成本低廉，性价比很高。用户只需要设置所需校正的幅频特性曲线的相关参数，即可获取数字滤波器相应的抽头系数。根据获得的抽头系数修改相应的参数，即可完成相应的幅频特性校正。并且，因为本发明所校正的幅频特性是由信号源的输出端测试获得，所以校准的对象不仅仅是由于滤波器和DAC采样保持所引起的幅频特性不平坦，还包括后续通道幅度精调、衰减、放大等部分由于元器件值的影响所产生的幅频特性不平坦。The invention provides a fully digital amplitude-frequency characteristic correction function for a DDS-based signal source (function generator or arbitrary waveform generator). In fact, the implementation cost is low and the cost performance is high. The user only needs to set the relevant parameters of the amplitude-frequency characteristic curve to be corrected, and then the corresponding tap coefficient of the digital filter can be obtained. Modify the corresponding parameters according to the obtained tap coefficients to complete the correction of the corresponding amplitude-frequency characteristics. And, because the amplitude-frequency characteristic corrected by the present invention is obtained by testing the output end of the signal source, the object of calibration is not only the uneven amplitude-frequency characteristic caused by the filter and DAC sampling and holding, but also the subsequent channel amplitude accuracy. Adjustment, attenuation, amplification, etc. are partially due to the uneven amplitude-frequency characteristics caused by the influence of component values.

附图说明Description of drawings

图1是本发明DDS信号源的整体原理框图。Fig. 1 is the overall functional block diagram of the DDS signal source of the present invention.

图2是数字滤波模块的原理框图。Fig. 2 is the functional block diagram of the digital filtering module.

具体实施方式Detailed ways

下面结合附图，通过实施例进一步说明本发明，但不以任何方式限制本发明的范围。Below in conjunction with accompanying drawing, further illustrate the present invention through embodiment, but do not limit the scope of the present invention in any way.

如图1所示，在本发明的DDS信号源中，波形数据合成模块主要包括高速相位累加器、RAM查找表和采样时钟。RAM查找表可以根据所设计的信号源要达到的波形存储深度与采样速率来选择，一般选择的存储深度为64K*12bit。高速相位累加器也需根据信号源频率分辨率的要求来设计，满足公式Δf＝f_clk/2^N，其中f_clk为采样时钟的频率，N为相位累加器的位数，Δf为频率分辨率。目前FPGA工作速度快，内部资源丰富，是高速相位累加设计的首选，本发明推荐使用高性能的FPGA。As shown in Fig. 1, in the DDS signal source of the present invention, the waveform data synthesis module mainly includes a high-speed phase accumulator, a RAM look-up table and a sampling clock. The RAM lookup table can be selected according to the waveform storage depth and sampling rate to be achieved by the designed signal source, and the generally selected storage depth is 64K*12bit. The high-speed phase accumulator also needs to be designed according to the frequency resolution requirements of the signal source, satisfying the formula Δf=f_clk /2^N , where f_clk is the frequency of the sampling clock, N is the number of bits of the phase accumulator, and Δf is the frequency resolution . At present, FPGA has fast working speed and abundant internal resources, and is the first choice for high-speed phase accumulation design. The present invention recommends using FPGA with high performance.

DDS信号源幅频特性函数的获取主要通过矢量网络分析仪来完成。矢量网络分析仪实际上是一个扫频源外加一个频谱分析仪，通过矢量网络分析仪，可以获得所设计的信号发生器的通道的幅频特性。The acquisition of the amplitude-frequency characteristic function of the DDS signal source is mainly completed by a vector network analyzer. The vector network analyzer is actually a frequency sweep source plus a spectrum analyzer. Through the vector network analyzer, the amplitude-frequency characteristics of the channel of the designed signal generator can be obtained.

数字滤波模块如图2所示，包括数据存储单元、抽头系数查找表、高速乘法器、高速累加器、状态控制逻辑单元。根据所获取的信号发生器幅频特性，可以计算出抽头系数h(0)～h(N-1)，其计算方法采用频率抽样法。将计算好的抽头系数填入数字滤波模块的抽头系数查找表中。其中抽头系数的个数取决于系统的工作频率与误差要求，一般N＞16。数字滤波的实施也完全集成在FPGA中。The digital filtering module is shown in Figure 2, including a data storage unit, a tap coefficient lookup table, a high-speed multiplier, a high-speed accumulator, and a state control logic unit. According to the obtained amplitude-frequency characteristics of the signal generator, the tap coefficients h(0)~h(N-1) can be calculated, and the calculation method adopts the frequency sampling method. Fill the calculated tap coefficients into the tap coefficient lookup table of the digital filtering module. The number of tap coefficients depends on the operating frequency and error requirements of the system, generally N>16. The implementation of the digital filtering is also fully integrated in the FPGA.

CPU建议选用高速、高性能的嵌入式处理器，用来完成整个系统的调度，包括控制相位累加器的频率控制字，传送RAM查找表的波形数据，设置数字滤波模块的参数，并对选择开关进行控制。The CPU is recommended to use a high-speed, high-performance embedded processor to complete the scheduling of the entire system, including controlling the frequency control word of the phase accumulator, transmitting the waveform data of the RAM lookup table, setting the parameters of the digital filter module, and selecting the switch Take control.

本发明在CPCI接口的DDS信号源中得到了应用，该信号源采样频率为40MSa/S，最大输出正弦信号频率为15MHz。使用罗德施瓦茨公司的手持式频谱仪FSH3测得信号源输出幅度为500mV时，校正前后的幅值对照表，如表1所示。可见未校正前，幅度不平坦最大差距为2.5dB，经过校正后，差距缩小为0.5dB。很好的改善了信号源的幅频特性。The invention is applied in the DDS signal source of the CPCI interface, the sampling frequency of the signal source is 40MSa/S, and the maximum output sinusoidal signal frequency is 15MHz. When the handheld spectrum analyzer FSH3 of Rohde & Schwarz is used to measure the output amplitude of the signal source is 500mV, the amplitude comparison table before and after correction is shown in Table 1. It can be seen that before correction, the maximum difference in amplitude unevenness is 2.5dB, and after correction, the difference is reduced to 0.5dB. It improves the amplitude-frequency characteristics of the signal source very well.

表1Table 1

  输出频率 Output frequency  校正前的幅值(dBmV)Amplitude before correction (dBmV)  校正后的幅值(dBmV)Corrected amplitude (dBmV)  100kHz500KHz1MHz5MHz10MHz15MHz100kHz500KHz1MHz5MHz10MHz15MHz  54.053.953.853.452.551.554.053.953.853.452.551.5  54.054.053.953.953.654.154.054.053.953.953.654.1

Claims (7)

Translated fromChinese

1.一种DDS信号源幅频特性补偿方法，在DDS信号源的RAM查找表和数模转换器之间设置一个数字滤波模块和一个选择开关，依据下列步骤进行幅频特性校正：1. A DDS signal source amplitude-frequency characteristic compensation method, a digital filtering module and a selector switch are set between the RAM look-up table and the digital-to-analog converter of the DDS signal source, and the amplitude-frequency characteristic correction is carried out according to the following steps:1)设置选择开关，选择将RAM查找表输出的数据直接送到数模转换器进行数模转换；1) Set the selector switch to select the data output by the RAM lookup table to be directly sent to the digital-to-analog converter for digital-to-analog conversion;2)通过测试DDS信号源的输出信号获取该信号源的幅频特性函数；2) Obtain the amplitude-frequency characteristic function of the signal source by testing the output signal of the DDS signal source;3)对所获取的幅频特性函数取倒数；3) taking the reciprocal of the obtained amplitude-frequency characteristic function;4)根据幅频特性函数的倒数利用频率抽样法计算数字滤波模块的抽头系数；4) Utilize the frequency sampling method to calculate the tap coefficient of the digital filtering module according to the reciprocal of the amplitude-frequency characteristic function;5)将抽头系数填入数字滤波模块的抽头系数查找表；5) fill in the tap coefficient look-up table of the digital filtering module with the tap coefficient;6)设置选择开关，让RAM查找表输出的数据通过数字滤波模块后输出到数模转换器。6) The selection switch is set so that the data output by the RAM look-up table is output to the digital-to-analog converter after passing through the digital filter module.2.根据权利要求1所述的DDS信号源幅频特性补偿方法，其特征在于：在所述步骤2)利用矢量网络分析仪获取DDS信号源的幅频特性函数。2. DDS signal source amplitude-frequency characteristic compensation method according to claim 1, is characterized in that: in said step 2) utilize vector network analyzer to obtain the amplitude-frequency characteristic function of DDS signal source.3.一种DDS信号源，包括：3. A DDS signal source, comprising:进行系统总体控制的中央处理模块；Central processing module for overall system control;产生所需频率波形数据的波形数据合成模块；A waveform data synthesis module that generates waveform data of the required frequency;将波形数据从数字信号转换为模拟信号的数模转换器；以及A digital-to-analog converter that converts the waveform data from digital to analog; and对模拟信号进行滤波、调节信号的幅度与偏移并输出的信号调理模块；A signal conditioning module that filters the analog signal, adjusts the amplitude and offset of the signal and outputs it;其特征在于，该DDS信号源在波形数据合成模块和数模转换器之间还设置有数字滤波模块和选择开关，数字滤波模块将波形数据合成模块输出的波形数据幅度信息进行幅度预校正后送到选择开关，而选择开关同时连接波形数据合成模块和数字滤波模块，在中央处理模块的控制下进行切换，选择是将波形数据合成模块产生的幅度信息直接还是经过数字滤波模块进行幅度预校正后送到数模转换器进行数模转换。It is characterized in that the DDS signal source is also provided with a digital filter module and a selection switch between the waveform data synthesis module and the digital-to-analog converter, and the digital filter module performs amplitude pre-correction on the amplitude information of the waveform data output by the waveform data synthesis module and then sends it to to the selection switch, and the selection switch is connected to the waveform data synthesis module and the digital filter module at the same time, and is switched under the control of the central processing module to select whether to use the amplitude information generated by the waveform data synthesis module directly or after the amplitude pre-correction by the digital filter module sent to the digital-to-analog converter for digital-to-analog conversion.4.根据权利要求3所述的DDS信号源，其特征在于：所述波形数据合成模块主要由相位累加器、RAM查找表、采样时钟并辅以相应的逻辑控制电路组成，相位累加器根据中央处理模块设置的频率控制字，在采样时钟的控制下产生地址信号对RAM查找表进行寻址，RAM查找表将波形的相位信息转换为幅度信息。4. DDS signal source according to claim 3, it is characterized in that: described waveform data synthesizing module is mainly made up of phase accumulator, RAM look-up table, sampling clock and is supplemented with corresponding logical control circuit, and phase accumulator is according to central The frequency control word set by the processing module generates an address signal under the control of the sampling clock to address the RAM lookup table, and the RAM lookup table converts the phase information of the waveform into amplitude information.5.根据权利要求4所述的DDS信号源，其特征在于，所述数字滤波模块包括数据存储单元、抽头系数查找表、乘法器、累加器和状态控制逻辑单元，其中：状态控制逻辑单元和累加器分别与波形数据合成模块中的采样时钟连接；数据存储单元与RAM查找表的输出端连接；状态控制逻辑单元在采样时钟的控制下进行状态的改变，根据当前状态的不同输出控制信息给数据存储单元、抽头系数查找表和累加器，数据存储单元将波形数据合成模块产生的幅度信息存放在相应的存储位置并选择相应的幅度信息输出给乘法器，抽头系数查找表将相应的抽头系数传送给乘法器，乘法器完成幅度信息与抽头系数的相乘后将结果送到累加器单元进行累加操作，输出校正后的幅度信息。5. DDS signal source according to claim 4, is characterized in that, described digital filtering module comprises data storage unit, tap coefficient look-up table, multiplier, accumulator and state control logic unit, wherein: state control logic unit and The accumulator is respectively connected to the sampling clock in the waveform data synthesis module; the data storage unit is connected to the output end of the RAM lookup table; the state control logic unit changes the state under the control of the sampling clock, and outputs control information to the Data storage unit, tap coefficient lookup table and accumulator, the data storage unit stores the amplitude information generated by the waveform data synthesis module in the corresponding storage location and selects the corresponding amplitude information to output to the multiplier, and the tap coefficient lookup table stores the corresponding tap coefficient It is transmitted to the multiplier, and the multiplier completes the multiplication of the amplitude information and the tap coefficient, and then sends the result to the accumulator unit for accumulation operation, and outputs the corrected amplitude information.6.根据权利要求5所述的DDS信号源，其特征在于，所述相位累加器、数字滤波模块与选择开关集成在一个现场可编程逻辑阵列中。6. The DDS signal source according to claim 5, wherein the phase accumulator, the digital filter module and the selection switch are integrated in a field programmable logic array.7.根据权利要求3～6中任一权利要求所述的DDS信号源，其特征在于，所述中央处理模块是一嵌入式的数字信号处理器。7. The DDS signal source according to any one of claims 3-6, wherein the central processing module is an embedded digital signal processor.

Images