CN101123113A

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Publication number: CN101123113A
Application number: CNA2007100461455A
Authority: CN
Inventors: 竺加毅; 周大江; 刘佩林
Original assignee: Shanghai Jiao Tong University
Current assignee: Shanghai Jiao Tong University
Priority date: 2007-09-20
Filing date: 2007-09-20
Publication date: 2008-02-13
Anticipated expiration: 2027-09-20
Also published as: CN101123113B

Abstract

一种数字集成电路系统中的同步动态随机访问存储器的访问方法及控制装置。本发明先寄存下用户发出的读写事务描述信息，然后将读写事务描述信息中的起始地址设为SDRAM读命令或写命令的目标地址，激活该目标地址所指定的存储阵列中的存储行，再向SDRAM发出读命令或写命令并更新读命令或写命令的目标地址和累计访问的访问单元的数量，接下来检测下一次访问是否需要关闭当前存储阵列中的存储行，如果需要则发送关闭命令，然后再激活新的目标地址所指定的存储阵列中的存储行并进行新一轮的访问，如果不需要发送关闭命令则直接进行新一轮的访问。本发明允许用户指定突发访问外部存储器时的地址增量以适应电路系统中对突发访问外部存储器的地址增量的要求。

An access method and control device for a synchronous dynamic random access memory in a digital integrated circuit system. The present invention first registers the read-write transaction description information issued by the user, and then sets the start address in the read-write transaction description information as the target address of the SDRAM read command or write command, and activates the storage in the storage array specified by the target address. line, then send a read command or write command to SDRAM and update the target address of the read command or write command and the number of accumulatively accessed access units, and then detect whether the next access needs to close the storage row in the current storage array, and if necessary, Send a close command, and then activate the storage row in the storage array specified by the new target address and perform a new round of access. If there is no need to send a close command, then directly perform a new round of access. The invention allows the user to designate the address increment when burst accessing the external memory so as to adapt to the requirement of the address increment for burst accessing the external memory in the circuit system.

Description

Translated fromChinese

同步动态随机访问存储器的访问方法及控制装置Access method and control device for synchronous dynamic random access memory

技术领域technical field

本发明涉及一种数字电路技术领域的方法及装置，具体是一种同步动态随机访问存储器的访问方法及控制装置。The invention relates to a method and a device in the technical field of digital circuits, in particular to an access method and a control device for a synchronous dynamic random access memory.

背景技术Background technique

同步动态随机访问存储器(SDRAM)在数字集成电路系统中是非常常用的，SDRAM的速度一般比SRAM(静态随机访问存储器)要慢，访问SDRAM的带宽经常会是一个数字集成电路系统设计中的关键和难点。要访问SDRAM中的某个基本存储单元，必须先激活该基本存储单元所在的SDRAM中的某个存储阵列中的某个存储行，在这之前如果该存储阵列中有另一个存储行打开着，必须先将它关闭。激活和关闭这些动作都需要一定的时间来完成，降低这部分时间在整个访问SDRAM过程中所占据的比例，就能提高真正的数据传输时间在整个整个访问SDRAM过程中所占据的比例，才能够提高访问SDRAM的效率。Synchronous dynamic random access memory (SDRAM) is very commonly used in digital integrated circuit systems. The speed of SDRAM is generally slower than that of SRAM (static random access memory). The bandwidth of accessing SDRAM is often the key to the design of a digital integrated circuit system. and difficult. To access a basic storage unit in SDRAM, you must first activate a storage row in a storage array in the SDRAM where the basic storage unit is located. Before that, if another storage row in the storage array is open, It must be closed first. It takes a certain amount of time to activate and deactivate these actions. Reducing the proportion of this part of time in the entire process of accessing SDRAM can increase the proportion of real data transmission time in the entire process of accessing SDRAM. Improve the efficiency of accessing SDRAM.

现有技术在访问SDRAM时，其突发长度只能设定为SDRAM芯片所支持的有限几种长度，比如1，2，4，8或全页式。虽然突发访问的方式能够有效地提高存储器的访问效率，但是SDRAM芯片所提供的突发长度选项太少，而且长度比较短，不足以支持高存储器带宽要求的情形。另外，按照一次突发访问中访问基本存储单元的顺序，SDRAM芯片只支持递增型和交织型两种类型的突发访问，不够灵活的突发访问类型限制了突发访问可以应用的场合，从而降低存储器访问效率。In the prior art, when accessing SDRAM, the burst length can only be set to several limited lengths supported by the SDRAM chip, such as 1, 2, 4, 8 or full page. Although the burst access method can effectively improve the access efficiency of the memory, the burst length options provided by the SDRAM chip are too few, and the length is relatively short, which is not enough to support the situation of high memory bandwidth requirements. In addition, according to the order of accessing basic storage units in a burst access, SDRAM chips only support two types of burst accesses: incremental and interleaved. The inflexible burst access types limit the occasions where burst access can be applied, thus Reduce memory access efficiency.

经过现有技术的文献检索发现，Tomasz Szymanski等人在VI-thInternational Conference the Experience of Designning and Application ofCAD Systems in Microelecronics(第四届微电子计算机辅助设计系统的设计与应用经验国际学术会议)上所发表的文章《SDRAM controller for real timedigital image processing systems》(适用于实时数字图像处理系统的同步动态随机访问存储器的控制器)即采用现有技术。该系统主要分为四个部分，分别负责初始化，刷新，以及读和写的控制，其核心部分--读和写的控制部分，把突发访问类型定为递增型，突发长度定为4，以提高访问存储器效率。尽管相比突发长度为1的单个基本存储单元的访问而言，该SDRAM控制器的效率已经有所增加，但是对于例如视频解码器等高外部存储器带宽要求的设计来说，这样的效率还是远远不够。After searching the literature of the prior art, it was found that Tomasz Szymanski et al. published on the VI-thInternational Conference the Experience of Designning and Application of CAD Systems in Microelecronics The article "SDRAM controller for real time digital image processing systems" (a controller for synchronous dynamic random access memory suitable for real-time digital image processing systems) adopts the existing technology. The system is mainly divided into four parts, which are responsible for initialization, refresh, and read and write control respectively. The core part - the read and write control part, sets the burst access type as incremental, and the burst length as 4 , to improve memory access efficiency. Although the efficiency of this SDRAM controller has been increased compared to accessing a single basic memory location with a burst length of 1, such efficiency is still insufficient for designs with high external memory bandwidth requirements such as video decoders. Far from enough.

发明内容Contents of the invention

本发明针对现有技术的不足，提供一种同步动态随机访问存储器(SDRAM)的访问方法及控制装置。本发明允许SDRAM用户用一组读写事务描述信息来描述对SDRAM的访问要求，然后根据这组读写事务描述信息向SDRAM发出一系列SDRAM命令来完成对SDRAM的访问要求，能够明显地提高访问SDRAM的效率。Aiming at the deficiencies of the prior art, the present invention provides an access method and control device for a synchronous dynamic random access memory (SDRAM). The invention allows SDRAM users to use a set of read-write transaction description information to describe the access requirements to SDRAM, and then send a series of SDRAM commands to SDRAM according to this set of read-write transaction description information to complete the SDRAM access requirements, which can significantly improve the access requirements. SDRAM efficiency.

本发明是通过以下技术方案实现的：The present invention is achieved through the following technical solutions:

本发明涉及的同步动态随机访问存储器的访问方法，具体包括以下步骤：The access method of the synchronous dynamic random access memory that the present invention relates to, specifically comprises the following steps:

第一步，获得用户发起的读写事务描述信息，包括读写事务访问类型(读或写)，读写事务起始地址S，读写事务地址增量I和读写事务突发长度L；The first step is to obtain the description information of the read-write transaction initiated by the user, including the access type of the read-write transaction (read or write), the start address S of the read-write transaction, the increment I of the read-write transaction address and the burst length L of the read-write transaction;

第二步，设定读写事务起始地址S为SDRAM目标地址A，目标地址A由存储阵列(bank)地址BA，存储行(row)地址RA和基本存储单元(col)地址CA组成；The second step is to set the read and write transaction starting address S as the SDRAM target address A, and the target address A is composed of a storage array (bank) address BA, a storage row (row) address RA and a basic storage unit (col) address CA;

第三步，向目标地址A中所隐含的存储阵列地址BA和存储行地址RA发送激活命令；The third step is to send an activation command to the storage array address BA and the storage row address RA implied in the target address A;

第四步，等待SDRAM芯片所要求的必要的时间后，根据读写事务的信息所指定的访问类型发送读命令把SDRAM中位于目标地址A的访问单元传送给用户或发送写命令把用户提供的访问单元存入SDRAM中的目标地址A处；同时设定新的SDRAM目标地址为原SDRAM目标地址加上读写事务地址增量A＝A+I并且更新累计访问的访问单元数量；Step 4: After waiting for the necessary time required by the SDRAM chip, send a read command according to the access type specified by the read and write transaction information to transfer the access unit located at the target address A in the SDRAM to the user or send a write command to transfer the access unit provided by the user to the user. Access unit is stored in the target address A place in SDRAM; Set new SDRAM target address simultaneously and be former SDRAM target address plus reading and writing transaction address increment A=A+I and update the access unit quantity of accumulative visit;

第五步，根据目标地址A检测是否需要发送必要的关闭命令，如果需要则发送；检测的判据是，如果累计访问的访问单元数量等于读写事务的突发长度或者第四步中更新后目标地址A中的BA或RA部分与更新前目标地址A中的BA或RA部分不同，则判为需要发送关闭命令；否则重复第四步；The fifth step is to detect whether it is necessary to send the necessary close command according to the target address A, and send it if necessary; the criterion for detection is that if the accumulative number of access units accessed is equal to the burst length of the read and write transactions or after the update in the fourth step If the BA or RA part of the target address A is different from the BA or RA part of the target address A before the update, it is judged that a shutdown command needs to be sent; otherwise, repeat the fourth step;

第六步，等待SDRAM芯片所要求的必要的时间后，重复第三到第五步直到累计访问的访问单元数量等于读写事务的突发长度。In the sixth step, after waiting for the necessary time required by the SDRAM chip, repeat the third to fifth steps until the accumulative number of accessed access units is equal to the burst length of the read and write transactions.

所述SDRAM可以是SDR(单倍数据速率)SDRAM，DDR(双倍数据速率)SDRAM或DDR2(双倍数据速率2代)SDRAM中的一种。The SDRAM may be one of SDR (Single Data Rate) SDRAM, DDR (Double Data Rate) SDRAM or DDR2 (Double Data Rate 2) SDRAM.

所述访问单元是指对SDRAM芯片发出一次读或写命令所访问到的基本存储单元的组合，等于给SDRAM配置的突发长度所指定数量的基本存储单元。访问单元可以在若干个周期内传送完毕，如果是单倍数据速率的SDRAM，则传送完访问单元所需要的周期书等于给SDRAM配置的突发长度，如果是双倍数据速率的SDRAM，则传送完访问单元所需要的周期书等于给SDRAM配置的突发长度的一半。The access unit refers to a combination of basic storage units accessed by issuing a read or write command to the SDRAM chip, which is equal to the number of basic storage units specified by the burst length configured for the SDRAM. The access unit can be transmitted in several cycles. If it is a single data rate SDRAM, the cycle book required to transmit the access unit is equal to the burst length configured for SDRAM. If it is a double data rate SDRAM, then the transmission The cycle book required to complete the access unit is equal to half of the burst length configured for SDRAM.

本发明还涉及一种同步动态随机访问存储器的控制装置，即SDRAM控制器，包括信息寄存器堆，有限状态机和命令译码器三个模块。信息寄存器堆采集外部输入的读写事务描述信息，把这些信息输出到有限状态机并在处理整个读写事务的过程中保持不变，直到接收到有限状态机发送出来的读写事务完成信号，才清空信息寄存器堆。有限状态机接受到来自信息寄存器堆的读写事务描述信息后，开始运作，它负责根据读写事务描述信息产生一系列的SDRAM命令以及这些命令所作用的地址，传送给命令译码器；当完成读写事务描述信息所描述的访问要求后，发送读写事务完成信号给信息寄存器堆。命令译码器接受到来自有限状态机的SDRAM命令以及这些命令所作用的地址后将这些命令翻译成SDRAM芯片可以识别的命令线信号，和这些命令所作用的地址一起输出到SDRAM芯片。The invention also relates to a control device for a synchronous dynamic random access memory, that is, an SDRAM controller, which includes three modules of an information register file, a finite state machine and a command decoder. The information register file collects the externally input read and write transaction description information, outputs the information to the finite state machine and keeps it unchanged during the entire process of processing the read and write transactions, until it receives the read and write transaction completion signal sent by the finite state machine, The information register file is cleared. After receiving the read and write transaction description information from the information register file, the finite state machine starts to operate. It is responsible for generating a series of SDRAM commands and the addresses that these commands act on according to the read and write transaction description information, and sends them to the command decoder; when After the access requirements described in the read and write transaction description information are completed, a read and write transaction completion signal is sent to the information register file. After receiving the SDRAM commands from the finite state machine and the addresses that these commands act on, the command decoder translates these commands into command line signals that can be recognized by the SDRAM chip, and outputs them to the SDRAM chip together with the addresses that these commands act on.

所述信息寄存器堆包括读写事务访问类型寄存器、读写事务起始地址寄存器，读写事务地址增量寄存器和读写事务突发长度寄存器共四个寄存器。读写事务访问类型寄存器的输入数据是SDRAM用户输入的读写事务描述信息中的读写事务访问类型信号；读写事务起始地址寄存器的输入数据是SDRAM用户输入的读写事务描述信息中的读写事务起始地址信号；读写事务地址增量寄存器的输入数据是SDRAM用户输入的读写事务描述信息中的读写事务地址增量信号；读写事务突发长度寄存器的输入数据是SDRAM用户输入的读写事务描述信息中的读写事务突发长度信号；上述四个寄存器负责采集并在整个读写事务的处理过程中保存读写事务的各项描述信息，然后传送给有限状态机，以供有限状态机作状态转换的依据之用。当有限状态机发送读写事务完成信号给信息寄存器堆时，上述四个寄存器全部清空。The information register file includes four registers including a read-write transaction access type register, a read-write transaction start address register, a read-write transaction address increment register and a read-write transaction burst length register. The input data of the read-write transaction access type register is the read-write transaction access type signal in the read-write transaction description information input by the SDRAM user; the input data of the read-write transaction start address register is the read-write transaction description information input by the SDRAM user The start address signal of the read and write transaction; the input data of the read and write transaction address increment register is the read and write transaction address increment signal in the read and write transaction description information input by the SDRAM user; the input data of the read and write transaction burst length register is the SDRAM The read-write transaction burst length signal in the read-write transaction description information input by the user; the above four registers are responsible for collecting and storing the various description information of the read-write transaction during the entire process of reading and writing transactions, and then sending them to the finite state machine , which is used as the basis for the state transition of the finite state machine. When the finite state machine sends a read and write transaction completion signal to the information register file, the above four registers are all cleared.

所述有限状态机的输入信号是来自信息寄存器堆输入的读写事务描述信息，包括读写事务访问类型，读写事务起始地址，读写事务地址增量和读写事务突发长度。有限状态机根据读写事务描述信息产生一系列输出信号以完成该信息所描述的访问请求。有限状态机的输出信号包括输出到信息寄存器堆的读写事务完成信号，输出到命令译码器的SDRAM命令，包括读命令、写命令、激活命令和关闭命令以及同样输出到命令译码器的存储阵列地址BA，存储行地址RA和基本存储单元地址CA。The input signal of the finite state machine is the read-write transaction description information input from the information register file, including the read-write transaction access type, the read-write transaction start address, the read-write transaction address increment and the read-write transaction burst length. The finite state machine generates a series of output signals according to the read and write transaction description information to complete the access request described by the information. The output signal of the finite state machine includes the read and write transaction completion signal output to the information register file, the SDRAM command output to the command decoder, including the read command, write command, activation command and shutdown command, and the same output to the command decoder. Storage array address BA, storage row address RA and basic storage unit address CA.

所述有限状态机包括当前地址寄存器(cur_addr)、剩余突发长度寄存器(cur_bl)、临时存储阵列地址寄存器(BA_tmp)、临时存储行地址寄存器(RA_tmp)和主状态寄存器(state)共五个状态寄存器。The finite state machine includes a current address register (cur_addr), a remaining burst length register (cur_bl), a temporary storage array address register (BA_tmp), a temporary storage row address register (RA_tmp) and a total of five states of the main state register (state) register.

所述主状态寄存器(state)表示有限状态机所处的状态，包括读状态、写状态、激活状态、关闭状态、激活后状态、关闭后状态和空闲状态，一共七个状态。在整个装置复位时，主状态寄存器(state)处于空闲状态，当检测到来自信息寄存器堆的读写事务描述信息中的读写事务访问类型信号为有效的读或者写而不是空时，主状态寄存器(state)从空闲状态进入激活状态，处于激活状态时，有限状态机输出激活命令和cur_addr中所隐含的BA和RA到命令译码器，激活状态只维持一个周期；下一个周期state马上进入激活后状态，等待若干个周期直到SDRAM芯片所要求的必要的时间间隔满足后，state根据读写事务描述信息中的读写事务访问类型决定进入写状态还是读状态，处于写状态或者读状态时，有限状态机发出读命令或者写命令和cur_addr中所隐含的CA到命令译码器，同时cur_addr和cur_bl或进行更新。state根据更新的cur_addr和cur_bl决定下一周期的状态，如果cur_bl等于0，则发出读写事务完成信号，表示完成了读写任务，如果cur_bl不等于0，则比较cur_addr中隐含的BA和RA与分别保存cur_bl更新前所隐含的BA和RA的BA_tmp和RA_tmp寄存器，如果BA或者RA不相同，则下一周期state进入关闭状态，如果BA和RA都相同，则下一个周期仍然保持原来的读状态或者写状态；处于关闭状态时，有限状态机发出关闭命令和BA_tmp及RA_tmp到命令译码器，关闭状态只维持一个周期；下一个周期state马上进入关闭后状态，等待若干个周期直到SDRAM芯片所要求的必要的时间间隔满足后，state再次进入激活状态，由此形成循环，直到读写事务完成信号被发出。The main state register (state) indicates the state of the finite state machine, including read state, write state, active state, closed state, activated state, closed state and idle state, a total of seven states. When the whole device is reset, the main state register (state) is in an idle state. When it is detected that the read-write transaction access type signal in the read-write transaction description information from the information register file is valid read or write rather than empty, the main state The register (state) enters the active state from the idle state. When it is in the active state, the finite state machine outputs the active command and the BA and RA implied in cur_addr to the command decoder. The active state is only maintained for one cycle; the next cycle state is immediately After entering the activated state, wait for several cycles until the necessary time interval required by the SDRAM chip is satisfied, the state decides whether to enter the write state or the read state according to the read and write transaction access type in the read and write transaction description information, and is in the write state or the read state When, the finite state machine issues a read command or a write command and the implicit CA in cur_addr to the command decoder, and cur_addr and cur_bl are updated at the same time. The state determines the state of the next cycle according to the updated cur_addr and cur_bl. If cur_bl is equal to 0, a read and write transaction completion signal is sent, indicating that the read and write tasks are completed. If cur_bl is not equal to 0, then compare the implicit BA and RA in cur_addr Save the BA_tmp and RA_tmp registers of BA and RA implied before cur_bl update respectively. If BA or RA is not the same, the next cycle state will enter the closed state. If both BA and RA are the same, the next cycle will still maintain the original Read state or write state; in the closed state, the finite state machine sends a closed command and BA_tmp and RA_tmp to the command decoder, and the closed state is only maintained for one cycle; the next cycle state immediately enters the closed state and waits for several cycles until SDRAM After the necessary time interval required by the chip is met, the state enters the active state again, thus forming a loop until the read and write transaction completion signal is sent.

所述当前地址寄存器(cur_addr)在有限状态机检测到信息寄存器堆发送来有效的读写事务描述信息时，寄存其中的读写事务起始地址信号，然后在有限状态机处于读状态或者写状态时递增，递增量为从信息寄存器堆中送来的读写事务地址增量。cur_addr递增是为了获得下一个SDRAM访问单元的地址。cur_addr包含了存储阵列地址BA，存储行地址RA和基本存储单元地址CA三个字段，所以cur_addr更新的时候，这三个字段同样也更新了，BA和RA会在有限状态机处于激活状态或者关闭状态的时候发送给命令译码器，BA和CA会在有限状态机处于读状态或者写状态的时候发送给命令译码器。The current address register (cur_addr) registers the read-write transaction starting address signal therein when the finite state machine detects that the information register file sends effective read-write transaction description information, and then the finite-state machine is in the read state or the write state It is incremented every time, and the increment is the increment of the read and write transaction address sent from the information register file. Cur_addr is incremented to obtain the address of the next SDRAM access unit. cur_addr contains three fields of storage array address BA, storage row address RA and basic storage unit address CA, so when cur_addr is updated, these three fields are also updated, and BA and RA will be activated or closed in the finite state machine BA and CA will be sent to the command decoder when the finite state machine is in the read or write state.

所述剩余突发长度寄存器(cur_bl)在有限状态机检测到信息寄存器堆发送来有效的读写事务描述信息时，寄存其中的读写事务突发长度信号，然后在有限状态机处于读状态或者写状态时递减1。cur_bl递减是为了对已经发送的访问请求计数，当发送的访问请求数达到读写事务突发长度时，即剩余突发长度寄存器中的值为0时，表示这次读写事务完成了，这时有限状态机应进入关闭状态。The remaining burst length register (cur_bl) registers the burst length signal of read and write transactions therein when the finite state machine detects that the information register file sends effective read and write transaction description information, and then the finite state machine is in the read state or Decrement by 1 when writing status. Cur_bl is decremented to count the access requests that have been sent. When the number of access requests sent reaches the burst length of the read and write transactions, that is, when the value in the remaining burst length register is 0, it means that the read and write transactions are completed. When the finite state machine should enter the closed state.

所述临时存储阵列地址寄存器(BA_tmp)和临时存储行地址寄存器(RA_tmp)在有限状态机处于读状态或者写状态的时候，寄存上一周期当前地址寄存器(cur_addr)中的BA部分和RA部分，用于与本周期cur_addr中的BA部分和RA部分比较，在cur_bl不等于0的情况下，如果BA_tmp与BA不同或者RA_tmp与RA不同，则有限状态机需要进入关闭状态，否则有限状态机保持原来的读状态或者写状态。进入关闭状态后，有限状态机要向命令译码器发送关闭命令，同时发送BA_tmp里的值到命令译码器已指定关闭命令所作用的存储阵列。The temporary storage array address register (BA_tmp) and the temporary storage row address register (RA_tmp) store the BA part and the RA part in the current address register (cur_addr) of the last cycle when the finite state machine is in the read state or the write state, It is used to compare with the BA part and RA part in cur_addr in this cycle. In the case that cur_bl is not equal to 0, if BA_tmp is different from BA or RA_tmp is different from RA, the finite state machine needs to enter the closed state, otherwise the finite state machine remains the same read or write status. After entering the shutdown state, the finite state machine will send the shutdown command to the command decoder, and at the same time send the value in BA_tmp to the memory array that the command decoder has specified to be affected by the shutdown command.

所述命令译码器包括一个译码器，一个选择器，一个或门和一个存储阵列地址寄存器。译码器的输入信号是来自有限状态机的SDRAM命令，包括读命令，写命令，激活命令和关闭命令，译码器对其译码输出SDRAM芯片能够识别的命令信号；或门的输入是来自有限状态机的读命令信号和写命令信号，输出作为选择器的选择信号；选择器的输入数据是来自有限状态机的存储行地址RA和基本存储单元地址CA，输入选择器的选择信号是或门的输出，选择器根据选择信号选择RA或者CA为输出到SDRAM芯片的地址信号ADDR；存储阵列地址寄存器的输入数据是来自有限状态机的存储阵列地址信号BA，存储阵列地址寄存器起到把BA保存一个周期，然后和ADDR在同一个周期送到SDRAM芯片。The command decoder includes a decoder, a selector, an OR gate and a storage array address register. The input signal of the decoder is the SDRAM command from the finite state machine, including the read command, the write command, the activation command and the closing command, and the decoder decodes and outputs the command signal that the SDRAM chip can recognize; the input of the OR gate is from The read command signal and write command signal of the finite state machine are output as the selection signal of the selector; the input data of the selector is the storage row address RA and the basic storage unit address CA from the finite state machine, and the selection signal input to the selector is or The output of the gate, the selector selects RA or CA as the address signal ADDR output to the SDRAM chip according to the selection signal; the input data of the storage array address register is the storage array address signal BA from the finite state machine, and the storage array address register acts as the BA Save a cycle, and then send it to the SDRAM chip in the same cycle as ADDR.

本发明提出了一种高效地访问SDRAM的方法来提高与SDRAM之间的数据传输效率。本发明允许SDRAM用户用一组读写事务描述信息来描述对SDRAM的访问要求，然后根据这组读写事务描述信息向SDRAM发出一系列SDRAM命令来完成对SDRAM的访问要求。The invention proposes a method for efficiently accessing the SDRAM to improve the data transmission efficiency with the SDRAM. The invention allows SDRAM users to use a set of read-write transaction description information to describe the SDRAM access requirements, and then send a series of SDRAM commands to the SDRAM according to the set of read-write transaction description information to complete the SDRAM access requirements.

本发明能够明显地提高访问SDRAM的效率，在每次突发访问都考虑一个激活命令的情况下，在166MHz情况下，激活命令需要三个周期。现有技术访问效率即使设为最高的8，也只能达到72.7％。采用本发明，突发访问的长度可以很长，同时不一定受限于相邻地址的基本存储单元的突发访问，这样就增强了突发访问的适应性，使之跟容易被应用，从而提高了访问SDRAM的效率。The invention can obviously improve the efficiency of accessing the SDRAM. In the case of considering an activation command for each burst access, in the case of 166MHz, the activation command needs three cycles. Even if the prior art access efficiency is set to the highest 8, it can only reach 72.7%. By adopting the present invention, the length of burst access can be very long, and it is not necessarily limited to the burst access of basic storage units of adjacent addresses, which enhances the adaptability of burst access and makes it easy to be applied, thereby Improve the efficiency of accessing SDRAM.

附图说明Description of drawings

图1是SDRAM控制器的位置示意图；Figure 1 is a schematic diagram of the location of the SDRAM controller;

图2是有限状态机的状态转移示意图；Fig. 2 is a schematic diagram of a state transition of a finite state machine;

图3是以不同地址增量突发访问存在SDRAM中的图象的示意图；Fig. 3 is the schematic diagram that is stored in the image in SDRAM with burst access of different address increments;

图4是SDRAM控制器内部结构框图；Fig. 4 is a block diagram of the internal structure of the SDRAM controller;

图5是命令译码器内部结构示意图。Figure 5 is a schematic diagram of the internal structure of the command decoder.

具体实现方式Specific implementation

下面结合附图对本发明的实施例作详细说明：本实施例在以本发明技术方案为前提下进行实施，给出了详细的实施方式和过程，但本发明的保护范围不限于下述的实施例。The embodiments of the present invention are described in detail below in conjunction with the accompanying drawings: the present embodiment is implemented on the premise of the technical solution of the present invention, and detailed implementation methods and processes are provided, but the protection scope of the present invention is not limited to the following implementations example.

以下详细说明本发明在访问图像时的实施例。Embodiments of the present invention when accessing images will be described in detail below.

本实施例的方法，首先寄存下用户发出的读写事务描述信息，然后将读写事务描述信息中的读写事务起始地址设定为SDRAM读命令或者写命令的目标地址，激活该目标地址所指定的存储阵列中的存储行，再向SDRAM发出读命令或写命令并更新读命令或写命令的目标地址和累计访问的访问单元的数量，接下来检测下一次访问是否需要关闭当前存储阵列中的存储行，如果需要则发送关闭命令，然后再激活新的目标地址所指定的存储阵列中的存储行并进行新一轮的访问，如果不需要发送关闭命令则直接访问下一个访问单元。In the method of this embodiment, at first register the read-write transaction description information sent by the user, then set the read-write transaction start address in the read-write transaction description information as the target address of the SDRAM read command or write command, and activate the target address The storage row in the specified storage array, and then send a read command or write command to SDRAM and update the target address of the read command or write command and the number of accumulatively accessed access units, and then detect whether the next access needs to close the current storage array If necessary, send a closing command to the storage row in the storage array, and then activate the storage row in the storage array specified by the new target address and perform a new round of access. If there is no need to send a closing command, then directly access the next access unit.

本实施例中访问同步动态随机访问存储器的控制装置包括信息寄存器堆，有限状态机和命令译码器三个模块(图4)。The control device for accessing the synchronous dynamic random access memory in this embodiment includes three modules (FIG. 4), an information register file, a finite state machine and a command decoder.

信息寄存器堆包括读写事务访问类型寄存器、读写事务起始地址寄存器，读写事务地址增量寄存器和读写事务突发长度寄存器共四个寄存器。信息寄存器堆的输入信号包括SDRAM用户输入的读写事务描述信息和有限状态机模块输入的读写事务完成信号。所述读写事务描述信息包括读写事务访问类型，读写事务起始地址，读写事务地址增量和读写事务突发长度。信息寄存器堆输出读写事务描述信息到有限状态机模块(图4)。信息寄存器堆的工作流程如下：当发现SDRAM用户发出访问请求且信息寄存器堆空闲的时候，把上述读写事务描述信息寄存到相应的寄存器中，并传送给有限状态机。直到有限状态机完成该读写事务所要求的读写任务后，发送读写事务完成任务的信号给信息寄存器堆。信息寄存器堆接受到有限状态机发出的读写事务完成信号后，把所有寄存器清零，表示信息寄存器堆处于空闲状态。The information register file includes a read-write transaction access type register, a read-write transaction start address register, a read-write transaction address increment register, and a read-write transaction burst length register. The input signal of the information register file includes the read and write transaction description information input by the SDRAM user and the read and write transaction completion signal input by the finite state machine module. The read-write transaction description information includes the read-write transaction access type, the read-write transaction start address, the read-write transaction address increment and the read-write transaction burst length. The information register file outputs the read and write transaction description information to the finite state machine module (Figure 4). The working process of the information register file is as follows: when it is found that the SDRAM user sends an access request and the information register file is idle, the above-mentioned read and write transaction description information is stored in the corresponding register and sent to the finite state machine. After the finite state machine completes the read and write tasks required by the read and write transaction, it sends a signal of the completion of the read and write transaction to the information register file. After the information register file receives the read and write transaction completion signal sent by the finite state machine, all registers are cleared, indicating that the information register file is in an idle state.

有限状态机包括当前地址寄存器(cur_addr)、剩余突发长度寄存器(cur_bl)、临时存储阵列地址寄存器(BA_tmp)、临时存储行地址寄存器(RA_tmp)和主状态寄存器(state)共五个状态寄存器。有限状态机包括读状态，写状态，激活状态，关闭状态，激活后状态，关闭后状态和空闲状态，一共七个状态(图2)。有限状态机的输入信号是来自信息寄存器堆的读写事务描述信息，包括读写事务访问类型，读写事务起始地址，读写事务地址增量和读写事务突发长度。有限状态机的输出信号包括输出到信息寄存器堆的读写事务完成信号，输出到命令译码器的SDRAM命令，包括读命令，写命令，激活命令和关闭命令以及同样输出到命令译码器的存储阵列地址BA，存储行地址RA和基本存储单元地址CA(图4)。有限状态机的工作流程如下(图2)：主状态寄存器(state)开始处于空闲状态，当检测到来自信息寄存器堆的读写事务描述信息中的读写事务访问类型信号为读或者写而不是空时，当前地址寄存器(cur_addr)寄存读写事务信息中的读写事务起始地址信号，其中包括BA，RA和CA，剩余突发长度寄存器(cur_bl)寄存读写事务信息中的读写事务突发长度信号，主状态寄存器(state)从空闲状态进入激活状态，处于激活状态时，有限状态机输出激活命令和cur_addr中所隐含的BA和RA到命令译码器，激活状态只维持一个周期；下一个周期state马上进入激活后状态，等待若干个周期直到SDRAM芯片所要求的必要的时间间隔满足后，state根据读写事务描述信息中的读写事务访问类型决定进入写状态还是读状态，处于写状态或者读状态时，有限状态机发出写命令或者读命令和cur_addr中所隐含的CA到命令译码器，同时cur_addr自增读写事务描述信息中的读写事务地址增量，cur_bl自减1；处于读状态或写状态时，有限状态机根据更新的cur_addr和cur_bl决定下一周期的状态，如果cur_bl等于0，则发出读写事务完成信号，表示完成了读写任务，如果cur_bl不等于0，则比较cur_addr中隐含的BA和RA与cur_bl更新前所隐含的BA和RA，如果BA相同而RA不相同，则表示下个访问单元处于同一存储阵列的不同存储行，必须先关闭该存储阵列，即下一周期state进入关闭状态，同时保存cur_addr更新前所隐含的BA和RA到BA_tmp和RA_tmp，如果BA不同，不管RA是否相同，则表示下一个访问单元处于另一个存储阵列中，为了简化有限状态机，故这种情况下也让state进入关闭状态，同时保存cur_addr更新前所隐含的BA和RA到BA_tmp和RA_tmp，如果BA和RA都相同，则下一个周期仍然保持原来的读状态或者写状态；处于关闭状态时，有限状态机发出关闭命令和BA_tmp及RA_tmp到命令译码器，关闭状态只维持一个周期；下一个周期state马上进入关闭后状态，等待若干个周期直到SDRAM芯片所要求的必要的时间间隔满足后，state再次进入激活状态，由此形成循环，直到读写事务完成信号被发出。The finite state machine includes a current address register (cur_addr), a remaining burst length register (cur_bl), a temporary storage array address register (BA_tmp), a temporary storage row address register (RA_tmp) and a main state register (state). The finite state machine includes read state, write state, active state, closed state, activated state, closed state and idle state, a total of seven states (Figure 2). The input signal of the finite state machine is the read and write transaction description information from the information register file, including the read and write transaction access type, the read and write transaction start address, the read and write transaction address increment and the read and write transaction burst length. The output signal of the finite state machine includes the read and write transaction completion signal output to the information register file, the SDRAM command output to the command decoder, including the read command, write command, activation command and shutdown command, and the same output to the command decoder. Storage array address BA, storage row address RA and basic storage unit address CA (Figure 4). The working process of the finite state machine is as follows (Figure 2): the main state register (state) starts to be in an idle state, when it is detected that the read-write transaction access type signal in the read-write transaction description information from the information register file is read or write instead of When empty, the current address register (cur_addr) stores the read-write transaction start address signal in the read-write transaction information, including BA, RA and CA, and the remaining burst length register (cur_bl) stores the read-write transaction in the read-write transaction information Burst length signal, the main state register (state) enters the active state from the idle state. When in the active state, the finite state machine outputs the active command and the BA and RA implied in cur_addr to the command decoder, and the active state only maintains one cycle; the next cycle state immediately enters the activated state, waits for several cycles until the necessary time interval required by the SDRAM chip is satisfied, and the state decides to enter the write state or the read state according to the read and write transaction access type in the read and write transaction description information , when in the write state or read state, the finite state machine sends a write command or read command and the implicit CA in cur_addr to the command decoder, and cur_addr automatically increments the read-write transaction address increment in the read-write transaction description information, cur_bl is decremented by 1; when it is in the read state or write state, the finite state machine determines the state of the next cycle according to the updated cur_addr and cur_bl, if cur_bl is equal to 0, it sends a read and write transaction completion signal, indicating that the read and write tasks are completed, if cur_bl is not equal to 0, then compare the BA and RA implied in cur_addr with the BA and RA implied before cur_bl is updated, if BA is the same but RA is not the same, it means that the next access unit is in a different storage row of the same storage array, The storage array must be closed first, that is, the state enters the closed state in the next cycle, and at the same time save the BA and RA implied before the update of cur_addr to BA_tmp and RA_tmp. If the BA is different, regardless of whether the RA is the same, it means that the next access unit is in another In a storage array, in order to simplify the finite state machine, the state is also turned off in this case, and the BA and RA implied before the cur_addr update are saved to BA_tmp and RA_tmp. If BA and RA are the same, the next The cycle still maintains the original read state or write state; when it is in the closed state, the finite state machine sends a close command and BA_tmp and RA_tmp to the command decoder, and the closed state only maintains one cycle; the next cycle state immediately enters the closed state, waiting After several cycles until the necessary time interval required by the SDRAM chip is satisfied, the state enters the active state again, thereby forming a cycle until the read and write transaction completion signal is sent.

命令译码器包括一个译码器，一个选择器，一个或门和一个存储阵列地址寄存器。命令译码器的输入信号包括有限状态机输入的SDRAM命令以及存储阵列地址BA，存储行地址RA和基本存储单元地址CA。命令译码器的输出信号包括输出到SDRAM芯片的SDRAM芯片能够识别的命令信号，SDRAM地址ADDR以及SDRAM的存储阵列地址BS(图4)。命令译码器的工作流程如下：有限状态机输入的SDRAM命令进入译码器后，翻译为SDRAM芯片能够识别的命令信号；有限状态机输入的存储阵列地址BA经寄存后作为命令译码器的输出；有限状态机输入的SDRAM命令信号输入选择器，如果这个命令为读命令或者写命令，则命令译码器的输出SDRAM地址ADDR等于CA，否则等于RA。The command decoder includes a decoder, a selector, an OR gate and a memory array address register. The input signals of the command decoder include the SDRAM command input by the finite state machine, the storage array address BA, the storage row address RA and the basic storage unit address CA. The output signal of the command decoder includes the command signal output to the SDRAM chip that the SDRAM chip can recognize, the SDRAM address ADDR and the storage array address BS of the SDRAM (Figure 4). The working process of the command decoder is as follows: After the SDRAM command input by the finite state machine enters the decoder, it is translated into a command signal that can be recognized by the SDRAM chip; the storage array address BA input by the finite state machine is registered as the command decoder. Output: The SDRAM command signal input by the finite state machine is input to the selector. If the command is a read command or a write command, the output SDRAM address ADDR of the command decoder is equal to CA, otherwise it is equal to RA.

在本实施例中，假设某视频解码器要以纵向突发的形式读取一幅存在SDRAM中宽度为n，长度为m个访问单元的图像中的纵方向上的一条边(图3)，本装置在系统中处于视频解码器和SDRAM芯片之间(图1)，视频解码器向本装置，即SDRAM控制器发出包含读写事务描述信息的访问SDRAM芯片的请求，SDRAM控制器根据读写事务描述信息发出一系列SDRAM芯片所能够识别的命令给SDRAM芯片，来完成读写事务描述信息所描述的访问存储器的要求。具体过程如下：In this embodiment, it is assumed that a certain video decoder needs to read a side in the vertical direction of an image stored in the SDRAM with a width of n and a length of m access units in the form of a vertical burst (FIG. 3), The device is located between the video decoder and the SDRAM chip in the system (Figure 1). The video decoder sends a request to the device, that is, the SDRAM controller, to access the SDRAM chip including the read and write transaction description information. The SDRAM controller reads and writes according to the The transaction description information sends a series of commands that the SDRAM chip can recognize to the SDRAM chip to complete the requirements for accessing the memory described in the read and write transaction description information. The specific process is as follows:

第一步视频解码器发起包含读写事务描述信息的请求，读写事务描述信息包括读写事务访问类型，读写事务起始地址S，读写事务地址增量n和读写事务突发长度L。SDRAM控制器的信息寄存器堆收到视频解码器的请求以后，寄存下上述信息(图4)；The first step is that the video decoder initiates a request containing the description information of the read-write transaction. The description information of the read-write transaction includes the access type of the read-write transaction, the start address S of the read-write transaction, the increment n of the read-write transaction address, and the burst length of the read-write transaction L. After the information register file of the SDRAM controller receives the request of the video decoder, the above information is registered (Fig. 4);

第二步信息寄存器堆将所寄存的读写事务描述信息传给有限状态机(图4)，有限状态机设定临时地址寄存器cur_addr为S，剩余突发长度寄存器cur_bl为L，有限状态机开始工作；In the second step, the information register file transmits the registered read and write transaction description information to the finite state machine (Figure 4), the finite state machine sets the temporary address register cur_addr to S, the remaining burst length register cur_bl to L, and the finite state machine starts Work;

第三步主状态寄存器(state)从空闲状态进入激活状态(图2)，有限状态机向命令译码器发送激活命令和cur_addr中的存储阵列地址BA和存储行地址RA，激活状态只维持一个周期，下一个周期主状态寄存器(state)进入激活后状态(图2)；命令译码器接受到激活命令以及BA和RA后(图4)，译码器将激活命令翻译成SDRAM芯片可以识别的激活命令，存储阵列地址寄存器寄存下BA，选择器根据为0值的选择信号，把存储行地址RA的信号赋给地址ADDR(图5)；In the third step, the main state register (state) enters the active state from the idle state (Figure 2), and the finite state machine sends the activation command and the storage array address BA and the storage row address RA in cur_addr to the command decoder, and the activation state only maintains one cycle, the next cycle the main state register (state) enters the post-activation state (Figure 2); after the command decoder receives the activation command and BA and RA (Figure 4), the decoder translates the activation command into an SDRAM chip that can recognize The activation command of the storage array address register registers the lower BA, and the selector assigns the signal of the storage row address RA to the address ADDR (Fig. 5) according to the selection signal of 0 value;

第四步等待SDRAM芯片所要求的必要的时间限制满足后，主状态寄存器(state)根据读写事务描述信息中的读写事务访问类型信号是读还是写决定进入读状态还是写状态(图2)；有限状态机向命令译码器发送对应主状态寄存器状态的读(read)命令或写(write)命令和cur_addr中的基本存储阵单元地址CA；同时保存cur_addr中的BA部分到临时存储阵列地址寄存器BA_tmp中去，RA部分到临时存储行地址寄存器RA_tmp中去；更新cru_addr为原cur_addr加上读写事务地址增量cur_addr＝cur_addr+I；更新剩余的要访问的访问单元数量cur_bl＝cur_bl-1；命令译码器接受到读命令或者写命令以及CA后(图4)，译码器将读命令或着写命令翻译成SDRAM芯片可以识别的读命令或写命令，选择器根据为1值的选择信号，把基本存储单元地址CA赋给地址ADDR(图5)；The fourth step waits for the necessary time limit required by the SDRAM chip to be satisfied, and the main state register (state) decides whether to enter the read state or the write state according to whether the read-write transaction access type signal in the read-write transaction description information is read or write (Figure 2 ); the finite state machine sends a read (read) command corresponding to the state of the main state register or a write (write) command and the basic storage array unit address CA in the cur_addr to the command decoder; simultaneously save the BA part in the cur_addr to the temporary storage array Go in the address register BA_tmp, RA part goes in the temporary storage row address register RA_tmp; Update cru_addr to add read and write transaction address increment cur_addr=cur_addr+I for original cur_addr; Update remaining access unit quantity cur_bl=cur_bl- to be visited 1; After the command decoder receives the read command or write command and CA (Figure 4), the decoder translates the read command or write command into a read command or write command that can be recognized by the SDRAM chip, and the selector is based on a value of 1 The selection signal of basic storage unit address CA is given to address ADDR (Fig. 5);

第五步有限状态机如果发现cur_bl等于0，或者发现cur_addr中的BA或RA部分与BA_tmp或RA_tmp部分不同，则判断为需要发送关闭命令，主状态寄存器(state)进入关闭状态(图2)，有限状态机向命令译码器发送关闭命令和cur_addr中的存储阵列地址BA，关闭状态只维持一个周期，下一个周期主状态寄存器(state)进入关闭后状态(图2)，如果判断为不需要发送关闭命令，则重复第四步；命令译码器接受到关闭命令以及BA后(图4)，译码器将关闭命令翻译成SDRAM芯片可以识别的关闭命令，存储阵列地址寄存器寄存下BA，选择器根据为0值的选择信号，把存储行地址RA赋给地址ADDR(图5)；In the fifth step, if the finite state machine finds that cur_bl is equal to 0, or finds that the BA or RA part in cur_addr is different from the BA_tmp or RA_tmp part, then it is judged that a shutdown command needs to be sent, and the main state register (state) enters the shutdown state (Figure 2), The finite state machine sends the shutdown command and the storage array address BA in cur_addr to the command decoder. The shutdown state is only maintained for one cycle, and the main state register (state) enters the state after the shutdown in the next cycle (Figure 2). If it is judged that it is not needed Send the shutdown command, then repeat the fourth step; after the command decoder receives the shutdown command and BA (Figure 4), the decoder translates the shutdown command into a shutdown command that can be recognized by the SDRAM chip, and the storage array address register registers the BA, The selector assigns the storage row address RA to the address ADDR (Fig. 5) according to the selection signal of 0 value;

第六步等待SDRAM芯片所要求的必要的时间限制满足后，重复第三到第五步直到检测到cur_bl等于0时，有限状态机向信息寄存器堆发出读写事务完成信号(图4)，信息寄存器堆清空。After the sixth step waits for the necessary time limit required by the SDRAM chip to meet, repeat the third to fifth steps until it detects that cur_bl is equal to 0, the finite state machine sends a read and write transaction completion signal to the information register file (Figure 4), and the information The register file is cleared.

如此，一次对于图像的纵向访问完成了。In this way, a vertical access to the image is completed.

在视频解码器中，滤波模块往往会访问完成滤波的一排纵向像素。由于纵排方向上相邻像素的地址并不是相邻的，所以无法用现有技术对其进行突发长度超过1的突发访问，而只能单个单个的访问像素，在166MHz和需要一次激活的条件下，访问存储器的效率只有25％。而使用本发明，可以轻松的访问一个宏块16个像素，同样条件下，访问存储器的效率达到84.2％。In a video decoder, the filtering module often accesses a row of vertical pixels for filtering. Since the addresses of adjacent pixels in the tandem direction are not adjacent, it is impossible to use the existing technology to perform burst access with a burst length of more than 1, but only a single access pixel, at 166MHz and requires one activation Under certain conditions, the efficiency of accessing memory is only 25%. However, with the present invention, 16 pixels of a macroblock can be easily accessed, and under the same condition, the efficiency of accessing memory reaches 84.2%.

本发明与现有技术的效果对比见下表：The effect contrast of the present invention and prior art sees the following table:

应用本发明提高突发长度Apply the present invention to increase the burst length现有技术不能提高突发长度Existing techniques cannot increase the burst length突发长度burst length 数据传输效率Data transmission efficiency 数据传输效率 Data Transmission Efficiency 1 1 25％25% 25％25% 2 2 40％40% 25％25% 33 50％50% 25％25% 44 57％57% 25％25%

55 62.5％62.5% 25％25% 66 66.7％66.7% 25％25% 77 70％70% 25％25% 8 8 72.7％72.7% 25％25% 9 9 75％75% 25％25% 1010 76.9％76.9% 25％25% 1111 78.6％78.6% 25％25% 1212 80％80% 25％25% 1313 81.25％81.25% 25％25% 1414 82.4％82.4% 25％25% 1515 83.3％83.3% 25％25% 1616 84.2％84.2% 25％25%