CN101090123A - Thin film transistor with copper wire structure and manufacturing method thereof - Google Patents

Abstract

A thin film transistor with copper wire structure and its manufacturing method, which uses at least a copper alloy layer and a copper metal layer to compose the grid of multi-layer metal structure, after heat treatment, it can improve the atom arrangement between lattice interfaces and the bond between atoms (i.e. increase the adhesion), and reduce the resistance, inhibit the copper ion diffusion, make the thin film transistor electric conduction efficiency better. In addition, when the multi-layer metal thin layer is patterned, only a single-layer copper etching solution is needed to simplify the patterning process of the conducting wire, and only a copper alloy thin layer is used in the structure, so that the cost for manufacturing the thin film transistor can be reduced.

Description

The thin-film transistor of tool copper conducting wire structure and manufacture method thereof

Technical field

The invention relates to a kind of tft liquid crystal screen, be meant a kind of thin-film transistor and manufacture method thereof of tool copper conducting wire structure especially.

Background technology

Along with liquid crystal display applications is extensive gradually, the size of display is also along with increasing gradually.Yet along with the size of display increases, the delay issue of RC circuit is also more and more serious, therefore develops the copper metal that with low resistance as lead.But copper is relatively poor to the adhesive force of insulated substrate; and the Cu ion easily diffuses to active layer; cause component failures; in order to increase Cu and lower floor's adhesive force and to suppress the copper ion diffusion, regular meeting uses metals such as Mo, Ti, Ta to form multilayer structure, but when etch process; need two kinds of metal levels of etching respectively; use single etching solution etching plied timber as desire, because the metal species difference, difficulty has desirable etching result.

In addition, if only be used as metal gates with copper alloy, can suppress the copper ion diffusion and with ground good bonding effect be arranged though copper alloy has been proved, copper alloy is because resistance is higher, and target cost of manufacture height, still has doubt on using.

Summary of the invention

The present invention is the thin-film transistor and the manufacture method thereof of a tool copper conducting wire structure, is the grid that forms multi-layer metal structure with an at least one copper alloy layer and a copper metal layer, with the diffusion of reduction resistance, the degree of adhering to that improves copper metal layer and inhibition copper ion.In addition, copper alloy layer and copper metal layer when graphical, are only needed the individual layer copper etchant solution, and need not two kinds of different metallic films of etching, the graphical technology of lead can be simplified.

In an embodiment provided by the present invention; form copper conductor in regular turn with at least one copper alloy layer and a copper metal layer; then; behind the figure of definition copper conductor; the action of heat-treating, to produce patterned grid, last; from bottom to top gate insulator, active layer, ohmic contact layer, data wire, source electrode, drain electrode, protective layer and the pixel electrode of storehouse formation patterning have the thin-film transistor of multi-layer metal structure copper conductor with formation on grid in regular turn.

In another embodiment provided by the present invention, be with the foregoing description difference, do heat treatment earlier after, the definition copper conductor figure, to produce patterned grid.

Wherein, heat treated temperature is about 100 to 500 ℃.Except the alloying element of itself, remaining alloying element content is about 0.2 to 10 percentage in the copper alloy layer.The thickness of copper alloy layer is about 10 to 2000 dusts, and the thickness of copper metal layer is about 1000 to 4000 dusts.

Description of drawings

Figure 1A～Fig. 1 C is the process section of the grid of the double-level-metal structure of content of the present invention;

Fig. 2 to Fig. 5 is the process section of the thin-film transistor of content of the present invention; And

Fig. 6 is the process section of the grid of the three-layer metal structure of content of the present invention.

Symbol description:

Substrate 121

Grid 131

Gate line 133

Gate insulator 140

Active layer 150

Ohmic contact layer 160

Source electrode 171

Drain electrode 172

Protective layer 180

Pixel electrode 190

Copper alloy layer C1

Copper metal layer C2

Drain electrode contact opening D

Embodiment

Please also refer to Figure 1A to Fig. 1 C, it is the process section of the grid of the double-level-metal structure of content of the present invention.

At first, produce among the embodiment of grid (gate) 131 and gate line (gate line) 133 in the present invention, shown in Figure 1A to Figure 1B, be on substrate (substrate) 121, deposition forms copper alloy layer (the copper alloy layer) C1 of about 10 to 2000 dusts (angstrom) of a layer thickness and copper metal layer (copper layer) C2 of about 1000 to 4000 dusts of a layer thickness in regular turn.Then, shown in Fig. 1 C, define the figure of double-level-metal structures such as established copper alloy layer C1 and copper metal layer C2,, heat-treat (heattreatment) with about 100 to 500 ℃ temperature again to produce the copper conductor of double-level-metal structure.

Produce among another embodiment ofgrid 131 andgate line 133 in the present invention, shown in Figure 1A to Figure 1B, be onsubstrate 121, deposition forms a layer thickness and is approximately the copper alloy layer C1 of 10 to 2000 dusts and the copper metal layer C2 that a layer thickness is approximately 1000 to 4000 dusts in regular turn.Then, with about 100 to 500 ℃ temperature,substrate 121, copper alloy layer C1 and copper metal layer C2 are heat-treated, then, shown in Fig. 1 C, define the figure of double-level-metal structures such as established copper alloy layer C1 and copper metal layer C2 again, to produce the copper conductor of double-level-metal structure.

Wherein, deposit the copper alloy layer C1 of above-mentioned ground floor and the copper metal layer C2 of the second layer, be to utilize physical vaporous deposition (physical vapor deposition, PVD), electroplate (electro plating, EP), revolve plating (spin coating), printing (printing) and electroless plating (electro less plating, ELP) etc. mode is wherein a kind of, be deposited as thegrid 131 andgate line 133 of bimetal structure in regular turn, andgrid 131 is to be extended by gate line 133.And the copper alloy element of above-mentioned copper alloy layer C1 can be magnesium (magnesium), chromium (Chromium), tungsten (wolfram), molybdenum (molybdenum), niobium (niobium), ruthenium (ruthenium), nitrogen (nitrogen), silver (silver), carbon (carbon) and hybrid alloys thereof.

Thus, the ability that copper metal layer C2 can utilize the good degree of adhering to (adhesion) of copper alloy layer C1 itself and suppress copper ion diffusion (diffusion), make the copper metal layer C2 can be by copper alloy layer C1 attached on thesubstrate 121, especially in heat treated process, utilize copper alloy layer C1 as metal barrier layer (metal barrier layer), make the copper ion of copper metal layer C2 be difficult for diffusing tosubstrate 121, and the substrate after theheat treatment 121, can bond (bonding) get better between lattice interface (grainboundary) atom between copper alloy layer C1 and copper metal layer C2, to reducesubstrate 121, resistance between copper alloy layer C1 and copper metal layer C2.In addition, thickness 10 to 2000 dusts only because of copper alloy layer C1, therefore not only can reduce the consumption of target (target), reduce the manufacturing cost of making Thin Film Transistor-LCD, and the resistance of copper alloy layer C1 is unlikely to influence the resistance of whole copper conductor and the speed of electrically transmitting.In addition, copper alloy layer C1 and copper metal layer C2 when graphical, are only needed the individual layer copper etchant solution, and need not two kinds of different metallic films of etching, the graphical technology of lead can be simplified.

Then, as shown in Figure 2, in regular turn on the double-level-metal structure, be ongrid 131 and thegate line 133, with chemical vapour deposition (CVD) (chemical vapor deposition, CVD) mode, deposition forms a gate insulator (gate insulation layer) 140, one active layer (active layer) 150 and one ohmic contact layer (ohmic contact layer) 160.Wherein,gate insulator 140 is that (active layer 150 is amorphous silicon (amorphous silicon) to silicon nitride for silicon nitride, inorganic material (inorganic material) such as SiNx), andohmic contact layer 160 is the dense doping (n of N type⁺Doped) amorphous silicon.

Gate insulator 140 is formed on thesubstrate 121, and covers ongrid 131 and the gate line 133.Active layer 150 is formed on thegate insulator 140, and only covers on the part of grid pole 131.160 of ohmic contact layers are formed on theactive layer 150.

As shown in Figure 3, shown in Figure 1A to Fig. 1 C, in regular turn copper alloy layer C1 and copper metal layer C2 deposition are formed on theohmic contact layer 160, and with this double-level-metal structure graphization, produce source electrode (sourceelectrode) 171, drain electrode (drainelectrode) 172 and data wire T, and the spacing of being separated by betweensource electrode 171 and the drain electrode 172.Wherein,source electrode 171 anddrain 172 process and process structure, identical withgrid 131, all can utilize physical vaporous deposition, electroplate, revolve the wherein a kind of of modes such as plating, printing and electroless plating, come the copper alloy layer C1 of about 10 to 2000 dusts of deposit thickness and the copper metal layer C2 of about 1000 to 4000 dusts of thickness, and heat treated temperature is controlled at about 100 to 500℃.Source electrode 171 is to be extended by data wire T, and data wire T then intersects withgate line 133, to define a pixel coverage (pixelrange).

At last, as Fig. 4 and shown in Figure 5, with physical vaporous deposition, electroplate, revolve the wherein a kind of of modes such as plating, printing and electroless plating, deposition forms aprotective layer 180 and a pixel electrode (pixelelectrode) 190 in regular turn.Thisprotective layer 180 is formed on thegate insulator 160, and covers to data wire T,source electrode 171 anddrain 172, and forms drain electrode contact opening (contact hole)D.Pixel electrode 190 then is formed on the interiorprotective layer 180 of pixel coverage, and is linked todrain electrode 172 by drain electrode contact openingD.Pixel electrode 190 can for tin indium oxide (Indium tin oxide, ITO), the amorphism indium zinc oxide (Indium zinc oxide, IZO) or the transparency conducting layer of zinc oxide (ZnO) etc.

In order to set forth content of the present invention in more detail, please refer to shown in Figure 6ly, it is the structural representation of the grid of the three-layer metal structure of content of the present invention.Identical with the technology mode of double-level-metal structure, with physical vaporous deposition, electroplate, revolve the wherein a kind of of modes such as plating, printing and electroless plating, deposition forms copper alloy layer C1, copper metal layer C2 and a metal level C3 in regular turn.This metal level C3 is a copper alloy layer, and this copper alloy element comprises magnesium, chromium, tungsten, molybdenum, niobium, ruthenium, nitrogen, silver, carbon and hybrid alloys thereof.

On the double-level-metal structure, add the layer of copper alloy-layer again, not only can avoid the oxidation of copper, can also increase andgate insulator 140 between degree of adhering to, and the effect that increases metallic barrier.In addition, because copper metal layer C2 itself easily produces the phenomenon of protrusion of surface (Hillock) because of follow-up heat treatment, therefore, can effectively suppress the phenomenon of copper metal layer C2 protrusion of surface if on copper metal layer C2, cover layer of metal layer C3 again.

In addition, the copper alloy element that is comprised in copper alloy layer C1 and the metal level C3, except the copper metallic element, the shared composition of remaining alloying element is about 0.2 to 10 percentage.

The advantage that content of the present invention provided is, utilizes multi-layer metal structure to make the grid of thin-film transistor, source electrode and drain electrode.

Another advantage that content of the present invention provided is, utilizes a copper metal layer and a copper alloy layer to form the grid of double-level-metal structure, after heat treatment, can improve the atomic arrangement between the lattice interface, and interatomic bond (promptly promoting degree of adhering to), and reduce resistance, suppress the copper ion diffusion.

The advantage again that content of the present invention provided is, utilize two copper alloy layers to come double team one copper metal layer to form the grid of three-layer metal structure, the advantage that not only has the double-level-metal structure more can be avoided the phenomenon of burning, increases the effect with the degree of adhering to and the resistance barrier of gate insulator interlayer.

The advantage again that content of the present invention provided is, copper alloy layer and copper metal layer when graphical, are only needed the individual layer copper etchant solution, and need not two kinds of different metallic films of etching, can simplify the graphical technology of lead.

The advantage again that content of the present invention provided is, on the copper metal layer of double-level-metal structure, covers the layer of metal layer again, suppresses the phenomenon of copper metal layer surface because of follow-up heat treatment generation projection, with the inefficacy of avoiding causing the TFT assembly electrical.

The advantage again that content of the present invention provided is, forms earlier copper alloy layer and copper metal layer in regular turn on substrate, and is again that it is graphical, does heat treatment at last, to produce grid.

The advantage again that content of the present invention provided is, forms earlier copper alloy layer and copper metal layer in regular turn on substrate, and is again that it is graphical at last again with its heat treatment, to produce grid.

The advantage again that content of the present invention provided is that heat treated temperature is about 100 to 500 ℃.

The advantage again that content of the present invention provided is that the thickness of copper alloy layer is about 10 to 2000 dusts, and the thickness of copper metal layer is about 1000 to 4000 dusts, and about 0.2 to 10 the percentage of the content except the copper metallic element in the copper alloy element.

Appended graphic reference and the explanation usefulness of only providing not is to be used for the present invention is limited.The above only is a preferable possible embodiments of the present invention, and non-so promptly inflexible limit claim of the present invention so the equivalent structure that uses specification of the present invention and icon content to do such as changes, all in like manner is contained in the scope of the present invention, closes and gives Chen Ming.

Claims (18)

Translated fromChinese

1.一种薄膜晶体管，其特征在于，包含：1. A thin film transistor, characterized in that it comprises:一栅极与一栅极线，形成在一基板上，而每一栅极与栅极线皆包含至少一铜合金层及一铜金属层，且该栅极为该栅极线的延伸；A gate and a gate line are formed on a substrate, each of the gate and the gate line includes at least a copper alloy layer and a copper metal layer, and the gate is an extension of the gate line;一栅极绝缘层，形成在该基板上，且覆盖在该栅极与该栅极线上方；a gate insulating layer formed on the substrate and covering the gate and the gate line;一有源层，形成在该栅极绝缘层上，且覆盖在部分该栅极上；an active layer formed on the gate insulating layer and covering part of the gate;一欧姆接触层，形成在该有源层上；an ohmic contact layer formed on the active layer;一数据线，形成在该栅极绝缘层上，且与该栅极线相交，以定义出一像素范围；A data line is formed on the gate insulating layer and intersects with the gate line to define a pixel range;一源极与一漏极，皆形成在该欧姆接触层上，且该源极是由该数据线延伸而出，以及该漏极配置于该源极相隔一间距之处；A source and a drain are both formed on the ohmic contact layer, and the source is extended from the data line, and the drain is arranged at a distance from the source;一保护层，形成在该栅极绝缘层上，且覆盖至该数据线、该源极及该漏极，其中该保护层包含一漏极接触口；以及a protection layer is formed on the gate insulating layer and covers the data line, the source and the drain, wherein the protection layer includes a drain contact; and一像素电极，形成在该像素范围内的该保护层上，且通过该漏极接触口来连结于该漏极。A pixel electrode is formed on the protection layer within the pixel range and connected to the drain through the drain contact opening.2.如权利要求1所述的薄膜晶体管，其特征在于，该铜合金层的铜合金元素为镁、铬、钨、钼、铌、氮、银、钌、碳及其混合合金，且该铜合金层除了其本身的金属元素外，其余的金属元素成分含量为0.2至10的百分比。2. The thin film transistor according to claim 1, wherein the copper alloy elements of the copper alloy layer are magnesium, chromium, tungsten, molybdenum, niobium, nitrogen, silver, ruthenium, carbon and mixed alloys thereof, and the copper In addition to the metal elements of the alloy layer itself, the composition content of other metal elements is 0.2 to 10%.3.如权利要求1所述的薄膜晶体管，其特征在于，该源极与该漏极皆为具有另一铜合金层及另一铜金属层的双层金属结构，且与该栅极及该栅极线有同样的厚度与成分。3. The thin film transistor according to claim 1, wherein the source and the drain are double-layer metal structures having another copper alloy layer and another copper metal layer, and are connected to the gate and the drain. The gate lines have the same thickness and composition.4.如权利要求1所述的薄膜晶体管，其特征在于，该铜合金层的厚度为10到2000埃，该铜金属层的厚度为1000到4000埃。4. The thin film transistor according to claim 1, wherein the copper alloy layer has a thickness of 10 to 2000 angstroms, and the copper metal layer has a thickness of 1000 to 4000 angstroms.5.一种薄膜晶体管的栅极，其特征在于，包含：5. A gate of a thin film transistor, characterized in that it comprises:一铜合金层，形成在一基板上；以及a copper alloy layer formed on a substrate; and一铜金属层，形成在该铜合金层上。A copper metal layer is formed on the copper alloy layer.6.如权利要求5所述的薄膜晶体管的栅极，其特征在于，该铜合金层的厚度为10到2000埃，该铜金属层的厚度为1000到4000埃。6 . The gate of a thin film transistor as claimed in claim 5 , wherein the copper alloy layer has a thickness of 10 to 2000 angstroms, and the copper metal layer has a thickness of 1000 to 4000 angstroms.7.如权利要求5所述的薄膜晶体管的栅极，其特征在于，该铜合金层的铜合金元素为镁、铬、钨、钼、铌、氮、钌、银、碳及其混合合金，且该铜合金层除了其本身的金属元素外，其余的金属元素成分含量为0.2至10的百分比。7. The gate electrode of a thin film transistor according to claim 5, wherein the copper alloy elements of the copper alloy layer are magnesium, chromium, tungsten, molybdenum, niobium, nitrogen, ruthenium, silver, carbon and mixed alloys thereof, In addition to the metal elements of the copper alloy layer itself, the content of other metal elements is 0.2 to 10%.8.如权利要求5所述的薄膜晶体管的栅极，其特征在于，该栅极更进一步包含另一铜合金层，制作在该铜金属层上。8. The gate of a thin film transistor as claimed in claim 5, wherein the gate further comprises another copper alloy layer fabricated on the copper metal layer.9.如权利要求8所述的薄膜晶体管的栅极，其特征在于，该另一铜合金层的铜合金元素、比例及厚度皆与形成在该基板上的铜合金层相同。9 . The gate electrode of a thin film transistor as claimed in claim 8 , wherein the copper alloy element, proportion and thickness of the another copper alloy layer are the same as those of the copper alloy layer formed on the substrate.10.一种薄膜晶体管的制造方法，其特征在于，包含：10. A method for manufacturing a thin film transistor, characterized in that it comprises:依序形成至少一铜合金层及一铜金属层于一基板上，以产生一图形化的栅极与栅极线，其中，该栅极是由该栅极线延伸而来；sequentially forming at least one copper alloy layer and a copper metal layer on a substrate to produce a patterned gate and gate lines, wherein the gate is extended from the gate line;依序于该基板、该栅极与该栅极线上，由下而上堆栈形成图案化的一栅极绝缘层、一有源层及一欧姆接触层；sequentially forming a patterned gate insulating layer, an active layer and an ohmic contact layer stacked from bottom to top on the substrate, the gate and the gate line;形成一数据线、一源极及一漏极，其中该数据线设置于该栅极绝缘层上，且与该栅极线相交，以定义出一像素范围，该源极是由该数据线延伸至该欧姆接触层，该漏极则单独设置于在该欧姆接触层上离该源极一间距之处；forming a data line, a source and a drain, wherein the data line is arranged on the gate insulating layer and intersects with the gate line to define a pixel range, and the source is extended from the data line To the ohmic contact layer, the drain is separately disposed on the ohmic contact layer at a distance from the source;形成一保护层于该栅极绝缘层上，并覆盖过该数据线、该源极及该漏极，其中，该保护层包含一漏极接触口，使该漏极暴露出一部分；以及forming a protection layer on the gate insulating layer and covering the data line, the source and the drain, wherein the protection layer includes a drain contact opening to expose a part of the drain; and形成一像素电极于该保护层上，其中该像素电极通过该漏极接触口来接触该漏极。A pixel electrode is formed on the protective layer, wherein the pixel electrode contacts the drain through the drain contact opening.11.如权利要求10所述的薄膜晶体管的制造方法，其特征在于，形成该栅极与该栅极线更进一步包含：11. The method for manufacturing a thin film transistor according to claim 10, wherein forming the gate and the gate line further comprises:依序由下至上形成该铜合金层及该铜金属层于该基板上；forming the copper alloy layer and the copper metal layer on the substrate sequentially from bottom to top;将该铜合金层与该铜金属层图形化；以及patterning the copper alloy layer and the copper metal layer; and将该基板、该铜合金层与该铜金属层进行热处理，以形成该图形化的栅极与栅极线。The substrate, the copper alloy layer and the copper metal layer are heat-treated to form the patterned gate and gate lines.12.如权利要求10所述的薄膜晶体管的制造方法，其特征在于，形成该栅极与该栅极线更进一步包含：12. The method for manufacturing a thin film transistor according to claim 10, wherein forming the gate and the gate line further comprises:依序由下至上形成该铜合金层及该铜金属层于该基板上；forming the copper alloy layer and the copper metal layer on the substrate sequentially from bottom to top;将该铜合金层与该铜金属层作热处理；以及heat treating the copper alloy layer and the copper metal layer; and将该基板、该铜合金层与该铜金属层图形化，以形成该图形化的栅极与栅极线。The substrate, the copper alloy layer and the copper metal layer are patterned to form the patterned gate and gate lines.13.如权利要求10所述的薄膜晶体管的制造方法，其特征在于，形成该栅极与该栅极线所需的热处理的温度为100至500℃。13 . The method for manufacturing a thin film transistor as claimed in claim 10 , wherein the temperature of heat treatment required for forming the gate and the gate line is 100 to 500° C. 14 .14.如权利要求10所述的薄膜晶体管的制造方法，其特征在于，该源极与该漏极皆为具有另一铜合金层及另一铜金属层的多层金属结构，且与该栅极及该栅极线有同样的厚度、成分及热处理温度。14. The manufacturing method of a thin film transistor according to claim 10, wherein the source and the drain are multilayer metal structures having another copper alloy layer and another copper metal layer, and are connected to the gate The electrode and the gate line have the same thickness, composition and heat treatment temperature.15.一种薄膜晶体管的栅极的制造方法，其特征在于，包含：15. A method for manufacturing a gate of a thin film transistor, comprising:依序形成至少一铜合金层及一铜金属层于一基板上，以产生该栅极。At least one copper alloy layer and one copper metal layer are sequentially formed on a substrate to produce the gate.16.如权利要求15所述的薄膜晶体管的栅极的制造方法，其特征在于，更进一步包含：16. The method for manufacturing the gate of a thin film transistor according to claim 15, further comprising:依序由下至上形成该铜合金层及该铜金属层于该基板上；forming the copper alloy layer and the copper metal layer on the substrate sequentially from bottom to top;将该铜合金层与该铜金属层图形化；以及patterning the copper alloy layer and the copper metal layer; and将该基板、该铜合金层与该铜金属层进行热处理，以形成该图形化的栅极。The substrate, the copper alloy layer and the copper metal layer are heat-treated to form the patterned grid.17.如权利要求15所述的薄膜晶体管的栅极的制造方法，其特征在于，更进一步包含：17. The method for manufacturing the gate of a thin film transistor according to claim 15, further comprising:依序由下至上形成该铜合金层及该铜金属层于该基板上；forming the copper alloy layer and the copper metal layer on the substrate sequentially from bottom to top;将该铜合金层及该铜金属层作热处理；heat-treating the copper alloy layer and the copper metal layer;将该铜合金层及该铜金属层图形化，以形成该图形化的栅极。The copper alloy layer and the copper metal layer are patterned to form the patterned grid.18.如权利要求15所述的薄膜晶体管的栅极的制造方法，其特征在于，形成该栅极所需的热处理的温度是在100至500℃。18 . The method for manufacturing a gate of a thin film transistor as claimed in claim 15 , wherein the temperature of heat treatment required for forming the gate is 100 to 500° C.

Images