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CN101079967B - Solid-state imaging device, manufacturing method thereof, and video camera - Google Patents

Solid-state imaging device, manufacturing method thereof, and video camera
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CN101079967B
CN101079967BCN2007101282503ACN200710128250ACN101079967BCN 101079967 BCN101079967 BCN 101079967BCN 2007101282503 ACN2007101282503 ACN 2007101282503ACN 200710128250 ACN200710128250 ACN 200710128250ACN 101079967 BCN101079967 BCN 101079967B
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film
photodetector
solid
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imaging device
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丸山康
山口哲司
安藤崇志
桧山晋
大岸裕子
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Sony Corp
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Abstract

Translated fromChinese

本发明提供一种固态成像装置,包括具有第一表面和第二表面的衬底,光入射在第二表面侧;设置在第一表面侧的布线层;形成在衬底中且包括第一导电类型的第一区的光电检测器;设置在衬底的第一表面上且邻近光电检测器的转移栅极,转移栅极传输积累在光电检测器中的信号电荷;设置在衬底的第一表面且叠置在光电检测器上的至少一个控制栅极,控制栅极控制第一表面附近该光电检测器的电势。

The present invention provides a solid-state imaging device, including a substrate having a first surface and a second surface, light is incident on the second surface side; a wiring layer arranged on the first surface side; a photodetector formed in the substrate and including a first region of a first conductivity type; a transfer gate arranged on the first surface of the substrate and adjacent to the photodetector, the transfer gate transferring signal charge accumulated in the photodetector; and at least one control gate arranged on the first surface of the substrate and superimposed on the photodetector, the control gate controlling the potential of the photodetector near the first surface.

Description

Translated fromChinese
固态成像装置及其制造方法、以及摄像机Solid-state imaging device, manufacturing method thereof, and video camera

技术领域technical field

本发明涉及固态成像装置、制造该装置的方法、以及包括该固态成像装置的摄像机(camera)。The present invention relates to a solid-state imaging device, a method of manufacturing the same, and a camera including the solid-state imaging device.

背景技术Background technique

已知在固态成像装置例如电荷耦合装置(CCD)图像传感器和互补金属氧化物半导体(CMOS)图像传感器中,在用作光敏接收器(photoreceiver)的光电二极管(photodiode)中的晶体缺陷、以及光敏接收器与光敏接收器上的绝缘膜之间的每个界面处的界面态起到暗电流(dark current)的源的作用。为了抑制由于界面态而产生暗电流,有效地使用嵌入式(buried)光电二极管结构。嵌入式光电二极管包括用于抑制暗电流的n型半导体区和浅p型半导体区(空穴积累区),p型半导体区具有高杂质浓度并设置在n型半导体区的表面上,即设置在n型半导体区和绝缘膜之间的界面附近。制造嵌入式光电二极管的方法通常包括注入用作p型杂质的B离子或BF2离子;以及进行退火以在构成光电二极管的n型半导体区和绝缘膜之间的界面附近形成p型半导体区。Crystal defects in photodiodes (photodiodes) used as photoreceivers, and photosensitive The interface state at each interface between the receiver and the insulating film on the photosensitive receiver functions as a source of dark current. In order to suppress the generation of dark current due to the interface state, a buried photodiode structure is effectively used. The embedded photodiode includes an n-type semiconductor region for suppressing dark current and a shallow p-type semiconductor region (hole accumulation region). Near the interface between the n-type semiconductor region and the insulating film. A method of manufacturing an embedded photodiode generally includes implanting B ions or BF2 ions serving as p-type impurities; and performing annealing to form a p-type semiconductor region near the interface between an n-type semiconductor region constituting the photodiode and an insulating film.

然而,在通过已知的离子注入形成嵌入式光电二极管的情况下,在高达700℃或更高的温度下的热处理对于杂质的激活是必要的。因此,在400℃或更低温度的低温工艺中,难以通过离子注入形成p型半导体区。此外,考虑到杂质扩散的抑制,通过离子注入和高温下长时段的激活退火来形成p型半导体区的方法是不期望的。However, in the case of forming an embedded photodiode by known ion implantation, heat treatment at a temperature as high as 700° C. or higher is necessary for the activation of impurities. Therefore, it is difficult to form a p-type semiconductor region by ion implantation in a low-temperature process of 400° C. or lower. Furthermore, a method of forming a p-type semiconductor region by ion implantation and activation annealing at a high temperature for a long period of time is not desirable in view of suppression of impurity diffusion.

在CMOS图像传感器中,每个像素包括光电二极管和各种晶体管,诸如读取晶体管(read transistor)、复位晶体管(reset transistor)、以及放大晶体管(amplifying transistor)。用光电二极管光电转换的信号用晶体管处理。每个像素覆盖有包括多个金属引线(lead)子层的布线层。布线层覆盖有滤色器和芯片上透镜(on-chip lens),滤色器确定入射在光电二极管上的光的波长,芯片上透镜将光会聚在光电二极管上。In a CMOS image sensor, each pixel includes a photodiode and various transistors, such as a read transistor, a reset transistor, and an amplifying transistor. The signal photoelectrically converted by the photodiode is processed by the transistor. Each pixel is covered with a wiring layer comprising a plurality of metal lead sub-layers. The wiring layer is covered with color filters that determine the wavelength of light incident on the photodiodes and on-chip lenses that focus the light on the photodiodes.

在CMOS图像传感器中,像素上的引线不利地阻挡光,从而降低灵敏度。当从引线反射的光入射在相邻像素上时,造成色混(color mixture)等。因此,日本未审专利申请公开No.2003-31785公开了一种背面照射固态成像装置,其光电转换从包括光电二极管和各种晶体管的硅衬底的背面入射的光,硅衬底具有通过抛光其背面而减小的厚度。如上所述,光电二极管包括用于抑制暗电流的浅p型半导体区(空穴积累区),该p型半导体区具有高杂质浓度。在背面照射固态成像装置中,空穴积累区设置在衬底的正面和背面的每个处。In CMOS image sensors, the leads on the pixels disadvantageously block light, reducing sensitivity. When light reflected from a lead is incident on an adjacent pixel, color mixture or the like is caused. Accordingly, Japanese Unexamined Patent Application Publication No. 2003-31785 discloses a back-illuminated solid-state imaging device that photoelectrically converts light incident from the back side of a silicon substrate including photodiodes and various transistors having The thickness of its back is reduced. As described above, a photodiode includes a shallow p-type semiconductor region (hole accumulation region) having a high impurity concentration for suppressing dark current. In a back-illuminated solid-state imaging device, a hole accumulation region is provided at each of the front and back sides of a substrate.

然而,离子注入限制了具有高杂质浓度的浅p型半导体区的形成。因此,为了抑制暗电流,在p型半导体区中的杂质浓度的进一步增加加深了p型半导体区。深p型半导体区会降低转移栅极(transfer gate)的读取能力,因为光电二极管的pn结远离转移栅极。However, ion implantation limits the formation of shallow p-type semiconductor regions with high impurity concentrations. Therefore, further increase in impurity concentration in the p-type semiconductor region deepens the p-type semiconductor region in order to suppress dark current. The deep p-type semiconductor region reduces the readability of the transfer gate because the pn junction of the photodiode is far away from the transfer gate.

发明内容Contents of the invention

考虑到上述问题,期望提供一种能够抑制由于至少界面态引起的暗电流的固态成像装置、制造该装置的方法、以及包括该固态成像装置的摄像机。In view of the above-mentioned problems, it is desirable to provide a solid-state imaging device capable of suppressing dark current due to at least an interface state, a method of manufacturing the device, and a video camera including the solid-state imaging device.

根据本发明一实施例的固态成像装置包括:具有第一表面和第二表面的衬底,光入射在该第二表面侧;设置在该第一表面侧的布线层;形成在该衬底中且包括第一导电类型的第一区的光电检测器(photodetector);设置在该衬底的第一表面上且与该光电检测器相邻的转移栅极,该转移栅极传输在光电检测器中积累的信号电荷;以及设置在该衬底的第一表面上且叠置在该光电检测器上的至少一个控制栅极,该控制栅极控制该第一表面附近该光电检测器的电势。A solid-state imaging device according to an embodiment of the present invention includes: a substrate having a first surface and a second surface on which light is incident; a wiring layer provided on the first surface side; and a photodetector (photodetector) comprising a first region of the first conductivity type; a transfer gate disposed on the first surface of the substrate and adjacent to the photodetector, the transfer gate transmitting the photodetector and at least one control gate disposed on the first surface of the substrate overlying the photodetector, the control gate controlling the potential of the photodetector near the first surface.

根据本发明一实施例的制造固态成像装置的方法,该固态成像装置包括具有第一表面和第二表面的衬底,设置在该第一表面侧的布线层,光入射在该第二表面侧,该方法包括步骤:在该衬底中形成包括第一导电类型的第一区的光电检测器;形成在该衬底的第一表面上的区域处且与该光电检测器相邻的转移栅极;以及形成在该衬底的第一表面上的区域处且叠置在该光电检测器上的控制栅极。According to a method of manufacturing a solid-state imaging device according to an embodiment of the present invention, the solid-state imaging device includes a substrate having a first surface and a second surface, a wiring layer provided on the first surface side, and light incident on the second surface side , the method comprising the steps of: forming a photodetector comprising a first region of a first conductivity type in the substrate; forming a transfer gate adjacent to the photodetector at a region on the first surface of the substrate and a control gate formed at a region on the first surface of the substrate and overlying the photodetector.

根据本发明一实施例的摄像机包括:固态成像装置,该固态成像装置具有衬底,该衬底具有第一表面和第二表面,光入射在该第二表面侧,以及设置在该第一表面侧的布线层;将入射光引导到第二表面侧的光学系统;以及处理该固态成像装置的输出信号的信号处理电路;其中该固态成像装置还包括设置在该衬底中且包括第一导电类型的第一区的光电检测器,设置在该衬底的第一表面上且与该光电检测器相邻的转移栅极,该转移栅极传输在该光电检测器中积累的信号电荷;以及设置在该衬底的第一表面上且叠置在该光电检测器上的控制栅极,该控制栅极控制该第一表面附近该光电检测器的电势。A video camera according to an embodiment of the present invention includes: a solid-state imaging device having a substrate having a first surface and a second surface on which light is incident and disposed on the first surface. a wiring layer on the side; an optical system that guides incident light to the second surface side; and a signal processing circuit that processes an output signal of the solid-state imaging device; wherein the solid-state imaging device also includes a first conductive a photodetector of the first region of the type, a transfer gate disposed on the first surface of the substrate adjacent to the photodetector, the transfer gate transferring signal charges accumulated in the photodetector; and A control gate is disposed on the first surface of the substrate overlying the photodetector, the control gate controlling the potential of the photodetector proximate the first surface.

根据本发明一实施例,该控制栅极可以控制该第一表面附近该光电检测器的电势,因此抑制暗电流的产生。此外,信号电荷积累在第一导电类型的第一区中和光电检测器的第一表面附近,因此提高了转移栅极读取信号电荷的能力。According to an embodiment of the present invention, the control gate can control the potential of the photodetector near the first surface, thereby suppressing the generation of dark current. In addition, signal charges are accumulated in the first region of the first conductivity type and near the first surface of the photodetector, thus improving the ability of the transfer gate to read signal charges.

根据本发明一实施例的固态成像装置包括设置在光电检测器的光接收表面上方的透明导电膜;以及设置在光接收表面和透明导电膜之间的绝缘膜,该绝缘膜具有50nm或更小的厚度。A solid-state imaging device according to an embodiment of the present invention includes a transparent conductive film provided over a light receiving surface of a photodetector; and an insulating film provided between the light receiving surface and the transparent conductive film, the insulating film having a thickness of 50 nm or less thickness of.

根据本发明一实施例的固态成像装置包括设置在光电检测器的光接收表面上方的透明导电膜;以及设置在光接收表面和透明导电膜之间的层叠膜,该层叠膜包括至少两类子膜,其中与光接收表面接触的子膜是具有50nm或更小厚度的硅氧化物子膜。A solid-state imaging device according to an embodiment of the present invention includes a transparent conductive film provided over a light-receiving surface of a photodetector; and a laminated film provided between the light-receiving surface and the transparent conductive film, the laminated film including at least two types of A film wherein the subfilm in contact with the light receiving surface is a silicon oxide subfilm having a thickness of 50 nm or less.

根据本发明一实施例的制造固态成像装置的方法包括步骤:在形成于衬底中的光电检测器的光接收表面上形成绝缘膜,该光电检测器包括第一导电类型的第一区,该绝缘膜具有50nm或更小的厚度;以及在该绝缘膜上形成透明导电膜。A method of manufacturing a solid-state imaging device according to an embodiment of the present invention includes the step of forming an insulating film on a light-receiving surface of a photodetector formed in a substrate, the photodetector including a first region of a first conductivity type, the the insulating film has a thickness of 50 nm or less; and a transparent conductive film is formed on the insulating film.

根据本发明一实施例的制造固态成像装置的方法包括步骤:在具有第一导电类型的第一区的光电检测器的光接收表面上形成层叠绝缘膜,该光电检测器形成于衬底中,该层叠绝缘膜包括至少两类子膜且包括与该光接收表面接触的硅氧化物子膜,该硅氧化物子膜具有50nm或更小的厚度;以及在该层叠绝缘膜上形成透明导电膜。A method of manufacturing a solid-state imaging device according to an embodiment of the present invention includes the steps of: forming a laminated insulating film on a light-receiving surface of a photodetector having a first region of a first conductivity type, the photodetector being formed in a substrate, The laminated insulating film includes at least two types of subfilms and includes a silicon oxide subfilm in contact with the light receiving surface, the silicon oxide subfilm having a thickness of 50 nm or less; and forming a transparent conductive film on the laminated insulating film .

根据本发明一实施例的摄像机包括:将入射光引导到固态成像装置的光电检测器的光学系统;以及处理固态成像装置的输出信号的信号处理电路;其中该固态成像装置包括设置在该光电检测器的光接收表面上方的透明导电膜,以及设置在该光接收表面和该透明导电膜之间的绝缘膜,该绝缘膜具有50nm或更小的厚度。A video camera according to an embodiment of the present invention includes: an optical system that guides incident light to a photodetector of a solid-state imaging device; and a signal processing circuit that processes an output signal of the solid-state imaging device; A transparent conductive film over a light-receiving surface of the device, and an insulating film disposed between the light-receiving surface and the transparent conductive film, the insulating film having a thickness of 50 nm or less.

根据本发明一实施例的摄像机包括将入射光引导到固态成像装置的光电检测器的光学系统;以及处理该固态成像装置的输出信号的信号处理电路;其中该固态成像装置包括设置在该光电检测器的光接收表面上方的透明导电膜,以及设置在该光接收表面和该透明导电膜之间的层叠膜,该层叠膜包括至少两类子膜,其中与光接收表面接触的子膜是具有50nm或更小厚度的硅氧化物子膜。A video camera according to an embodiment of the present invention includes an optical system that guides incident light to a photodetector of a solid-state imaging device; and a signal processing circuit that processes an output signal of the solid-state imaging device; A transparent conductive film above the light receiving surface of the device, and a laminated film disposed between the light receiving surface and the transparent conductive film, the laminated film includes at least two types of sub-films, wherein the sub-film in contact with the light-receiving surface has A silicon oxide sub-film with a thickness of 50nm or less.

根据本发明一实施例,该透明导电膜可以控制光电检测器的光接收表面的电势,从而抑制暗电流的产生。此外,因为设置在该光接收表面和该透明导电膜之间的绝缘膜的厚度设置为50nm或更小,绝缘膜和透明导电膜的组合形成抗反射膜。可替换地,在层叠绝缘膜的情况,与光接收表面接触的硅氧化物子膜的厚度设置为50nm或更小,绝缘膜和透明导电膜的组合形成抗反射膜。所得抗反射膜改善了光电检测器中的光吸收系数,从而提高灵敏度。According to an embodiment of the present invention, the transparent conductive film can control the potential of the light-receiving surface of the photodetector, thereby suppressing the generation of dark current. Furthermore, since the thickness of the insulating film provided between the light receiving surface and the transparent conductive film is set to 50 nm or less, the combination of the insulating film and the transparent conductive film forms an antireflection film. Alternatively, in the case of laminating an insulating film, the thickness of the silicon oxide sub-film in contact with the light-receiving surface is set to 50 nm or less, and the combination of the insulating film and the transparent conductive film forms an antireflection film. The resulting antireflection film improves the light absorption coefficient in the photodetector, thereby increasing sensitivity.

根据本发明一实施例的固态成像装置包括设置在光电检测器的光接收表面上且具有负固定电荷的膜。优选地,具有负固定电荷的膜是至少部分晶化的绝缘膜。A solid-state imaging device according to an embodiment of the present invention includes a film provided on a light-receiving surface of a photodetector and having negative fixed charges. Preferably, the film having a negative fixed charge is an at least partially crystallized insulating film.

根据本发明一实施例的摄像机包括将入射光引导到固态成像装置的光电检测器的光学系统;以及处理固态成像装置的输出信号的信号处理电路;其中该固态成像装置包括设置在该光电检测器的光接收表面上且具有负固定电荷的膜。A video camera according to an embodiment of the present invention includes an optical system that guides incident light to a photodetector of a solid-state imaging device; and a signal processing circuit that processes an output signal of the solid-state imaging device; wherein the solid-state imaging device includes an optical system disposed on the photodetector A film with a negative fixed charge on the light-receiving surface.

根据本发明一实施例,所述膜设置在光电检测器的光接收表面上且具有负固定电荷,从而在光电检测器的表面上形成空穴积累状态,且抑制由于界面态引起的暗电流的产生。According to an embodiment of the present invention, the film is disposed on the light-receiving surface of the photodetector and has negative fixed charges, thereby forming a hole accumulation state on the surface of the photodetector and suppressing the generation of dark current due to the interface state. produce.

附图说明Description of drawings

图1是根据本发明第一至第六实施例的固态成像装置的示意框图;1 is a schematic block diagram of solid-state imaging devices according to first to sixth embodiments of the present invention;

图2是像素部分的单位像素的示意电路图;2 is a schematic circuit diagram of a unit pixel of a pixel portion;

图3是固态成像装置的示意剖面图;3 is a schematic cross-sectional view of a solid-state imaging device;

图4是根据第一实施例的固态成像装置的衬底的局部剖面图;4 is a partial sectional view of a substrate of the solid-state imaging device according to the first embodiment;

图5是示出根据第一实施例的固态成像装置的操作中的偏压示例的表;5 is a table showing an example of bias voltages in the operation of the solid-state imaging device according to the first embodiment;

图6A和6B每个是剖面图,示出根据第一实施例的固态成像装置的制造工艺的示例;6A and 6B are each a sectional view showing an example of a manufacturing process of the solid-state imaging device according to the first embodiment;

图7A和7B每个是剖面图,示出根据第一实施例的固态成像装置的制造工艺的示例;7A and 7B are each a sectional view showing an example of the manufacturing process of the solid-state imaging device according to the first embodiment;

图8A-8C每个是剖面图,示出根据第一实施例的固态成像装置的制造工艺的另一示例;8A-8C are each a sectional view showing another example of the manufacturing process of the solid-state imaging device according to the first embodiment;

图9A-9C每个是剖面图,示出根据第一实施例的固态成像装置的制造工艺的另一示例;9A-9C are each a sectional view showing another example of the manufacturing process of the solid-state imaging device according to the first embodiment;

图10示出摄像机的示意构造;Fig. 10 shows the schematic structure of video camera;

图11是根据第二实施例的固态成像装置的衬底的局部剖面图;11 is a partial sectional view of a substrate of a solid-state imaging device according to a second embodiment;

图12是表,示出根据第二实施例的固态成像装置的操作中的偏压示例;12 is a table showing an example of bias voltages in the operation of the solid-state imaging device according to the second embodiment;

图13是根据第三实施例的固态成像装置的衬底的局部剖面图;13 is a partial sectional view of a substrate of a solid-state imaging device according to a third embodiment;

图14是根据第四实施例的固态成像装置的衬底的局部剖面图;14 is a partial sectional view of a substrate of a solid-state imaging device according to a fourth embodiment;

图15是曲线图,示出根据第四实施例的固态成像装置的光电二极管中蓝光和绿光的吸收系数,吸收系数通过模拟确定;15 is a graph showing absorption coefficients of blue light and green light in a photodiode of a solid-state imaging device according to a fourth embodiment, the absorption coefficients being determined by simulation;

图16是强度曲线图,示出根据第四实施例的固态成像装置的光电二极管中具有450nm波长的光的吸收系数;16 is an intensity graph showing an absorption coefficient of light having a wavelength of 450 nm in a photodiode of a solid-state imaging device according to a fourth embodiment;

图17是强度曲线图,示出根据第四实施例的固态成像装置的光电二极管中具有550nm波长的光的吸收系数;17 is an intensity graph showing an absorption coefficient of light having a wavelength of 550 nm in a photodiode of a solid-state imaging device according to a fourth embodiment;

图18是曲线图,示出根据第四实施例的固态成像装置的光电二极管中蓝光和绿光的吸收系数,硅氧化物膜的厚度固定到20nm,透明导电膜(ITO膜)的厚度变化;18 is a graph showing the absorption coefficients of blue light and green light in the photodiode of the solid-state imaging device according to the fourth embodiment, the thickness of the silicon oxide film is fixed to 20 nm, and the thickness change of the transparent conductive film (ITO film);

图19是曲线图,示出根据第四实施例的固态成像装置的光电二极管中蓝光和绿光的吸收系数,硅氧化物膜的厚度固定到160nm,ITO膜的厚度变化;19 is a graph showing absorption coefficients of blue light and green light in a photodiode of a solid-state imaging device according to a fourth embodiment, the thickness of the silicon oxide film is fixed to 160 nm, and the thickness of the ITO film is changed;

图20是根据第五实施例的固态成像装置的衬底的局部剖面图;20 is a partial sectional view of a substrate of a solid-state imaging device according to a fifth embodiment;

图21A-21D每个是工艺图(1),示出制造根据第四实施例的固态成像装置的方法;21A-21D are each a process diagram (1) showing a method of manufacturing the solid-state imaging device according to the fourth embodiment;

图22E-22G每个是工艺图(2),示出制造根据第四实施例的固态成像装置的方法;22E-22G are each a process diagram (2) showing a method of manufacturing the solid-state imaging device according to the fourth embodiment;

图23A-23D每个是工艺图(1),示出制造根据第五实施例的固态成像装置的方法;23A-23D are each a process diagram (1) showing a method of manufacturing the solid-state imaging device according to the fifth embodiment;

图24E-24G每个是工艺图(2),示出制造根据第五实施例的固态成像装置的方法;24E-24G are each a process diagram (2) showing a method of manufacturing the solid-state imaging device according to the fifth embodiment;

图25是根据第六实施例的固态成像装置的衬底的局部剖面图;25 is a partial sectional view of a substrate of a solid-state imaging device according to a sixth embodiment;

图26是曲线图,示出根据第六实施例的包括铪氧化物膜的固态成像装置的蓝和绿光电二极管中光的吸收系数;26 is a graph showing absorption coefficients of light in blue and green photodiodes of a solid-state imaging device including a hafnium oxide film according to a sixth embodiment;

图27A和27B每个是有或没有热处理的铪氧化物膜的TEM照片;27A and 27B are each a TEM photograph of a hafnium oxide film with or without heat treatment;

图28是曲线图,示出包括铪氧化物膜的MOS电容器的平带电压Vfb与热处理时间的相关性;28 is a graph showing the dependence of the flat-band voltage Vfb of a MOS capacitor including a hafnium oxide film on the heat treatment time;

图29是曲线图,示出包括铪氧化物膜的MOS电容器的平带电压Vfb与热处理温度的相关性;29 is a graph showing the dependence of the flat-band voltage Vfb of a MOS capacitor including a hafnium oxide film on the heat treatment temperature;

图30A-30C每个是工艺图(1),示出制造根据第六实施例的固态成像装置的方法;30A-30C are each a process diagram (1) showing a method of manufacturing the solid-state imaging device according to the sixth embodiment;

图31D和31E每个是工艺图(2),示出制造根据第六实施例的固态成像装置的方法;以及31D and 31E are each a process diagram (2) showing a method of manufacturing the solid-state imaging device according to the sixth embodiment; and

图32F和32G每个是工艺图(3),示出制造根据第六实施例的固态成像装置的方法。32F and 32G are each a process diagram (3) showing a method of manufacturing the solid-state imaging device according to the sixth embodiment.

具体实施方式Detailed ways

下面参照附图描述本发明的实施例。Embodiments of the present invention are described below with reference to the drawings.

图1是根据本发明一实施例的固态成像装置的示意框图。FIG. 1 is a schematic block diagram of a solid-state imaging device according to an embodiment of the present invention.

固态成像装置包括像素部分11和外围电路,像素部分11和外围电路设置在相同的半导体衬底上。在该实施例中,外围电路包括垂直选择电路12、取样保持相关双取样(S/H CDS)电路13、水平选择电路14、时序发生器(timing generator,TG)15、自动增益控制(AGC)电路16、A/D转换器电路17、以及数字放大器18。The solid-state imaging device includes apixel portion 11 and peripheral circuits, which are provided over the same semiconductor substrate. In this embodiment, the peripheral circuit includes avertical selection circuit 12, a sample-and-hold correlated double sampling (S/H CDS)circuit 13, ahorizontal selection circuit 14, a timing generator (timing generator, TG) 15, an automatic gain control (AGC)circuit 16 , A/D converter circuit 17 , anddigital amplifier 18 .

像素部分11包括以矩阵排列的许多单位像素,如下所述。寻址线等沿像素的行延伸。信号线等沿像素的列延伸。Thepixel section 11 includes many unit pixels arranged in a matrix, as described below. Addressing lines and the like extend along rows of pixels. Signal lines and the like extend along columns of pixels.

垂直选择电路12以一行接一行为基础连续选择像素。垂直选择电路12以一列接一列为基础读取像素信号,并且通过垂直信号线将像素信号发送到S/H CDS电路13。S/H CDS电路13进行从像素的列读取的像素信号的信号处理,诸如CDS。Thevertical selection circuit 12 continuously selects pixels on a row-by-row basis. Thevertical selection circuit 12 reads pixel signals on a column-by-column basis, and sends the pixel signals to the S/H CDS circuit 13 through vertical signal lines. The S/H CDS circuit 13 performs signal processing, such as CDS, of pixel signals read from columns of pixels.

水平选择电路14连续读取存储在S/H CDS电路13中的像素信号,然后将像素信号输出到AGC电路16。AGC电路16以预定增益放大从水平选择电路14输送的信号,然后将所得信号输出到A/D转换器电路17。Thehorizontal selection circuit 14 continuously reads the pixel signals stored in the S/H CDS circuit 13, and then outputs the pixel signals to theAGC circuit 16. TheAGC circuit 16 amplifies the signal supplied from thehorizontal selection circuit 14 with a predetermined gain, and then outputs the resulting signal to the A/D converter circuit 17 .

A/D转换器电路17将模拟信号转换成数字信号,然后将信号输出到数字放大器18。数字放大器18适当地放大从A/D转换器电路17输送的数字信号,然后从焊盘(pad)(端子(terminal))输出信号。The A/D converter circuit 17 converts the analog signal into a digital signal, and then outputs the signal to thedigital amplifier 18 . Thedigital amplifier 18 appropriately amplifies the digital signal sent from the A/D converter circuit 17, and then outputs the signal from a pad (terminal).

垂直选择电路12、S/H CDS电路13、水平选择电路14、AGC电路16、A/D转换器电路17、以及数字放大器18的操作基于从时序发生器15输送的各种时序信号。The operations of thevertical selection circuit 12, the S/H CDS circuit 13, thehorizontal selection circuit 14, theAGC circuit 16, the A/D converter circuit 17, and thedigital amplifier 18 are based on various timing signals supplied from thetiming generator 15.

图2是像素部分11中的单位像素的示例的示意电路图。FIG. 2 is a schematic circuit diagram of an example of a unit pixel in thepixel portion 11 .

单位像素包括例如作为光电换能器的光电二极管21。单位像素还包括四个晶体管,即转移晶体管22、放大晶体管23、寻址(address)晶体管24、以及复位(reset)晶体管25,作为每单个光电二极管21的有源元件。A unit pixel includes, for example, aphotodiode 21 as a photoelectric transducer. The unit pixel also includes four transistors, namely, atransfer transistor 22 , anamplification transistor 23 , anaddress transistor 24 , and areset transistor 25 as active elements of eachindividual photodiode 21 .

光电二极管21将入射光光电转换成与光量对应的电荷(在该情况为电子)。转移晶体管22连接于光电二极管21和浮置扩散(FD)区之间。通过驱动线26将驱动信号发送给栅极(转移栅极)导致通过光电二极管21光电转换的电子传输到浮置扩散区。Thephotodiode 21 photoelectrically converts incident light into charges (in this case, electrons) corresponding to the amount of light. Thetransfer transistor 22 is connected between thephotodiode 21 and a floating diffusion (FD) region. Sending a drive signal to the gate (transfer gate) through thedrive line 26 causes the electrons photoelectrically converted by thephotodiode 21 to be transferred to the floating diffusion region.

浮置扩散区连接到放大晶体管23的栅极。放大晶体管23经过寻址晶体管24连接垂直信号线27,并且与设置在像素部分外的恒流源组合构成源跟随器(source follower)。寻址信号通过驱动线28发送到寻址晶体管24的栅极。当寻址晶体管24导通时,放大晶体管23放大浮置扩散区的电势,并且输出与该电势对应的电压到垂直信号线27。从每个像素输出的电压通过垂直信号线27发送到S/H CDS电路13。The floating diffusion is connected to the gate of theamplification transistor 23 . Theamplification transistor 23 is connected to thevertical signal line 27 via theaddress transistor 24, and forms a source follower in combination with a constant current source provided outside the pixel portion. The addressing signal is sent to the gate of addressingtransistor 24 throughdrive line 28 . When theaddress transistor 24 is turned on, theamplification transistor 23 amplifies the potential of the floating diffusion region, and outputs a voltage corresponding to the potential to thevertical signal line 27 . The voltage output from each pixel is sent to the S/H CDS circuit 13 through thevertical signal line 27.

复位晶体管25连接在电源Vdd和浮置扩散区之间。通过驱动线29将复位信号发送到复位晶体管25的栅极将浮置扩散区的电势复位到电源Vdd的电势。以行排列的像素的晶体管的这些操作同时进行,因为以行排列的转移晶体管22、寻址晶体管24、以及复位晶体管25的栅极是连接的。Thereset transistor 25 is connected between the power supply Vdd and the floating diffusion. Sending a reset signal to the gate of thereset transistor 25 through thedrive line 29 resets the potential of the floating diffusion region to the potential of the power supply Vdd. These operations of the transistors of the pixels arranged in a row are performed simultaneously because the gates of thetransfer transistor 22, theaddress transistor 24, and thereset transistor 25 arranged in a row are connected.

图3是固态成像装置的像素部分和外围电路部分的示意剖面图。根据该实施例的固态成像装置从与布线层38位于的第一表面侧相反的第二表面侧接收光。3 is a schematic cross-sectional view of a pixel portion and a peripheral circuit portion of the solid-state imaging device. The solid-state imaging device according to this embodiment receives light from the second surface side opposite to the first surface side where thewiring layer 38 is located.

衬底30是例如n型硅衬底且对应于根据本发明一实施例的衬底。衬底30包括多个光电检测器31,其每个构成单位像素。每个光电检测器31对应于图2所示的光电二极管21。每个光电检测器31由衬底30中的pn结形成。衬底30通过以一方式减小硅晶片的厚度而形成,这样光入射在衬底背侧。衬底30的厚度取决于固态成像装置的类型。在固态成像装置用于可见光的情况,衬底30具有2-6μm的厚度。在固态成像装置用于近红外线的情况,衬底30具有6-10μm的厚度。Thesubstrate 30 is, for example, an n-type silicon substrate and corresponds to a substrate according to an embodiment of the present invention. Thesubstrate 30 includes a plurality ofphotodetectors 31 each constituting a unit pixel. Eachphotodetector 31 corresponds to thephotodiode 21 shown in FIG. 2 . Eachphotodetector 31 is formed by a pn junction in thesubstrate 30 . Thesubstrate 30 is formed by reducing the thickness of the silicon wafer in such a way that light is incident on the backside of the substrate. The thickness of thesubstrate 30 depends on the type of solid-state imaging device. In the case of a solid-state imaging device for visible light, thesubstrate 30 has a thickness of 2-6 μm. In the case of a solid-state imaging device for near-infrared rays, thesubstrate 30 has a thickness of 6-10 μm.

遮光膜33设置在衬底30的第二表面侧(背侧和光入射侧)和由硅氧化物构成的绝缘膜32上。遮光膜33具有位于每个光电检测器31上的开口33a。遮光膜33被覆盖以氮化硅构成的保护膜34。Thelight shielding film 33 is provided on the second surface side (the back side and the light incident side) of thesubstrate 30 and the insulatingfilm 32 made of silicon oxide. Thelight shielding film 33 has anopening 33 a on eachphotodetector 31 . Thelight shielding film 33 is covered with a protective film 34 made of silicon nitride.

保护膜34被覆盖以滤色器35,其仅透射具有预定波长的光。使入射光会聚在每个光电检测器31上的微透镜36设置在滤色器35上。The protective film 34 is covered with acolor filter 35 that transmits only light having a predetermined wavelength. Amicrolens 36 that condenses incident light on eachphotodetector 31 is provided on thecolor filter 35 .

在衬底30的第一表面侧形成各种晶体管。衬底30的像素部分包括图2所示的晶体管22-25(图3中未示出)。衬底30的外围电路部分包括p阱和n阱(未示出)。这些阱包括CMOS电路。Various transistors are formed on the first surface side of thesubstrate 30 . The pixel portion ofsubstrate 30 includes transistors 22-25 shown in FIG. 2 (not shown in FIG. 3). The peripheral circuit portion of thesubstrate 30 includes p-wells and n-wells (not shown). These wells comprise CMOS circuits.

包括多个金属引线子层的布线层38设置在衬底30的第一表面(正面)上。支承衬底39设置在布线层38上,粘合层(未示出)设置在其间。设置支承衬底39以增加衬底30的强度。支承衬底39例如是硅衬底。Awiring layer 38 including a plurality of metal wiring sublayers is disposed on the first surface (front side) of thesubstrate 30 . Asupport substrate 39 is provided on thewiring layer 38 with an adhesive layer (not shown) provided therebetween. Asupport substrate 39 is provided to increase the strength of thesubstrate 30 . Thesupport substrate 39 is, for example, a silicon substrate.

图4是衬底30的像素部分的局部剖面图。FIG. 4 is a partial cross-sectional view of a pixel portion of thesubstrate 30 .

在衬底30的每个光电检测器31中形成n型电荷积累区41(第一导电类型区域)。为了使存储电荷的部分靠近第一表面侧,优选地以一方式形成电荷积累区41从而杂质浓度随着更接近第一表面侧而增大。此外,为了有效地引进入射光,电荷积累区41可以以这样的方式形成,即电荷积累区41的面积随着更接近第二表面侧而增大。An n-type charge accumulation region 41 (first conductivity type region) is formed in eachphotodetector 31 of thesubstrate 30 . In order to make the portion where charges are stored close to the first surface side, it is preferable to form thecharge accumulation region 41 in such a manner that the impurity concentration increases closer to the first surface side. Furthermore, in order to efficiently introduce incident light, thecharge accumulation region 41 may be formed in such a manner that the area of thecharge accumulation region 41 increases closer to the second surface side.

在衬底30中电荷积累区41被P阱42包围。在衬底30的第二表面侧和像素部分的整个表面上形成浅P型空穴积累区43(第二导电类型区域)。在衬底30的第一表面侧和每个光电检测器31上形成浅P型空穴积累区44(第二导电类型区域)。空穴积累区43和44分别形成在电荷积累区41的第一和第二表面侧,从而构成嵌入式光电二极管形成的每个光电检测器31。Charge accumulation region 41 is surrounded by P well 42 insubstrate 30 . Shallow P-type hole accumulation region 43 (second conductivity type region) is formed on the second surface side ofsubstrate 30 and the entire surface of the pixel portion. Shallow P-type hole accumulation regions 44 (second conductivity type regions) are formed on the first surface side ofsubstrate 30 and eachphotodetector 31 .Hole accumulation regions 43 and 44 are respectively formed on the first and second surface sides of thecharge accumulation region 41, thereby constituting eachphotodetector 31 formed of an embedded photodiode.

在衬底30的第一表面侧形成由硅氧化物构成的元件隔离绝缘膜40。在衬底30的第一表面侧形成n型浮置扩散区45。在浮置扩散区45和电荷积累区41之间形成p型区46以将浮置扩散区45与电荷积累区41电分隔开。An elementisolation insulating film 40 made of silicon oxide is formed on the first surface side of thesubstrate 30 . An n-type floatingdiffusion region 45 is formed on the first surface side of thesubstrate 30 . A p-type region 46 is formed between the floatingdiffusion region 45 and thecharge accumulation region 41 to electrically separate the floatingdiffusion region 45 from thecharge accumulation region 41 .

转移晶体管22的转移栅极51形成在衬底30的第一表面上,栅极绝缘膜(未示出)设置于其间。转移栅极51位于与光电检测器31相邻且形成在P型区46上面。转移栅极51例如由多晶硅构成。Thetransfer gate 51 of thetransfer transistor 22 is formed on the first surface of thesubstrate 30 with a gate insulating film (not shown) interposed therebetween.Transfer gate 51 is located adjacent tophotodetector 31 and formed above P-type region 46 . Thetransfer gate 51 is made of, for example, polysilicon.

控制栅极52形成在衬底30的第一表面上,栅极绝缘膜(未示出)设置于其间。控制栅极52叠置在光电检测器31的整个表面上。控制栅极52例如由多晶硅构成。考虑到可加工性和电阻,优选控制栅极52具有与转移栅极51的厚度相当的厚度。光入射在第二表面侧且因此不被设置在光电检测器31的第一表面侧的绝缘膜32遮挡。Thecontrol gate 52 is formed on the first surface of thesubstrate 30 with a gate insulating film (not shown) interposed therebetween. Thecontrol grid 52 is overlaid on the entire surface of thephotodetector 31 . Thecontrol gate 52 is made of, for example, polysilicon. In consideration of workability and resistance, it is preferable that thecontrol gate 52 has a thickness comparable to that of thetransfer gate 51 . The light is incident on the second surface side and thus is not blocked by the insulatingfilm 32 provided on the first surface side of thephotodetector 31 .

除了像素中的转移晶体管22之外,晶体管即图2所示的放大晶体管23、寻址晶体管24和复位晶体管25形成在形成于衬底30的第一表面侧的p阱42上。Transistors, ie,amplification transistor 23 ,address transistor 24 , and resettransistor 25 shown in FIG. 2 , are formed on p-well 42 formed on the first surface side ofsubstrate 30 in addition totransfer transistor 22 in the pixel.

下面参照图4和5描述根据该实施例的固态成像装置的操作。图5是表,示出固态成像装置的操作期间的偏压(bias)示例。The operation of the solid-state imaging device according to this embodiment will be described below with reference to FIGS. 4 and 5 . FIG. 5 is a table showing an example of bias during operation of the solid-state imaging device.

在电荷积累周期,光沿图中所示的箭头指示的方向入射,然后被光电检测器(光电二极管)31光电转换以产生响应于入射光的量的信号电荷。信号电荷在电荷积累区41中漂移且在空穴积累区44附近的电荷积累区41中积累。在电荷积累周期中向转移栅极5 1施加负电压导致转移晶体管22的截止状态。向控制栅极52施加负电压导致空穴在衬底30的界面(第一表面)附近的积累,从而减小暗电流。In the charge accumulation period, light is incident in the direction indicated by the arrow shown in the figure, and is then photoelectrically converted by the photodetector (photodiode) 31 to generate signal charges in response to the amount of incident light. The signal charge drifts in thecharge accumulation region 41 and accumulates in thecharge accumulation region 41 near thehole accumulation region 44 . Application of a negative voltage to transfergate 51 during a charge accumulation period results in an off state oftransfer transistor 22. Application of a negative voltage to controlgate 52 results in accumulation of holes near the interface (first surface) ofsubstrate 30, thereby reducing dark current.

施加到控制栅极52的负电压响应于控制栅极52下面的杂质浓度和栅极氧化物膜的厚度而变化。例如,在通过0.25μm生成工艺形成具有1×1016/cm3的p型杂质浓度的空穴积累区44的情况,约-1V的电压的施加可以充分地抑制暗电流的产生。The negative voltage applied to thecontrol gate 52 varies in response to the impurity concentration under thecontrol gate 52 and the thickness of the gate oxide film. For example, in the case of forminghole accumulation region 44 having a p-type impurity concentration of 1×1016 /cm3 by a 0.25 μm growth process, application of a voltage of about −1 V can sufficiently suppress generation of dark current.

在读操作中,向转移栅极51施加正电压导致转移晶体管22的导通状态。在光电检测器31中积累的信号电荷转移到浮置扩散区45。正电压例如等于电源电压(3.3V或2.7V)。In a read operation, application of a positive voltage to transfergate 51 results in a conductive state oftransfer transistor 22 . The signal charges accumulated in thephotodetector 31 are transferred to the floatingdiffusion region 45 . The positive voltage is eg equal to the supply voltage (3.3V or 2.7V).

在读操作中,与积累中相同的负电压(例如-1V)基本上施加给控制栅极52。可替换地,在读操作中,约+1V的正电压可施加给控制栅极52。在这种情况下,积累的信号电荷接近第一表面侧,从而提高转移栅极51的读能力。读出所需的时间周期远短于积累周期。因此,由于向控制栅极52施加正电压而引起的暗电流低。In a read operation, substantially the same negative voltage (eg -1V) as in accumulation is applied to thecontrol gate 52 . Alternatively, a positive voltage of about +1V may be applied to controlgate 52 during a read operation. In this case, the accumulated signal charge is close to the first surface side, thereby improving the readability of thetransfer gate 51 . The time period required for readout is much shorter than the accumulation period. Therefore, the dark current due to the application of a positive voltage to thecontrol gate 52 is low.

浮置扩散区45的电势根据传输的信号电荷的量而变化。浮置扩散区45的电势通过放大晶体管23被放大。响应于该电势的电压输出到垂直信号线27(参见图2)。The potential of the floatingdiffusion region 45 varies according to the amount of transferred signal charges. The potential of the floatingdiffusion region 45 is amplified by theamplification transistor 23 . A voltage corresponding to this potential is output to the vertical signal line 27 (see FIG. 2 ).

在复位操作中,向复位晶体管25的栅极施加正电压使浮置扩散区45的电压复位到电源电压Vdd。在这种情况下,负电压施加给转移栅极51,导致转移晶体管22的截止状态。此外,负电压施加给控制栅极52。In a reset operation, applying a positive voltage to the gate of thereset transistor 25 resets the voltage of the floatingdiffusion region 45 to the power supply voltage Vdd. In this case, a negative voltage is applied to thetransfer gate 51 , resulting in an off state of thetransfer transistor 22 . In addition, a negative voltage is applied to thecontrol gate 52 .

重复上述积累操作、读取操作和复位操作。The accumulation operation, read operation, and reset operation described above are repeated.

下面描述制造固态成像装置的方法。在该实施例中,将描述同时形成转移栅极51和控制栅极52的示例性方法。A method of manufacturing a solid-state imaging device is described below. In this embodiment, an exemplary method of simultaneously forming thetransfer gate 51 and thecontrol gate 52 will be described.

如图6A所示,通过浅槽隔离(STI)在衬底30上形成元件隔离绝缘膜40。然后,通过离子注入形成n型电荷积累区41、p阱42、p型空穴积累区44、以及p型区46。所述区域的形成顺序没有限制。As shown in FIG. 6A, an elementisolation insulating film 40 is formed on asubstrate 30 by shallow trench isolation (STI). Then, n-typecharge accumulation region 41, p-well 42, p-typehole accumulation region 44, and p-type region 46 are formed by ion implantation. The order in which the regions are formed is not limited.

如图6B所示,通过热氧化在衬底30上形成由硅氧化物构成的栅极绝缘膜60。随后,通过化学气相沉积(CVD)在栅极绝缘膜60上形成由多晶硅构成的电极层50。由多晶硅构成的电极层具有100nm至300nm的厚度。杂质在膜形成期间被引入到多晶硅中。As shown in FIG. 6B, agate insulating film 60 made of silicon oxide is formed on thesubstrate 30 by thermal oxidation. Subsequently,electrode layer 50 made of polysilicon is formed ongate insulating film 60 by chemical vapor deposition (CVD). The electrode layer composed of polysilicon has a thickness of 100 nm to 300 nm. Impurities are introduced into polysilicon during film formation.

如图7A所示,用抗蚀剂掩模蚀刻电极层50以形成转移栅极51和控制栅极52。此时,同时形成其它晶体管的栅极(参见图2)。As shown in FIG. 7A , theelectrode layer 50 is etched using a resist mask to form atransfer gate 51 and acontrol gate 52 . At this time, gates of other transistors are formed simultaneously (see FIG. 2 ).

如图7B所示,在整个表面上沉积硅氧化物或硅氮化物以用绝缘膜61填充转移栅极51和控制栅极52之间的间隙。As shown in FIG. 7B , silicon oxide or silicon nitride is deposited on the entire surface to fill the gap betweentransfer gate 51 andcontrol gate 52 with insulating film 61 .

由此,形成了转移栅极51和控制栅极52。下面将参照图3描述形成栅极之后的工艺。在衬底30的第一表面侧重复形成绝缘膜和引线以形成布线层38。然后,支承衬底39结合到布线层38。Thus, thetransfer gate 51 and thecontrol gate 52 are formed. The process after forming the gate will be described below with reference to FIG. 3 . An insulating film and leads are repeatedly formed on the first surface side of thesubstrate 30 to form awiring layer 38 . Then, thesupport substrate 39 is bonded to thewiring layer 38 .

通过化学机械抛光(CMP)抛光衬底30的背侧以减小衬底30的厚度。进行离子注入以及然后的激活退火以在衬底30的第二表面上形成p型空穴积累区43(参见图4)。优选地,激活退火时的温度不超过温度上限,因为在形成布线层之后进行激活退火。为了满足要求,优选采用对布线层没有热影响的激光退火。The backside of thesubstrate 30 is polished by chemical mechanical polishing (CMP) to reduce the thickness of thesubstrate 30 . Ion implantation followed by activation annealing is performed to form p-typehole accumulation regions 43 on the second surface of substrate 30 (see FIG. 4 ). Preferably, the temperature at the time of the activation annealing does not exceed the upper temperature limit because the activation annealing is performed after the wiring layer is formed. In order to meet the requirements, it is preferable to use laser annealing which has no thermal influence on the wiring layer.

通过CVD在衬底30上形成由硅氧化物构成的绝缘膜32。遮光膜33形成且构图在绝缘膜32上。通过CVD在遮光膜33上形成由硅氮化物构成的保护膜34。然后,形成滤色器35和微透镜36。An insulatingfilm 32 made of silicon oxide is formed on thesubstrate 30 by CVD. Thelight shielding film 33 is formed and patterned on the insulatingfilm 32 . A protective film 34 made of silicon nitride is formed on thelight shielding film 33 by CVD. Then,color filters 35 andmicrolenses 36 are formed.

因此,制成了根据该实施例的背侧照射型固态成像装置。Thus, a backside-illuminated solid-state imaging device according to this embodiment was produced.

参照图8和9描述形成每个是单层的转移栅极51和控制栅极52的另一示例性方法。在图8和9中,省略衬底的结构。Another exemplary method of forming thetransfer gate 51 and thecontrol gate 52 each being a single layer is described with reference to FIGS. 8 and 9 . In FIGS. 8 and 9, the structure of the substrate is omitted.

以与上述相同的方式通过浅槽隔离(STI)在衬底30上形成元件隔离绝缘膜40。然后,通过离子注入形成n型电荷积累区41、p阱42、p型空穴积累区44和p型区46(参见图6A)。所述区域的形成顺序没有限制。The elementisolation insulating film 40 is formed on thesubstrate 30 by shallow trench isolation (STI) in the same manner as above. Then, n-typecharge accumulation region 41, p-well 42, p-typehole accumulation region 44, and p-type region 46 are formed by ion implantation (see FIG. 6A). The order in which the regions are formed is not limited.

如图8A所示,通过热氧化在衬底30上形成由硅氧化物构成的栅极绝缘膜60。随后,通过化学气相沉积(CVD)在栅极绝缘膜60上形成由多晶硅构成的电极层50。由多晶硅构成的电极层具有100nm至300nm的厚度。在膜形成期间杂质被引入到多晶硅中。随后,通过CVD在电极层50上沉积硅氧化物膜62a和硅氮化物膜62b以形成包括硅氧化物膜62a和硅氮化物膜62b的硬掩模62。As shown in FIG. 8A, agate insulating film 60 made of silicon oxide is formed on thesubstrate 30 by thermal oxidation. Subsequently,electrode layer 50 made of polysilicon is formed ongate insulating film 60 by chemical vapor deposition (CVD). The electrode layer composed of polysilicon has a thickness of 100 nm to 300 nm. Impurities are introduced into polysilicon during film formation. Subsequently, asilicon oxide film 62a and asilicon nitride film 62b are deposited on theelectrode layer 50 by CVD to form ahard mask 62 including thesilicon oxide film 62a and thesilicon nitride film 62b.

如图8B所示,用光刻形成的抗蚀剂掩模构图硬掩模62以在硬掩模62中形成具有宽度W1的开口。宽度W1的最小值取决于光刻分辨率的限制。As shown in FIG. 8B , thehard mask 62 is patterned with a photolithographically formed resist mask to form an opening having a width W1 in thehard mask 62 . The minimum value of width W1 depends on the limitation of lithographic resolution.

如图8C所示,在硬掩模62中的开口的侧壁上形成侧壁绝缘膜63。通过在包括硬掩模62中的开口的内表面的整个表面上用CVD沉积硅氧化物膜且回蚀该硅氧化物膜来形成侧壁绝缘膜63。侧壁绝缘膜63的形成导致具有比取决于光刻分辨率限制的宽度W1更小的宽度W2的开口。As shown in FIG. 8C , asidewall insulating film 63 is formed on the sidewall of the opening in thehard mask 62 . Thesidewall insulating film 63 is formed by depositing a silicon oxide film by CVD on the entire surface including the inner surface of the opening in thehard mask 62 and etching back the silicon oxide film. The formation of thesidewall insulating film 63 results in an opening having a width W2 smaller than the width W1 depending on the lithographic resolution limit.

如图9A所示,用硬掩模62和侧壁绝缘膜63干蚀刻电极层50以形成转移栅极51和控制栅极52。转移栅极51和控制栅极52之间的间隙的宽度基本等于宽度W2。根据需要,间隙下的部分衬底30经历离子注入。As shown in FIG. 9A , theelectrode layer 50 is dry-etched with thehard mask 62 and the sidewall insulating film 63 to form thetransfer gate 51 and thecontrol gate 52 . The width of the gap between thetransfer gate 51 and thecontrol gate 52 is substantially equal to the width W2. Portions of thesubstrate 30 under the gap are subjected to ion implantation as needed.

如图9B所示,在转移栅极51、控制栅极52、以及间隙的整个表面上通过CVD相继形成硅氧化物膜64a和硅氮化物膜64b以完成嵌入式绝缘膜64。As shown in FIG. 9B , a silicon oxide film 64 a and a silicon nitride film 64 b are successively formed by CVD on the entire surfaces of thetransfer gate 51 , thecontrol gate 52 , and the gap to complete the embedded insulating film 64 .

如图9C所示,形成在硬掩模62上的嵌入式绝缘膜64被回蚀从而仅留下形成在转移栅极51和控制栅极52之间的间隙中的嵌入式绝缘膜64。As shown in FIG. 9C , the embedded insulating film 64 formed on thehard mask 62 is etched back to leave only the embedded insulating film 64 formed in the gap between thetransfer gate 51 and thecontrol gate 52 .

随后的步骤与上面相同。在该实施例中,作为示例描述了形成每个是单层的转移栅极51和控制栅极52的方法,但不限于此。例如,在形成控制栅极52之后,通过氧化在控制栅极52的表面上形成硅氧化物膜,然后可以形成转移栅极51。供选地,可以预先形成转移栅极51,通过氧化在转移栅极51的侧壁上形成硅氧化物膜之后,可以形成控制栅极52。当预先形成转移栅极51时,可以用转移栅极51作为用于离子注入的掩模来形成空穴积累区44。Subsequent steps are the same as above. In this embodiment, a method of forming thetransfer gate 51 and thecontrol gate 52 each being a single layer has been described as an example, but is not limited thereto. For example, after thecontrol gate 52 is formed, a silicon oxide film is formed on the surface of thecontrol gate 52 by oxidation, and then thetransfer gate 51 can be formed. Alternatively, thetransfer gate 51 may be formed in advance, and after forming a silicon oxide film on the sidewall of thetransfer gate 51 by oxidation, thecontrol gate 52 may be formed. When thetransfer gate 51 is formed in advance, thehole accumulation region 44 can be formed using thetransfer gate 51 as a mask for ion implantation.

图10是包括固态成像装置的摄像机的示意框图。Fig. 10 is a schematic block diagram of a video camera including a solid-state imaging device.

摄像机100包括上述固态成像装置101、光学系统102和信号处理电路103。根据本发明实施例的摄像机可以是包括固态成像装置101、光学系统102和信号处理电路103的摄像机模块。Thevideo camera 100 includes the above-described solid-state imaging device 101 , anoptical system 102 , and asignal processing circuit 103 . A camera according to an embodiment of the present invention may be a camera module including a solid-state imaging device 101 , anoptical system 102 and asignal processing circuit 103 .

光学系统102将来自目标的光(入射光)聚焦在固态成像装置101的成像区域上。入射光在固态成像装置101的光电检测器31中被转化成与入射光量对应的信号电荷。信号电荷在光电检测器31中积累预定时间周期。Theoptical system 102 focuses light from a subject (incident light) on an imaging area of the solid-state imaging device 101 . Incident light is converted into signal charges corresponding to the amount of incident light in thephotodetector 31 of the solid-state imaging device 101 . Signal charges are accumulated in thephotodetector 31 for a predetermined time period.

信号处理电路103进行从固态成像装置101供给的输出信号的信号处理且输出图像信号。Thesignal processing circuit 103 performs signal processing of the output signal supplied from the solid-state imaging device 101 and outputs an image signal.

下面将描述根据该实施例的固态成像装置、制造该固态成像装置的方法、以及该摄像机的优点。The solid-state imaging device, method of manufacturing the solid-state imaging device, and advantages of the video camera according to the embodiment will be described below.

在根据该实施例的固态成像装置中,控制栅极52设置在衬底30的第一表面上且叠置在光电检测器31上。向控制栅极52施加负电压导致空穴在衬底30的第一表面附近积累,从而降低暗电流。In the solid-state imaging device according to this embodiment, thecontrol gate 52 is provided on the first surface of thesubstrate 30 and superimposed on thephotodetector 31 . Applying a negative voltage to thecontrol gate 52 causes holes to accumulate near the first surface of thesubstrate 30, thereby reducing dark current.

因此,即使当空穴积累区44具有低p型杂质浓度时,也能够抑制暗电流。因此,光电检测器31的pn结能够靠近第一表面侧,从而提高转移栅极51的读能力。能够读取的信号电荷的量能够增加,从而改善了动态范围。Therefore, even when thehole accumulation region 44 has a low p-type impurity concentration, dark current can be suppressed. Therefore, the pn junction of thephotodetector 31 can be close to the first surface side, thereby improving the readability of thetransfer gate 51 . The amount of signal charges that can be read can be increased, thereby improving the dynamic range.

在过去,为了抑制暗电流,会需要将空穴积累区44中的p型杂质浓度增加到约1×1018/cm3。在该实施例中,空穴积累区44中的p型杂质浓度可以减小到约1×1016/cm3。为了进一步降低空穴积累区44中的杂质浓度,可以增大施加到控制栅极52的负电压。In the past, in order to suppress dark current, it would have been necessary to increase the p-type impurity concentration in thehole accumulation region 44 to about 1×1018 /cm3 . In this embodiment, the p-type impurity concentration in thehole accumulation region 44 can be reduced to about 1×1016 /cm3 . In order to further reduce the impurity concentration in thehole accumulation region 44, the negative voltage applied to thecontrol gate 52 may be increased.

根据制造上述实施例的固态成像装置的方法,能够制造包括转移栅极51和控制栅极52的固态成像装置。特别地,当同时形成转移栅极51和控制栅极52时,能够用较小增加的制造步骤数制造固态成像装置。According to the method of manufacturing the solid-state imaging device of the above-described embodiment, a solid-state imaging device including thetransfer gate 51 and thecontrol gate 52 can be manufactured. In particular, when thetransfer gate 51 and thecontrol gate 52 are formed at the same time, the solid-state imaging device can be manufactured with a small increase in the number of manufacturing steps.

摄像机包括上述固态成像装置。因此,可以制造具有低暗电流和宽动态范围的摄像机。The camera includes the solid-state imaging device described above. Therefore, cameras with low dark current and wide dynamic range can be manufactured.

第二实施例second embodiment

图11是根据第二实施例的固态成像装置的衬底30的像素部分的局部剖面图。与第一实施例中相同的元件用相同的附图标记表示,不再重复多余的描述。11 is a partial sectional view of a pixel portion of asubstrate 30 of a solid-state imaging device according to the second embodiment. The same elements as those in the first embodiment are denoted by the same reference numerals, and redundant descriptions will not be repeated.

两个控制栅极,即第一控制栅极52-1和第二控制栅极52-2形成在衬底30的第一表面上,栅极绝缘膜(未示出)设置在其间。第一控制栅极52-1位于转移栅极51和第二控制栅极52-2之间。第一和第二控制栅极52-1和52-2叠置在光电检测器31上。第一和第二控制栅极52-1和52-2例如由多晶硅构成。考虑到可加工性和电阻,第一和第二控制栅极52-1和52-2的每个优选具有与转移栅极51的厚度相当的厚度。光入射在第二表面侧且因此不被位于第一表面侧的第一和第二控制栅极52-1和52-2阻挡。此外,三个或更多控制栅极可位于光电检测器31上。Two control gates, namely, a first control gate 52-1 and a second control gate 52-2 are formed on the first surface of thesubstrate 30 with a gate insulating film (not shown) interposed therebetween. The first control gate 52-1 is located between thetransfer gate 51 and the second control gate 52-2. The first and second control gates 52 - 1 and 52 - 2 are superimposed on thephotodetector 31 . The first and second control gates 52-1 and 52-2 are made of, for example, polysilicon. Each of the first and second control gates 52 - 1 and 52 - 2 preferably has a thickness comparable to that of thetransfer gate 51 in consideration of workability and resistance. Light is incident on the second surface side and thus is not blocked by the first and second control gates 52-1 and 52-2 located on the first surface side. Additionally, three or more control gates may be located on thephotodetector 31 .

上述固态成像装置以与第一实施例相同的方式制造。例如,转移栅极51以及第一和第二控制栅极52-1和52-2可以以与第一实施例相同的方式同时形成。供选地,在形成第一控制栅极52-1之后,在第一控制栅极52-1的表面上通过氧化形成硅氧化物膜,然后转移栅极51和第二控制栅极52-2可以形成在第一控制栅极52-1的两侧。The solid-state imaging device described above was manufactured in the same manner as in the first embodiment. For example, thetransfer gate 51 and the first and second control gates 52-1 and 52-2 may be formed simultaneously in the same manner as in the first embodiment. Alternatively, after forming the first control gate 52-1, a silicon oxide film is formed by oxidation on the surface of the first control gate 52-1, and then thetransfer gate 51 and the second control gate 52-2 It may be formed on both sides of the first control gate 52-1.

下面将参照图11和12描述根据该实施例的固态成像装置的操作。图12是表,示出固态成像装置的操作期间偏压的示例。The operation of the solid-state imaging device according to this embodiment will be described below with reference to FIGS. 11 and 12 . FIG. 12 is a table showing an example of bias voltages during operation of the solid-state imaging device.

在电荷积累周期,光沿图中所示箭头指示的方向入射,然后通过光电检测器(光电二极管)31被光电转换从而产生响应于入射光量的信号电荷。信号电荷在电荷积累区41中漂移且积累在空穴积累区44附近的电荷积累区41中。在电荷积累周期中向转移栅极51施加负电压导致转移晶体管22的截止状态。向第一和第二控制栅极52-1和52-2施加负电压导致空穴在衬底30的界面(第一表面)附近的积累,从而减少暗电流。In the charge accumulation period, light is incident in the direction indicated by the arrow shown in the figure, and is then photoelectrically converted by the photodetector (photodiode) 31 to generate signal charges in response to the amount of incident light. Signal charges drift in thecharge accumulation region 41 and are accumulated in thecharge accumulation region 41 near thehole accumulation region 44 . Application of a negative voltage to transfergate 51 during the charge accumulation period results in an off state oftransfer transistor 22 . Applying a negative voltage to the first and second control gates 52-1 and 52-2 causes accumulation of holes near the interface (first surface) of thesubstrate 30, thereby reducing dark current.

施加给第一和第二控制栅极52-1和52-2的负电压响应于控制栅极52下面的杂质浓度和栅极氧化物膜的厚度而变化。例如,在通过0.25μm生成工艺形成具有1×1016/cm3的p型杂质浓度的空穴积累区44的情况下,施加约-1V的电压可以充分抑制暗电流的产生。信号电荷积累在空穴积累区44附近的电荷积累区41中。The negative voltage applied to the first and second control gates 52-1 and 52-2 varies in response to the impurity concentration under thecontrol gate 52 and the thickness of the gate oxide film. For example, in the case of forminghole accumulation region 44 having a p-type impurity concentration of 1×1016 /cm3 by a 0.25 μm growth process, application of a voltage of about −1 V can sufficiently suppress generation of dark current. Signal charges are accumulated in thecharge accumulation region 41 near thehole accumulation region 44 .

在读操作(读1)中,正电压(例如约+1V)施加到第一控制栅极52-1上。因此,基于与CCD相同的原理,电荷积累区41中的信号电荷聚集在第一控制栅极52-1下方。In a read operation (read 1), a positive voltage (eg, about +1V) is applied to the first control gate 52-1. Therefore, the signal charges in thecharge accumulation region 41 are accumulated under the first control gate 52-1 based on the same principle as the CCD.

正电压施加到转移栅极51。负电压施加到第一控制栅极52-1(参见读2),导致转移晶体管22的导通状态。聚集在第一控制栅极52-1下面的信号电荷传输到浮置扩散区45。施加到转移栅极5 1的正电压例如等于电源电压(3.3V或2.7V)。向第一控制栅极52-1施加负电压导致电场沿水平方向施加到衬底30,从而有效地将信号电荷传输到浮置扩散区45。A positive voltage is applied to thetransfer gate 51 . A negative voltage is applied to the first control gate 52 - 1 (see read 2 ), resulting in a conductive state of thetransfer transistor 22 . The signal charges accumulated under the first control gate 52 - 1 are transferred to the floatingdiffusion region 45 . The positive voltage applied to thetransfer gate 51 is, for example, equal to the power supply voltage (3.3V or 2.7V). Applying a negative voltage to the first control gate 52 - 1 causes an electric field to be applied to thesubstrate 30 in a horizontal direction, effectively transferring signal charges to the floatingdiffusion region 45 .

浮置扩散区45的电势根据传输的信号电荷的量而变化。浮置扩散区45的电势通过放大晶体管23被放大。响应于该电势的电压输出到垂直信号线27(参见图2).The potential of the floatingdiffusion region 45 varies according to the amount of transferred signal charges. The potential of the floatingdiffusion region 45 is amplified by theamplification transistor 23 . A voltage in response to this potential is output to the vertical signal line 27 (see FIG. 2 ).

在复位操作中,向复位晶体管25的栅极施加正电压使浮置扩散区45的电压复位到电源电压Vdd。在该情况下,负电压施加到转移栅极51,导致转移晶体管22的截止状态。此外,负电压施加到第一和第二控制栅极52-1和52-2。In a reset operation, applying a positive voltage to the gate of thereset transistor 25 resets the voltage of the floatingdiffusion region 45 to the power supply voltage Vdd. In this case, a negative voltage is applied to thetransfer gate 51 , resulting in an off state of thetransfer transistor 22 . In addition, a negative voltage is applied to the first and second control gates 52-1 and 52-2.

重复上述积累操作、读取操作和复位操作。The accumulation operation, read operation, and reset operation described above are repeated.

在该实施例中,在光电检测器31上形成多个第一和第二控制栅极52-1和52-2。第一和第二控制栅极52-1和52-2的顺序导通/截止导致产生沿水平方向的电场,从而有效地传输电荷。In this embodiment, a plurality of first and second control gates 52 - 1 and 52 - 2 are formed on thephotodetector 31 . Sequential turning on/off of the first and second control gates 52-1 and 52-2 results in generation of an electric field in the horizontal direction, thereby efficiently transferring charges.

在过去,从电荷的有效读出的立场,当在衬底30中水平产生电场时,会需要改变电荷积累区41中沿水平方向的杂质浓度。在该情况,在电荷积累区41的杂质浓度低的区域电势阱较浅,从而减小了积累的电荷量和动态范围。在该实施例中,不需要沿水平方向的浓度梯度;因此,没有观察到动态范围的减小。该实施例对于包括大像素的固态成像装置特别有效。In the past, from the standpoint of efficient readout of electric charges, when an electric field was generated horizontally insubstrate 30, it would have been necessary to change the impurity concentration in thecharge accumulation region 41 in the horizontal direction. In this case, the potential well is shallow in the region where the impurity concentration of thecharge accumulation region 41 is low, thereby reducing the amount of accumulated charges and the dynamic range. In this example, no concentration gradient along the horizontal direction was required; therefore, no reduction in dynamic range was observed. This embodiment is particularly effective for solid-state imaging devices including large pixels.

根据制造固态成像装置的方法,能够制造包括转移栅极51以及第一和第二控制栅极52-1和52-2的固态成像装置。特别地,当同时形成转移栅极51以及第一和第二控制栅极52-1和52-2时,能够以较少增加的制造步骤数制造该固态成像装置。According to the method of manufacturing a solid-state imaging device, a solid-state imaging device including thetransfer gate 51 and the first and second control gates 52-1 and 52-2 can be manufactured. In particular, when thetransfer gate 51 and the first and second control gates 52-1 and 52-2 are formed at the same time, the solid-state imaging device can be manufactured with a less increased number of manufacturing steps.

摄像机包括上述固态成像装置。因此,可以制造具有低的暗电流和宽的动态范围的摄像机。The camera includes the solid-state imaging device described above. Therefore, a camera with low dark current and wide dynamic range can be manufactured.

第三实施例third embodiment

图13是根据第三实施例的固态成像装置的衬底30的像素部分的局部剖面图。与第一实施例中相同的元件用相同的附图标记表示,不再重复多余的描述。13 is a partial cross-sectional view of a pixel portion of asubstrate 30 of a solid-state imaging device according to the third embodiment. The same elements as those in the first embodiment are denoted by the same reference numerals, and redundant descriptions will not be repeated.

控制栅极52形成在衬底30的第一表面上,栅极绝缘膜(未示出)设置于其间。在该实施例中,控制栅极52部分交迭光电检测器31。空穴积累区44不形成在控制栅极52之下。即,形成接着转移栅极51的仅定位控制栅极52的区域和仅定位空穴积累区44的区域。供选地,空穴积累区44可形成在光电检测器31的整个表面上。此外,控制栅极52和空穴积累区44可以相反地布置。Thecontrol gate 52 is formed on the first surface of thesubstrate 30 with a gate insulating film (not shown) interposed therebetween. In this embodiment,control gate 52 partially overlapsphotodetector 31 . Thehole accumulation region 44 is not formed under thecontrol gate 52 . That is, a region where only thecontrol gate 52 is located and a region where only thehole accumulation region 44 is located next to thetransfer gate 51 are formed. Alternatively, thehole accumulation region 44 may be formed on the entire surface of thephotodetector 31 . In addition, thecontrol gate 52 and thehole accumulation region 44 may be reversely arranged.

以与第一实施例中相同的方式制造上述固态成像装置。例如,可以用与第一实施例中相同的方式同时形成转移栅极51和控制栅极52。供选地,在形成控制栅极52之后,通过氧化在控制栅极52的表面上形成硅氧化物膜,然后可以形成转移栅极51。供选地,形成转移栅极51,且在通过氧化在转移栅极51的侧壁上形成硅氧化物膜之后,可以形成控制栅极52。可在形成转移栅极51和控制栅极52之前形成空穴积累区44。供选地,用转移栅极51和控制栅极52作为掩模,空穴积累区44可通过离子注入形成。The solid-state imaging device described above was manufactured in the same manner as in the first embodiment. For example, thetransfer gate 51 and thecontrol gate 52 can be formed simultaneously in the same manner as in the first embodiment. Alternatively, after thecontrol gate 52 is formed, a silicon oxide film is formed on the surface of thecontrol gate 52 by oxidation, and then thetransfer gate 51 may be formed. Alternatively, thetransfer gate 51 is formed, and after forming a silicon oxide film on the side wall of thetransfer gate 51 by oxidation, thecontrol gate 52 may be formed. Thehole accumulation region 44 may be formed before thetransfer gate 51 and thecontrol gate 52 are formed. Alternatively, thehole accumulation region 44 may be formed by ion implantation using thetransfer gate 51 and thecontrol gate 52 as masks.

下面参照图13描述根据该实施例的固态成像装置的操作。固态成像装置操作期间的偏压示例与第一实施例中相同(参见图5)。The operation of the solid-state imaging device according to this embodiment will be described below with reference to FIG. 13 . An example of bias voltage during operation of the solid-state imaging device is the same as in the first embodiment (see FIG. 5 ).

在电荷积累周期,光沿图中所示箭头指示的方向入射,且然后通过光电检测器(光电二极管)31被光电转换从而产生响应于入射光量的信号电荷。信号电荷在电荷积累区41中漂移且积累在电荷积累区41的第一表面侧。在电荷积累周期中向转移栅极51施加负电压导致转移晶体管22的截止状态。负电压施加到控制栅极52。由于空穴积累区44和控制栅极52,空穴积累在光电检测器31的第一表面附近,从而减少暗电流。In the charge accumulation period, light is incident in the direction indicated by the arrow shown in the figure, and is then photoelectrically converted by the photodetector (photodiode) 31 to generate signal charges in response to the amount of incident light. Signal charges drift in thecharge accumulation region 41 and are accumulated on the first surface side of thecharge accumulation region 41 . Application of a negative voltage to transfergate 51 during the charge accumulation period results in an off state oftransfer transistor 22 . A negative voltage is applied to thecontrol gate 52 . Due to thehole accumulation region 44 and thecontrol gate 52 , holes are accumulated near the first surface of thephotodetector 31 , thereby reducing dark current.

在读操作中,向转移栅极51施加正电压导致转移晶体管22的导通状态。积累在光电检测器31中的信号电荷传输到浮置扩散区45。正电压例如等于电源电压(3.3V或2.7V)。In a read operation, application of a positive voltage to transfergate 51 results in a conductive state oftransfer transistor 22 . The signal charges accumulated in thephotodetector 31 are transferred to the floatingdiffusion region 45 . The positive voltage is eg equal to the supply voltage (3.3V or 2.7V).

在读操作中,与积累时相同的负电压(例如-1V)基本施加到控制栅极52。供选地,在读操作中,约+1V的正电压可施加到控制栅极52。在该情况下,信号电荷靠近第一表面侧,从而提高了转移栅极51的读能力。读取所需的时间周期远短于积累周期。因此,由于向控制栅极52施加正电压而引起的暗电流较低。In a read operation, substantially the same negative voltage (eg -1V) as in accumulation is applied to thecontrol gate 52 . Alternatively, a positive voltage of approximately +1V may be applied to controlgate 52 during a read operation. In this case, the signal charge is close to the first surface side, thereby improving the readability of thetransfer gate 51 . The time period required for reading is much shorter than the accumulation period. Therefore, the dark current due to the application of a positive voltage to thecontrol gate 52 is lower.

浮置扩散区45的电势根据传输的信号电荷量而变化。浮置扩散区45的电势通过放大晶体管23被放大。响应于该电势的电压输出到垂直信号线27(参见图2)。The potential of the floatingdiffusion region 45 changes according to the transferred signal charge amount. The potential of the floatingdiffusion region 45 is amplified by theamplification transistor 23 . A voltage corresponding to this potential is output to the vertical signal line 27 (see FIG. 2 ).

在复位操作中,向复位晶体管25的栅极施加正电压使浮置扩散区45的电压复位到电源电压Vdd。在该情况下,负电压施加到转移栅极51,导致转移晶体管22的截止状态。此外,负电压施加到控制栅极52。In a reset operation, applying a positive voltage to the gate of thereset transistor 25 resets the voltage of the floatingdiffusion region 45 to the power supply voltage Vdd. In this case, a negative voltage is applied to thetransfer gate 51 , resulting in an off state of thetransfer transistor 22 . In addition, a negative voltage is applied to thecontrol gate 52 .

重复上述积累操作、读取操作和复位操作。The accumulation operation, read operation, and reset operation described above are repeated.

根据该实施例的固态成像装置,即使当控制栅极52部分交迭光电检测器31,也可以实现与第一实施例中相同的效果,即可以减小暗电流和提高读能力。此外,通过设置控制栅极52,可以仅在部分光电检测器31中形成空穴积累区44。According to the solid-state imaging device of this embodiment, even when thecontrol grid 52 partially overlaps thephotodetector 31, the same effects as in the first embodiment can be achieved, that is, the dark current can be reduced and the readability can be improved. Furthermore, by providing thecontrol gate 52 , thehole accumulation region 44 can be formed only in part of thephotodetector 31 .

当空穴积累区44形成在仅部分光电检测器31中时,空穴积累区44可以用转移栅极51和控制栅极52作为掩模通过离子注入以自对准方式形成。可在光电检测器31的整个表面上形成空穴积累区44。When thehole accumulation region 44 is formed in only part of thephotodetector 31, thehole accumulation region 44 can be formed in a self-aligned manner by ion implantation using thetransfer gate 51 and thecontrol gate 52 as a mask. Thehole accumulation region 44 may be formed on the entire surface of thephotodetector 31 .

摄像机包括上述固态成像装置。因此,可以制造具有低暗电流和宽动态范围的摄像机。The camera includes the solid-state imaging device described above. Therefore, cameras with low dark current and wide dynamic range can be manufactured.

根据上述第一至第三实施例,可以制造具有低暗电流和改善的读能力的固态成像装置和摄像机。According to the first to third embodiments described above, a solid-state imaging device and video camera having low dark current and improved readability can be manufactured.

第四实施例Fourth embodiment

图14是根据第四实施例的固态成像装置的像素部分的局部剖面图。与第一实施例中相同的元件用相同的附图标记表示,不再重复多余的描述。14 is a partial sectional view of a pixel portion of a solid-state imaging device according to a fourth embodiment. The same elements as those in the first embodiment are denoted by the same reference numerals, and redundant descriptions will not be repeated.

根据该实施例的固态成像装置包括在构成作为光电转换器的光电二极管的光电检测器31的光接收表面上的透明导电膜74,即在第一导电类型的区域(n型电荷积累区)41的光接收表面上,单层绝缘膜71设置在其间。固态成像装置以这样的方式构造使得负电压施加到透明导电膜74。透明导电膜74起到控制栅极的作用,其控制光接收表面的电势。透明导电膜74被覆盖以平坦化膜76,绝缘膜例如硅氧化物膜75设置在其间。平坦化膜76被覆盖以滤色器35。滤色器35被覆盖以芯片上微透镜36。透明导电膜74通过硅氧化物膜75连接到引线77(也起遮光膜的作用)。引线77从成像部分81(对应于像素部分11)延伸到外围电路部分82。The solid-state imaging device according to this embodiment includes a transparentconductive film 74 on the light-receiving surface of thephotodetector 31 constituting a photodiode as a photoelectric converter, that is, in the region of the first conductivity type (n-type charge accumulation region) 41 On the light-receiving surface of , a single-layer insulating film 71 is provided therebetween. The solid-state imaging device is configured in such a manner that a negative voltage is applied to the transparentconductive film 74 . The transparentconductive film 74 functions as a control gate, which controls the potential of the light receiving surface. The transparentconductive film 74 is covered with aplanarization film 76 with an insulating film such as asilicon oxide film 75 interposed therebetween. Theplanarization film 76 is covered with thecolor filter 35 . Thecolor filter 35 is covered with an on-chip microlens 36 . The transparentconductive film 74 is connected to a lead 77 (also functions as a light-shielding film) through asilicon oxide film 75 . Thelead wire 77 extends from the imaging section 81 (corresponding to the pixel section 11 ) to theperipheral circuit section 82 .

在这个实施例中,透明导电膜74下面的绝缘膜71的厚度d1,即该实施例中硅氧化物膜的厚度d1,设置在50nm或更小,从而具有透明导电膜74的该结构有利地在光电二极管中具有优良的光吸收系数。优选地,是绝缘膜71的硅氧化物膜的厚度d1设定在50nm或更小,适应于硅氧化物膜的厚度d1优化透明导电膜74的厚度d2。绝缘膜71可以是氮氧化硅膜和硅氧化物膜。In this embodiment, the thickness d1 of the insulatingfilm 71 under the transparentconductive film 74, that is, the thickness d1 of the silicon oxide film in this embodiment, is set at 50 nm or less, so that the structure having the transparentconductive film 74 is advantageous Excellent light absorption coefficient in photodiodes. Preferably, the thickness d1 of the silicon oxide film which is the insulatingfilm 71 is set at 50 nm or less, and the thickness d2 of the transparentconductive film 74 is optimized in accordance with the thickness d1 of the silicon oxide film. The insulatingfilm 71 may be a silicon nitride oxide film or a silicon oxide film.

在透明导电膜74是含有铟和锡的氧化物膜,即铟锡氧化物(ITO)膜的情况下,形成由透明导电膜(ITO膜)74和绝缘膜(硅氧化物膜)71构成的抗反射膜,因为透明导电膜(ITO膜)74具有约2.0的折射率,绝缘膜(硅氧化物膜)71具有约1.45的折射率。透明导电膜74可以是包含锌的氧化物膜即氧化锌膜以及ITO膜。In the case where the transparentconductive film 74 is an oxide film containing indium and tin, that is, an indium tin oxide (ITO) film, a transparent conductive film (ITO film) 74 and an insulating film (silicon oxide film) 71 are formed. Anti-reflection film, since the transparent conductive film (ITO film) 74 has a refractive index of about 2.0, and the insulating film (silicon oxide film) 71 has a refractive index of about 1.45. The transparentconductive film 74 may be a zinc oxide film which is an oxide film containing zinc, or an ITO film.

绝缘膜71的厚度d1可以是50nm或更小,在1.0nm至50nm的范围,优选30nm或更小,更优选地15nm至30nm。当优化硅氧化物膜(厚度d1)和ITO膜(厚度d2)时,绝缘膜71的较薄厚度d1改善了透射率,从而导致固态成像装置的更高灵敏度。超过50nm的厚度增大反射分量。小于1.0nm的厚度降低绝缘性能。The thickness d1 of the insulatingfilm 71 may be 50 nm or less, in the range of 1.0 nm to 50 nm, preferably 30 nm or less, more preferably 15 nm to 30 nm. When the silicon oxide film (thickness d1) and the ITO film (thickness d2) are optimized, the thinner thickness d1 of the insulatingfilm 71 improves transmittance, resulting in higher sensitivity of the solid-state imaging device. Thicknesses exceeding 50 nm increase the reflection component. A thickness of less than 1.0 nm degrades insulating properties.

根据第四实施例,透明导电膜74形成在构成光电二极管的光电检测器31的光接收表面上,具有单层结构的绝缘膜71设置于其间。向透明导电膜74施加负电压导致光电二极管表面上的空穴积累状态。换言之,空穴积累在光电二极管的表面上,从而抑制由于界面态导致的暗电流分量。此外,当折射率低于透明导电膜74的折射率的绝缘膜71的厚度d1设定在50nm或更小时,绝缘膜71设置在透明导电膜74之下,形成透明导电膜74和绝缘膜71构成的抗反射膜。因此,即使当设置透明导电膜74时,灵敏度不减小。因此,根据该实施例,可以制造具有低暗电流和高灵敏度的固态成像装置。According to the fourth embodiment, the transparentconductive film 74 is formed on the light receiving surface of thephotodetector 31 constituting the photodiode with the insulatingfilm 71 having a single-layer structure interposed therebetween. Application of a negative voltage to the transparentconductive film 74 results in a hole accumulation state on the surface of the photodiode. In other words, holes are accumulated on the surface of the photodiode, thereby suppressing the dark current component due to the interface state. Furthermore, when the thickness d1 of the insulatingfilm 71 having a refractive index lower than that of the transparentconductive film 74 is set at 50 nm or less, the insulatingfilm 71 is disposed under the transparentconductive film 74, forming the transparentconductive film 74 and the insulatingfilm 71 Composed of anti-reflection film. Therefore, even when the transparentconductive film 74 is provided, the sensitivity does not decrease. Therefore, according to this embodiment, a solid-state imaging device having low dark current and high sensitivity can be manufactured.

以与嵌入式光电二极管相同的方式,通过在光电二极管的表面上形成透明导电膜,绝缘膜设置于其间,且施加负电压到透明导电膜以在光电二极管的表面上形成空穴积累态,可以抑制由于界面而导致的暗电流。然而,该结构中有缺点。透明导电膜的形成增加了堆叠在光电二极管上的层数,从而增大了从上面的层之间的界面反射的反射分量,或者增大了透明导电膜诸如ITO膜中较短波长的光的吸收。尽管能够降低暗电流,但由于这些光学缺点而会降低灵敏度。In the same manner as the embedded photodiode, by forming a transparent conductive film on the surface of the photodiode with an insulating film interposed therebetween, and applying a negative voltage to the transparent conductive film to form a hole accumulation state on the surface of the photodiode, it is possible to Dark current due to the interface is suppressed. However, there are disadvantages in this structure. The formation of the transparent conductive film increases the number of layers stacked on the photodiode, thereby increasing the reflection component reflected from the interface between the upper layers, or increasing the absorption of shorter wavelength light in the transparent conductive film such as the ITO film. absorb. Although dark current can be reduced, sensitivity is reduced due to these optical disadvantages.

相反,根据该实施例,透明导电膜74下面的单层绝缘膜71例如硅氧化物膜或氮氧化硅膜的厚度d1设定为50nm或更小,然后适应于厚度d1优化透明导电膜74的厚度d2,从而达到界面处暗电流的抑制和灵敏度的改善之间的平衡。On the contrary, according to this embodiment, the thickness d1 of the single-layer insulating film 71 such as a silicon oxide film or a silicon oxynitride film under the transparentconductive film 74 is set to 50 nm or less, and then the transparentconductive film 74 is optimized for the thickness d1. Thickness d2, so as to achieve a balance between the suppression of dark current at the interface and the improvement of sensitivity.

具体地,当透明导电膜74下面的绝缘膜71(在该实施例中为硅氧化物膜)的厚度设定在50nm或更小时,光电二极管中的光吸收系数的优势参照图15-19得到证实。Specifically, when the thickness of the insulating film 71 (silicon oxide film in this embodiment) under the transparentconductive film 74 is set at 50 nm or less, the advantage of the light absorption coefficient in the photodiode is obtained with reference to FIGS. 15-19 confirmed.

下面描述如图14所示的装置结构,包括在绝缘膜(硅氧化物膜)71上的透明导电膜(ITO膜)74。图15是曲线图,示出光电二极管中的光吸收系数,吸收系数通过用透明导电膜(ITO)74的厚度d2和绝缘膜(硅氧化物膜)71的厚度d1作为参数的模拟来确定。The device structure shown in FIG. 14 including a transparent conductive film (ITO film) 74 on an insulating film (silicon oxide film) 71 will be described below. 15 is a graph showing the light absorption coefficient in the photodiode determined by simulation using the thickness d2 of the transparent conductive film (ITO) 74 and the thickness d1 of the insulating film (silicon oxide film) 71 as parameters.

在图15中,光电二极管的深度采用4μm。水平轴表示光电二极管中450nm光的吸收系数,蓝光的吸收系数。纵轴表示光电二极管中550nm光的吸收系数,绿光的吸收系数。两种吸收系数都绘出。图中图例所示的“Ox”意指是设置在透明导电膜(ITO膜)74下面的绝缘膜的硅氧化物膜的厚度。相关于图中用曲线(细线)表示的硅氧化物膜的厚度,ITO膜的厚度以10nm的步幅从0nm改变到100nm。图例中的术语“无ITO”的曲线意指硅氧化物膜的厚度单独从0nm改变到200nm而没有形成ITO膜的情况下的数据。In FIG. 15 , the depth of the photodiode is 4 μm. The horizontal axis represents the absorption coefficient of 450 nm light in the photodiode, the absorption coefficient of blue light. The vertical axis represents the absorption coefficient of 550 nm light in the photodiode, the absorption coefficient of green light. Both absorption coefficients are plotted. “Ox” shown in the legend in the figure means the thickness of the silicon oxide film which is the insulating film provided under the transparent conductive film (ITO film) 74 . With respect to the thickness of the silicon oxide film indicated by a curve (thin line) in the figure, the thickness of the ITO film was changed from 0 nm to 100 nm in steps of 10 nm. The graph of the term "without ITO" in the legend means the data in the case where the thickness of the silicon oxide film was changed from 0 nm to 200 nm alone without forming an ITO film.

设置在透明导电膜(ITO膜)之上的上膜固定。设置在透明导电膜(ITO膜)74上的绝缘膜(硅氧化物膜)75采用100nm厚度。平坦化膜76采用由包含硅(Si)、氧(O)和碳(C)的材料构成,具有1.5的折射率,且具有1μm的厚度。滤色器35采用由具有约1.6至1.7的折射率的材料构成。The upper film provided on the transparent conductive film (ITO film) is fixed. The insulating film (silicon oxide film) 75 provided on the transparent conductive film (ITO film) 74 has a thickness of 100 nm. Theplanarization film 76 is made of a material containing silicon (Si), oxygen (O), and carbon (C), has a refractive index of 1.5, and has a thickness of 1 μm. Thecolor filter 35 is made of a material having a refractive index of about 1.6 to 1.7.

图15示出适应于设置在透明导电膜(ITO膜)74之下的绝缘膜(硅氧化物膜)的厚度d1,ITO膜的最优厚度d2的存在,以实现蓝光和绿光吸收系数之间的平衡。该曲线图证实即使在设定最佳ITO膜厚时,蓝光和绿光的最大吸收系数取决于设置在ITO膜下面的硅氧化物膜的厚度d1。光电二极管中光的吸收系数优选存在于实线表示的框内(光电二极管中蓝光和绿光每个的吸收系数的范围为约73%或更大)。更优选地,蓝光和绿光的吸收系数每个是80%或更大。与具有硅氧化物膜而没有ITO膜的结构相比,在具有ITO膜的结构中,会要求设置在ITO膜下面的至少硅氧化物膜具有50nm或更小的厚度d1以保持光电二极管中光吸收系数的优势。ITO膜优选具有30nm或更小的厚度从而包括ITO膜的结构与不包括ITO膜的结构相比在光电二极管中的光吸收系数方面具有优势。15 shows the existence of an optimal thickness d2 of the ITO film adapted to the thickness d1 of the insulating film (silicon oxide film) disposed under the transparent conductive film (ITO film) 74, to realize the difference between the absorption coefficients of blue light and green light. balance between. This graph confirms that even when the optimum ITO film thickness is set, the maximum absorption coefficients of blue light and green light depend on the thickness d1 of the silicon oxide film disposed under the ITO film. The absorption coefficient of light in the photodiode preferably exists within the box indicated by the solid line (the range of the absorption coefficients of each of blue light and green light in the photodiode is about 73% or more). More preferably, the absorption coefficients of blue light and green light are each 80% or more. Compared with a structure having a silicon oxide film without an ITO film, in the structure having the ITO film, at least the silicon oxide film provided under the ITO film will be required to have a thickness d1 of 50 nm or less in order to keep light in the photodiode. The advantage of the absorption coefficient. The ITO film preferably has a thickness of 30 nm or less so that the structure including the ITO film has an advantage in light absorption coefficient in the photodiode compared to the structure not including the ITO film.

图16和17每个是强度曲线图,示出光电二极管中蓝光和绿光的吸收系数,设置在ITO膜下面的硅氧化物膜的厚度d1和ITO膜的厚度d2改变。图16示出光电二极管中具有450nm波长的蓝光的吸收系数。图17示出光电二极管中具有550nm波长的绿光的吸收系数。图16和17显示,为了增加蓝光和绿光的吸收系数,设置在ITO膜下面的硅氧化物膜的较小的厚度d1是优选的。在图16和17中,白区域84和85是最佳区域。16 and 17 are each an intensity graph showing the absorption coefficient of blue light and green light in the photodiode, the thickness d1 of the silicon oxide film disposed under the ITO film and the thickness d2 of the ITO film are varied. FIG. 16 shows the absorption coefficient of blue light having a wavelength of 450 nm in a photodiode. FIG. 17 shows the absorption coefficient of green light having a wavelength of 550 nm in a photodiode. 16 and 17 show that a smaller thickness d1 of the silicon oxide film disposed under the ITO film is preferable in order to increase the absorption coefficient of blue light and green light. In FIGS. 16 and 17,white areas 84 and 85 are optimal areas.

此外,图18是曲线图,示出光电二极管中蓝光和绿光的吸收系数,设置在ITO膜下面的硅氧化物膜的厚度d1是20nm。图19是曲线图,示出光电二极管中蓝光和绿光的吸收系数,设置在ITO膜下面的硅氧化物膜的厚度d1是160nm。当图19所示硅氧化物膜的厚度d1是160nm时,ITO膜的厚度d2的蓝光峰值与厚度d2的绿光峰值不同。即,蓝光和绿光的吸收系数没有良好地平衡。另一方面,如图18所示,当硅氧化物膜的厚度d1小时,通过优化ITO膜的厚度d2实现蓝光和绿光的吸收系数之间的平衡。In addition, FIG. 18 is a graph showing the absorption coefficients of blue light and green light in the photodiode, and the thickness d1 of the silicon oxide film provided under the ITO film is 20 nm. FIG. 19 is a graph showing the absorption coefficients of blue light and green light in a photodiode where the thickness d1 of the silicon oxide film provided under the ITO film is 160 nm. When the thickness d1 of the silicon oxide film shown in FIG. 19 is 160 nm, the blue peak of the thickness d2 of the ITO film is different from the green peak of the thickness d2. That is, the absorption coefficients of blue light and green light are not well balanced. On the other hand, as shown in FIG. 18, when the thickness d1 of the silicon oxide film is small, the balance between the absorption coefficients of blue light and green light is achieved by optimizing the thickness d2 of the ITO film.

根据本发明的该实施例,包括根据第四实施例的固态成像装置的摄像机可具有低的暗电流和改善的灵敏度。According to this embodiment of the present invention, a video camera including the solid-state imaging device according to the fourth embodiment can have low dark current and improved sensitivity.

在第四实施例中,单层结构的硅氧化物膜或氮氧化硅膜形成为透明导电膜74下面的绝缘膜71。可替换地,包括至少两类子膜的层叠膜可形成为绝缘膜。下面描述该情况的实施例。In the fourth embodiment, a silicon oxide film or a silicon oxynitride film of a single-layer structure is formed as the insulatingfilm 71 under the transparentconductive film 74 . Alternatively, a laminated film including at least two types of sub-films may be formed as an insulating film. An example of this is described below.

第五实施例fifth embodiment

图20是根据第五实施例的固态成像装置的像素部分的局部剖面图。另外,在该实施例中,固态成像装置是背面照射型。与第一实施例相同的元件用相同的附图标记表示,不再重复多余的描述。20 is a partial sectional view of a pixel portion of a solid-state imaging device according to a fifth embodiment. In addition, in this embodiment, the solid-state imaging device is a back-illuminated type. The same elements as those of the first embodiment are denoted by the same reference numerals, and redundant descriptions will not be repeated.

根据该实施例的固态成像装置包括在光电检测器31的光接收表面上的透明导电膜74,即在第一导电类型的区域(n型电荷积累区)41的光接收表面上,层叠的绝缘膜83设置在其间,光电检测器31构成作为光电转换器的光电二极管。在该实施例中,层叠的绝缘膜83具有两层结构,包括下绝缘子膜72(硅氧化物(SiO2)子膜)和上绝缘子膜73(氮化硅(SiN)子膜)。固态成像装置以负电压施加到透明导电膜74上的方式配置。透明导电膜74起控制栅极的作应,其控制光接收表面的电势。下绝缘子膜(硅氧化物膜)72形成得接触光电检测器的光接收表面。透明导电膜74被覆盖以平坦化膜76,绝缘膜例如硅氧化物膜75设置在其间。平坦化膜76被覆盖以滤色器35。滤色器35被覆盖以芯片上微透镜36。透明导电膜74穿过硅氧化物膜75连接到引线77(也起遮光膜的作用)。引线77从成像部分81(对应于像素部分11)延伸到外围电路部分82。The solid-state imaging device according to this embodiment includes the transparentconductive film 74 on the light-receiving surface of thephotodetector 31, that is, on the light-receiving surface of the region (n-type charge accumulation region) 41 of the first conductivity type, laminated insulating Thefilm 83 is disposed therebetween, and thephotodetector 31 constitutes a photodiode as a photoelectric converter. In this embodiment, the laminated insulatingfilm 83 has a two-layer structure including a lower insulating subfilm 72 (silicon oxide (SiO2 ) subfilm) and an upper insulating subfilm 73 (silicon nitride (SiN) subfilm). The solid-state imaging device is configured such that a negative voltage is applied to the transparentconductive film 74 . The transparentconductive film 74 functions as a control grid, which controls the potential of the light receiving surface. The lower insulator film (silicon oxide film) 72 is formed in contact with the light receiving surface of the photodetector. The transparentconductive film 74 is covered with aplanarization film 76 with an insulating film such as asilicon oxide film 75 interposed therebetween. Theplanarization film 76 is covered with thecolor filter 35 . Thecolor filter 35 is covered with an on-chip microlens 36 . The transparentconductive film 74 is connected to a lead 77 (also functions as a light-shielding film) through asilicon oxide film 75 . Thelead wire 77 extends from the imaging section 81 (corresponding to the pixel section 11 ) to theperipheral circuit section 82 .

在两绝缘子膜72和73中,上绝缘子膜73(氮化硅子膜)具有约2.0的折射率。透明导电膜74诸如ITO膜具有约2.0的折射率。因此,上绝缘子膜具有与透明导电膜基本相同的光学属性。因此,透明导电膜(ITO膜)74的厚度d2实际上被视为具有基本相同折射率的透明导电膜(ITO膜)74和上绝缘子膜(氮化硅子膜)73的总厚度。具有约2.0折射率的铪氧化物(HfO2)子膜可用作上绝缘子膜73来代替氮化硅子膜。Of the twoinsulator films 72 and 73, the upper insulator film 73 (silicon nitride sub-film) has a refractive index of about 2.0. The transparentconductive film 74 such as an ITO film has a refractive index of about 2.0. Therefore, the upper insulator film has substantially the same optical properties as the transparent conductive film. Therefore, the thickness d2 of the transparent conductive film (ITO film) 74 is actually regarded as the total thickness of the transparent conductive film (ITO film) 74 and the upper insulating sub-film (silicon nitride sub-film) 73 having substantially the same refractive index. A hafnium oxide (HfO2 ) subfilm having a refractive index of about 2.0 may be used as the upper insulatingsubfilm 73 instead of the silicon nitride subfilm.

在该实施例中,透明导电膜74下面的下绝缘子膜(硅氧化物子膜)72的厚度d1设定为50nm或更小,如第四实施例那样。优选地,下绝缘子膜(硅氧化物子膜)72的厚度d1设定为50nm或更小,适应于绝缘子膜(硅氧化物子膜)的厚度d1优化透明导电膜的有效厚度d2。氮氧化硅子膜可用作下绝缘子膜72来代替硅氧化物子膜。氧化锌膜也和ITO膜一样可用作透明导电膜74。In this embodiment, the thickness d1 of the lower insulating subfilm (silicon oxide subfilm) 72 under the transparentconductive film 74 is set to 50 nm or less, as in the fourth embodiment. Preferably, the thickness d1 of the lower insulating subfilm (silicon oxide subfilm) 72 is set to 50nm or less, and the effective thickness d2 of the transparent conductive film is optimized for the thickness d1 of the insulating subfilm (silicon oxide subfilm). A silicon oxynitride subfilm may be used as the lower insulatingsubfilm 72 instead of the silicon oxide subfilm. A zinc oxide film can also be used as the transparentconductive film 74 like an ITO film.

当上绝缘子膜73是铪氧化物(HfO2子膜)时,下绝缘子膜(硅氧化物子膜)72的厚度d1可减小到约0.5nm。因此,厚度d1可以是50nm或更小,在1.0nm-50nm的范围,优选30nm或更小,更优选15nm-30nm。When theupper insulator film 73 is hafnium oxide (HfO2 sub-film), the thickness d1 of the lower insulator film (silicon oxide sub-film) 72 can be reduced to about 0.5 nm. Therefore, the thickness d1 may be 50nm or less, in the range of 1.0nm-50nm, preferably 30nm or less, more preferably 15nm-30nm.

当对于根据该实施例的包括层叠绝缘膜83的结构测量图15所示的数据时,ITO膜的厚度d2被有效地视为ITO膜74和由氮化硅或铪氧化物构成的上绝缘子膜73的总厚度。因此,在第五实施例中,也观察到与图15相同的趋势。When the data shown in FIG. 15 is measured for the structure including the laminated insulatingfilm 83 according to this embodiment, the thickness d2 of the ITO film is effectively regarded as theITO film 74 and the upper insulator film made of silicon nitride orhafnium oxide 73 total thickness. Therefore, also in the fifth embodiment, the same tendency as that of FIG. 15 is observed.

根据第五实施例,透明导电膜74形成在构成光电二极管的光电检测器31的光接收表面上,层叠绝缘膜83设置在其间,层叠绝缘膜83包括由硅氧化物构成的下绝缘子膜72,如第四实施例那样。向透明导电膜74施加负电压导致光电二极管的表面上的空穴积累状态。换言之,在光电二极管的表面上积累空穴,从而抑制由于界面态造成的暗电流分量。此外,在透明导电膜74下面的硅氧化物子膜的厚度d1设定在50nm或更小的情况下,即使当使用透明导电膜74时,也不会降低灵敏度。因此,可以制造具有低暗电流和高灵敏度的固态成像装置。According to the fifth embodiment, the transparentconductive film 74 is formed on the light receiving surface of thephotodetector 31 constituting the photodiode with the laminated insulatingfilm 83 including thelower insulator film 72 made of silicon oxide disposed therebetween, Like the fourth embodiment. Application of a negative voltage to the transparentconductive film 74 results in a hole accumulation state on the surface of the photodiode. In other words, holes are accumulated on the surface of the photodiode, thereby suppressing the dark current component due to the interface state. Furthermore, in the case where the thickness d1 of the silicon oxide sub-film under the transparentconductive film 74 is set at 50 nm or less, even when the transparentconductive film 74 is used, the sensitivity does not decrease. Therefore, a solid-state imaging device with low dark current and high sensitivity can be manufactured.

根据本发明该实施例,包括根据第五实施例的固态成像装置的摄像机能够有低的暗电流和改善的灵敏度。According to this embodiment of the present invention, a video camera including the solid-state imaging device according to the fifth embodiment can have low dark current and improved sensitivity.

图21A-22G示出制造根据第四实施例的固态成像装置的方法的实施例。图21A-22G每个是示意剖面图,示出成像部分81和外围电路部分82。21A-22G show an example of a method of manufacturing the solid-state imaging device according to the fourth embodiment. 21A-22G are each a schematic sectional view showing theimaging section 81 and theperipheral circuit section 82 .

如图21A所示,具有预定厚度的单层绝缘膜71和具有预定厚度的透明导电膜74层叠在衬底30的背面,衬底30包括在成像部分81中的具有光电二极管和布线层的像素以及在外围电路部分82中的预定外围电路,绝缘膜71和透明导电膜74设置在光电二极管和外围电路侧的整个表面上。绝缘膜71优选具有小的厚度。As shown in FIG. 21A, a single-layer insulating film 71 having a predetermined thickness and a transparentconductive film 74 having a predetermined thickness are laminated on the back surface of asubstrate 30 including a pixel having a photodiode and a wiring layer in animaging portion 81. As well as a predetermined peripheral circuit in theperipheral circuit portion 82, the insulatingfilm 71 and the transparentconductive film 74 are provided on the entire surface on the photodiode and peripheral circuit side. The insulatingfilm 71 preferably has a small thickness.

在该实施例中,考虑到耐受电压和吸收系数,形成具有单层结构和15nm厚度的绝缘膜(硅氧化物膜)71。在绝缘膜(硅氧化物膜)71上形成具有50nm厚度的作为透明导电膜74的ITO膜。作为绝缘膜71的硅氧化物膜可通过例如用SiH4和O2作为源气体的等离子体增强CVD或用四乙氧基硅烷(TEOS)的等离子体增强CVD形成。作为透明导电膜74的ITO膜可用ITO靶通过溅射形成。在该情况下,会需要适应于下绝缘膜(硅氧化物膜)71的厚度d1优化透明导电膜(ITO膜)74的厚度d2。如上所述,绝缘膜(硅氧化物膜)的厚度d1是15nm。因此,透明导电膜(ITO膜)74的厚度适应于厚度d1优化为50nm。当然,当硅氧化物膜的厚度d1改变时,ITO膜的厚度d2也适应于厚度d1而改变。In this embodiment, an insulating film (silicon oxide film) 71 having a single-layer structure and a thickness of 15 nm is formed in consideration of a withstand voltage and an absorption coefficient. An ITO film as a transparentconductive film 74 is formed on the insulating film (silicon oxide film) 71 with a thickness of 50 nm. The silicon oxide film as the insulatingfilm 71 can be formed by, for example, plasma-enhanced CVD using SiH4 and O2 as source gases or plasma-enhanced CVD using tetraethoxysilane (TEOS). The ITO film as the transparentconductive film 74 is formed by sputtering using an ITO target. In this case, it may be necessary to optimize the thickness d2 of the transparent conductive film (ITO film) 74 to the thickness d1 of the lower insulating film (silicon oxide film) 71 . As described above, the thickness d1 of the insulating film (silicon oxide film) is 15 nm. Therefore, the thickness of the transparent conductive film (ITO film) 74 is optimized to be 50 nm for the thickness d1. Of course, when the thickness d1 of the silicon oxide film is changed, the thickness d2 of the ITO film is also changed in accordance with the thickness d1.

如图21B所示,选择性地蚀刻ITO膜74,从而在期望的部分上留下ITO膜74,即,仅在形成像素的成像部分81上。As shown in FIG. 21B , theITO film 74 is selectively etched so as to leave theITO film 74 on a desired portion, ie, only on animaging portion 81 where a pixel is formed.

如图21C所示,在透明导电膜(ITO膜)74和外围电路部分82侧的整个表面上形成具有预定厚度的绝缘膜(硅氧化物膜)75。在该实施例中,通过等离子体增强CVD形成具有约150nm厚度的绝缘膜(硅氧化物膜)75。As shown in FIG. 21C, an insulating film (silicon oxide film) 75 having a predetermined thickness is formed on the entire surface of the transparent conductive film (ITO film) 74 and theperipheral circuit portion 82 side. In this embodiment, an insulating film (silicon oxide film) 75 having a thickness of about 150 nm is formed by plasma-enhanced CVD.

如图21D所示,在绝缘膜(硅氧化物膜)75中形成用于施加偏压给透明导电膜(ITO膜)74的引线的接触孔86。As shown in FIG. 21D , acontact hole 86 for applying a bias voltage to a lead of the transparent conductive film (ITO film) 74 is formed in the insulating film (silicon oxide film) 75 .

如图22E所示,在包括接触孔86的整个表面上形成起遮光膜和引线作用的金属膜77a。金属膜77a可具有多层结构。多层结构可以是Al/TiN/Ti结构,最上层由Al构成。As shown in FIG. 22E, on the entire surface including thecontact hole 86, ametal film 77a functioning as a light-shielding film and a lead is formed. Themetal film 77a may have a multilayer structure. The multilayer structure may be an Al/TiN/Ti structure with the uppermost layer made of Al.

如图22F所示,构图金属膜77a,以形成朝外围电路部分82延伸并且还起遮光膜作用的引线77。As shown in FIG. 22F, themetal film 77a is patterned to form thelead 77 extending toward theperipheral circuit portion 82 and also functioning as a light-shielding film.

如图22G所示,在整个表面上形成具有预定厚度的平坦化膜76。在该实施例中,主要由硅(Si)、氧(O)和碳(C)组成的绝缘材料以这样的方式施加,即所得膜具有约1μm的厚度,然后所得膜被退火以形成平坦化膜76。在平坦化膜76上形成滤色器35。此外,在其上形成用于聚集光的芯片上微透镜36。从而,制造了根据第四实施例的目标固态成像装置。As shown in FIG. 22G, aplanarization film 76 having a predetermined thickness is formed on the entire surface. In this example, an insulating material mainly composed of silicon (Si), oxygen (O) and carbon (C) is applied in such a way that the resulting film has a thickness of about 1 μm, and then the resulting film is annealed to form aplanarized Film 76. Thecolor filter 35 is formed on theplanarizing film 76 . Furthermore, an on-chip microlens 36 for collecting light is formed thereon. Thus, the target solid-state imaging device according to the fourth embodiment was manufactured.

图23A-24G示出制造根据第五实施例的固态成像装置的方法的实施例。图23A-24G每个是示意剖面图,示出成像部分81和外围电路部分82。23A-24G show an example of a method of manufacturing the solid-state imaging device according to the fifth embodiment. 23A-24G are each a schematic sectional view showing theimaging section 81 and theperipheral circuit section 82 .

如图23A所示,在衬底30的背面层叠具有预定厚度的层叠绝缘膜83和具有预定厚度的透明导电膜74,衬底30包括在成像部分81中的具有光电二极管和布线层的像素以及在外围电路部分82中的预定外围电路,层叠绝缘层83和透明导电膜74设置在光电二极管和外围电路侧的整个表面上。As shown in FIG. 23A, a laminate insulatingfilm 83 having a predetermined thickness and a transparentconductive film 74 having a predetermined thickness are laminated on the back surface of asubstrate 30 including a pixel having a photodiode and a wiring layer in animaging portion 81 and In the predetermined peripheral circuit in theperipheral circuit portion 82, the laminate insulatinglayer 83 and the transparentconductive film 74 are provided on the entire surface on the photodiode and peripheral circuit side.

在该实施例中,形成具有约15nm厚度的硅氧化物子膜作为下绝缘子膜72。作为上绝缘子膜73的氮化硅子膜形成在其上以形成层叠绝缘膜83。此外,作为透明导电膜74的ITO膜形成在其上。作为下绝缘子膜72的硅氧化物子膜可通过例如用SiH4和O2作为源气体的等离子体增强CVD或用四乙氧基硅烷(TEOS)的等离子体增强CVD形成。作为上绝缘子膜73的氮化硅子膜可通过用SiH4和NH3或者用SiH4和N2作为气体源的等离子体增强CVD形成。作为透明导电膜74的ITO膜可通过用ITO靶的溅射形成。上绝缘子膜(氮化硅子膜)73和透明导电膜(ITO膜)74的总厚度d2会需要适应于下绝缘子膜(硅氧化物子膜)72的厚度来优化。下绝缘子膜(硅氧化物子膜)72优选具有小的厚度。在该情况下,下绝缘子膜(硅氧化物子膜)72具有约15nm的厚度。适应于下绝缘子膜72的厚度,上绝缘子膜(氮化硅子膜)73的厚度优化为约30nm,透明导电膜(ITO膜)优化为约20nm。当然,当绝缘子膜(硅氧化物子膜)72的厚度d1改变时,上绝缘子膜(氮化硅子膜)73和透明导电膜(ITO膜)的厚度也改变。In this embodiment, a silicon oxide subfilm having a thickness of about 15 nm is formed as the lower insulatingsubfilm 72 . A silicon nitride subfilm as the upper insulatingsubfilm 73 is formed thereon to form a laminated insulatingfilm 83 . Furthermore, an ITO film as a transparentconductive film 74 is formed thereon. The silicon oxide subfilm as the lower insulatingsubfilm 72 can be formed by, for example, plasma-enhanced CVD using SiH4 and O2 as source gases or plasma-enhanced CVD using tetraethoxysilane (TEOS). The silicon nitride sub-film as the upper insulatingsub-film 73 can be formed by plasma-enhanced CVD using SiH4 and NH3 or SiH4 and N2 as gas sources. The ITO film as the transparentconductive film 74 can be formed by sputtering with an ITO target. The total thickness d2 of the upper insulating sub-film (silicon nitride sub-film) 73 and the transparent conductive film (ITO film) 74 may need to be optimized for the thickness of the lower insulating sub-film (silicon oxide sub-film) 72 . The lower insulating subfilm (silicon oxide subfilm) 72 preferably has a small thickness. In this case, the lower insulating subfilm (silicon oxide subfilm) 72 has a thickness of about 15 nm. Adapting to the thickness of the lower insulatingsub-film 72, the thickness of the upper insulating sub-film (silicon nitride sub-film) 73 is optimized to be about 30 nm, and the thickness of the transparent conductive film (ITO film) is optimized to be about 20 nm. Of course, when the thickness d1 of the insulating subfilm (silicon oxide subfilm) 72 is changed, the thicknesses of the upper insulating subfilm (silicon nitride subfilm) 73 and the transparent conductive film (ITO film) are also changed.

如图23B所示,选择性地蚀刻透明导电膜(ITO膜)74以在期望部分留下ITO膜74,即仅在形成像素的成像部分81上。As shown in FIG. 23B, the transparent conductive film (ITO film) 74 is selectively etched to leave theITO film 74 on a desired portion, ie, only on theimaging portion 81 where the pixel is formed.

如图23C所示,在透明导电膜(ITO膜)74和外围电路部分82侧的整个表面上形成具有预定厚度的绝缘膜(硅氧化物膜)75。在该实施例中,通过等离子体增强CVD形成具有约150nm厚度的绝缘膜(硅氧化物膜)75。As shown in FIG. 23C, an insulating film (silicon oxide film) 75 having a predetermined thickness is formed on the entire surface of the transparent conductive film (ITO film) 74 and theperipheral circuit portion 82 side. In this embodiment, an insulating film (silicon oxide film) 75 having a thickness of about 150 nm is formed by plasma-enhanced CVD.

如图23D所示,在绝缘膜(硅氧化物膜)75中形成用于施加偏压给透明导电膜(ITO膜)74的引线的接触孔86。As shown in FIG. 23D , acontact hole 86 for applying a bias voltage to a lead of the transparent conductive film (ITO film) 74 is formed in the insulating film (silicon oxide film) 75 .

如图24E所示,在包括接触孔86的整个表面上形成起遮光膜和引线作用的金属膜77a。金属膜77a可具有多层结构。多层结构可以是Al/TiN/Ti结构,最上层由A1构成。As shown in FIG. 24E, on the entire surface including thecontact hole 86, ametal film 77a functioning as a light-shielding film and a lead is formed. Themetal film 77a may have a multilayer structure. The multilayer structure may be an Al/TiN/Ti structure, and the uppermost layer is composed of Al.

如图24F所示,构图金属膜77a以形成朝外围电路部分82延伸并且还起遮光膜作用的引线77。As shown in FIG. 24F, themetal film 77a is patterned to form thelead 77 extending toward theperipheral circuit portion 82 and also functioning as a light-shielding film.

如图24G所示,在整个表面上形成具有预定厚度的平坦化膜76。在该实施例中,主要由硅(Si)、氧(O)和碳(C)构成的绝缘材料以这样的方式施加,即所得膜具有约1μm的厚度,然后所得膜被退火以形成平坦化膜76。在平坦化膜76上形成滤色器35。此外,用于聚集光的芯片上微透镜36形成在其上。从而,制造了根据第五实施例的目标固态成像装置。As shown in FIG. 24G, aplanarization film 76 having a predetermined thickness is formed on the entire surface. In this embodiment, an insulating material mainly composed of silicon (Si), oxygen (O) and carbon (C) is applied in such a manner that the resulting film has a thickness of about 1 μm, and then the resulting film is annealed to form aplanarized Film 76. Thecolor filter 35 is formed on theplanarization film 76 . In addition, an on-chip microlens 36 for collecting light is formed thereon. Thus, the target solid-state imaging device according to the fifth embodiment was manufactured.

根据制造该实施例的固态成像装置的方法,能够制造实现由于界面态而导致的暗电流与高灵敏度之间的良好平衡的背面照射CMOS固态成像装置。According to the method of manufacturing the solid-state imaging device of this embodiment, it is possible to manufacture a back-illuminated CMOS solid-state imaging device that achieves a good balance between dark current due to an interface state and high sensitivity.

在第六实施例中,可以使用这样的结构,其中图14和20的每个所示的固态成像装置还包括用于抑制暗电流的p型半导体区(空穴积累区),p型半导体区形成在构成光电二极管的n型半导体区的光接收表面上。嵌入式光电二极管的组合减小了施加给透明导电膜的负电压,且减小了在界面p型半导体区中的杂质浓度,从而获得如已知技术中那样抑制暗电流的效果。In the sixth embodiment, a structure may be used in which the solid-state imaging device shown in each of FIGS. 14 and 20 further includes a p-type semiconductor region (hole accumulation region) for suppressing dark current, the p-type semiconductor region Formed on the light-receiving surface of the n-type semiconductor region constituting the photodiode. The combination of embedded photodiodes reduces the negative voltage applied to the transparent conductive film and reduces the impurity concentration in the interface p-type semiconductor region, thereby obtaining the effect of suppressing dark current as in the known technology.

此外,第四、第五、或第六实施例可以与第一、第二、或第三实施例组合。Furthermore, the fourth, fifth, or sixth embodiment may be combined with the first, second, or third embodiment.

在第四、第五和第六实施例中,提供了背面照射型CMOS图像传感器。可替换地,可以提供正面照射型CMOS图像传感器。此外,还可以提供CCD图像传感器。In the fourth, fifth, and sixth embodiments, a back-illuminated type CMOS image sensor is provided. Alternatively, a front-illuminated CMOS image sensor may be provided. In addition, CCD image sensors are also available.

如上所述,根据第四、第五和第六实施例,可以制造实现低暗电流和改善的灵敏度之间的良好平衡的摄像机。As described above, according to the fourth, fifth, and sixth embodiments, a video camera achieving a good balance between low dark current and improved sensitivity can be manufactured.

第六实施例Sixth embodiment

下面描述根据本发明第六实施例的固态成像装置。A solid-state imaging device according to a sixth embodiment of the present invention will be described below.

图25是根据第六实施例的固态成像装置的像素部分的局部剖面图。在该实施例中,固态成像装置也是背面照射型。与第一实施例相同的元件用相同的附图标记表示,不再重复多余的描述。25 is a partial sectional view of a pixel portion of a solid-state imaging device according to a sixth embodiment. In this embodiment, the solid-state imaging device is also a back-illuminated type. The same elements as those of the first embodiment are denoted by the same reference numerals, and redundant descriptions will not be repeated.

根据该实施例的固态成像装置包括具有预定厚度d3和负固定电荷的膜,例如至少部分结晶的绝缘膜92,该膜设置在光电检测器31的光接收表面(即衬底的第二表面侧)上,光电检测器31构成起光电转换器作用的光电二极管,换言之,该膜设置在第一导电类型区(n型电荷积累区)41的光接收表面上。至少部分结晶的绝缘膜92是由选自铪、锆、铝、钽、钛、钇、镧系元素等的元素的氧化物构成的绝缘膜。至少部分结晶的绝缘膜92在绝缘膜中具有至少部分结晶的区域。The solid-state imaging device according to this embodiment includes a film having a predetermined thickness d3 and negative fixed charges, such as an at least partially crystallized insulatingfilm 92, which is provided on the light receiving surface of the photodetector 31 (ie, the second surface side of the substrate) ), thephotodetector 31 constitutes a photodiode functioning as a photoelectric converter, in other words, the film is provided on the light receiving surface of the first conductivity type region (n-type charge accumulation region) 41 . The at least partially crystalline insulatingfilm 92 is an insulating film composed of oxides of elements selected from hafnium, zirconium, aluminum, tantalum, titanium, yttrium, lanthanoids, and the like. The at least partially crystalline insulatingfilm 92 has an at least partially crystalline region in the insulating film.

至少部分结晶的绝缘膜92可具有3nm-100nm的厚度。在小于3nm的厚度,该膜不易于结晶。从实际观点出发,厚度的上限可为约100nm。不需要更大的厚度。考虑到光学性能诸如透射率,数十纳米的厚度是较佳的。The at least partially crystalline insulatingfilm 92 may have a thickness of 3 nm to 100 nm. At thicknesses less than 3 nm, the film is not prone to crystallization. From a practical point of view, the upper limit of the thickness may be about 100 nm. Greater thickness is not required. In consideration of optical properties such as transmittance, a thickness of several tens of nanometers is preferable.

在结晶的绝缘膜92和光电检测器31的光接收表面之间的界面处形成具有预定厚度d3的绝缘膜93(在该实施例中为硅氧化物膜)。作为结晶的绝缘膜92的铪氧化物膜在预定温度经历结晶退火以在膜中产生负电荷。所得的结晶的绝缘膜92具有控制光电检测器31的光接收表面的电势的电致控制功能。An insulating film 93 (a silicon oxide film in this embodiment) having a predetermined thickness d3 is formed at the interface between the crystallized insulatingfilm 92 and the light receiving surface of thephotodetector 31 . The hafnium oxide film as the crystallized insulatingfilm 92 is subjected to crystallization annealing at a predetermined temperature to generate negative charges in the film. The resulting crystallized insulatingfilm 92 has an electro-controlling function of controlling the potential of the light-receiving surface of thephotodetector 31 .

结晶的绝缘膜92被覆盖以平坦化膜95,具有预定厚度的绝缘膜94诸如硅氧化物膜设置在其间。平坦化膜95被覆盖以滤色器35。滤色器35被覆盖以芯片上微透镜36。遮光膜97设置在与成像部分81(对应于像素部分11)相邻的外围电路部分82中在绝缘膜(硅氧化物)94上。The crystallized insulatingfilm 92 is covered with aplanarization film 95 with an insulatingfilm 94 having a predetermined thickness such as a silicon oxide film interposed therebetween. Theplanarizing film 95 is covered with thecolor filter 35 . Thecolor filter 35 is covered with an on-chip microlens 36 . Thelight shielding film 97 is provided on the insulating film (silicon oxide) 94 in theperipheral circuit portion 82 adjacent to the imaging portion 81 (corresponding to the pixel portion 11 ).

结晶的绝缘膜92例如铪氧化物膜具有约2.0的折射率。设置在结晶的绝缘膜92上的绝缘膜(硅氧化物膜)94具有约1.45的折射率。因此,形成结晶的绝缘膜(铪氧化物膜)92和绝缘膜(硅氧化物膜)94构成的抗反射膜。Crystallized insulatingfilm 92 such as a hafnium oxide film has a refractive index of about 2.0. The insulating film (silicon oxide film) 94 provided on the crystallized insulatingfilm 92 has a refractive index of about 1.45. Thus, an antireflection film composed of a crystallized insulating film (hafnium oxide film) 92 and insulating film (silicon oxide film) 94 is formed.

根据第六实施例的固态成像装置,在光电检测器31的光接收表面上形成具有负固定电荷的膜,例如至少部分结晶的绝缘膜92,从而导致在光电二极管的表面上的空穴积累状态。这可以抑制由于界面态造成的暗电流分量。此外,空穴积累状态可以产生在光电二极管的表面上,而没有已知的用于形成空穴积累层的离子注入或退火,或者尽管是低剂量,因此抑制了由于界面态导致的暗电流。此外,通过具有负固定电荷的膜例如结晶的绝缘膜92(例如铪氧化物膜)和结晶的绝缘膜92上的绝缘膜(硅氧化物膜)94构成抗反射膜,由此实现了低按电流和高灵敏度。According to the solid-state imaging device of the sixth embodiment, a film having negative fixed charges, such as the at least partially crystallized insulatingfilm 92, is formed on the light receiving surface of thephotodetector 31, thereby causing a hole accumulation state on the surface of the photodiode . This can suppress the dark current component due to the interface state. Furthermore, a hole accumulation state can be generated on the surface of the photodiode without known ion implantation or annealing for forming a hole accumulation layer, or despite a low dose, thus suppressing dark current due to interface states. In addition, the antireflection film is constituted by a film having a negative fixed charge such as a crystallized insulating film 92 (for example, a hafnium oxide film) and an insulating film (silicon oxide film) 94 on the crystallized insulatingfilm 92, thereby realizing a low voltage current and high sensitivity.

根据本发明的实施例,包括根据第六实施例的固态成像装置的摄像机可具有低暗电流和改善的灵敏度。According to an embodiment of the present invention, a video camera including the solid-state imaging device according to the sixth embodiment can have low dark current and improved sensitivity.

下面进一步详细地描述该实施例。上述光电二极管,即具有设置在第一导电类型的第一区域(n型电荷积累区)的表面侧的第二导电类型的第二区域(p型电荷积累区)的嵌入式光电二极管结构,通过在界面附近形成空穴积累区抑制了因为界面态而由载流子生成(carrier generation)导致的暗电流。当空穴积累状态不能通过离子注入形成时,表面附近的空穴积累状态不通过光电二极管中的杂质剖面分布(profile)(掺杂剂剖面分布)形成,而是通过光电二极管的上层中的固定电荷形成。与光电检测器接触的膜优选具有较低的界面态密度,因为暗电流被减小。即,需要形成具有低界面态密度和在膜中具有负固定电荷的膜。This embodiment is described in further detail below. The photodiode described above, that is, the embedded photodiode structure having the second region (p-type charge accumulation region) of the second conductivity type provided on the surface side of the first region (n-type charge accumulation region) of the first conductivity type, is formed by Forming a hole accumulation region near the interface suppresses dark current caused by carrier generation due to the interface state. When the hole accumulation state cannot be formed by ion implantation, the hole accumulation state near the surface is formed not by the impurity profile (dopant profile) in the photodiode but by the fixed charge in the upper layer of the photodiode form. The film in contact with the photodetector preferably has a lower interface state density because the dark current is reduced. That is, it is necessary to form a film with a low interface state density and negative fixed charges in the film.

通过原子层沉积而沉积的铪氧化物适于作为形成具有低界面态密度和在膜中具有负固定电荷的膜的材料。Hafnium oxide deposited by atomic layer deposition is suitable as a material for forming a film having a low interface state density and having negative fixed charges in the film.

在低功耗LSI中,为了实现低漏电流,近来已经研究了每个具有数纳米厚度的铪氧化物膜。此外,已知铪氧化物的结晶增大了漏电流。通常,用于栅极绝缘膜且每个具有数纳米厚度的铪氧化物膜大约在500℃结晶。因此,为了提高耐热性,采用通过将Si引入到铪氧化物中来提高结晶温度的方法。然而,在铪氧化物膜不用于栅极绝缘膜,而是形成在图像传感器的光电二极管表面上的情况,漏电流特性不产生问题。In low power consumption LSIs, in order to realize low leakage current, hafnium oxide films each having a thickness of several nanometers have been studied recently. Furthermore, crystallization of hafnium oxide is known to increase leakage current. In general, hafnium oxide films used for gate insulating films and each having a thickness of several nanometers are crystallized at about 500°C. Therefore, in order to improve heat resistance, a method of increasing the crystallization temperature by introducing Si into hafnium oxide is employed. However, in the case where the hafnium oxide film is not used for the gate insulating film but is formed on the surface of the photodiode of the image sensor, no problem arises in the leakage current characteristic.

为了获得低反射膜结构,如图26所示,铪氧化物(HfO2)膜优选具有约50nm的厚度。图26是曲线图,示出光电二极管结构的吸收系数与厚度的相关性,光电二极管结构具有硅氧化物(SiO2)膜、铪氧化物(HfO2)膜、硅氧化物(SiO2)膜、以及滤色器,其顺序形成在光电二极管上,铪氧化物膜的厚度以10nm的步幅从10nm改变到100nm。纵轴表示绿光电二极管中光的吸收系数(%)。水平轴表示蓝光电二极管中光的吸收系数(%)。在约50nm厚度,蓝光电二极管中光的吸收系数是90%或更大,绿光电二极管中光的吸收系数是80%或更大。In order to obtain a low reflection film structure, as shown in FIG. 26, the hafnium oxide (HfO2 ) film preferably has a thickness of about 50 nm. 26 is a graph showing the dependence of the absorption coefficient on the thickness of a photodiode structure having a silicon oxide (SiO2 ) film, a hafnium oxide (HfO2 ) film, a silicon oxide (SiO2 ) film , and a color filter, which were sequentially formed on the photodiode, the thickness of the hafnium oxide film was changed from 10 nm to 100 nm in steps of 10 nm. The vertical axis represents the absorption coefficient (%) of light in the green photodiode. The horizontal axis represents the absorption coefficient (%) of light in the blue photodiode. At a thickness of about 50 nm, the absorption coefficient of light in the blue photodiode is 90% or more, and the absorption coefficient of light in the green photodiode is 80% or more.

如上所述,发现过去没有用于已知MOS-LSI的厚铪氧化物膜具有低结晶温度,在约300℃开始结晶。图27A和27B每个是有或没有在320℃热处理16小时的铪氧化物膜的TEM照片。图27A是没有热氧化处理的铪氧化物膜的TEM照片。图27B是热氧化处理之后的铪氧化物膜的TEM照片。在图27A和27B的每个中,硅氧化物膜202、铪氧化物膜203和用作保护膜的硅氧化物膜204顺序层叠在硅衬底201上。图27B显示,铪氧化物膜203在热处理之后完全结晶。在图27A所示的没有经历热处理的铪氧化物膜203中,结晶被限制在膜的局部区域。As described above, it was found that a thick hafnium oxide film that has not been used in the known MOS-LSI in the past has a low crystallization temperature, starting to crystallize at about 300°C. 27A and 27B are each a TEM photograph of a hafnium oxide film with or without heat treatment at 320° C. for 16 hours. Fig. 27A is a TEM photograph of a hafnium oxide film without thermal oxidation treatment. FIG. 27B is a TEM photograph of the hafnium oxide film after thermal oxidation treatment. In each of FIGS. 27A and 27B , asilicon oxide film 202 , ahafnium oxide film 203 , and asilicon oxide film 204 serving as a protective film are sequentially stacked on asilicon substrate 201 . FIG. 27B shows that thehafnium oxide film 203 is completely crystallized after heat treatment. In thehafnium oxide film 203 shown in FIG. 27A that has not been subjected to heat treatment, crystallization is limited to a localized region of the film.

图28示出在通过热处理结晶期间铪氧化物膜中固定电荷的属性。图29示出包括具有10nm厚的铪氧化物(HfO2)膜和硅氧化物(SiO2)膜的层叠膜的MOS电容器的C-V特性,层叠膜起栅极绝缘膜的作用。图28示出MOS电容器的平带电压Vfb的测量结果,热处理温度固定在320℃,热处理时间改变。图28显示,平带电压Vfb随着热处理时间延长而朝较高电压偏移。即,该结果表明在铪氧化物膜中负电荷量的增大。FIG. 28 shows properties of fixed charges in a hafnium oxide film during crystallization by heat treatment. FIG. 29 shows CV characteristics of a MOS capacitor including a laminated film having a thickness of 10 nm of a hafnium oxide (HfO2 ) film and a silicon oxide (SiO2 ) film, which functions as a gate insulating film. FIG. 28 shows the measurement results of the flat-band voltage Vfb of the MOS capacitor with the heat treatment temperature fixed at 320° C. and the heat treatment time varied. Figure 28 shows that the flat-band voltage Vfb shifts toward higher voltages as the heat treatment time increases. That is, the results indicate an increase in the amount of negative charges in the hafnium oxide film.

类似地,图29示出MOS电容器的平带电压Vfb的属性,热处理时间固定在一小时,热处理温度改变。在该情况下,结果表明平带电压Vfb随着热处理温度增大而朝较高电压移动。即,该结果表明铪氧化物膜中负电荷量的增大。Similarly, FIG. 29 shows the properties of the flat band voltage Vfb of the MOS capacitor with the heat treatment time fixed at one hour and the heat treatment temperature varied. In this case, the results show that the flatband voltage Vfb shifts toward higher voltages as the heat treatment temperature increases. That is, this result indicates an increase in the amount of negative charges in the hafnium oxide film.

使用具有例如50nm厚度的厚铪氧化物膜能够实现低反射结构,且能够降低结晶温度以增大绝缘膜中负电荷的量。因此,铪氧化物膜适于固态成像装置。如上所述,发现具有10nm或更大厚度的铪氧化物膜在400℃或更低温度的热处理导致结晶铪氧化物膜的形成。此外,发现随着热处理时间或热处理温度增加,即随着结晶进行,在铪氧化物膜中形成负电荷。对于用于MOS-LSI和栅极绝缘膜的已知应用,由于结晶引起的大量负电荷和漏电流增大是不利的特性。然而,在该实施例中,铪氧化物膜对于固态成像装置的光电二极管的表面上空穴的积累是显著有效的。通过在400℃或更低温度下的低温工艺,铪氧化物膜的使用导致光电二极管的表面上空穴积累状态的形成,从而抑制暗电流。Using a thick hafnium oxide film having a thickness of, for example, 50 nm can realize a low reflection structure, and can lower the crystallization temperature to increase the amount of negative charges in the insulating film. Therefore, hafnium oxide films are suitable for solid-state imaging devices. As described above, it was found that heat treatment of a hafnium oxide film having a thickness of 10 nm or more at a temperature of 400° C. or lower resulted in the formation of a crystalline hafnium oxide film. Furthermore, it was found that negative charges were formed in the hafnium oxide film as the heat treatment time or heat treatment temperature increased, that is, as crystallization proceeded. For known applications for MOS-LSI and gate insulating films, a large amount of negative charges and an increase in leakage current due to crystallization are unfavorable characteristics. However, in this example, the hafnium oxide film is remarkably effective for the accumulation of holes on the surface of the photodiode of the solid-state imaging device. The use of the hafnium oxide film leads to the formation of a hole accumulation state on the surface of the photodiode through a low-temperature process at 400° C. or lower, thereby suppressing dark current.

在该实施例中,已经描述了铪氧化物膜。可替换地,由选自锆、铝、钽、钛、钇、镧系元素等的元素的氧化物构成的绝缘膜也能够在膜中形成负固定电荷。在光接收表面上形成这些氧化物绝缘膜之一导致光电二极管表面上空穴积累状态的形成,从而抑制暗电流。In this embodiment, the hafnium oxide film has been described. Alternatively, an insulating film composed of oxides of elements selected from zirconium, aluminum, tantalum, titanium, yttrium, lanthanoids, and the like can also form negative fixed charges in the film. Formation of one of these oxide insulating films on the light-receiving surface leads to the formation of a hole accumulation state on the surface of the photodiode, thereby suppressing dark current.

图30A-32G示出制造根据第六实施例的固态成像装置的方法的实施例。图30A-32G每个是示意剖面图,示出成像部分81和外围电路部分82。30A-32G show an example of a method of manufacturing the solid-state imaging device according to the sixth embodiment. 30A-32G are each a schematic sectional view showing theimaging section 81 and theperipheral circuit section 82 .

多个像素以二维阵列形成在图30A所示的半导体衬底30的成像部分81中。逻辑电路等形成在外围电路部分82中。A plurality of pixels are formed in a two-dimensional array in theimaging portion 81 of thesemiconductor substrate 30 shown in FIG. 30A . Logic circuits and the like are formed in theperipheral circuit portion 82 .

如图30B所示,在成像部分81和外围电路部分82的整个表面上通过ALD形成铪氧化物膜92。铪氧化物膜92具有约2.0的折射率。因此,膜厚度的适当调整导致抗反射效果的获得。优选地,形成具有50nm-60nm厚度的铪氧化物膜92。此外,当通过ALD形成铪氧化物膜92时,在衬底30的表面即光电二极管的表面与铪氧化物膜92之间的界面处形成具有约1nm厚度的硅氧化物膜93。As shown in FIG. 30B , ahafnium oxide film 92 is formed by ALD on the entire surfaces of theimaging portion 81 and theperipheral circuit portion 82 .Hafnium oxide film 92 has a refractive index of about 2.0. Therefore, proper adjustment of the film thickness leads to the acquisition of the anti-reflection effect. Preferably,hafnium oxide film 92 is formed to have a thickness of 50 nm to 60 nm. Further, whenhafnium oxide film 92 is formed by ALD,silicon oxide film 93 having a thickness of about 1 nm is formed at the interface between the surface ofsubstrate 30 , that is, the surface of the photodiode, andhafnium oxide film 92 .

如图30C所示,铪氧化物膜92经历结晶退火以在铪氧化物膜中形成负固定电荷。As shown in FIG. 30C,hafnium oxide film 92 undergoes crystallization annealing to form negative fixed charges in the hafnium oxide film.

如图30D所示,硅氧化物膜94且然后遮光膜97形成在铪氧化物膜92上。通过形成硅氧化物膜94,铪氧化物膜92不直接接触遮光膜97,从而抑制了铪氧化物膜92和遮光膜97由于其接触而反应。此外,在蚀刻遮光膜97期间,硅氧化物膜94能够防止铪氧化物膜92的表面被蚀刻。遮光膜97优选由具有合意的遮光能力的钨(W)构成。As shown in FIG. 30D , asilicon oxide film 94 and then alight shielding film 97 are formed on thehafnium oxide film 92 . By forming thesilicon oxide film 94, thehafnium oxide film 92 does not directly contact thelight shielding film 97, thereby suppressing the reaction of thehafnium oxide film 92 and thelight shielding film 97 due to their contact. In addition, thesilicon oxide film 94 can prevent the surface of thehafnium oxide film 92 from being etched during etching of thelight shielding film 97 . The light-shieldingfilm 97 is preferably composed of tungsten (W) having desirable light-shielding ability.

如图31E所示,遮光膜97被选择性去除,使得成像部分81被部分覆盖以遮光膜97,且使得外围电路部分82被完全覆盖以遮光膜97。处理过的遮光膜97在光电二极管中形成遮光区。图像的黑度级(black level)由光电二极管的输出确定。此外,遮光膜97抑制了由于入射在外围电路部分82上的光造成的性能变化。As shown in FIG. 31E , thelight shielding film 97 is selectively removed so that theimaging portion 81 is partially covered with thelight shielding film 97 and so that theperipheral circuit portion 82 is completely covered with thelight shielding film 97 . The processed light-shieldingfilm 97 forms a light-shielding region in the photodiode. The black level of the image is determined by the output of the photodiode. In addition, the light-shieldingfilm 97 suppresses changes in performance due to light incident on theperipheral circuit portion 82 .

如图32F所示,形成平坦化膜95以平整由于遮光膜97造成的隆起。As shown in FIG. 32F , a flatteningfilm 95 is formed to flatten the bumps due to the light-shieldingfilm 97 .

如图32G所示,在平坦化膜95上在成像部分81侧形成滤色器35。此外,聚集光的芯片上微透镜36形成在其上。从而,制造了根据第六实施例的目标固态成像装置。As shown in FIG. 32G , thecolor filter 35 is formed on theimaging portion 81 side on theplanarizing film 95 . In addition, an on-chip microlens 36 that collects light is formed thereon. Thus, the target solid-state imaging device according to the sixth embodiment was manufactured.

本发明不限于实施例的描述。The invention is not limited to the description of the examples.

例如,在实施例中描述的值和材料用作示例。本发明不限于此。For example, the values and materials described in the Examples are used as examples. The present invention is not limited thereto.

此外,可以进行各种修改而不偏离本发明的范围。In addition, various modifications may be made without departing from the scope of the present invention.

本领域普通技术人员将理解,在所附权利要求书及其等价物的范围内,可以根据设计需要和其他因素产生各种修改、组合、子组合、以及替换。It will be understood by those skilled in the art that various modifications, combinations, sub-combinations, and substitutions may occur depending on design requirements and other factors within the scope of the appended claims and the equivalents thereof.

本发明包含与2006年3月17向日本专利局提交的日本专利申请JP2006-048173相关的主题,在此引用其全部内容作为参考。The present invention contains subject matter related to Japanese Patent Application JP2006-048173 filed in the Japan Patent Office on Mar. 17, 2006, the entire content of which is hereby incorporated by reference.

Claims (4)

Translated fromChinese
1.一种背面照射类型的固态成像装置,包括:1. A solid-state imaging device of a backside illumination type, comprising:衬底,具有第一表面和第二表面,光入射在该第二表面侧;a substrate having a first surface and a second surface on which light is incident;布线层,设置在该第一表面侧;a wiring layer disposed on the first surface side;光电检测器,形成在该衬底中且包括第一导电类型的第一区;a photodetector formed in the substrate and comprising a first region of a first conductivity type;转移栅极,设置在该衬底的该第一表面上且邻近该光电检测器,该转移栅极传输积累在该光电检测器中的信号电荷;以及a transfer gate disposed on the first surface of the substrate adjacent to the photodetector, the transfer gate transferring signal charges accumulated in the photodetector; and至少一个控制栅极,设置在该衬底的该第一表面上且叠置在该光电检测器上,该控制栅极控制该第一表面附近该光电检测器的电势;at least one control gate disposed on the first surface of the substrate overlying the photodetector, the control gate controlling the potential of the photodetector near the first surface;其中,所述至少一个控制栅极包括多个控制栅极,且该多个控制栅极相关于单个光电检测器设置。Wherein, the at least one control gate includes a plurality of control gates, and the plurality of control gates are arranged relative to a single photodetector.2.如权利要求1所述的固态成像装置,其中该光电检测器包括第二导电类型的第二区,该第二区至少设置在该第一表面侧或该第二表面侧。2. The solid-state imaging device according to claim 1, wherein the photodetector includes a second region of the second conductivity type, the second region being provided at least on the first surface side or the second surface side.3.一种制造背面照射类型的固态成像装置的方法,该固态成像装置包括具有第一表面和第二表面的衬底,布线层设置在该第一表面侧,光入射在该第二表面侧,该方法包括步骤:3. A method of manufacturing a back-illuminated type solid-state imaging device comprising a substrate having a first surface and a second surface, a wiring layer is provided on the first surface side, and light is incident on the second surface side , the method includes the steps of:在衬底中形成包括第一导电类型的第一区的光电检测器;forming a photodetector comprising a first region of a first conductivity type in a substrate;形成在该衬底的该第一表面上的区域处且邻近该光电检测器的转移栅极;以及a transfer gate formed at a region on the first surface of the substrate adjacent to the photodetector; and形成在该衬底的该第一表面上的区域处且叠置在该光电检测器上的控制栅极;a control gate formed at a region on the first surface of the substrate and overlying the photodetector;其中所述控制栅极包括多个控制栅极,且该多个控制栅极相关于单个光电检测器设置。Wherein the control gate comprises a plurality of control gates, and the plurality of control gates are arranged relative to a single photodetector.4.一种摄像机,包括:4. A video camera, comprising:背面照射类型的固态成像装置,包括Solid-state imaging devices of the back-illuminated type, including衬底,具有第一表面和第二表面,光入射在该第二表面侧;以及a substrate having a first surface and a second surface on which light is incident; and布线层,设置在该第一表面侧;a wiring layer disposed on the first surface side;光学系统,将入射光引导向所述第二表面侧;以及an optical system that guides incident light toward the second surface side; and信号处理电路,处理该固态成像装置的输出信号;a signal processing circuit for processing an output signal of the solid-state imaging device;其中该固态成像装置还包括Wherein the solid-state imaging device also includes光电检测器,设置在该衬底中且包括第一导电类型的第一区,a photodetector disposed in the substrate and comprising a first region of a first conductivity type,转移栅极,设置在该衬底的该第一表面上且邻近该光电检测器,该转移栅极传输积累在该光电检测器中的信号电荷;以及a transfer gate disposed on the first surface of the substrate adjacent to the photodetector, the transfer gate transferring signal charges accumulated in the photodetector; and控制栅极,设置在该衬底的该第一表面上且叠置在该光电检测器上,该控制栅极控制该第一表面附近该光电检测器的电势;a control gate disposed on the first surface of the substrate overlying the photodetector, the control gate controlling the potential of the photodetector near the first surface;其中所述至少一个控制栅极包括多个控制栅极,且该多个控制栅极相关于单个光电检测器设置。Wherein the at least one control gate comprises a plurality of control gates, and the plurality of control gates are arranged relative to a single photodetector.
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