CN101030602B

Movatterモバイル変換

Info

Publication number: CN101030602B
Application number: CN2007100391861A
Authority: CN
Inventors: 康晓旭
Original assignee: Shanghai Integrated Circuit Research and Development Center Co Ltd
Current assignee: Shanghai IC R&D Center Co Ltd
Priority date: 2007-04-06
Filing date: 2007-04-06
Publication date: 2012-03-21
Anticipated expiration: 2027-04-06
Also published as: US8193057B2; US20080246087A1; CN101030602A; US20110059588A1

Abstract

The invention is concerned with MOS transistor and production to reduce short-channel effects. Existing process has the problem of high complexity and high cost to reduce short-channel effects by using epitaxial method to produce raised source and drain. This MOS transistor produced on silicon underlay with finished field isolation area, relating to grid pile, grid sidewall, source and drain. The silicon underlay has groove and the grid pile set in the groove. The process of this MOS transistor is making groove at first, the carrying injecting of trap, breakdown protection and threshold voltage adjustment, producing grid pile in the groove and carrying lightly doped drain injecting and corona injecting to get grid sidewall, the carrying source injecting to get source and drain, the last step producing silicide on top of source and drain.

Description

Translated fromChinese

一种可减小短沟道效应的MOS晶体管及其制作方法A MOS transistor capable of reducing short-channel effect and its manufacturing method

技术领域technical field

本发明涉及半导体制造领域，特别涉及一种可减小短沟道效应的MOS晶体管及其制作方法。The invention relates to the field of semiconductor manufacturing, in particular to a MOS transistor capable of reducing short-channel effects and a manufacturing method thereof.

背景技术Background technique

半导体器件通过按比例缩小来实现工作速度的提升。MOS晶体管的沟道长度也在不断的按比例缩短，但当MOS晶体管的沟道长度变得非常短时，短沟道效应会使器件性能劣化，甚至无法正常工作。减小栅极绝缘层的厚度或制作浅结的源极和漏极均可有效的减小短沟道效应，但现在栅极绝缘层的厚度已达到极限，当再减小时易导致栅极的漏电流增大或栅极的击穿，故无法通过减小栅极绝缘层的厚度来减小短沟道效应；另外为确保栅、漏极的较小的接触电阻，故需确保栅、漏极表面具一定厚度的金属硅化物层，故也很难通过制作浅结的源极和漏极来减小短沟道效应。Semiconductor devices achieve increased operating speeds by scaling down. The channel length of the MOS transistor is also continuously shortened in proportion, but when the channel length of the MOS transistor becomes very short, the short channel effect will degrade the performance of the device, or even fail to work normally. Reducing the thickness of the gate insulating layer or making the source and drain of the shallow junction can effectively reduce the short channel effect, but now the thickness of the gate insulating layer has reached the limit, and when it is further reduced, it will easily lead to the short channel effect. Leakage current increases or gate breakdown, so the short channel effect cannot be reduced by reducing the thickness of the gate insulating layer; in addition, in order to ensure the small contact resistance of the gate and drain, it is necessary to ensure The pole surface has a metal silicide layer with a certain thickness, so it is also difficult to reduce the short channel effect by making shallow junction source and drain electrodes.

为减小上述短沟道效应，现通常使用外延工艺制作抬高的源极和漏极。但是外延工艺是一种成本很高、难于控制的工艺技术，存在高复杂性、高成本、高缺陷密度等问题。In order to reduce the above-mentioned short-channel effect, the raised source and drain are usually fabricated by epitaxial process. However, the epitaxy process is a high-cost and difficult-to-control process technology, which has problems such as high complexity, high cost, and high defect density.

发明内容Contents of the invention

本发明的目的在于提供一种可减小短沟道效应的MOS晶体管及其制作方法，通过所述MOS晶体管及其制作方法可有效的减小短沟道效应，并可降低工艺难度和制作成本。The object of the present invention is to provide a MOS transistor capable of reducing the short-channel effect and its manufacturing method, through which the short-channel effect can be effectively reduced, and the process difficulty and manufacturing cost can be reduced .

本发明的目的是这样实现的：一种可减小短沟道效应的MOS晶体管，该MOS晶体管制作在已制成场隔离区的硅衬底上，该MOS晶体管包括栅极堆层、栅极侧墙、源极以及漏极，其中，该栅极堆层包括依次层叠的栅极绝缘层与栅极，该源极和漏极顶部具有金属硅化物层，其中，该硅衬底上制作有凹槽，该栅极堆层设置在该凹槽中。The object of the present invention is achieved like this: a kind of MOS transistor that can reduce the short channel effect, and this MOS transistor is made on the silicon substrate that has made field isolation region, and this MOS transistor comprises gate stack layer, gate sidewall, source and drain, wherein the gate stack layer includes a gate insulating layer and a gate stacked in sequence, the top of the source and drain has a metal silicide layer, wherein the silicon substrate is fabricated A groove, the gate stack layer is disposed in the groove.

在上述的可减小短沟道效应的MOS晶体管中，该凹槽的面积不小于该栅极堆层的面积。In the above-mentioned MOS transistor capable of reducing the short channel effect, the area of the groove is not smaller than the area of the gate stack.

在上述的可减小短沟道效应的MOS晶体管中，该MOS晶体管还包括轻掺杂漏结构。In the above MOS transistor capable of reducing the short channel effect, the MOS transistor further includes a lightly doped drain structure.

在上述的可减小短沟道效应的MOS晶体管中，该MOS晶体管还包括晕注入结构。In the above MOS transistor capable of reducing the short channel effect, the MOS transistor further includes a halo implantation structure.

本发明还提供一种可减小短沟道效应的MOS晶体管的制作方法，该MOS晶体管制作在已制成场隔离区的硅衬底上，该方法包括以下步骤：(1)在该硅衬底上制作凹槽；(2)进行阱注入、防穿通注入和阈值电压调整注入；(3)在该凹槽中制作栅极堆层，该栅极堆层包括依次层叠的栅极绝缘层与栅极；(4)进行轻掺杂漏注入和晕注入；(5)制作栅极侧墙；(6)进行源漏注入，以制成源极和漏极；(7)在源极和漏极顶部制作金属硅化物层。The present invention also provides a method for manufacturing a MOS transistor capable of reducing the short channel effect, the MOS transistor is manufactured on a silicon substrate having field isolation regions, and the method comprises the following steps: (1) forming a MOS transistor on the silicon substrate making a groove on the bottom; (2) carrying out well implantation, anti-punching implantation and threshold voltage adjustment implantation; (3) making a gate stack layer in the groove, and the gate stack layer includes a sequentially stacked gate insulating layer and Gate; (4) Perform lightly doped drain implantation and halo implantation; (5) Make gate sidewall; (6) Perform source-drain implantation to make source and drain; (7) In source and drain A metal silicide layer is made on the top of the pole.

在上述的可减小短沟道效应的MOS晶体管的制作方法中，该步骤(1)包括以下步骤：(10)光刻出对应栅极的凹槽图形；(11)通过刻蚀制成凹槽；(12)去除光刻胶并优化硅衬底的表面。In the above-mentioned manufacturing method of the MOS transistor that can reduce the short channel effect, the step (1) includes the following steps: (10) photocutting a groove pattern corresponding to the gate; (11) forming a concave groove pattern by etching groove; (12) removing photoresist and optimizing the surface of the silicon substrate.

在上述的可减小短沟道效应的MOS晶体管的制作方法中，在步骤(11)中，通过湿法刻蚀制成该凹槽。In the above method of manufacturing a MOS transistor capable of reducing short channel effect, in step (11), the groove is formed by wet etching.

在上述的可减小短沟道效应的MOS晶体管的制作方法中，在步骤(12)中，通过氧化和湿法腐蚀工艺来优化硅衬底的表面。In the above-mentioned manufacturing method of the MOS transistor capable of reducing the short channel effect, in step (12), the surface of the silicon substrate is optimized through oxidation and wet etching processes.

在上述的可减小短沟道效应的MOS晶体管的制作方法中，该凹槽的面积不小于该栅极堆层的面积。In the above method of manufacturing a MOS transistor capable of reducing short channel effect, the area of the groove is not smaller than the area of the gate stack.

与现有技术中采用外延工艺制作抬高的源极和漏极来减小短沟道效应相比，本发明的可减小短沟道效应的MOS晶体管及其制作方法将栅极堆层制作在低于源漏极的凹槽中，以达成相对抬高源漏极的目的，从而可有效的减小短沟道效应，另外可降低工艺难度和制作成本，再者，可降低栅极堆层的高度，为后续金属前栅堆层间介质淀积工艺提供更大的工艺窗口。Compared with the use of epitaxial technology to make raised source and drain in the prior art to reduce the short channel effect, the MOS transistor and its manufacturing method which can reduce the short channel effect of the present invention make the gate stack layer In the groove below the source and drain, the purpose of relatively raising the source and drain can be achieved, which can effectively reduce the short channel effect, and can also reduce the process difficulty and manufacturing cost. Furthermore, the gate stack can be reduced The height of the layer provides a larger process window for the subsequent metal front gate stack interlayer dielectric deposition process.

附图说明Description of drawings

本发明的可减小短沟道效应的MOS晶体管及其制作方法由以下的实施例及附图给出。The MOS transistor capable of reducing the short channel effect and its manufacturing method of the present invention are given by the following embodiments and accompanying drawings.

图1为本发明的可减小短沟道效应的MOS晶体管的剖视图；Fig. 1 is the sectional view of the MOS transistor that can reduce short channel effect of the present invention;

图2为本发明的可减小短沟道效应的MOS晶体管的制作方法的实施例的流程图；Fig. 2 is the flowchart of the embodiment of the manufacturing method of the MOS transistor that can reduce short channel effect of the present invention;

图3为完成图2中步骤S20后的硅衬底的剖视图；Fig. 3 is a cross-sectional view of the silicon substrate after step S20 in Fig. 2 is completed;

图4为完成图2中步骤S21后的硅衬底的剖视图。FIG. 4 is a cross-sectional view of the silicon substrate after step S21 in FIG. 2 is completed.

具体实施方式Detailed ways

以下将对本发明的可减小短沟道效应的MOS晶体管及其制作方法作进一步的详细描述。The MOS transistor capable of reducing the short channel effect and its manufacturing method of the present invention will be further described in detail below.

如图1所示，本发明的可减小短沟道效应的MOS晶体管1制作在硅衬底2上，所述硅衬底2上已制成了场隔离区(未图示)，所述可减小短沟道效应的MOS晶体管1包括栅极堆层10、栅极侧墙11、源极12、漏极13、轻掺杂漏(LDD)结构14、晕注入(halo)结构15。As shown in Fig. 1, the MOS transistor 1 that can reduce the short channel effect of the present invention is made on thesilicon substrate 2, and the field isolation region (not shown) has been made on the describedsilicon substrate 2, described The MOS transistor 1 capable of reducing the short channel effect includes agate stack 10 , agate spacer 11 , asource 12 , adrain 13 , a lightly doped drain (LDD)structure 14 , and a halo implantation (halo)structure 15 .

所述栅极堆层10包括栅极绝缘层100和栅极102。所述硅衬底2上对应栅极堆层10制作有凹槽(未图示)，所述凹槽的面积不小于所述栅极堆层10的面积，所述栅极堆层10设置在所述凹槽中。Thegate stack 10 includes agate insulating layer 100 and agate 102 . A groove (not shown) is made on thesilicon substrate 2 corresponding to thegate stack 10, the area of the groove is not smaller than the area of thegate stack 10, and thegate stack 10 is arranged on in the groove.

所述栅极侧墙11设置在栅极堆层10两侧，用于确保栅极堆层10与源极12和漏极13之间的绝缘。Thegate spacers 11 are arranged on both sides of thegate stack 10 to ensure the insulation between thegate stack 10 and thesource 12 and thedrain 13 .

所述源极12和漏极13设置在硅衬底2内且排布在栅极10两侧，所述源极12和漏极13顶部具有金属硅化物层120和130。Thesource 12 and thedrain 13 are disposed in thesilicon substrate 2 and arranged on both sides of thegate 10 , withmetal silicide layers 120 and 130 on top of thesource 12 and thedrain 13 .

在本实施例中，通过浅沟槽隔离技术制成所述场隔离区，所述栅极绝缘层100为氧化硅层，所述栅极102为多晶硅栅极，所述栅极侧墙11由氧化硅制成。In this embodiment, the field isolation region is formed by shallow trench isolation technology, thegate insulating layer 100 is a silicon oxide layer, thegate 102 is a polysilicon gate, and thegate spacer 11 is made of Made of silicon oxide.

所述轻掺杂漏结构14和晕注入结构15均可在一定程度上减小短沟道效应，但不能彻底的解决短沟道效应。通过本发明的凹槽使得MOS晶体管1的沟道低于源极12和漏极13的平面，如此可有效减小短沟道效应。Both the lightly dopeddrain structure 14 and thehalo implantation structure 15 can reduce the short channel effect to a certain extent, but cannot completely solve the short channel effect. The channel of the MOS transistor 1 is lower than the plane of thesource 12 and thedrain 13 through the groove of the present invention, so that the short channel effect can be effectively reduced.

参见图2，配合参见图1，本发明的可减小短沟道效应的MOS晶体管1的制作方法首先进行步骤S20，光刻出对应栅极堆层10的凹槽图形。参见图3，显示了完成步骤S20后硅衬底2的剖视图，如图所示，光阻3覆盖在硅衬底2，且光阻3上已生成有凹槽图形。Referring to FIG. 2 and referring to FIG. 1 , the manufacturing method of the MOS transistor 1 capable of reducing the short channel effect of the present invention firstly performs step S20 , where a groove pattern corresponding to thegate stack layer 10 is photoetched. Referring to FIG. 3 , it shows a cross-sectional view of thesilicon substrate 2 after step S20 is completed. As shown in the figure, thephotoresist 3 covers thesilicon substrate 2 , and a pattern of grooves has been formed on thephotoresist 3 .

接着继续步骤S21，通过刻蚀制成凹槽。在本实施例中，通过湿法刻蚀制成凹槽。参见图4，显示了完成步骤S21后硅衬底2的剖视图，如图所示，硅衬底2上制成了凹槽20。Then continue to step S21, forming grooves by etching. In this embodiment, the grooves are formed by wet etching. Referring to FIG. 4 , it shows a cross-sectional view of thesilicon substrate 2 after step S21 is completed. As shown in the figure, agroove 20 is formed on thesilicon substrate 2 .

接着继续步骤S22，去除光刻胶并优化硅衬底2的表面。在本实施例中，通过氧化和湿法腐蚀工艺来优化硅衬底的表面。Then continue to step S22 , removing the photoresist and optimizing the surface of thesilicon substrate 2 . In this embodiment, the surface of the silicon substrate is optimized by oxidation and wet etching processes.

接着继续步骤S23，进行阱注入、防穿通注入和阈值电压调整注入。Next, step S23 is continued to perform well implantation, anti-puncture implantation and threshold voltage adjustment implantation.

接着继续步骤S24，在所述凹槽中制作栅极堆层10，所述栅极堆层10包括栅极绝缘层100和栅极102。在本实施例中，首先先沉积栅极绝缘层100，然后再沉积栅极102，最后经光刻和刻蚀制成栅极堆层10。Then continue to step S24 , forming agate stack 10 in the groove, and thegate stack 10 includes agate insulating layer 100 and agate 102 . In this embodiment, thegate insulating layer 100 is deposited first, then thegate 102 is deposited, and finally thegate stack 10 is formed by photolithography and etching.

接着继续步骤S25，进行轻掺杂漏注入和晕注入，以形成轻掺杂漏结构14和晕注入结构15。Then continue to step S25 , performing lightly doped drain implantation and halo implantation to form the lightly dopeddrain structure 14 and thehalo implantation structure 15 .

接着继续步骤S26，制作栅极侧墙11。Then continue to step S26 to fabricate thegate spacer 11 .

接着继续步骤S27，进行源漏注入，以制成源极12和漏极13。Then continue to step S27 , perform source-drain implantation to form thesource electrode 12 and thedrain electrode 13 .

接着继续步骤S28，在源极12和漏极13顶部制作金属硅化物层120和130。Then continue to step S28 , formingmetal silicide layers 120 and 130 on top of thesource electrode 12 and thedrain electrode 13 .

需说明的是，步骤S20和步骤S24中，一般使用两张光罩形成所需的图形，也可使用相同的光罩但使用极性不同的光刻胶进行光刻，其中，在步骤S20中使用反光刻胶，在步骤S24中使用正光刻胶，如此可大大节约成本。It should be noted that, in step S20 and step S24, two photomasks are generally used to form the required pattern, and the same photomask but photoresists with different polarities can also be used for photolithography, wherein, in step S20 Using a reflective photoresist and using a positive photoresist in step S24 can greatly save costs.

综上所述，本发明的可减小短沟道效应的MOS晶体管1及其制作方法将栅极堆层制作在低于源漏极的凹槽中，以达成相对抬高源漏极的目的，从而可有效的减小短沟道效应，另外可降低工艺难度和制作成本，再者，可降低栅极堆层的高度，为后续金属前栅堆层间介质淀积工艺提供更大的工艺窗口。To sum up, the MOS transistor 1 capable of reducing the short channel effect of the present invention and its manufacturing method make the gate stack layer in the groove lower than the source and drain, so as to achieve the purpose of relatively raising the source and drain , so that the short channel effect can be effectively reduced, and the process difficulty and production cost can be reduced. Moreover, the height of the gate stack can be reduced, providing a larger process for the subsequent metal front gate stack interlayer dielectric deposition process. window.

Claims

1. the manufacture method of the MOS transistor of a decreasing short channel, this MOS transistor is produced on the silicon substrate of processing an isolated area, it is characterized in that, and this method may further comprise the steps: (1) makes groove on this silicon substrate; (2) carry out trap and inject, prevent break-through injection and threshold voltage adjustment injection; (3) manufacturing grid heap layer in this groove, this grid pile layer comprises gate insulator and the grid that stacks gradually; (4) carry out lightly doped drain injection and dizzy the injection; (5) manufacturing grid side wall; (6) carry out the source and leak injection, to process source electrode and drain electrode; (7) make metal silicide layer at source electrode and drain electrode top.

2. the manufacture method of the MOS transistor of decreasing short channel as claimed in claim 1 is characterized in that, this step (1) may further comprise the steps: (10) make the groove pattern of corresponding grid by lithography; (11) through being etched into groove; (12) remove photoresist and optimize surface of silicon substrate.

3. the manufacture method of the MOS transistor of decreasing short channel as claimed in claim 2 is characterized in that, in step (11), processes this groove through wet etching.

4. the manufacture method of the MOS transistor of decreasing short channel as claimed in claim 2 is characterized in that, in step (12), optimizes surface of silicon substrate through oxidation and wet corrosion technique.

5. the manufacture method of the MOS transistor of decreasing short channel as claimed in claim 1 is characterized in that, the area of this groove is not less than the area of this grid pile layer.

6. the MOS transistor of a kind of decreasing short channel of making of the manufacture method of the MOS transistor of decreasing short channel as claimed in claim 1; This MOS transistor is produced on the silicon substrate of processing an isolated area; This MOS transistor comprises grid pile layer, grid curb wall, source electrode and drain electrode, and wherein, this grid pile layer comprises gate insulator and the grid that stacks gradually; This source electrode has metal silicide layer with the drain electrode top; It is characterized in that, be manufactured with groove on this silicon substrate, this grid pile layer is arranged in this groove.

7. the MOS transistor of decreasing short channel as claimed in claim 6 is characterized in that, the area of this groove is not less than the area of this grid pile layer.

8. the MOS transistor of decreasing short channel as claimed in claim 6 is characterized in that, this MOS transistor also comprises the lightly doped drain structure.

9. the MOS transistor of decreasing short channel as claimed in claim 6 is characterized in that, this MOS transistor also comprises dizzy injecting structure.