CN101022286A - Bit scramble parallel processing method and apparatus - Google Patents

Abstract

Translated fromChinese

本发明公开了一种比特加扰并行处理方法和装置，适用于宽带码分多址系统的高速下行分组接入领域，将比特加扰扰码的取值扩展到负无穷大；再将16比特相位值存储器中的比特加扰扰码序列对应的相位值向正无穷大方向移动N减M个相位，并进行存储，其中N为并行数据序列的比特数，M为第一个并行数据序列中位于低比特的无效比特数；输入并行数据序列，利用移动后的比特加扰扰码序列与所述并行数据序列完成加扰操作。本发明通过在扰码序列前插入部分多余相位的方式，只需要16个二选一的选择器，从而降低比特加扰并行处理结构的复杂度。

The invention discloses a bit scrambling parallel processing method and device, which are suitable for the field of high-speed downlink packet access in a wideband code division multiple access system, and extend the value of the bit scrambling scrambling code to negative infinity; then the 16-bit phase value The phase value corresponding to the bit scrambling scrambling code sequence in the memory is moved to positive infinity by N minus M phases, and stored, where N is the number of bits in the parallel data sequence, and M is the low bit position in the first parallel data sequence The number of invalid bits: input the parallel data sequence, and use the shifted bit scrambling scrambling code sequence and the parallel data sequence to complete the scrambling operation. The present invention only needs 16 selectors to select one of the two by inserting some redundant phases before the scrambling code sequence, thereby reducing the complexity of the bit scrambling parallel processing structure.

Description

Translated fromChinese

一种比特加扰并行处理方法和装置A bit scrambling parallel processing method and device

技术领域technical field

本发明涉及宽带码分多址(WCDMA)系统的高速下行分组接入(HSDPA)技术领域，尤其涉及一种比特加扰并行处理方法和装置。The invention relates to the high-speed downlink packet access (HSDPA) technical field of a wideband code division multiple access (WCDMA) system, in particular to a bit scrambling parallel processing method and device.

背景技术Background technique

第三代移动伙伴关系(3GPP)标准组织定义了WCDMA高速下行分组接入(HSDPA)符号级处理中的比特加扰的操作过程，具体如下：The 3rd Generation Partnership Partnership (3GPP) standard organization defines the operation process of bit scrambling in WCDMA High Speed Downlink Packet Access (HSDPA) symbol-level processing, as follows:

用b_im，1，b_im，2，b_im，3，...，b_im，B表示输入到比特加扰模块处理的比特流，其中B表示比特流中的比特数，i表示传输信道号，用d_im，1，d_im，2，d_im，3，...，d_im，B表示比特加扰模块处理后输出的比特流。Use bi_{im, 1} , bi_{im, 2} , bi_{im, 3} , ..., bi_{im, B} to represent the bit stream input to the bit scrambling module, where B represents the number of bits in the bit stream, and i represents the transmission channel No. d_{im, 1,} d_{im, 2} , d_{im, 3} , .

则这两个比特流间的关系可以表示为：Then the relationship between the two bit streams can be expressed as:

d_im，k＝(b_im，k+y_k)mod2    k＝1，2，...，B，其中mod表示取模操作，y_k为扰码序列y的第k个值，根据下式生成：d_{im, k} = (b_{im, k} + y_k ) mod2 k = 1, 2, ..., B, where mod represents a modulo operation, and y_k is the kth value of the scrambling code sequence y, according to the following formula generate:

${\mathrm{<span><span>y</span>the\; y</span>}}_{\mathrm{<span><span>\&gamma;</span>\&gamma;</span>}}<span><span>=</span>=</span>\left\{\begin{array}{c}\mathrm{<span><span>0</span>0</span>}<span><span>,</span>,</span><span><span>-</span>-</span>\mathrm{<span><span>15</span>15</span>}<span><span><</span><</span>\mathrm{<span><span>\&gamma;</span>\&gamma;</span>}<span><span><</span><</span>\mathrm{<span><span>1</span>1</span>}\\ \mathrm{<span><span>1</span>1</span>}<span><span>,</span>,</span>\mathrm{<span><span>\&gamma;</span>\&gamma;</span>}<span><span>=</span>=</span>\mathrm{<span><span>1</span>1</span>}\\ <span><span>(</span>(</span>\underset{\mathrm{<span><span>x</span>x</span>}<span><span>=</span>=</span>\mathrm{<span><span>1</span>1</span>}}{\overset{\mathrm{<span><span>16</span>16</span>}}{\mathrm{<span><span>\&Sigma;</span>\&Sigma;</span>}}}{\mathrm{<span><span>g</span>g</span>}}_{\mathrm{<span><span>x</span>x</span>}}<span><span>\&CenterDot;</span>\&CenterDot;</span>{\mathrm{<span><span>y</span>the\; y</span>}}_{\mathrm{<span><span>\&gamma;</span>\&gamma;</span>}<span><span>-</span>-</span>\mathrm{<span><span>x</span>x</span>}}<span><span>)</span>)</span>\mathrm{<span><span>mod</span><figure-callout\; label="mod"\; filenames="A20071008929200181.png"\; state="\{\{state\}\}"><figure-callout\; label="mod"\; filenames="A20071008929200181.png"\; state="\{\{state\}\}">mod</figure-callout></figure-callout></span>}\mathrm{<span><span>2,1</span>2,1</span>}<span><span><</span><</span>\mathrm{<span><span>\&gamma;</span>\&gamma;</span>}<span><span>\&le;</span>\&le;</span>\mathrm{<span><span>B</span>B</span>}\end{array}\right.$

本式中，序列 g＝{g₁，g₂，...，g₁₆}＝{0，0，0，0，0，0，0，0，0，0，1，0，1，1，0，1}。In this formula, the sequence g={g₁ , g₂ ,...,g₁₆ }={0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1 , 0, 1}.

从第一个公式可以看出，在进行比特加扰时，每输入一个信息比特b_im，k，比特加扰模块获得对应的扰码序列比特y_k，两者进行二进制加法操作，就完成了该输入比特的比特加扰操作。全部信息比特顺序输入后，即完成了整个码块的比特加扰操作。It can be seen from the first formula that when bit scrambling is performed, every time an information bit b_im,k is input, the bit scrambling module obtains the corresponding scrambling code sequence bit y_k , and the binary addition operation of the two is completed. A bit scrambling operation for the input bits. After all information bits are input in sequence, the bit scrambling operation of the entire code block is completed.

HSDPA的一个传输时间间隔(TTI)只有2毫秒，通常需要在2毫秒内完成全部符号级处理。串行方式一个节拍只完成一个信息比特的加扰，比特加扰操作时间跟输入比特流长度B成正比。随着HSDPA业务流量的增加，以及需要支持的扇区数的增加，比特加扰处理时间越来越可观，使得留给其他处理步骤的处理时间缩短，增加HSDPA符号级处理实现复杂度。为解决这个问题，比特加扰操作需要采用并行处理结构。A transmission time interval (TTI) of HSDPA is only 2 milliseconds, and it is usually necessary to complete all symbol-level processing within 2 milliseconds. In the serial mode, only one information bit is scrambled in one beat, and the bit scrambling operation time is proportional to the length B of the input bit stream. With the increase of HSDPA service traffic and the number of sectors to be supported, the bit scrambling processing time becomes more and more considerable, which shortens the processing time left for other processing steps and increases the complexity of HSDPA symbol-level processing. To solve this problem, the bit scrambling operation requires a parallel processing structure.

为了方便说明，以下假设加扰操作的并行度为N，且N不小于16。对于N小于16的情况，处理机理跟N不小于16时类似。For the convenience of description, it is assumed that the degree of parallelism of the scrambling operation is N, and N is not less than 16. For the case where N is less than 16, the processing mechanism is similar to that when N is not less than 16.

图1为现有技术中比特加扰并行处理装置的结构示意图。如图1所示，它由两部分组成：扰码序列生成器110和序列加扰器120。当一个传输块的第一个并行数据序列输入时，同时提供一个有效的新数据块指示，使得扰码序列生成器110输出对应的N比特扰码序列y_N*(j-1)+1，y_N*(j-1)+2，y_N*(j-1)+3，...，y_(N*j)(j＝1)，该序列输入到序列加扰器120完成同输入序列的加扰操作。以后每输入一个数据序列，扰码序列生成器均输出相应的扰码序列，输入到序列加扰器完成同输入序列的加扰操作。FIG. 1 is a schematic structural diagram of a bit scrambling parallel processing device in the prior art. As shown in FIG. 1 , it consists of two parts: a scramblingcode sequence generator 110 and asequence scrambler 120 . When the first parallel data sequence of a transmission block is input, a valid new data block indication is provided at the same time, so that the scramblingcode sequence generator 110 outputs the corresponding N-bit scrambling code sequence y_N*(j-1)+1 , y_N*(j-1)+2 , y_N*(j-1)+3 , ..., y_(N*j) (j=1), the sequence is input to the sequence scrambler 120 to complete the same input The scrambling operation of the sequence. After each data sequence is input, the scrambling code sequence generator outputs the corresponding scrambling code sequence, which is input to the sequence scrambler to complete the scrambling operation of the same input sequence.

由于扰码序列y_k可以预先通过3GPP提供的公式计算得到，该序列为一个固定内容的序列，因此，在现在比特加扰并行处理装置中，常常使用一个只读存储器(ROM)来存储全部的扰码序列y_k。对于并行度为N的情况，相位为j的扰码序列y_N*(j-1)+1，y_N*(j-1)+2，y_N*(j-1)+3，...，y_(N*j)存放在该ROM的地址(j-1)。这样输入数据的相位信息j，就可以从ROM中读出得到跟并行数据相对应的扰码序列。Since the scrambling code sequence y_k can be calculated in advance through the formula provided by 3GPP, the sequence is a sequence of fixed content, therefore, in the current bit scrambling parallel processing device, a read-only memory (ROM) is often used to store all Scrambling code sequence y_k . For the case where the degree of parallelism is N, the scrambling sequence y_N*(j-1)+1 , y_N*(j-1)+2 , y_N*(j-1)+3 , .. ., y_(N*j) is stored in the address (j-1) of the ROM. In this way, the phase information j of the input data can be read out from the ROM to obtain the scrambling code sequence corresponding to the parallel data.

对于HSDPA业务，一个传输信道数据块的最大尺寸为28800比特，加上16比特循环冗余校验(CRC)比特，可得到对应的该ROM的最大存储空间需要28816比特。为了节省硬件开销，该ROM也可以用硬件逻辑取代，根据数据序列相位信息实时生成对应的扰码序列。For the HSDPA service, the maximum size of a transport channel data block is 28800 bits, plus 16-bit cyclic redundancy check (CRC) bits, the corresponding maximum storage space of the ROM needs to be 28816 bits. In order to save hardware overhead, the ROM can also be replaced by hardware logic to generate the corresponding scrambling code sequence in real time according to the phase information of the data sequence.

图2为扰码序列生成器硬件逻辑结构示意图。如图2所示，它由两部分组成：16比特相位值存储器210和N比特新相位值生成器220。16比特相位值存储器210用于存储前一次加扰结束后的扰码序列相位信息。每输入一个新的并行数据序列时，旧的扰码序列相位信息从16比特相位值存储器210中输出到N比特新相位值生成器220，得到给该新数据序列对应的扰码序列。由于加扰操作并行度为N，因此，该新相位下的扰码序列一共为N比特，它输出到附图1的序列加扰器120完成对数据序列的加扰操作，同时把它的高16比特反馈到16比特相位值存储器210，存储起来供下一个数据使用。当一个新的传输信道数据块输入时，新数据块指示有效，16比特相位值存储器210输出的16比特值为3GPP规范规定的比特加扰使用的扰码序列y_k的y_-15到y₀等16个值。Fig. 2 is a schematic diagram of the hardware logic structure of the scrambling code sequence generator. As shown in Figure 2, it consists of two parts: 16-bitphase value memory 210 and N-bit newphase value generator 220. The 16-bitphase value memory 210 is used to store the phase information of the scrambling code sequence after the previous scrambling. Whenever a new parallel data sequence is input, the phase information of the old scrambling code sequence is output from the 16-bitphase value memory 210 to the N-bit newphase value generator 220 to obtain the corresponding scrambling code sequence for the new data sequence. Since the parallelism of the scrambling operation is N, the scrambling code sequence under the new phase is N bits in total, and it is output to thesequence scrambler 120 of the accompanyingdrawing 1 to complete the scrambling operation on the data sequence, and simultaneously put its high The 16 bits are fed back to the 16-bitphase value memory 210 and stored for use in the next data. When a new transport channel data block is input, the new data block indication is valid, and the 16-bit value output by the 16-bitphase value memory 210 is y_-15 to_y0 of the scrambling code sequence y_k used for bit scrambling specified in the 3GPP specification and so on for 16 values.

无论使用ROM还是使用硬件逻辑实现扰码序列生成器，当输入数据块尺寸B是N的整数倍时，现有的并行比特加扰装置都可以顺利完成数据比特加扰操作。但是在实际系统中，数据块尺寸B不一定都是N的整数倍。这时，比特加扰前的处理是循环冗余校验(CRC)操作，为了处理方便，通常是在数据块的头部增加无效比特。这样，新的传输信道数据块数据开始进入到比特加扰模块时，第一个输入的N比特数据不一定全部都是需要加扰的有效信息比特，之后的每一次输入的N比特数据才全部都是需要加扰的有效信息比特。设定第一次输入的N比特数据从低比特开始，前M比特都是无效比特，进行比特加扰前需要把这M比特丢弃，使得第(M+1)比特和第一个扰码序列的最低比特即y₁对齐进行加扰。为了达到这个目的，有两种方法：第一种是把数据序列进行移动，第二种是把扰码序列进行移动。Regardless of using ROM or using hardware logic to implement the scrambling code sequence generator, when the input data block size B is an integer multiple of N, the existing parallel bit scrambling device can successfully complete the data bit scrambling operation. However, in an actual system, the data block size B is not necessarily an integer multiple of N. At this time, the processing before bit scrambling is a cyclic redundancy check (CRC) operation. For processing convenience, invalid bits are usually added to the head of the data block. In this way, when the new transmission channel data block data starts to enter the bit scrambling module, the first input N-bit data may not all be effective information bits that need to be scrambled, and each subsequent input N-bit data will be completely scrambled. All are effective information bits that need to be scrambled. It is set that the N-bit data input for the first time starts from the low bit, and the first M bits are all invalid bits, and these M bits need to be discarded before bit scrambling, so that the (M+1)th bit and the first scrambling code sequence The lowest bit of y₁ is aligned for scrambling. In order to achieve this goal, there are two methods: the first is to move the data sequence, and the second is to move the scrambling code sequence.

第一种方法是把数据序列进行移动，保持扰码序列不动。数据序列前M个比特为无效比特，需要从第(M+1)比特起，每N比特组成一个新的序列，输入到序列加扰器。The first method is to move the data sequence and keep the scrambling code sequence unchanged. The first M bits of the data sequence are invalid bits, and it is necessary to form a new sequence for every N bits starting from the (M+1)th bit, and input it to the sequence scrambler.

图3为对输入数据序列进行调整的比特加扰并行处理装置的结构示意图。如图3所示，在输入数据序列输入到序列加扰器320之前，增加了两个部分处理逻辑：一个是输入数据的延迟器330，它实现对数据数据延迟一个节拍的功能；一个是数据选择器340，它根据无效比特M值，从N比特的输入数据和经过延迟的上一个数据序列的N比特中，选择出跟扰码序列相对应的N比特数据。因为M值可以随机的从0、1直到(N-1)中取值，对应表示存在在数据块头部没有无效比特、存在1个无效比特直到存在(N-1)个无效比特(也就是只存在一个有效比特)等N种情况，因此该数据选择器340由N个N选1选择器组成。Fig. 3 is a schematic structural diagram of a bit scrambling parallel processing device for adjusting an input data sequence. As shown in Figure 3, before the input data sequence is input to thesequence scrambler 320, two parts of processing logic are added: one is thedelay device 330 of the input data, which realizes the function of delaying one beat of the data data; Theselector 340 selects the N-bit data corresponding to the scrambling code sequence from the N-bit input data and the delayed N-bits of the previous data sequence according to the invalid bit M value. Because the M value can be randomly selected from 0, 1 until (N-1), correspondingly means that there is no invalid bit at the head of the data block, there is 1 invalid bit until there are (N-1) invalid bits (that is, There are N situations such as only one effective bit), so thedata selector 340 is composed of N N-to-1 selectors.

第二种处理方法是保持输入数据序列不动，对扰码序列进行调整。当在数据块头部存在M个无效比特时，在3GPP规定使用的扰码序列前插入M个任意的比特，扰码序列的第(M+1)个序列值对应y₁。当扰码序列生成器使用ROM实现时，ROM存储的内容固定，仍然需要采用图3中的数据延迟和选择结构，同时获得相邻两个存储地址中的序列值，从这2N个序列值中选择N个值，因此也需要一个N比特的延迟单元和一个由N个N选1选择器组成的数据选择器单元。The second processing method is to keep the input data sequence unchanged and adjust the scrambling code sequence. When there are M invalid bits at the header of the data block, M arbitrary bits are inserted before the scrambling code sequence specified by 3GPP, and the (M+1)th sequence value of the scrambling code sequence corresponds to y₁ . When the scrambling code sequence generator is implemented using ROM, the content stored in the ROM is fixed, and the data delay and selection structure in Figure 3 still needs to be used to obtain the sequence values in two adjacent storage addresses at the same time, from the 2N sequence values To select N values, an N-bit delay unit and a data selector unit consisting of N 1-to-N selectors are also required.

当扰码序列生成器使用硬件逻辑实现时，可以不使用延迟单元，但是由N个N选1选择器组成的数据选择器单元也不可少。When the scrambling code sequence generator is implemented using hardware logic, the delay unit may not be used, but the data selector unit composed of N N-to-1 selectors is also indispensable.

图4为对扰码序列进行调整的扰码序列生成器的硬件逻辑结构示意图。同图2相比，它除了增加了一个数据选择器430外，还必须将图2的N比特新相位值生成器修改为2*N比特新相位值生成器420，其功能是基于提供的16比特扰码序列值，生成其对应的扰码序列相位之后的2*N个比特的扰码序列值。FIG. 4 is a schematic diagram of a hardware logic structure of a scrambling code sequence generator for adjusting the scrambling code sequence. Compared with Fig. 2, except that it has increased adata selector 430, the N bit new phase value generator of Fig. 2 must also be revised to 2*N bit newphase value generator 420, and its function is based on the provided 16 Bit scrambling code sequence value to generate 2*N bit scrambling code sequence value after its corresponding scrambling code sequence phase.

数据选择器430由N个N选1的数据选择器组成，2*N比特新相位值生成器基于提供的16比特扰码序列值，生成其对应的扰码序列相位之后的2*N个比特的扰码序列值，根据数据块前无效比特数M，数据选择器430可以从这2*N个比特的扰码序列值中选择出跟输入并行数据序列相对应的N比特扰码序列值，并把这2*N个比特中的低N比特的高16比特反馈回16比特相位值存储器410存储起来。Thedata selector 430 is composed of N data selectors where N selects 1, and the 2*N bit new phase value generator generates 2*N bits after the corresponding scrambling code sequence phase based on the provided 16-bit scrambling code sequence value The scrambling code sequence value, according to the number M of invalid bits before the data block, thedata selector 430 can select the N-bit scrambling code sequence value corresponding to the input parallel data sequence from the 2*N bit scrambling code sequence values, And the lower N bits and the upper 16 bits of the 2*N bits are fed back to the 16-bitphase value memory 410 for storage.

因此对扰码序列进行调整时，至少仍然需要使用包含N个N选1的数据选择器，使得对应新传输块的第一个并行输入数据，最后输出的N比特扰码序列从低到高，第(M+1)比特开始才是3GPP规范规定的扰码序列y_k，也就是第(M+1)比特为y₁，第(M+2)比特为y₂，依次下去。Therefore, when adjusting the scrambling code sequence, it is still necessary to use at least N data selectors containing N to select 1, so that corresponding to the first parallel input data of the new transmission block, the final output N-bit scrambling code sequence is from low to high, The beginning of the (M+1)th bit is the scrambling code sequence y_k specified in the 3GPP specification, that is, the (M+1)th bit is y₁ , the (M+2)th bit is y₂ , and so on.

因此，当一个传输块尺寸B不是并行度N的整数倍时，无论对输入数据进行处理，还是对扰码序列进行处理，都至少需要一个由N个N选1的数据选择器组成的数据选择单元，存在占用资源多的缺点。Therefore, when the size B of a transmission block is not an integer multiple of the parallelism N, at least one data selector composed of N data selectors with N selected 1 is required no matter whether the input data is processed or the scrambled sequence is processed. Units have the disadvantage of occupying a lot of resources.

发明内容Contents of the invention

本发明提出一种比特加扰并行处理方法和装置，能够解决现有技术中占用资源多的问题。The invention provides a bit scrambling parallel processing method and device, which can solve the problem of occupying many resources in the prior art.

为此，本发明采取以下技术方案：For this reason, the present invention takes the following technical solutions:

一种比特加扰并行处理方法，适用于宽带码分多址系统的高速下行分组接入领域，包括以下步骤：A bit scrambling parallel processing method is applicable to the high-speed downlink packet access field of a wideband code division multiple access system, comprising the following steps:

A、将比特加扰扰码的取值扩展到负无穷大；A. Extend the value of the bit scrambling scrambling code to negative infinity;

B、将16比特相位值存储器中的初始相位值向正无穷大方向移动N减M个相位，并进行存储，其中N为并行数据序列的比特数，M为第一个并行数据序列中位于低比特的无效比特数；B. Move the initial phase value in the 16-bit phase value memory to the positive infinity direction by N minus M phases, and store it, where N is the number of bits in the parallel data sequence, and M is the low bit in the first parallel data sequence the number of invalid bits;

C、输入并行数据序列，利用移动后的比特加扰扰码序列与所述并行数据序列完成加扰操作。C. Input the parallel data sequence, and use the shifted bit scrambling scrambling code sequence and the parallel data sequence to complete the scrambling operation.

步骤A中，所述比特加扰扰码序列符合以下公式：In step A, the bit scrambling scrambling code sequence conforms to the following formula:

${\mathrm{<span><span>y</span>the\; y</span>}}_{\mathrm{<span><span>k</span>k</span>}}<span><span>=</span>=</span>\left\{\begin{array}{c}\mathrm{<span><span>0</span>0</span>}<span><span>,</span>,</span><span><span>-</span>-</span>\mathrm{<span><span>15</span>15</span>}<span><span><</span><</span>\mathrm{<span><span>k</span>k</span>}<span><span><</span><</span>\mathrm{<span><span>1</span>1</span>}\\ \mathrm{<span><span>1</span>1</span>}<span><span>,</span>,</span>\mathrm{<span><span>k</span>k</span>}<span><span>=</span>=</span>\mathrm{<span><span>1</span>1</span>}\\ {\mathrm{<span><span>y</span>the\; y</span>}}_{\mathrm{<span><span>k</span>k</span>}<span><span>-</span>-</span>\mathrm{<span><span>16</span>16</span>}}<span><span>+</span>+</span>{\mathrm{<span><span>y</span>the\; y</span>}}_{\mathrm{<span><span>k</span>k</span>}<span><span>-</span>-</span>\mathrm{<span><span>14</span>14</span>}}<span><span>+</span>+</span>{\mathrm{<span><span>y</span>the\; y</span>}}_{\mathrm{<span><span>k</span>k</span>}<span><span>-</span>-</span>\mathrm{<span><span>13</span>13</span>}}<span><span>+</span>+</span>{\mathrm{<span><span>y</span>the\; y</span>}}_{\mathrm{<span><span>k</span>k</span>}<span><span>-</span>-</span>\mathrm{<span><span>11</span>11</span>}}<span><span>,</span>,</span>\mathrm{<span><span>1</span>1</span>}<span><span><</span><</span>\mathrm{<span><span>k</span>k</span>}<span><span>\&le;</span>\&le;</span>\mathrm{<span><span>B</span>B</span>}\\ {\mathrm{<span><span>y</span>the\; y</span>}}_{\mathrm{<span><span>k</span>k</span>}<span><span>+</span>+</span>\mathrm{<span><span>2</span>2</span>}}<span><span>+</span>+</span>{\mathrm{<span><span>y</span>the\; y</span>}}_{\mathrm{<span><span>k</span>k</span>}<span><span>+</span>+</span>\mathrm{<span><span>3</span>3</span>}}<span><span>+</span>+</span>{\mathrm{<span><span>y</span>the\; y</span>}}_{\mathrm{<span><span>k</span>k</span>}<span><span>+</span>+</span>\mathrm{<span><span>5</span>5</span>}}<span><span>+</span>+</span>{\mathrm{<span><span>y</span>the\; y</span>}}_{\mathrm{<span><span>k</span>k</span>}<span><span>+</span>+</span>\mathrm{<span><span>16</span>16</span>}}<span><span>,</span>,</span>\mathrm{<span><span>k</span>k</span>}<span><span>\&le;</span>\&le;</span><span><span>-</span>-</span>\mathrm{<span><span>15</span>15</span>}\end{array}\right.<span><span>,</span>,</span>$

其中，y_k为所述比特加扰扰码序列y的第k个值，B为比特数据流的比特数。Wherein, y_k is the kth value of the bit-scrambling scrambling code sequence y, and B is the number of bits in the bit data stream.

步骤B进一步包括以下步骤：Step B further comprises the following steps:

B1、所述16比特相位值存储器从低到高依次装载对应比特加扰扰码序列y_-N-15到y_-N的初始相位值；B1. The 16-bit phase value memory is sequentially loaded with initial phase values corresponding to bit scrambling and scrambling code sequences y_-N-15 to y_-N from low to high;

B2、获取第一个并行数据序列中位于低比特的无效比特数M；B2. Obtain the number M of invalid bits located in the lower bits in the first parallel data sequence;

B3、提供N减M个周期的初始相位调整使能有效信号给初始相位调整器；B3. Provide an initial phase adjustment enabling valid signal of N minus M cycles to the initial phase adjuster;

B4、每个周期所述初始相位调整器将所述16比特相位值存储器中对应的比特加扰扰码序列的相位向正无穷大方向移动一位，再输入到所述16比特相位值存储器进行存储；B4. The initial phase adjuster in each cycle moves the phase of the bit scrambling scrambling code sequence corresponding to the 16-bit phase value memory to positive infinity by one bit, and then inputs it to the 16-bit phase value memory for storage;

B5、最后所述16比特相位值存储器存储的相位值对应比特加扰扰码序列的y_-M-15到y_-M。B5. Finally, the phase values stored in the 16-bit phase value memory correspond to y_-M-15 to y_-M of the bit-scrambling scrambling code sequence.

步骤C进一步包括以下步骤：Step C further comprises the following steps:

C1、输入所述并行数据序列；C1. Input the parallel data sequence;

C2、将所述16比特相位值存储器中存储的相位值输出到N比特新相位值生成器，生成比特加扰扰码序列的N比特值；C2. Outputting the phase value stored in the 16-bit phase value memory to an N-bit new phase value generator to generate an N-bit value of a bit-scrambling scrambling code sequence;

C3、将比特加扰扰码序列的N比特值输入到序列加扰器，与所述并行数据序列进行加扰操作。C3. Input the N-bit value of the bit-scrambling scrambling code sequence to the sequence scrambler, and perform a scrambling operation with the parallel data sequence.

还包括以下步骤：Also includes the following steps:

C4、将所述比特加扰扰码序列的N比特值的高16比特存储到所述16比特相位值存储器。C4. Store the upper 16 bits of the N-bit value of the bit-scrambling scrambling code sequence into the 16-bit phase value memory.

一种比特加扰并行处理装置，适用于宽带码分多址系统的高速下行分组接入领域，包括16比特相位值存储器、初始相位调整器、N比特新相位值生成器和序列加扰器，其中N为并行数据的比特数，所述16比特相位值存储器用于接收新数据块指示输入信号、序列相位信息输入信号、初始相位调整器输出的信号并向所述初始相位调整器和所述N比特新相位值生成器发送扰码相位信息，所述初始相位调整器用于接收初始相位调整使能信号和所述N比特新相位值生成器的高位比特信号，所述N比特新相位值生成器用于输出N比特的新扰码序列相位值到所述序列加扰器，所述序列加扰器用于接收并行数据序列并输出加扰后的数据。A bit scrambling parallel processing device, suitable for the high-speed downlink packet access field of wideband code division multiple access system, including 16-bit phase value memory, initial phase adjuster, N-bit new phase value generator and sequence scrambler, Where N is the number of bits of parallel data, the 16-bit phase value memory is used to receive the new data block indication input signal, the sequence phase information input signal, the signal output by the initial phase adjuster and send the signal to the initial phase adjuster and the The N-bit new phase value generator sends scrambling code phase information, and the initial phase adjuster is used to receive the initial phase adjustment enable signal and the high-order bit signal of the N-bit new phase value generator, and the N-bit new phase value generates The device is used to output the N-bit new scrambling code sequence phase value to the sequence scrambler, and the sequence scrambler is used to receive the parallel data sequence and output the scrambled data.

所述初始相位调整器包括16个二选一数据选择器和1个4输入的二进制加法器。The initial phase adjuster includes 16 binary data selectors and a 4-input binary adder.

采用了本发明的技术方案，在传输块尺寸B不是并行度N的整数倍时，通过在扰码序列前插入部分多余相位的方式，使得不再需要原有装置中对齐数据或者对齐扰码序列时必须使用的N个N选1的数据选择器单元，而只需要16个二选一的选择器，从而降低比特加扰并行处理结构的复杂度。Adopting the technical solution of the present invention, when the transmission block size B is not an integer multiple of the parallelism N, by inserting some redundant phases before the scrambling code sequence, it is no longer necessary to align data or align the scrambling code sequence in the original device N data selector units that must be used when selecting 1 from N must be used, but only 16 selectors that select one from two are required, thereby reducing the complexity of the bit scrambling parallel processing structure.

附图说明Description of drawings

图1是现有技术中比特加扰并行处理装置的结构示意图；FIG. 1 is a schematic structural diagram of a bit scrambling parallel processing device in the prior art;

图2是扰码序列生成器硬件逻辑结构示意图；Fig. 2 is a schematic diagram of the hardware logic structure of the scrambling code sequence generator;

图3为对输入数据序列进行调整的比特加扰并行处理装置的结构示意图；FIG. 3 is a schematic structural diagram of a bit scrambling parallel processing device for adjusting an input data sequence;

图4是对扰码序列进行调整的扰码序列生成器的硬件逻辑结构示意图；FIG. 4 is a schematic diagram of a hardware logic structure of a scrambling code sequence generator for adjusting the scrambling code sequence;

图5是本具体实施方式的比特加扰并行处理装置结构示意图；FIG. 5 is a schematic structural diagram of a bit scrambling parallel processing device in this specific embodiment;

图6是16比特相位值存储器和初始相位调整器之间信号交互的结构示意图；Fig. 6 is a structural schematic diagram of signal interaction between the 16-bit phase value memory and the initial phase adjuster;

图7是本具体实施方式中比特加扰并行处理的流程图。Fig. 7 is a flow chart of parallel processing of bit scrambling in this specific embodiment.

具体实施方式Detailed ways

下面结合附图，并通过具体实施方式对本发明的技术方案作进一步说明。The technical solutions of the present invention will be further described below in conjunction with the accompanying drawings and through specific implementation methods.

为了方便说明，本具体实施方式中仍假设加扰操作的并行度为N，且N不小于16。对于N小于16的情况，处理机理跟N不小于16时类似。For convenience of description, it is still assumed in this embodiment that the degree of parallelism of the scrambling operation is N, and N is not less than 16. For the case where N is less than 16, the processing mechanism is similar to that when N is not less than 16.

图5为本具体实施方式的比特加扰并行处理装置结构示意图。如图5所示，本具体实施方式中的比特加扰并行处理装置包括一个16比特相位值存储器520、一个初始相位调整器510、一个N比特新相位值生成器530、一个序列加扰器540。16比特相位值存储器520存在3个输入信号：新数据块指示输入信号、序列相位信息j输入信号、初始相位调整器输出的16比特信号，16比特相位值存储器520输出16比特的旧扰码相位信息到初始相位调整器510和N比特新相位值生成器530。N比特新相位值生成器530从16比特相位值存储器520接收16比特的旧扰码相位信息，输出N比特的新的扰码序列相位值，输出到序列加扰器540，同时N比特新相位值生成器530输出的N比特的新的扰码序列相位值的高16比特还输出到初始相位调整器。序列加扰器540从外部输入并行数据和接收N比特新相位值生成器530输出的N比特新扰码序列相位值。初始相位调整器510有初始相位调整使能信号和N比特新相位值生成器的输出端的高16比特信号两个输入，其输出信号连接作为16比特相位值存储器520的一个输入。FIG. 5 is a schematic structural diagram of a bit scrambling parallel processing device in this specific embodiment. As shown in Figure 5, the bit scrambling parallel processing device in this specific embodiment includes a 16-bitphase value memory 520, aninitial phase adjuster 510, an N-bit newphase value generator 530, and asequence scrambler 540 There are 3 input signals in the 16-bit phase value memory 520: the new data block indicates the input signal, the sequence phase information j input signal, the 16-bit signal output by the initial phase adjuster, and the 16-bitphase value memory 520 outputs the old scrambling code of 16 bits Phase information toinitial phase adjuster 510 and N-bit newphase value generator 530 . N-bit newphase value generator 530 receives 16-bit old scrambling code phase information from 16-bitphase value memory 520, outputs N-bit new scrambling code sequence phase value, and outputs it to sequencescrambler 540, and at the same time, N-bit new phase The upper 16 bits of the N-bit new scrambling code sequence phase value output by thevalue generator 530 are also output to the initial phase adjuster. Thesequence scrambler 540 inputs parallel data from the outside and receives the N-bit new scrambled code sequence phase value output by the N-bit newphase value generator 530 . Theinitial phase adjuster 510 has two inputs, the initial phase adjustment enable signal and the upper 16-bit signal of the output end of the N-bit new phase value generator, and its output signal is connected as an input of the 16-bitphase value memory 520 .

图6为16比特相位值存储器和初始相位调整器之间信号交互的结构示意图。如图6所示，图中以点划线为界，左侧部分为初始相位调整器510，右侧部分为16比特相位值存储器520。16比特相位值存储器520的比特#0直接输出，其他各个比特除了输出外，还反馈回初始相位调整器510的低一比特存储空间前的数据选择器，连接到该数据选择器的上方输入端口。比如比特#14，除了输出外，还反馈回初始相位调整器，连接到其中的比特#13的二选一的数据新选择器的上方数据输入端。FIG. 6 is a schematic structural diagram of signal interaction between the 16-bit phase value memory and the initial phase adjuster. As shown in Figure 6, the dotted line is used as the boundary in the figure, the left part is theinitial phase adjuster 510, and the right part is the 16-bitphase value memory 520. Thebit #0 of the 16-bitphase value memory 520 is directly output, and the other In addition to being output, each bit is also fed back to the data selector in front of the lower one-bit storage space of theinitial phase adjuster 510, and connected to the upper input port of the data selector. For example,bit #14, in addition to the output, is also fed back to the initial phase adjuster, which is connected to the upper data input terminal of the two-to-one data new selector ofbit #13.

初始相位调整器510由16个二选一的数据选择器511和一个4输入的二进制加法器512组成。4输入二进制加法器512的输出连接到比特#15的二选一数据选择器511的上方输入端，其输入为16比特相位值存储器520的存储空间#0、#2、#3、#5的输出数据。比特#15的数据选择器的下方输入数据为N比特的新的扰码序列相位值的高16比特中的比特#0，上方输入信号为4输入二进制加法器512的输出信号；其他各个比特的数据选择器下方输入数据为N比特的新的扰码序列相位值的高16比特的对应比特，上方输入数据为16比特相位值存储器520输出信号的对应的高一比特，比如比特#0的数据选择器的下方输入数据为16比特相位值存储器520输出信号的比特#1，依次下去，比特#14的数据选择器的下方输入数据为16比特相位值存储器520输出信号的比特#15。Theinitial phase adjuster 510 is composed of 16binary selectors 511 and a 4-inputbinary adder 512 . The output of the 4-inputbinary adder 512 is connected to the upper input end of the two-choice data selector 511 of thebit #15, and its input is thestorage space #0, #2, #3, #5 of the 16-bitphase value memory 520 Output Data. The lower input data of the data selector of bit #15 isbit #0 in the upper 16 bits of the new scrambling code sequence phase value of N bits, and the upper input signal is the output signal of 4 inputbinary adder 512; The input data below the data selector is the corresponding upper 16 bits of the new N-bit scrambling code sequence phase value, and the upper input data is the corresponding upper one bit of the output signal of the 16-bitphase value memory 520, such as the data ofbit #0 The lower input data of the selector isbit #1 of the output signal of the 16-bitphase value memory 520 , and in turn, the lower input data of the data selector of bit #14 is bit #15 of the output signal of the 16-bitphase value memory 520 .

初始相位调整器510的每个二选一数据选择器的功能为：当输入信号初始相位调整使能有效时，选择上方端口输入的数据，也就是16比特相位值存储器520中对应高一比特存储器的输出数据；当初始相位调整使能无效时，选择下方端口输入的数据，也就是从N比特新相位值生成器530的输出信号的对应比特。The function of each two-to-one data selector of theinitial phase adjuster 510 is: when the initial phase adjustment of the input signal is enabled to be valid, select the data input from the upper port, that is, the corresponding higher bit memory in the 16-bitphase value memory 520 output data; when the initial phase adjustment enable is invalid, select the data input from the lower port, that is, the corresponding bit of the output signal from the N-bit newphase value generator 530 .

图7为本具体实施方式中比特加扰并行处理的流程图。如图7所示，比特加扰并行处理方法包括以下步骤：Fig. 7 is a flow chart of parallel processing of bit scrambling in this specific embodiment. As shown in Figure 7, the bit scrambling parallel processing method includes the following steps:

步骤601、将比特加扰扰码的取值扩展到负无穷大。Step 601. Extend the value of the bit scrambling scrambling code to negative infinity.

即3GPP标准组织定义的比特加扰扰码序列yk扩展为：That is, the bit scrambling scrambling code sequence yk defined by the 3GPP standard organization is extended as:

${\mathrm{<span><span>y</span>the\; y</span>}}_{\mathrm{<span><span>k</span>k</span>}}<span><span>=</span>=</span>\left\{\begin{array}{c}\mathrm{<span><span>0</span>0</span>}<span><span>,</span>,</span><span><span>-</span>-</span>\mathrm{<span><span>15</span>15</span>}<span><span><</span><</span>\mathrm{<span><span>k</span>k</span>}<span><span><</span><</span>\mathrm{<span><span>1</span>1</span>}\\ \mathrm{<span><span>1</span>1</span>}<span><span>,</span>,</span>\mathrm{<span><span>k</span>k</span>}<span><span>=</span>=</span>\mathrm{<span><span>1</span>1</span>}\\ {\mathrm{<span><span>y</span>the\; y</span>}}_{\mathrm{<span><span>k</span>k</span>}<span><span>-</span>-</span>\mathrm{<span><span>16</span>16</span>}}<span><span>+</span>+</span>{\mathrm{<span><span>y</span>the\; y</span>}}_{\mathrm{<span><span>k</span>k</span>}<span><span>-</span>-</span>\mathrm{<span><span>14</span>14</span>}}<span><span>+</span>+</span>{\mathrm{<span><span>y</span>the\; y</span>}}_{\mathrm{<span><span>k</span>k</span>}<span><span>-</span>-</span>\mathrm{<span><span>13</span>13</span>}}<span><span>+</span>+</span>{\mathrm{<span><span>y</span>the\; y</span>}}_{\mathrm{<span><span>k</span>k</span>}<span><span>-</span>-</span>\mathrm{<span><span>11</span>11</span>}}<span><span>,</span>,</span>\mathrm{<span><span>1</span>1</span>}<span><span><</span><</span>\mathrm{<span><span>k</span>k</span>}<span><span>\&le;</span>\&le;</span>\mathrm{<span><span>B</span>B</span>}\\ {\mathrm{<span><span>y</span>the\; y</span>}}_{\mathrm{<span><span>k</span>k</span>}<span><span>+</span>+</span>\mathrm{<span><span>2</span>2</span>}}<span><span>+</span>+</span>{\mathrm{<span><span>y</span>the\; y</span>}}_{\mathrm{<span><span>k</span>k</span>}<span><span>+</span>+</span>\mathrm{<span><span>3</span>3</span>}}<span><span>+</span>+</span>{\mathrm{<span><span>y</span>the\; y</span>}}_{\mathrm{<span><span>k</span>k</span>}<span><span>+</span>+</span>\mathrm{<span><span>5</span>5</span>}}<span><span>+</span>+</span>{\mathrm{<span><span>y</span>the\; y</span>}}_{\mathrm{<span><span>k</span>k</span>}<span><span>+</span>+</span>\mathrm{<span><span>16</span>16</span>}}<span><span>,</span>,</span>\mathrm{<span><span>k</span>k</span>}<span><span>\&le;</span>\&le;</span><span><span>-</span>-</span>\mathrm{<span><span>15</span>15</span>}\end{array}\right.<span><span>.</span>.</span>$

步骤602、装载扰码序列y_k的y_-N-15到y_-N对应的初始相位值到16比特相位值存储器。Step 602: Load the initial phase values corresponding to y_-N-15 to y_-N of the scrambling code sequence y_k into the 16-bit phase value memory.

一个新的传输块数据输入前，输入信号新数据块指示置为有效电平，16比特相位值存储器从低到高依次装载初始相位值为y_k的y_-N-15到y_-N，即y_-N-15存放在最低比特，比特#0；y_-N-14存放在比特#1；依次下去；y_-N-1存放在比特#14，y_-N存放在最高比特，比特#15。Before a new transmission block data is input, the new data block indication of the input signal is set to an active level, and the 16-bit phase value memory_is sequentially loaded with initial phase values y_-N-15 to y_-N from low to high, namely y_-N-15 is stored in the lowest bit,bit #0; y_-N-14 is stored inbit #1; in turn; y_-N-1 is stored inbit #14, y_-N is stored in the highest bit,bit #15 .

步骤603、获取第一个并行数据序列中位于低比特的无效比特数M。Step 603. Obtain the number M of invalid bits located in the lower bits in the first parallel data sequence.

在数据块尺寸B不是并行度N的倍数，输入的第一个并行数据低M比特不是需要的信息比特时，M就是第一个并行数据序列中位于低比特的无效比特数。When the data block size B is not a multiple of the parallelism N, and the low M bits of the first parallel data input are not required information bits, M is the number of invalid bits located in the low bits in the first parallel data sequence.

步骤604、根据无效比特数M，通过初始相位调整器将16比特相位值存储器内存储的扰码序列相位值向正无穷大方向移动N-M位。Step 604: According to the number M of invalid bits, the phase value of the scrambling code sequence stored in the 16-bit phase value memory is shifted by N-M bits in the direction of positive infinity through the initial phase adjuster.

提供N-M个周期宽度的初始相位调整使能有效信号，该使能信号使得初始相位调整器中的各个二选一数据选择器选择从上方输入的信号，也就是从16比特相位值存储器中对应高一比特存储器的输出数据，比特#15的数据选择器则选择4输入二进制加法器的输出数据，这样，每个周期结束时，16比特相位值存储器内存储的扰码序列相位值同该周期开始时相比，向正无穷大方向移动了1位。Provide an initial phase adjustment enabling valid signal of N-M cycle width, which enables each data selector in the initial phase adjuster to select the signal input from above, that is, the corresponding high value from the 16-bit phase value memory. The output data of a bit memory, the data selector of bit #15 selects the output data of 4 input binary adders, so that at the end of each cycle, the phase value of the scrambling code sequence stored in the 16-bit phase value memory is the same as the beginning of the cycle Compared with time, it is moved by 1 bit in the direction of positive infinity.

本步骤结束时，初始相位调整使能置为无效信号，16比特相位值存储器内存储的扰码序列16比特的相位值从低到高比特对应为比特加扰扰码序列y_k的y_-M-15到y_-M。At the end of this step, the initial phase adjustment can be set as an invalid signal, and the phase value of the 16-bit scrambling code sequence stored in the 16-bit phase value memory corresponds to the y_-M- of the bit scrambling scrambling code sequence y_k from low to high bits₁₅ to y_-M .

步骤605、依次顺序输入数据块的各个并行数据完成比特加扰并行处理操作。Step 605, sequentially input each parallel data of the data block to complete bit scrambling parallel processing operation.

每输入一个并行数据，16比特相位值存储器输出16比特的相位信息给N比特相位值生成器生成加扰扰码序列的N比特值，再输入到序列加扰器，完成同输入的并行数据的加扰操作。Each time a parallel data is input, the 16-bit phase value memory outputs 16-bit phase information to the N-bit phase value generator to generate the N-bit value of the scrambling scrambling code sequence, and then input to the sequence scrambler to complete the addition of the same input parallel data disturbing operation.

步骤606、将比特加扰扰码序列的N比特值的高位比特存储到16比特相位值存储器。Step 606: Store the upper bits of the N-bit value of the bit-scrambling scrambling code sequence into a 16-bit phase value memory.

比特加扰扰码序列的高16比特反馈输入到初始相位调整器，这时初始相位调整使能信号为无效信号，初始相位调整器各个比特的数据选择器选择的对应比特，存入16比特相位值存储器的对应存储空间中。The high 16-bit feedback of the bit scrambling scrambling code sequence is input to the initial phase adjuster. At this time, the initial phase adjustment enable signal is an invalid signal, and the corresponding bit selected by the data selector of each bit of the initial phase adjuster is stored in the 16-bit phase value. in the corresponding storage space of the memory.

通过本具体实施方式，在传输块尺寸B不是并行度N的整数倍时，通过在扰码序列前插入部分多余相位的方式，使得不再需要原有装置中对齐数据或者对齐扰码序列时必须使用的N个N选1的数据选择器单元，而只需要16个二选一的选择器，从而降低比特加扰并行处理结构的复杂度。Through this specific implementation mode, when the transport block size B is not an integer multiple of the parallelism N, by inserting some redundant phases before the scrambling code sequence, it is no longer necessary to align data or align the scrambling code sequence in the original device. N number of data selector units for selecting one from N are used, and only 16 selectors for selecting one from two are needed, thereby reducing the complexity of the bit scrambling parallel processing structure.

以上所述，仅为本发明较佳的具体实施方式，但本发明的保护范围并不局限于此，本领域的技术人员在本发明所揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应该以权利要求的定义为准。The above is only a preferred embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Those skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention. All should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be defined by the claims.

Claims (7)

1, a kind of bit scramble parallel processing method is applicable to that the high speed downlink packet of broadband CDMA system inserts the field, it is characterized in that, may further comprise the steps:

A, the value of bit scramble scrambler is expanded to minus infinity;

B, the initial phase place value in the 16 bit phase value memories is moved N to the positive infinity direction subtract M phase place, and store, wherein N is the bit number of parallel data sequence, and M is for being positioned at the invalid bit number of low bit in first parallel data sequence;

C, input parallel data sequence utilize bit scramble scrambler sequence and described parallel data sequence after moving to finish the scrambling operation.

2, a kind of bit scramble parallel processing method according to claim 1 is characterized in that, in the steps A, described bit scramble scrambler sequence meets following formula:

$y_k=\left\{\begin{array}{c}0,-15<k<1\\ 1,k=1\\ y_{k-16}+y_{k-14}+y_{k-13}+y_{k-11},1<k\&le;B,\\ y_{k+2}+y_{k+3}+y_{k+5}+y_{k+16},k\&le;-15\end{array}\right.$

Wherein, y_kBe k the value of described bit scramble scrambler sequence y, B is the bit number of bit data flow.

3, a kind of bit scramble parallel processing method according to claim 1 and 2 is characterized in that step B further may further comprise the steps:

B1, described 16 bit phase value memories load corresponding bit scrambling scrambler sequence y from low to high successively_-N-15To y_-NThe initial phase place value;

B2, obtain the invalid bit number M that is positioned at low bit in first parallel data sequence;

B3, the initial phase adjustment that provides N to subtract M cycle enable useful signal to the initial phase adjuster;

B4, described initial phase adjuster of each cycle move one with the phase place of bit scramble scrambler sequence corresponding in the described 16 bit phase value memories to the positive infinity direction, are input to described 16 bit phase value memories again and store;

The y of the phase value corresponding bit scrambling scrambler sequence of B5, last described 16 bit phase value memory stores_-M-15To y_-M

4, a kind of bit scramble parallel processing method according to claim 1 is characterized in that step C further may further comprise the steps:

C1, the described parallel data sequence of input;

C2, the phase value of storing in the described 16 bit phase value memories is outputed to the new phase value maker of N bit, generate the N bit value of bit scramble scrambler sequence;

C3, the N bit value of bit scramble scrambler sequence is input to the sequence scrambler, carries out the scrambling operation with described parallel data sequence.

5, a kind of bit scramble parallel processing method according to claim 4 is characterized in that, and is further comprising the steps of:

C4, with high 16 bit storage of the N bit value of described bit scramble scrambler sequence to described 16 bit phase value memories.

6, a kind of bit scramble parallel processing apparatus, the high speed downlink packet that is applicable to broadband CDMA system inserts the field, it is characterized in that, comprise 16 bit phase value memories, the initial phase adjuster, new phase value maker of N bit and sequence scrambler, wherein N is the bit number of parallel data, described 16 bit phase value memories are used to receive new data block indication input signal, the sequence phase information input signal, the signal of initial phase adjuster output also sends scrambling code phase information to described initial phase adjuster and the new phase value maker of described N bit, described initial phase adjuster is used to receive the high order bit signal that initial phase is adjusted enable signal and the new phase value maker of described N bit, the new phase value maker of described N bit is used to export the new scrambler sequence phase value of N bit to described sequence scrambler, the data after described sequence scrambler is used to receive the parallel data sequence and exports scrambling.

7, a kind of scrambling parallel processing apparatus according to claim 6 is characterized in that, described initial phase adjuster comprises the binary adder of 16 alternative data selectors and 14 input.

Images