CN101018097B - Scrambling Code Generator - Google Patents
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Abstract
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Translated fromChinese技术领域technical field
本发明涉及一种扰码生成装置，尤其涉及一种用于数字通信系统中加扰和解扰信号的扰码生成装置。The invention relates to a scrambling code generating device, in particular to a scrambling code generating device for scrambling and descrambling signals in a digital communication system.
背景技术Background technique
在数字通信系统的信号处理中，加扰和解扰技术是非常重要和关键的技术手段。加扰和解扰技术简单来说就是与扰码相乘的操作，其中主要是利用了扰码的相关特性。因此扰码的生成很关键，扰码在数字通信系统中经常赋予许多重要的功能，例如，在异步通信系统中提供同步支持，地无线通信系统中抵抗无线信道对传输信号的干扰，在码分多址系统中区分不同的基站和用户，在同步数字体系/同步光纤网络(Synchronous Digital Hierarchy/Synchronous OpticalNetwork，SDH/SONET)中使从接收到的数据信号中恢复出精准的时钟，从而避免数据信息的丢失或错误。下面以用于SDH/SONET的扰码生成装置为例，来说明现有的扰码生成装置存在的缺点。In signal processing of digital communication systems, scrambling and descrambling techniques are very important and key technical means. The scrambling and descrambling technology is simply the operation of multiplying the scrambling code, which mainly utilizes the correlation characteristics of the scrambling code. Therefore, the generation of scrambling codes is very important. Scrambling codes often endow many important functions in digital communication systems, such as providing synchronization support in asynchronous communication systems, resisting interference from wireless channels to transmission signals in wireless communication systems, In the multiple access system, different base stations and users are distinguished, and in Synchronous Digital Hierarchy/Synchronous Optical Network (SDH/SONET), the precise clock is recovered from the received data signal, thereby avoiding data information missing or wrong. The following uses a scrambling code generating device for SDH/SONET as an example to illustrate the shortcomings of existing scrambling code generating devices.
SDH/SONET中最基本、最重要的模块信号是STM-1(Synchronous TransferMode，同步转移模式)信号，线速率为155.520Mbit/s，再将其同步复用、字节间插后得到更高级的STM-N信号，STM-N信号的线速率是N×155.520Mbit/s；这些信号在传输过程中都是按比特BIT串行传送信号，但没有传送本网络节点的时钟信号。各网络节点的接收端所需的数据接收及后续处理的时钟都是从接收到的数据信号中恢复出来的。根据常用的时钟与数据恢复(Clock and DataRecovery，CDR)原理，时钟恢复依靠数据信号的变化沿完成，如果接收到的数据流中有长0或长1序列出现，则按该原理恢复出的时钟不再精准，用这样恢复出来的时钟处理数据会导致数据信息的丢失或错误，因此为了保证在接收端能精准地进行数据接收和时钟提取，必须杜绝传输的数据流中有长0或长1序列出现。The most basic and important module signal in SDH/SONET is STM-1 (Synchronous Transfer Mode, synchronous transfer mode) signal, the line rate is 155.520Mbit/s, and then it is synchronously multiplexed and byte interleaved to obtain a more advanced STM-N signal, the line rate of STM-N signal is N×155.520Mbit/s; these signals are transmitted serially by bit BIT during the transmission process, but the clock signal of the network node is not transmitted. Clocks for data reception and subsequent processing required by the receiving end of each network node are all recovered from the received data signals. According to the commonly used clock and data recovery (Clock and Data Recovery, CDR) principle, clock recovery depends on the change edge of the data signal to complete, if there is a sequence of long 0 or long 1 in the received data stream, the clock recovered according to this principle It is no longer accurate, and processing data with such a recovered clock will lead to loss or error of data information. Therefore, in order to ensure accurate data reception and clock extraction at the receiving end, it is necessary to prevent long 0 or long 1 in the transmitted data stream sequence appears.
为此，国际电报电话咨询委员会(CCITT，即现在的国际电信联盟电信标准化部门ITU-T)在SDH/SONET协议中规定：传送的数据流中必须包含足够的定时信息以便网络节点能够根据数据流实现时钟的提取，要满足该要求，必须使数据流中避免有长0或长1序列出现。合适的数据流可以通过加扰来实现。For this reason, the Consultative Committee for International Telegraph and Telephone (CCITT, now ITU-T, the International Telecommunications Union's telecommunication standardization department) stipulates in the SDH/SONET protocol: the transmitted data stream must contain enough timing information so that the network nodes can follow the data stream To realize the extraction of the clock, to meet this requirement, it is necessary to prevent long 0 or long 1 sequences from appearing in the data stream. Proper data flow can be achieved by scrambling.
CCITT在ITU-T G.707/Y.1322协议中还规定，STM-N(N＝1，4，16，64，256……)扰码生成装置的扰码序列生成多项式为：1+X6+X7。CCITT also stipulates in the ITU-T G.707/Y.1322 protocol that the STM-N (N=1, 4, 16, 64, 256...) scrambling code generator polynomial is: 1+X6 +X7 .
现有的扰码生成装置通常用由7级D触发器组成的反馈式移位寄存器来实现，其反馈结构由生成多项式决定。STM-N信号的串行时钟加到每一级触发器的时钟输入端。在发送端，扰码生成装置生成的扰码序列与串行数据逐位以帧 头为起点按顺序进行异或运算，完成数据加扰过程；同理在接收端，同样的扰码序列与接收到的串行数据进行同样的运算，则恢复出真实数据，完成数据的解扰过程。The existing scrambling code generating device is usually implemented by a feedback shift register composed of 7-level D flip-flops, and its feedback structure is determined by a generator polynomial. The serial clock of the STM-N signal is added to the clock input end of each stage flip-flop. At the sending end, the scrambling code sequence generated by the scrambling code generating device and the serial data are subjected to XOR operation bit by bit starting from the frame header in order to complete the data scrambling process; similarly at the receiving end, the same scrambling code sequence and the receiving Perform the same operation on the received serial data to recover the real data and complete the data descrambling process.
请参阅图1，其是现有的帧同步加解扰器的电路原理图。该帧同步加解扰器包括扰码生成装置和一个异或门，该扰码生成装置包括7个用于移位的D触发器D0～D6，D触发器D1、D2…D6的输入端分别与上一个D触发器D0、D1…D5的输出端相连；该异或门用以实现对D触发器D5和D6的输出端进行异或运算，运算结果反馈至D触发器D0的输入端，D触发器D6的输出即为扰码生成装置输出的扰码序列，7个触发器D0～D6在STM-N的串行bit时钟作用下产生周期性的扰码序列，产生出来的扰码bit与输入的STM-N的bit异或得出扰码后的数据，该扰码数据可以保证避免长0或长1序列出现。Please refer to FIG. 1 , which is a schematic circuit diagram of an existing frame synchronization scrambler and descrambler. The frame synchronization descrambler includes a scrambling code generating device and an exclusive OR gate. The scrambling code generating device includes 7 D flip-flops D0~D6 for shifting. The input terminals of D flip-flops D1, D2...D6 are respectively Connected to the output terminals of the previous D flip-flop D0, D1...D5; the XOR gate is used to perform XOR operation on the output terminals of D flip-flops D5 and D6, and the operation result is fed back to the input end of D flip-flop D0, The output of D flip-flop D6 is the scrambling code sequence output by the scrambling code generating device. The 7 flip-flops D0~D6 generate periodic scrambling code sequences under the action of the serial bit clock of STM-N, and the generated scrambling code bits XOR with the bit of the input STM-N to obtain scrambled data, the scrambled data can guarantee to avoid long 0 or long 1 sequence.
由于扰码多项式提供的是串行算法：按STM-N的bit时钟，在实际应用中，输入的STM-N数据是并行数据的，因此必须把扰码算法改成并行算法，即一个STM-N字节输入时钟下，扰码生成装置提供M bit(M为STM-N的字节数据位宽)扰码数据与输入的M bit STM-N数据进行异或。现有技术实现做法都是由该串行算法推算出并行算法。对于STM-1业务，其字节数据位宽为8，因此需要一个8位宽的并行扰码算法。Since the scrambling polynomial provides a serial algorithm: according to the bit clock of STM-N, in practical applications, the input STM-N data is parallel data, so the scrambling algorithm must be changed into a parallel algorithm, that is, an STM-N Under the input clock of N bytes, the scrambling code generating device provides M bit (M is the byte data bit width of STM-N) scrambling code data and performs XOR with the input M bit STM-N data. The implementation methods in the prior art all calculate the parallel algorithm from the serial algorithm. For the STM-1 service, its byte data bit width is 8, so an 8-bit wide parallel scrambling algorithm is required.
并行算法的推导可以根据串行算法方法，如表1所示，假如8位扰码寄存器为Q00～Q07，按G.707协议要求，扰码生成装置的七个触发器初始值为“1111111”，8拍串行bit时钟之后就得到并行8位扰码寄存器的初始值为“11111110”，即Q6该列值；而之后并行扰码寄存器值将是Q07～Q00的函数：The derivation of the parallel algorithm can be based on the serial algorithm method, as shown in Table 1, if the 8-bit scrambling code registers are Q00~Q07, according to the requirements of the G.707 protocol, the initial value of the seven flip-flops of the scrambling code generating device is "1111111" , after 8 beats of the serial bit clock, the initial value of the parallel 8-bit scrambling code register is "11111110", that is, the column value of Q6; and then the parallel scrambling code register value will be a function of Q07~Q00:
表1Table 1
表2为并行扰码函数表：“^”表示逻辑异或，N表示当前时刻值，N-1表示前一时钟寄存器的值。Table 2 is a table of parallel scrambling code functions: "^" indicates logical XOR, N indicates the current time value, and N-1 indicates the value of the previous clock register.
表2Table 2
如果STM-N的位宽是16bit位，则并行扰码算法就必须按16bit进行推导，假设16bit扰码生成装置分别为Q17～Q10，Q07～Q00，则Qnm＝F(Q0k)，其中n＝1或0，m＝0～7；k＝0～7，即16位扰码生成装置都是Q07～Q00的函数。依次类推，对于STM-256，目前逻辑芯片一般采用155Mhzx256bit位宽，因此，并行推导公式必须推导出并行256位宽的算法，按8比特进行分组，需要32组，设为Q317～Q310，...Q07～Q00，每个寄存器都是Q07～Q00的函数。If the bit width of STM-N is 16 bits, the parallel scrambling algorithm must be derived according to 16 bits. Assume that the 16-bit scrambling code generating devices are Q17~Q10, Q07~Q00 respectively, then Qnm=F(Q0k), where n= 1 or 0, m=0~7; k=0~7, that is, the 16-bit scrambling code generator is a function of Q07~Q00. By analogy, for STM-256, the current logic chip generally adopts 155Mhzx256bit bit width. Therefore, the parallel derivation formula must derive a parallel 256-bit wide algorithm. Grouping by 8 bits requires 32 groups, set as Q317~Q310, .. .Q07～Q00, each register is a function of Q07～Q00.
从上述可知，现有的扰码生成装置产生的扰码序列对STM-N并行数据进行加解扰时，其必须根据STM-N的字节数据位宽的变化分别推导出适应本位宽要求的并行扰码公式，当一个设计需要同时兼容不同位宽的扰码，比如兼容STM-1和STM-16时，逻辑设计就必须同时包含两个扰码算法，因此，现有的扰码生成装置不能重用于多个应用场合，增加了逻辑设计规模。It can be seen from the above that when the scrambling code sequence generated by the existing scrambling code generating device performs scrambling and descrambling on STM-N parallel data, it must deduce the corresponding bit width according to the change of the byte data bit width of STM-N respectively. Parallel scrambling code formula, when a design needs to be compatible with scrambling codes of different bit widths at the same time, such as compatible with STM-1 and STM-16, the logic design must include two scrambling code algorithms at the same time, therefore, the existing scrambling code generation device Cannot be reused in multiple applications, increasing the logic design size.
由于目前常用的都是STM-1，STM-4，STM-16，而STM-64产品应用比较少，对于STM-256，市场上相关芯片更少，几乎没有，因此，对于STM-256的并行256位宽的推导将是很繁琐的一项工作，因此，现有的扰码生成装置对高位宽推导的工作量极大，易出错。Since STM-1, STM-4, and STM-16 are commonly used at present, and STM-64 products are rarely used, for STM-256, there are fewer related chips on the market, and there are almost no. Therefore, for STM-256 parallel The derivation of the 256-bit width will be a very cumbersome task. Therefore, the existing scrambling code generation device has a huge workload for deriving the high bit width and is prone to errors.
从并行算法上看，并行算法的每个寄存器都是最低8bit寄存器的函数，位宽越宽，低8bit的逻辑负载越大，因此逻辑芯片的时钟速度就越低。因此，现有的扰码生成装置对逻辑工作时钟有限制；比如STM-256，要求工作时钟为155Mhz，在并行扰码算法下就可能实现不了。From the perspective of the parallel algorithm, each register of the parallel algorithm is a function of the lowest 8-bit register. The wider the bit width, the greater the logic load of the lower 8 bits, so the clock speed of the logic chip will be lower. Therefore, the existing scrambling code generation device has limitations on the logical working clock; for example, STM-256 requires a working clock of 155Mhz, which may not be realized under the parallel scrambling code algorithm.
由于现有的扰码生成装置中采用了大量的异或门，当扰码位宽越宽时，这些异或门的逻辑资源耗费很大，因此，当扰码位宽越宽，现有的扰码生成装置的资源占用就越多。Since a large number of XOR gates are used in the existing scrambling code generation device, when the bit width of the scrambling code is wider, the logic resources of these XOR gates are consumed a lot. Therefore, when the bit width of the scrambling code is wider, the existing The resource occupation of the scrambling code generating device is more.
发明内容Contents of the invention
本发明所要解决的技术问题在于提供一种对于不同字节数据位宽的信号进行加扰和解扰不必重新推导，很容易使逻辑工作时钟工作在很高的频率上的扰码生成装置。The technical problem to be solved by the present invention is to provide a scrambling code generating device which can easily make the logic working clock work at a very high frequency without deriving scrambling and descrambling signals with different byte data bit widths.
为解决上述技术问题，本发明所采用的技术方案是：提供一种扰码生成装置，其采用一个位宽为L的移位寄存器，其中L＝M×X，M为扰码序列的生成多项式对应的扰码序列周期，X的取值必须满足L大于或等于N，N为所需加/解扰的数据的位宽，M、N和X均为正整数。In order to solve the above-mentioned technical problems, the technical solution adopted by the present invention is to provide a scrambling code generating device, which uses a shift register with a bit width of L, where L=M×X, and M is the generator polynomial of the scrambling code sequence For the corresponding scrambling sequence period, the value of X must satisfy that L is greater than or equal to N, where N is the bit width of the data to be added/descrambled, and M, N, and X are all positive integers.
上述移位寄存器包括L个D触发器D0～DL-1和L个多路选择器M0～ML-1，该L个多路选择器M0～ML-1的输出端分别对应与L个D触发器D0～DL-1的输入端连接，该L个D触发器D0～DL-1的输出端分别对应与L个多路选择器M0～ML-1的第一输入端连接，该N个D触发器D0～ DN-1的输出端还分别对应与N个多路选择器ML-N～ML-1的第二输入端连接，该L-N个D触发器DN～DL-1的输出端还分别对应与L-N个多路选择器M0～ML-N-1 的第二输入端连接，该L个多路选择器M0～ML-1的使能端连接在一起，由加扰使能来控制该L个多路选择器M0～ML-1的工作，该L个D触发器D0～DL-1的时钟端连接在一起。The above-mentioned shift register includes L D flip-flops D0 ~DL-1 and L multiplexers M0 ~ML-1 , and the output terminals of the L multiplexers M0 ~ML-1 are respectively Correspondingly connected to the input terminals of L D flip-flops D0 ~DL-1 , the output terminals of the L D flip-flops D0 ~DL-1 respectively correspond to the L multiplexers M0 ~ML- 1 , the output terminals of the N D flip-flops D0 ~ DN-1 are respectively connected to the second input terminals of the N multiplexers MLN ~ ML-1 , and the LN The output terminals of the D flip-flops DN ～DL-1 are respectively connected to the second input terminals of the LN multiplexers M0 ～MLN-1 , and the L multiplexers M0 ～ML The enable terminals of-1 are connected together, and the operation of the L multiplexers M0 ~ML-1 is controlled by the scrambling enable, and the clock terminals of the L D flip-flops D0 ~DL-1 connected together.
本发明的有益效果是：由于本发明的扰码生成装置采用一个位宽为L的移位寄存器，其中L＝M×X，M为扰码序列的生成多项式对应的扰码序列周期，X的取值必须满足L大于或等于N，N为所需加/解扰的数据的位宽，M、N和X均为正整数，因此本发明的扰码生成装置对于所有扰码序列的生成多项式来说，加扰算法都是采用同一个原理实现，不用费太多的推导工作量，特别对于位宽很多的情况下，而且可以很容易保证设计的正确性；且对不同的所需加/解扰的数据的位宽，特别当位宽小于扰码序列的生成多项式对应的扰码序列周期时，可以用一个设计，通过修改移位的位宽参数可以很容易适应各种位宽情况，不必为每种位宽重新推导格式；而且采用移位寄存器的方式也很容易使逻辑工作时钟工作在很高的频率上；另外，由于本发明采用的移位寄存器包括L个D触发器D0～DL-1和L个多路选择器M0～ML-1，不需要作异或运算的处理，因此使用的组合资源很少，且代码量很小，可以节省工作时间。The beneficial effects of the present invention are: since the scrambling code generating device of the present invention adopts a shift register with a bit width of L, wherein L=M×X, M is the scrambling code sequence period corresponding to the generating polynomial of the scrambling code sequence, and X The value must satisfy that L is greater than or equal to N, N is the bit width of the data to be added/descrambled, and M, N, and X are all positive integers, so the scrambling code generating device of the present invention has a generator polynomial for all scrambling code sequences Generally speaking, the scrambling algorithm is implemented using the same principle, without much derivation workload, especially for the case of a large bit width, and it is easy to ensure the correctness of the design; and for different required additions/ The bit width of the descrambled data, especially when the bit width is smaller than the scrambling code sequence period corresponding to the generator polynomial of the scrambling code sequence, can use a design, which can easily adapt to various bit width situations by modifying the shifted bit width parameter, It is not necessary to re-deduce the format for each kind of bit width; and the mode of adopting the shift register is also easy to make the logic operating clock work at a very high frequency; in addition, since the shift register adopted in the present invention includes L D flip-flops D0 ～DL-1 and L multiplexers M0 ～ML-1 do not need to be processed by XOR operation, so the combined resources used are few, and the amount of code is small, which can save working time.
附图说明Description of drawings
图1是现有的帧同步加解扰器的电路原理图；Fig. 1 is the circuit schematic diagram of existing frame synchronization descrambler;
图2是本发明扰码生成装置具体实施例的扰码算法的示意图；FIG. 2 is a schematic diagram of a scrambling algorithm of a specific embodiment of the scrambling code generating device of the present invention;
图3是本发明扰码生成装置具体实施例的扰码序列的示意图；Fig. 3 is a schematic diagram of a scrambling code sequence of a specific embodiment of the scrambling code generating device of the present invention;
图4是采用本发明扰码生成装置的帧同步并行加解扰器具体实施例的逻辑方框图；Fig. 4 is a logical block diagram of a specific embodiment of a frame synchronous parallel scrambling and descrambling device using the scrambling code generating device of the present invention;
图5是采用本发明扰码生成装置的帧同步并行加解扰器具体实施例的电路原理图。Fig. 5 is a schematic circuit diagram of a specific embodiment of a frame synchronous parallel scrambler and descrambler using the scrambling code generating device of the present invention.
具体实施方式Detailed ways
下面以采用本发明的扰码生成装置对STM-N(N＝1，4，16，64，256)并行数据进行扰码为例，来对本发明的扰码生成装置作详细的说明。The scrambling code generating device of the present invention will be described in detail below by using the scrambling code generating device of the present invention to scramble STM-N (N=1, 4, 16, 64, 256) parallel data as an example.
要对STM-256并行数据进行扰码则必须要产生256bit的扰码序列。根据扰码序列的生成多项式1+X6+X7可知该扰码序列是一个周期为127的伪随机序列，如果把周期127编号为0～126，则扰码算法就是如图2所示。扰码序列每127bit后重复1次，取2个周期254bit加上第3个周期的0和1与输入的STM-256并行数据的256bit进行异或，第3个周期的126之后又开始新的0～126的序列，因此可以把扰码序列看成是一个首尾相接的，3个周期为127的伪随机序列合在一块的周而复始的数据块，如图3所示。该数据块位宽为127x3＝381。由于扰码序列的生成多项式1+X6+X7的127位值是已知的，因此该数据块的每bit值也是已知的，当第一次加扰时，取该数据块的前面256bit与输入的256bit进行 异或，然后如图3所示方向转动256bit，则第二次从起点起取256bit，就是第二次所需要的并行的256bit的加扰值，该值与输入的第二个256bit数据相异或就得到第二个并行加扰后的数据，依次类推。To scramble the STM-256 parallel data, a 256-bit scrambling sequence must be generated. According to the
具体逻辑方框图如图4所示，本发明的扰码生成装置采用一个位宽为381的移位寄存器，其初值可以通过扰码序列的生成多项式得出。扰码产生工作原理如下：每个STM-256并行时钟周期，取移位寄存器的低256bit与输入的STM-256的256bit并行数据异或实现扰码，同时移位寄存器进行移位，移位方式为移位寄存器的高125bit赋值给移位寄存器的低125bit，低256bit值赋值给移存器的高256bit，从而实现256bit的移位。The specific logic block diagram is shown in Fig. 4. The scrambling code generating device of the present invention adopts a shift register with a bit width of 381, and its initial value can be obtained through the generator polynomial of the scrambling code sequence. The working principle of scrambling code generation is as follows: every STM-256 parallel clock cycle, the lower 256bit of the shift register is XORed with the input 256bit parallel data of STM-256 to realize the scrambling code, and the shift register is shifted at the same time. The high 125bit of the shift register is assigned to the low 125bit of the shift register, and the low 256bit value is assigned to the high 256bit of the shift register, thereby realizing a 256bit shift.
请参阅图5，是以256bit的并行扰码为例的，采用本发明扰码生成装置的帧同步并行加解扰器的电路原理图，该帧同步并行加解扰器包括扰码生成装置和256个异或门，该扰码生成装置包括381个D触发器D0～D380和381个多路选择器M0～M380。该381个多路选择器M0～M380均为2选1选择器，该381个多路选择器M0～M380的输出端分别对应与381个D触发器D0～D380的输入端连接。该381个D触发器D0～D380的输出端分别对应与381个多路选择器M0～M380的0输入端连接，该256个D触发器D0～D255的输出端还分别对应与256个多路选择器M125～M380的1输入端连接，该125个D触发器D256～D380的输出端还分别对应与125个多路选择器M0～M124的1输入端连接。该381个多路选择器M0～M380的使能端连接在一起，由加扰使能来控制该381个多路选择器M0～M380的工作。该381个D触发器D0～D380带有置位功能。381个D触发器D0～D380的时钟端连接在一起，由STM-256的并行时钟来控制，在每个STM-256并行时钟周期，取该256个D触发器D0～D255的输出通过数据总线与由总线输入的256位STM-256并行数据经256个异或门异或后输出扰码后的数据，该扰码数据可以保证避免长0或长1序列出现。Please refer to Fig. 5, taking the 256-bit parallel scrambling code as an example, the circuit principle diagram of the frame synchronous parallel descrambling device using the scrambling code generating device of the present invention, the frame synchronous parallel descrambling device includes a scrambling code generating device and There are 256 XOR gates, and the scrambling code generating device includes 381 D flip-flops D0-D380 and 381 multiplexers M0-M380. The 381 multiplexers M0-M380 are all 2-to-1 selectors, and the output terminals of the 381 multiplexers M0-M380 are respectively connected to the input terminals of the 381 D flip-flops D0-D380. The output terminals of the 381 D flip-flops D0-D380 are respectively connected to the 0 input terminals of the 381 multiplexers M0-M380, and the output terminals of the 256 D flip-flops D0-D255 are respectively corresponding to the 256 multiplexers The 1 input terminals of the selectors M125-M380 are connected, and the output terminals of the 125 D flip-flops D256-D380 are respectively connected to the 1 input terminals of the 125 multiplexers M0-M124. The enabling ports of the 381 multiplexers M0-M380 are connected together, and the scrambling enable controls the operation of the 381 multiplexers M0-M380. The 381 D flip-flops D0-D380 have a setting function. The clock terminals of 381 D flip-flops D0~D380 are connected together and controlled by the parallel clock of STM-256. In each STM-256 parallel clock cycle, the output of the 256 D flip-flops D0~D255 is passed through the data bus With the 256-bit STM-256 parallel data input by the bus, the scrambled data is output after 256 exclusive OR gates, and the scrambled data can guarantee to avoid long 0 or long 1 sequences.
在加扰开始时，381个触发器D0～D380置位3个周期的扰码值(每个周期具体值可以根据扰码多项式推算出来，共127bit，3个周期为381bit)，在加扰使能信号作用下(假设高有效)，则D触发器D255～D0共256个触发器的当前值按顺序赋值给D380～D125共256个触发器；D触发器Q380～Q256共125个触发器的当前值按顺序赋值给D124～D0触发器共125个触发器；上面的操作是在256bit的并行数据时钟作用下。下一个周期若加扰使能有效，则重复执行。当扰码使能无效时，每个触发器保持当前值。用于并行扰码的数据则从触发器D255～D0输出中取，用来与输入数据进行异或。At the beginning of scrambling, 381 flip-flops D0~D380 set the scrambling code value for 3 cycles (the specific value of each cycle can be calculated according to the scrambling code polynomial, 127 bits in total, and 3 cycles are 381 bits). Under the action of energy signal (assuming high effective), the current value of 256 flip-flops in D255~D0 will be assigned to 256 flip-flops in D380~D125 in sequence; 125 flip-flops in Q380~Q256 The current value is assigned to D124-D0 flip-flops in sequence, a total of 125 flip-flops; the above operation is under the action of 256bit parallel data clock. If the scrambling enable is valid in the next cycle, it will be executed repeatedly. Each flip-flop holds the current value when the scramble enable is disabled. The data used for parallel scrambling is taken from the output of flip-flops D255-D0, and is used for XOR with the input data.
如果输入数据是待扰码的数据，则输出就是扰码后的数据，相当于扰码过程；如果输入数据是扰码过的数据，输出相当是解扰码后的数据，相当于解扰码过程。If the input data is the data to be scrambled, the output is the scrambled data, which is equivalent to the scrambling process; if the input data is the scrambled data, the output is the descrambled data, which is equivalent to the descrambling process process.
另外，若对STM-64并行数据进行扰码，则采用本发明扰码生成装置的帧同步并行加解扰器包括扰码生成装置和64个异或门，该扰码生成装置包括127个D触发器D0～D126和127个多路选择器M0～M126。该127个多路选择器M0～M126均为2选1选择器，该127个多路选择器M0～M126的输出端分别对应与 127个D触发器D0～D126的输入端连接。该127个D触发器D0～D126的输出端分别对应与127个多路选择器M0～M126的0输入端连接，该64个D触发器D0～D63的输出端还分别对应与64个多路选择器M63～M126的1输入端连接，该63个D触发器D64～D126的输出端还分别对应与63个多路选择器M0～M62的1输入端连接。该127个多路选择器M0～M126的使能端连接在一起，由加扰使能来控制该127个多路选择器M0～M126的工作。该127个D触发器D0～D126带有置位功能。127个D触发器D0～D126的时钟端连接在一起，由STM-64的并行时钟来控制，在每个STM-64并行时钟周期，取该64个D触发器D0～D63的输出通过数据总线与由总线输入的64位STM-64并行数据经64个异或门异或后输出扰码后的数据。In addition, if STM-64 parallel data is scrambled, the frame synchronous parallel descrambler using the scrambling code generating device of the present invention includes a scrambling code generating device and 64 XOR gates, and the scrambling code generating device includes 127 D Flip-flops D0-D126 and 127 multiplexers M0-M126. The 127 multiplexers M0-M126 are all 2-to-1 selectors, and the output terminals of the 127 multiplexers M0-M126 are respectively connected to the input terminals of the 127 D flip-flops D0-D126. The output terminals of the 127 D flip-flops D0-D126 are respectively connected to the 0 input terminals of the 127 multiplexers M0-M126, and the output terminals of the 64 D flip-flops D0-D63 are respectively corresponding to the 64 multiplexer The 1 input terminals of the selectors M63-M126 are connected, and the output terminals of the 63 D flip-flops D64-D126 are respectively connected to the 1 input terminals of the 63 multiplexers M0-M62. The enabling ports of the 127 multiplexers M0-M126 are connected together, and the scrambling enable controls the work of the 127 multiplexers M0-M126. The 127 D flip-flops D0-D126 have a setting function. The clock terminals of 127 D flip-flops D0~D126 are connected together and controlled by the parallel clock of STM-64. In each STM-64 parallel clock cycle, the output of the 64 D flip-flops D0~D63 is passed through the data bus With the 64-bit STM-64 parallel data input by the bus, the scrambled data is output after being XORed by 64 XOR gates.
若对STM-16并行数据进行扰码，则采用本发明扰码生成装置的帧同步并行加解扰器包括扰码生成装置和16个异或门，该扰码生成装置包括127个D触发器D0～D126和127个多路选择器M0～M126。该127个多路选择器M0～M126均为2选1选择器，该127个多路选择器M0～M126的输出端分别对应与127个D触发器D0～D126的输入端连接。该127个D触发器D0～D126的输出端分别对应与127个多路选择器M0～M126的0输入端连接，该16个D触发器D0～D15的输出端还分别对应与16个多路选择器M111～M126的1输入端连接，该111个D触发器D16～D126的输出端还分别对应与111个多路选择器M0～M110的1输入端连接。该127个多路选择器M0～M126的使能端连接在一起，由加扰使能来控制该127个多路选择器M0～M126的工作。该127个D触发器D0～D126带有置位功能。127个D触发器D0～D126的时钟端连接在一起，由STM-16的并行时钟来控制，在每个STM-16并行时钟周期，取该16个D触发器D0～D15的输出通过数据总线与由总线输入的16位STM-16并行数据经16个异或门异或后输出扰码后的数据。If the STM-16 parallel data is scrambled, the frame synchronous parallel descrambler using the scrambling code generating device of the present invention includes a scrambling code generating device and 16 XOR gates, and the scrambling code generating device includes 127 D flip-flops D0～D126 and 127 multiplexers M0～M126. The 127 multiplexers M0-M126 are all 2-to-1 selectors, and the output terminals of the 127 multiplexers M0-M126 are respectively connected to the input terminals of the 127 D flip-flops D0-D126. The output terminals of the 127 D flip-flops D0-D126 are respectively connected to the 0 input terminals of the 127 multiplexers M0-M126, and the output terminals of the 16 D flip-flops D0-D15 are respectively corresponding to the 16 multiplexer The 1 input terminals of the selectors M111-M126 are connected, and the output terminals of the 111 D flip-flops D16-D126 are respectively connected to the 1 input terminals of the 111 multiplexers M0-M110. The enabling ports of the 127 multiplexers M0-M126 are connected together, and the scrambling enable controls the work of the 127 multiplexers M0-M126. The 127 D flip-flops D0-D126 have a setting function. The clock terminals of 127 D flip-flops D0~D126 are connected together and controlled by the parallel clock of STM-16. In each STM-16 parallel clock cycle, the output of the 16 D flip-flops D0~D15 is passed through the data bus With the 16-bit STM-16 parallel data input by the bus, the scrambled data is output after 16 XOR gates are XORed.
若对STM-4并行数据进行扰码，则采用本发明扰码生成装置的帧同步并行加解扰器包括扰码生成装置和4个异或门，该扰码生成装置包括127个D触发器D0～D126和127个多路选择器M0～M126。该127个多路选择器M0～M126均为2选1选择器，该127个多路选择器M0～M126的输出端分别对应与127个D触发器D0～D126的输入端连接。该127个D触发器D0～D126的输出端分别对应与127个多路选择器M0～M126的0输入端连接，该4个D触发器D0～D3的输出端还分别对应与4个多路选择器M123～M126的1输入端连接，该123个D触发器D4～D126的输出端还分别对应与123个多路选择器M0～M122的1输入端连接。该127个多路选择器M0～M126的使能端连接在一起，由加扰使能来控制该127个多路选择器M0～M126的工作。该127个D触发器D0～D126带有置位功能。127个D触发器D0～D126的时钟端连接在一起，由STM-4的并行时钟来控制，在每个STM-4并行时钟周期，取该4个D触发器D0～D3的输出通过数据总线与由总线输入的4位STM-4并行数据经4个异或门异或后输出扰码后的数据。If the STM-4 parallel data is scrambled, the frame synchronous parallel descrambler using the scrambling code generating device of the present invention includes a scrambling code generating device and 4 XOR gates, and the scrambling code generating device includes 127 D flip-flops D0～D126 and 127 multiplexers M0～M126. The 127 multiplexers M0-M126 are all 2-to-1 selectors, and the output terminals of the 127 multiplexers M0-M126 are respectively connected to the input terminals of the 127 D flip-flops D0-D126. The output terminals of the 127 D flip-flops D0-D126 are respectively connected to the 0 input terminals of the 127 multiplexers M0-M126, and the output terminals of the 4 D flip-flops D0-D3 are respectively corresponding to the 4 multiplexers The 1 input terminals of the selectors M123-M126 are connected, and the output terminals of the 123 D flip-flops D4-D126 are respectively connected to the 1 input terminals of the 123 multiplexers M0-M122. The enabling ports of the 127 multiplexers M0-M126 are connected together, and the scrambling enable controls the work of the 127 multiplexers M0-M126. The 127 D flip-flops D0-D126 have a setting function. The clock terminals of 127 D flip-flops D0~D126 are connected together and controlled by the parallel clock of STM-4. In each STM-4 parallel clock cycle, the output of the 4 D flip-flops D0~D3 is passed through the data bus With the 4-bit STM-4 parallel data input from the bus, the scrambled data is output after being XORed by 4 XOR gates.
若对STM-1并行数据进行扰码，则采用本发明扰码生成装置的帧同步并行 加解扰器包括扰码生成装置和1个异或门，该扰码生成装置包括127个D触发器D0～D126和127个多路选择器M0～M126。该127个多路选择器M0～M126均为2选1选择器，该127个多路选择器M0～M126的输出端分别对应与127个D触发器D0～D126的输入端连接。该127个D触发器D0～D126的输出端分别对应与127个多路选择器M0～M126的0输入端连接，该D触发器D0的输出端与多路选择器M126的1输入端连接，该126个D触发器D1～D126的输出端还分别对应与126个多路选择器M0～M125的1输入端连接。该127个多路选择器M0～M126的使能端连接在一起，由加扰使能来控制该127个多路选择器M0～M126的工作。该127个D触发器D0～D126带有置位功能。127个D触发器D0～D126的时钟端连接在一起，由STM-1的并行时钟来控制，在每个STM-1并行时钟周期，取D触发器D0的输出与输入的1位STM-1并行数据经1个异或门异或后输出扰码后的数据。If the STM-1 parallel data is scrambled, the frame synchronous parallel descrambler using the scrambling code generating device of the present invention includes a scrambling code generating device and an exclusive OR gate, and the scrambling code generating device includes 127 D flip-flops D0～D126 and 127 multiplexers M0～M126. The 127 multiplexers M0-M126 are all 2-to-1 selectors, and the output terminals of the 127 multiplexers M0-M126 are respectively connected to the input terminals of the 127 D flip-flops D0-D126. The output terminals of the 127 D flip-flops D0-D126 are respectively connected to the 0 input terminals of the 127 multiplexers M0-M126, and the output terminals of the D flip-flop D0 are connected to the 1-input terminals of the multiplexer M126, The output terminals of the 126 D flip-flops D1-D126 are also correspondingly connected to the 1 input terminals of the 126 multiplexers M0-M125. The enabling ports of the 127 multiplexers M0-M126 are connected together, and the scrambling enable controls the work of the 127 multiplexers M0-M126. The 127 D flip-flops D0-D126 have a setting function. The clock terminals of 127 D flip-flops D0~D126 are connected together and controlled by the parallel clock of STM-1. In each STM-1 parallel clock cycle, the output of D flip-flop D0 and the input 1-bit STM-1 After the parallel data is XORed by an XOR gate, the scrambled data is output.
对于STM-N(N＝1，4，64)，一般实际应用位宽最大为64bits，因此，移位寄存器采用127bit位宽，每次从移位寄存器取出用于扰码的位宽即为STM-N的数据位宽，同时执行移位操作方式同STM-256举例一样，只是所移动的bit位等于STM-N数据的位宽。For STM-N (N=1, 4, 64), the general actual application bit width is up to 64 bits, therefore, the shift register adopts a 127-bit bit width, and the bit width used for scrambling is taken out from the shift register every time is STM -N data bit width, and the shift operation method is the same as the STM-256 example, except that the shifted bit is equal to the bit width of STM-N data.
另外，对STM-N(N＝1，4，64)并行数据进行扰码时，本发明的扰码生成装置的D触发器和多路选择器的数量也可为254、381等，对STM-256并行数据进行扰码时，本发明的扰码生成装置的D触发器和多路选择器的数量也可为508、635等，总之本发明的扰码生成装置的D触发器和多路选择器的数量必须大于所需加/解扰的数据的位宽，同时还必须是所采用的扰码序列的生成多项式对应的扰码序列周期的正整数倍。上述的D触发器也可由RS触发器或JK触发器变换成具D触发器功能的模块来实现。In addition, when scrambling STM-N (N=1, 4, 64) parallel data, the number of D flip-flops and multiplexers of the scrambling code generating device of the present invention can also be 254, 381, etc., for STM When 256 parallel data are scrambled, the number of D flip-flops and multiplexers of the scrambling code generating device of the present invention can also be 508, 635, etc. In a word, the D flip-flops and multiplexers of the scrambling code generating device of the present invention The number of selectors must be greater than the bit width of the data to be scrambled/descrambled, and must be a positive integer multiple of the period of the scrambling code sequence corresponding to the generator polynomial of the scrambling code sequence used. The above-mentioned D flip-flop can also be realized by transforming RS flip-flop or JK flip-flop into a module with D flip-flop function.
本发明的扰码生成装置适用于所有扰码序列的生成多项式，例如g(x)＝x9 +x8+X5+x4+1、g(x)＝X9+X4+1、g(x)＝1+x14+x15等等，每个扰码序列的生成多项式对应的扰码序列都具有周期，例如扰码序列的生成多项式g(x)＝X9+X4+1，其所对应的扰码序列的周期为511。The scrambling code generation device of the present invention is applicable to generator polynomials of all scrambling code sequences, such as g(x)=x9 +x8 +X5 +x4 +1, g(x)=X9 +X4 +1, g(x)=1+x14 +x15 and so on, the scrambling code sequence corresponding to the generator polynomial of each scrambling code sequence has a period, for example, the generator polynomial of the scrambling code sequence g(x)=X9 +X4 + 1, the period of the corresponding scrambling code sequence is 511.
综上所述，可作出如下的推导：本发明的扰码生成装置采用一个位宽为L的移位寄存器，其中L＝M×X，M为扰码序列的生成多项式对应的扰码序列周期，X的取值必须满足L大于或等于N，N为所需加/解扰的数据的位宽，M、N和X均为正整数。该移位寄存器包括L个D触发器D0～DL-1和L个多路选择器M0～ML-1，该L个多路选择器M0～ML-1的输出端分别对应与L个D触发器D0～DL-1的输入端连接，该L个D触发器D0～DL-1的输出端分别对应与L个多路选择器M0～ML-1的第一输入端连接，该N个D触发器D0～DN-1的输出端还分别对应与N个多路选择器ML-N～ML-1的第二输入端连接，该L-N个D触发器DN～DL-1的输出端还分别对应与L-N个多路选择器M0～ML-N-1的第二输入端连接，该L个多路选择器M0～ML-1的使能端连接在一起，由加扰使能来控制该L个多路选择器M0～ML-1的工作，该L个D触发器D0～DL-1的时钟端连接在一起。In summary, the following derivation can be made: the scrambling code generation device of the present invention uses a shift register with a bit width of L, where L=M×X, and M is the period of the scrambling code sequence corresponding to the generator polynomial of the scrambling code sequence , the value of X must satisfy that L is greater than or equal to N, N is the bit width of the data to be scrambled/descrambled, and M, N, and X are all positive integers. The shift register includes L D flip-flops D0 to DL-1 and L multiplexers M0 to ML-1 , and the output terminals of the L multiplexers M0 to ML-1 are respectively Correspondingly connected to the input terminals of L D flip-flops D0 ~DL-1 , the output terminals of the L D flip-flops D0 ~DL-1 respectively correspond to the L multiplexers M0 ~ML- 1 , the output terminals of the N D flip-flops D0 ~DN-1 are respectively connected to the second input terminals of the N multiplexers MLN ~ML-1 , and the LN The output terminals of the D flip-flops DN ～DL-1 are respectively connected to the second input terminals of the LN multiplexers M0 ～MLN-1 , and the L multiplexers M0 ～ML The enable terminals of-1 are connected together, and the operation of the L multiplexers M0 ~ML-1 is controlled by the scrambling enable, and the clock terminals of the L D flip-flops D0 ~DL-1 connected together.
本发明的扰码生成装置对于所有扰码序列的生成多项式来说，加扰算法都 是采用同一个原理实现，不用费太多的推导工作量，特别对于位宽很多的情况下，而且可以很容易保证设计的正确性；In the scrambling code generation device of the present invention, for all generator polynomials of scrambling code sequences, the scrambling algorithm is realized by using the same principle, which does not require too much derivation workload, especially in the case of a large bit width, and can be easily It is easy to ensure the correctness of the design;
本发明的扰码生成装置实现的代码量很小，也可以节省工作时间。The amount of code realized by the scrambling code generating device of the present invention is very small, and the working time can also be saved.
本发明的扰码生成装置不需要作异或运算的处理，因此使用的组合资源很少。采用移位寄存器的方式也很容易使逻辑工作时钟工作在很高的频率上。The scrambling code generating device of the present invention does not need to perform XOR operation, so the combined resources used are few. It is also easy to make the logic working clock work at a very high frequency by using the shift register.
本发明的扰码生成装置对不同的所需加/解扰的数据的位宽，特别当位宽小于扰码序列的生成多项式对应的扰码序列周期时，可以用一个设计，通过修改移位的位宽参数可以很容易适应各种位宽情况，不必为每种位宽重新推导格式。The scrambling code generating device of the present invention can use one design for different bit widths of data to be added/descrambled, especially when the bit width is smaller than the scrambling code sequence period corresponding to the generator polynomial of the scrambling code sequence, by modifying the shift The bitwidth parameter of can be easily adapted to various bitwidth situations without having to re-deduce the format for each bitwidth.
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