CN101006406A - Method and device for intelligently setting dead time - Google Patents

Abstract

An apparatus for setting a dead time between on-times of two series switches within a power converter circuit connected to a supply voltage, the apparatus comprising: a circuit for monitoring a power converter circuit parameter and providing an output corresponding to the circuit parameter; a memory addressed by a signal related to the output of the monitoring circuit, the memory having stored therein values related to the dead time and associated with the value of the circuit parameter; a processor for providing a memory output associated with a value of the circuit parameter to set a dead time corresponding to the value stored in the memory; and a dead time implementation stage for implementing the dead time in dependence upon the output of the memory.

Description

The method and apparatus of intelligent set Dead Time

Related application

That the application requires to submit on July 6th, 2004, name is called " Intelligent Dead Time ", sequence number is No.60/585, the right of priority of 678 U.S. Provisional Patent Application, its whole disclosures are hereby expressly incorporated by to be quoted.

Background technology

The present invention relates to power supply and relate in particular to the electric pressure converter that adopts two controlled switchs, one of them switch is as synchronous rectifier work.Described two switches are controlled as two switches usually and never open simultaneously.Provide " Dead Time " to prevent the cross-conduction in dc voltage source between the opening time of two switches, wherein said two switches are connected between the described dc voltage source.

In the low-voltage output translator of voltage-dropping type (Buck), booster type (boost), inverse-excitation type (fly back) and positive activation type various topologys such as (forward), extensively adopted synchronous rectifier.By adopting switch mosfet substituted for silicon or Schottky (Schottky) diode, can reduce rectifier loss significantly.

For synchronous converter, keeping the non-overlapped cycle (Dead Time) is very important with the excessive cross-conduction that prevents gauge tap and synchronous rectifier switch.The additional conduction loss that is used for producing during significantly overlapping power loss penalty and the Dead Time is compared much higher.

However, the Dead Time loss is extremely important, particularly when the converter frequency of operation increases.The synchronous buck converter that use has a following characteristic is as example:

Frequency of operation=1Mhz

Input voltage=12 volt

Output voltage=1 volt

Output current=40 ampere

Synchro switch opening resistor=3 milliohms

The synchro switch body diode is the forward operating voltage (VF@40A)=0.8 volt of 40 ampere-hours at electric current

The real-time power loss is 4.8 watts when synchro switch FET opens, and when the body diode conducting is only arranged is 32 watts.Under these conditions, be converted into the power attenuation of additional 27mW at the Dead Time of per nanosecond.Two toggle edges in each cycle of 20ns Dead Time cause in the synchro switch 1.088 watts additional loss respectively, and the loss of this element has been increased by 20%.Use the schottky diode in parallel this numeral can be reduced 30% to 40%, but can bring additional cost and number of elements with described MOSFET.

In addition, in case the body diode conducting of synchro switch is easy to be subjected to the influence of inversion recovery cycle and associated charge, this must eliminate in connection.This is equivalent to cross-conduction and has caused added losses among the control FET.

The present invention is conceived to make the minimum power losses related with Dead Time.This is by Dead Time is minimized with the conduction loss of reduction body diode and in some cases by allowing the conducting of FET switch cross to realize to eliminate the loss that thereby the body diode conducting is eliminated with oppositely recovery is relevant fully.

The technology that has multiple reduction Dead Time at present.Comprise:

The adjustable dead band time.Thereby regulate during the design phase Dead Time under all working condition and the whole process that realizes all elements that described Dead Time relates to avoid cross-conduction in changing.It may be important that semi-conductive process changes, and circuit may be worked in wide in range scope.Therefore, when realize not having when intersection by the worst case element under worst case conditions, the Dead Time under optimal cases element and the condition is too much.The power consumption that causes excess waste like this.

The adaptive dead zone time.The adaptive dead zone time is a kind of improvement with respect to the adjustable deadband time, wherein along with condition changing and when the component variation one by one the carrying out of unit regulate simultaneously.This is logic control in essence, and the grid of one of them switch (gate) is detected at the grid of another switch and is prevented from opening before closing.To the eye, this has solved problem, but does not in fact have.Logic control and the grid of power switch self charged and discharge need the limited time cycle.In actual conditions, caused the Dead Time about the 10ns to 30ns when T.T. is each switch transition in each cycle of 20ns to 60ns like this.

The prediction Dead Time.The subject matter of adaptive dead zone time is to switch the FET required time of opening and closing.Thereby the prediction Dead Time has solved this defective until it near zero to reduce Dead Time by using phaselocked loop or some other ring.Seemed to provide a lot of advantages identical like this, but be to use control loop to have attendant disadvantages with the present invention.Since this method depend on certain kind control loop so that Dead Time to be set, in this ring, also exist association really immediately between.In transient condition, when described ring tries to settle into new steady state (SS) cross-conduction may take place.Fixing Dead Time to be avoiding cross-conduction if programmed in described ring, and then most of described times are can be than minimum Dead Time bigger and dependent loss is more.Under any circumstance, described ring solution depends on some electrical conditions and the loss related with Dead Time minimized arbitrarily.Test result shows that this method can not produce minimum possible power consumption.

Minimise power consumption Dead Time (PLMDT).This technology has all advantages of the present invention, and the optimum dead zone time of " memory " various conditions of work is not provided with except it.For power work, this optimization needs for a long time-tens of milliseconds.This means that in quick load transient environments, the PLMDT operation can not be caught up with power source change.Averaging allows the PLMDT circuit to find the mean value of under large-scale load current " optimum " of optimum work.Effect is fine like this, but still can not obtain accurately suitable Dead Time to each electric current.To be the applicant submit to February 16 in 2005 PLMDT, the theme of the patented claim IR-2673 that determines of end, U. S.application number 11/058,969 simultaneously, and its full content is incorporated into this as quoting.

Fig. 4 has shown the converter circuit that comprises transistor Q1 and Q2, and wherein PLMDT is used to be provided with Dead Time.The variation of the duty factor ofpwm signal 10 is used to the estimating power loss andchanges.Multiplication module 22 is used to by pwm signal modulation V_IN(supply voltage of switch Q1 and Q2) produces the signal DxV that is proportional to duty factor_INThis signal produces slow variable signal through low-pass filter 24, if the output voltage when this slow variable signal equals not have transducer loss.This signal (DxV_IN) be exaggerated (kxDxV by factor k_IN) and be split to two paths.One paths directly arrives judges comparer 26, another paths offer judge comparer 26 before through for example sampling and keeping module 28.Described sampling andmaintenance module 28 are used to preserve last time " kxDxV_IN" signal, thereby the signal that produces after can changing with Dead Time is relatively.

Fig. 4 shown sampling and keptmodule 28, but sampling and keep the function can accomplished in various ways comprises, for example uses " N " bit memory or other equivalence techniqueses.Similarly, comparator function can be carried out by for example logic value comparer or other equivalence techniqueses.

Dead Time processor 20 (DTP) among Fig. 4 can be realized by logical circuit, microcontroller or microprocessor.DTP20 control sampling andholding circuit 28 are provided with Dead Time byDead Time modulator 16 and 18, and handle " better (the Better) " signal from the output of judging comparer.If new signal (current D) is less than last signal (D last time), then new Dead Time " better " (comparer is output as height) and DTP20 preserve current new Dead Time value.Otherwise abandon described new Dead Time and recover old Dead Time.After changing Dead Time, need certain delay to allow the power supply feedback circuit to establish new duty factor.Several factors may influence this time, but in fact about 100 times of times of power supply switching cycle seem comparatively suitable.

Although do not need to prove principle, but in fact, DTP20 preferably before specific Dead Time is made final conclusion, averages a plurality of judgements in relative cycle long period, to obtain reliability and to prevent because the wrong dead band time setting that noise or transient state cause.Need hundreds of or more sample.The average so effectively influence of quick load transient to power supply.If use some additive method except that duty factor to determine power consumption, also can use identical averaging.

PLMDT can use combine digital PWM or digital signal processing (DSP) and realize, but rudimentary algorithm is identical in fact.

Fig. 5 has shown rudimentary algorithm, and this algorithm can be realized by digital signal processor, microprocessor, microcontroller or the logic state machine that realizes PLMDT.The example that has wherein also shown the program that realizes by Fig. 4 circuit fully.

With reference to figure 5, only shown the flow process of close synchronously (sync-off) passage.As described below, sync-on channel flow is identical in fact.From A, suppose that the result who is provided with sync-off delay and previous (previous) Dead Time is the power consumption that last time, (last) Dead Time produced, show that last time, sampling was better than previous sampling, promptly produce lower dutycycle and lower power consumption, the "Yes" by point " A " enters flow process.The test counter that count down to " N " increases progressively 50.In 52 samplings and preserve current power consumption.As shown in 54, Dead Time is shortened or reduces a step-length.This means to close to postpone to be increased, because Dead Time has been reduced.Whether be arbitrarily to Dead Time when initial if increasing or reducing.Yet, because target reduces power consumption and this is to realize by reducing Dead Time, so Dead Time preferably is reduced when initial.At the second portion (II) of Fig. 5 flow process, Dead Time is increased, and realizes producing the Dead Time of more low-power consumption.

Realize to postpone to allow as at the establishment supply voltage shown in 56.Now will new power consumption (after Dead Time changes) and old power consumption comparison 58.As shown in the 58A, old power consumption is saved by previous step 52.If new power consumption lower (for example determining by dutycycle), shown indetermination module 60, then flow process proceeds tomodule 62, and wherein " better " counter is incremented.Described " better " counting keeps following the tracks of the number of times that new power consumption is better than old power consumption.

If new power consumption is not better than old power consumption instep 60, then counter does not increase progressively.Flow process proceeds todetermination module 66 to determine whether N test is finished then.As mentioned above, preferably repeatedly test to obtain reliable results.If N test do not finished, flow process route via 69.71, recover last time Dead Time and in 73, realize postponing allowing establishing power supply, and test counter increases progressively 50 once more, and compare with old power consumption once more.In case finish N test, then arrive outlet 68.Dead Time was realized instep 54 last time.Carry out N test to guarantee it relatively is reliably, consider, then may lead to errors if only carry out the single test for for example noise or load transient.By repeatedly testing, can obtain higher degree of accuracy and fiduciary level.

Instep 68, determine whether that N/2+1 time test is more excellent, that is to say whether " better " counter shows the power consumption more excellent above the test shows of half.If then enter the part ii of flow process by flow line 70.If there is no N/2+1 time more excellent test then recovers oldDead Time 74, and realizes postponing 75 before proceeding tostep 76.

Instep 76, test counter " N " increases progressively once more.Current power consumption is saved 78,80 Dead Time is increased a step-length, reduces sync-off delay.82, realize postponing to allow to establish power supply.84, relatively in theold power consumption 84A ofstep 78 preservation and new power consumption.Old power consumption display is in84A.In step 86, determine whether new power consumption is lower along with Dead Time increases.If new power consumption is lower, then increase progressively " better " counter 88.If new power consumption is not lower or after 88 increase progressively described better counter, check to determine whether to have finished N test.If no, then return and increase progressively test counter once more, and compare once more 84 76 by path 93.In case instep 90, finished N test, then in 92, checked to determine that most cases is for more excellent in N the test.If such situation, then flow process proceeds to sync-on channel flow, and this flow process synchronous off channel example with shown in Figure 5 in fact is identical.Handling the sync-on channel Dead Time in the mode identical with synchronous off channel example shown in Figure 5 postpones.Therefore, in sync-on channel, can carry out similar flow process, it is older power consumption and corresponding to the new power consumption of the Dead Time that increases and reduce, if power consumption is more excellent, then keep new Dead Time, if power consumption is not more excellent, then recover old Dead Time, come down to as the mode in the synchronous off channel example shown in Figure 5.

The PLMDT technology has produced the Dead Time of optimizing.Yet the result is based on the compromise of averaging circuit condition rather than based on the accurate optimal value of instant condition of work.Intelligent Dead Time disclosed herein (IDT) has solved " speed " problem related with PLMDT.

Summary of the invention

According to the present invention, the equipment of the Dead Time between the opening time of two tandem taps that the power converter circuit that provides a kind of setting to be connected to supply voltage is interior, described equipment comprises: circuit is used for monitoring power converter circuit parameter and output corresponding to described circuit parameter is provided; Storer is addressed by the signal relevant with the output of described monitoring circuit, has stored in the described storer about described Dead Time and the value related with the value of described circuit parameter; Processor provides the storer output related with the value of described circuit parameter, to be provided with corresponding to the Dead Time that is stored in the value in the described storer; And Dead Time realization level, be used for realizing described Dead Time according to the output of described storer.

The present invention also comprises the method for the Dead Time between the opening time that two tandem taps in the power converter circuit be connected to supply voltage are set, and described method comprises monitoring power converter circuit parameter and output corresponding to described circuit parameter is provided; By the signal relevant storer is carried out addressing, stored in the described storer about described Dead Time and the value related with the value of described circuit parameter with described output; Provide the storer output related, to be provided with corresponding to the Dead Time that is stored in the value in the described storer with the value of described circuit parameter; And realize described Dead Time according to the output of described storer.

The present invention can be applied to be directly connected to the switch of supply voltage, and the topology that may be separated by transformer of two switches, for example in synchronous boost type, inverse-excitation type or positive activation type converter.

According to one aspect of the invention, be called intelligent Dead Time (IDT) at this, thereby use look-up table or suitable closing form to solve scheme and change Dead Time in response to changing converter and initial conditions.All use storer preservation Dead Time value or coefficient in order to waiting a moment use in both cases.When outage, keep this storer if desired, then need to use nonvolatile memory.Directly store look-up tables still solves scheme for closing form, can storage coefficient.

In a kind of enforcement, can use the minimum power losses Dead Time (PLMDT) (seeing above-mentioned while pending application application) of certain form, thereby with respect to the Dead Time of circuit condition map out optimum.Finish this process and have some selections.

By PLMDT, according to making the minimized mode of overall converter power losses change Dead Time.Can use Several Methods to come monitoring power consumption, comprise the combination that monitors the input and output voltage and current.If input and output voltage is fixed, then only need standby current, and if use averaging, then only need to measure input current.Yet tool cost efficiency is to use the relative tolerance of gauge tap duty factor as power attenuation with method easily.Thereby when the adjusting Dead Time minimizes duty factor, converter power losses is minimized.In a kind of enforcement, error amplifier output is used to substitute duty factor.This is possible, because error signal is the modulation input of PWM level.Therefore, the PWM duty factor is proportional to error voltage.

In one embodiment of the invention, thus use the Dead Time value of preserving after this can make minimum power losses and do not need at the moment according to PLMDT technology spending time search optimal value by PLMDT.Although preferably use PLMDT, also can adopt other technologies to upgrade the Dead Time value of being stored.

The Dead Time value of being stored can be determined in the design phase of prototype.An advantage of this selection is need not comprise the PLMDT circuit in final the application.Major defect is manufacturing changeability, component tolerance and the component ageing that Dead Time selects to comprise expectation.Can force the conservative more setting of use like this, cause the suboptimum loss.

If (typically in driver IC) combined the PLMDT circuit during the product after design was used, then can when starting first, shine upon Dead Time.The advantage of doing like this is manufacturing and component tolerance can be combined in the dead band time setting.Shortcoming is not comprise component ageing, must allow to wear out thereby be provided with.Sort circuit is optimized more than the design phase calibration, but still not ideal enough.Yet it is enough good using for majority.

Preferred selection is to shine upon with periodic intervals at the whole life period that product is used from the performance starting point.In this way, in case find optimized setting, then can be periodically updated.For example, PLMDT can periodically call to determine to be stored in the new optimized value in the storer in system.

Other features and advantages of the present invention can be clearer by following detailed description with reference to the accompanying drawings.

Description of drawings

With reference now to the more detailed description the present invention of accompanying drawing,, wherein:

Fig. 1 is the structural drawing of an embodiment realizing in a circuit according to the invention;

Figure 1A has shown second embodiment;

Fig. 2 has shown the waveform of the circuit of Fig. 1 or 1A;

Fig. 3 is the process flow diagram of the algorithm realized in the Digital Implementation of the present invention;

Fig. 4 has shown the circuit of realization minimum power losses Dead Time (PLMDT), and described circuit can use to update stored in the Dead Time value in the storer together in conjunction with the present invention; And

Fig. 5 has shown the process flow diagram of realizing the algorithm of PLMDT.

Embodiment

Refer again to accompanying drawing, Fig. 1 has shown that a kind of of converter circuit who realizes according to intelligent Dead Time of the present invention (IDT) method may realize.Various other realizations also are possible, because flesh and blood of the present invention is " memory " optimum Dead Time in the power work scope, and when after this needing " memory " then.By the condition under the described system monitoring according to the difference that realizes and difference still can comprise: input voltage, output current (for example synchronous switch current) and mosfet driver temperature.

Fig. 1 has shown a kind of may realize in conjunction with digital and analog circuit of the present invention.Other realizations also are possible, and most module and function can be implemented as digital circuit and mimic channel.

Fig. 1 has shown the DC-DC converter circuit, thereby this circuit is modified to comprise according to technology of the present invention minimise power consumption during Dead Time makes Dead Time is set intelligently.Preferably, described circuit is based on periodically adopting PLMDT to optimize and the renewal Dead Time.Described converter comprises two switch Q1 and Q2 (being generally MOSFET), at power supply node V_INAnd connect between the ground connection.Converter shown in the figure is a buck converter, but the present invention can be applied to any type of switched-mode power supply with synchronous rectification.

As known, the switching node N of buck converter is coupled to load by outputting inductance L.Output capacitance C is coupling in the load two ends.Thegate driver circuit 2 that the grid of each switch Q1 and Q2 shows by signal and 4 and below with the adjunct circuit of describing is coupled to pulse-length modulation (PWM) signal from PWM controller 12 (be respectively control and synchronously).Because gate drive signal is complementary, signal has showninverter 6 in a gate driving passage.As known, in buck converter, switch Q1 is as gauge tap work, and switch Q2 is as synchronous rectifier work.

Producepwm signal 10 byPWM controller 12 with knownmanner.Pwm signal 10 postpones by fixed delay block 14.Allow programmable Dead Time scope to comprise positive and negative Dead Time value like this.The shut-in time and the opening time of synchro switch Q2 signal can change, and as shown in Figure 2, thereby change the Dead Time amount.Open synchronously and postpone for example to realize thatmodulator 16 can comprise for example counter, tapped (tapped) simulation or digital delay line or single-shot circuit (single shot circuit) by 4 Dead Time modulators 16.Same, realize sync-off delay by similar modulator 18.They are independently programmed by Dead Timeprocessor 20A and allow independent regulation to open synchronously and the sync-off delay time.

In example shown in Figure 1, the output that monitors 3 A/D converters 15 of the electric current among the transistor Q2 is used to directly storer 23 be carried out addressing,storer 23 can be the part ofprocessor 20A, comprise determine by 3 bits 8 kinds may current level in each dead band time setting.Although as shown in the figure 3 bit pads, also can use to have the more i.e. converter of multidigit more of high resolvingpower.Counter 25 uses as lock usually, and along with memory content is loaded together to be sent to DeadTime modulator 16 and 18.These modulators are worked in the manner described above realizing Dead Time, and identical with the modulator that uses in the PLMDT technology.

Fig. 1 shown by the electric current in theparallel switch S 1 that connects of sensing and monitored the Q2 electric current, and S1 can be for carrying the more transistor switch of low current, and the electric current among its electric current and the Q2 has to be determined to concern.Switch S 1 has realized sampling and holding circuit and during the FET opening time that continues potential destructive voltage has been isolated from A/D converter 15.Other current sense solutions also are possible.For example, can use and export the simple sensing resistor RS that switch Q1 and Q2 (seeing Figure 1A) connect or the average dc voltage V at inductance L (seeing Figure 1A) two ends_DCIndicate as electric current.

Fig. 2 has shown the waveform of circuit shown in Figure 1.Wherein shown pwm signal 10.Signal controlling (CONTROL) postpones by the fixed delay of Postponement module 14.The signal Synchronization (SYNC) that offers the grid of synchro switch Q2 has variable sync-off delay and variable synchronous unlatching delay as mentioned above, thereby determines the Dead Time between signal CONTROL and the SYNC.The close synchronously signal is determined byDTP 20A and offersmodulator 18 as 4 position digital signals.The output ofmodulator 18 is provided for Dbistable multivibrator 30, and Dbistable multivibrator 30 is removed Dbistable multivibrator 32, off switch Q2 when variable delay after setting.Similarly,modulator 16 is opened switch Q2 by Dbistable multivibrator 32 is set when selected variable unlatching postpones.Whenbistable multivibrator 32 is output as when high, switch Q2 is unlocked.Whenbistable multivibrator 32 is output as when low, removebistable multivibrator 30, therebybistable multivibrator 30 will be set up when the next sync-off delay of being determined by modulator 18.Can in synchronizing channel, realize positive and negative Dead Time effectively thereby the fixed delay in thecontrol channel 14 postpones enoughtime quantum modulators 16 and 18 with the CONTROL pwm signal, effectively allow to open synchronously according to the requirement that realizes selected Dead Time and close synchronously is delayed or shift to an earlier date.

Dead Timeprocessor 20A preferably realizes the PLMDT algorithms bymodule 27 as mentioned above and in above-mentioned while pending application application.Provide signal corresponding to power attenuation toPLMDT module 27 by power attenuation testing circuit 40.Preferably, the duty factor of circuit monitors pwm signal as shown in the figure, but also can monitorother parameters.Circuit 40 can comprise element for example shown in Figure 4 22 and 24, and the signal that is proportional to duty factor and the power attenuation related with each Dead Time are provided.In another implementation, can determine power attenuation by the error amplifier output that monitors the pwm circuit of indicating duty factor.This is shown as the circuit of realizing PLMDT in Figure 1A.The output oferror amplifier 11 can be used to refer to duty factor and power attenuation.This is because error signal is the modulation input of PWM level.Therefore, the PWM duty factor is proportional to error voltage.PLMDT module 27 (preferably periodically) when being called is carried out the steps necessary of PLMDT algorithm to determine optimum Dead Time.As above described about the description of PLMDT,PLMDT module 27 can be the combination of numeral, simulation and software function.

Preferably, the PLMDT algorithm is periodically implemented.In the case,counter 25 can be used to test greater than with the Dead Time that is lower than the value of preserving in the storer (DT) value to check that wherein whether one be provided with than current DT and have lower loss.

Fig. 3 has shown the basic operation sequence of IDT.

With reference to figure 3, instep 100, when Q2 opens, the electric current among the sensing Q2.By the output of A/D converter 15storer 23 is carried out addressing instep 110, described A/D converter 15 provides the digital value of sensing circuit.The content ofstorer 23 is corresponding to the Dead Time (open synchronously and postpone and synchronous turn-off delay) of the corresponding mapping value of Q2electric current.At step 120counter 25 load id T memorycontents.Enable counter 25 outputs instep 130 and givemodulator 16 and 18 so that new DT value (open synchronously and postpone and sync-off delay) to be provided.

Q2 is being closed (140) by the appropriate time in the determined PWM of the sync-off delay cycle then.In 150, check then to determine whether to realize PLMDT.If not, then return round-robin and begin the place and open Q2 and repetitive cycling once more.If arrived the time (preferred periodically realization) of realizingPLMDT 150, then realize thePLMDT algorithm 27 ofprocessor 20A and upgrade the IDT storer with new, more excellent minimum power losses Dead Time (for the Q2 electric current that senses), the IDT storer that has upgraded is used to be implemented once more up to PLMDT in the next cycle.In one implementation, increase progressively by counter and the Dead Time value of testing of successively decreasing above and below storing value in the storer more excellent so which to be checked.

IDT can change the DT value of power cycle based on the cycle.Therefore there is not the load transient problem of operative association therewith.On the other hand, when periodically calling PLMDT, must be noted that and guarantee that the DT value of being stored is actual value corresponding to correct electric current.Consider can be by the result in the tens of millisecond the is averaged optimum PLMDT that finishes, above points for attention should finish.

Thereby a kind of method that realizes this operation is to use PLMDT circuit map out optimum Dead Time when power supply starts first.These values can be stored in the nonvolatile memory and use with the whole life period at power supply.This can by first between the starting period good the loading to power supply and in whole range of current, progressively change (stepping) described load then of application definition realize.

According to the present invention, make Dead Time control optimization, thereby make minimum power losses, and do not need the correct Dead Time of spended time search.Use net result just power attenuation rather than wave edges or synchro switch forward voltage Dead Time is set, avoided the secondary power loss in other sources.Because always select minimum power attenuation, so do not need to know the relative importance of minor cross conduction for the loss reduction in the reverse recovery of synchro switch.

Although described the present invention with reference to specific embodiment, those skilled in the art can easily make variations and modifications and other uses to it.Therefore, the present invention is not limited to certain content disclosed herein, but only is defined by the following claims.

Claims (53)

Translated fromChinese

1.一种设置连接到电源电压的功率转换器电路内的两个串联开关的开启时间之间的死区时间的设备，所述设备包括：1. A device for setting the dead time between the turn-on times of two series switches within a power converter circuit connected to a supply voltage, said device comprising:电路，用于监视功率转换器电路参数并且提供对应于所述电路参数的输出；circuitry for monitoring a power converter circuit parameter and providing an output corresponding to the circuit parameter;存储器，通过与监视电路的输出相关的信号而被寻址，所述存储器中存储了关于所述死区时间以及与所述电路参数的值关联的值；a memory addressed by a signal related to the output of the monitoring circuit, said memory storing therein values relating to said dead time and associated with values of said circuit parameters;处理器，提供与所述电路参数的值关联的存储器输出，以设置对应于存储在所述存储器中的值的死区时间；以及a processor providing a memory output associated with the value of the circuit parameter to set a dead time corresponding to the value stored in the memory; and死区时间实现级，用于根据所述存储器的输出而实现所述死区时间。a dead time implementation stage for implementing the dead time based on the output of the memory.2.根据权利要求1所述的设备，其中所述处理器包括用于在选定时间更新存储在所述存储器中的值以使死区时间期间的功耗最小化的装置。2. The apparatus of claim 1, wherein the processor includes means for updating values stored in the memory at selected times to minimize power consumption during dead times.3.根据权利要求1所述的设备，其中存储在所述存储器中的值是在所述转换器电路设计期间存储在存储器中的。3. The apparatus of claim 1, wherein the value stored in the memory is stored in memory during design of the converter circuit.4.根据权利要求1所述的设备，其中所述存储器包括查找表。4. The apparatus of claim 1, wherein the memory comprises a look-up table.5.根据权利要求1所述的设备，其中存储在所述存储器中的值是在所述转换器电路首次连接到负载并且电源被提供给所述转换器电路时被存储在存储器中的，由此通过将该值映射到所述转换器电路的工作范围内的电路参数而将该值存储在所述存储器中。5. The apparatus of claim 1 , wherein the value stored in the memory is stored in the memory when the converter circuit is first connected to a load and power is supplied to the converter circuit, by This stores the value in the memory by mapping the value to a circuit parameter within the operating range of the converter circuit.6.根据权利要求1所述的设备，其中所述电路参数包括经过一个所述开关的电流、所述功率转换器电路的输入电压或者至少一个所述开关的温度。6. The apparatus of claim 1, wherein the circuit parameter comprises a current through one of the switches, an input voltage to the power converter circuit, or a temperature of at least one of the switches.7.根据权利要求6所述的设备，其中一个所述开关为同步整流器，并且所述电路参数包括经过所述一个开关的电流。7. The apparatus of claim 6, wherein one of said switches is a synchronous rectifier, and said circuit parameter includes a current through said one switch.8.根据权利要求7所述的设备，其中所述监视电路包括电流感测电路，用于监视经过所述一个开关的电流。8. The apparatus of claim 7, wherein the monitoring circuit includes a current sensing circuit for monitoring current through the one switch.9.根据权利要求8所述的设备，其中所述电流检测电路包括与所述开关串联的感测电阻或者使用所述功率转换器电路的输出电感两端的平均DC电压的电路。9. The apparatus of claim 8, wherein the current sensing circuit includes a sense resistor in series with the switch or a circuit that uses the average DC voltage across an output inductor of the power converter circuit.10.根据权利要求8所述的设备，其中所述电流感测电路包括与所述一个开关并联耦合的第二开关。10. The apparatus of claim 8, wherein the current sensing circuit includes a second switch coupled in parallel with the one switch.11.根据权利要求1所述的设备，其中所述监视电路包括A/D转换器，用于提供对应于所述电路参数的数字值。11. The apparatus of claim 1, wherein the monitoring circuit includes an A/D converter for providing a digital value corresponding to the circuit parameter.12.根据权利要求11所述的设备，其中所述A/D转换器提供输出以对所述存储器进行寻址，从而所述存储器产生与存储在存储器中的死区时间关联的、与所述电路参数对应的值。12. The apparatus of claim 11 , wherein the A/D converter provides an output to address the memory such that the memory generates a value associated with the dead time stored in the memory. The corresponding value of the circuit parameter.13.根据权利要求12所述的设备，其进一步包括锁定电路，用于将来自所述存储器的值提供给所述死区时间实现级。13. The apparatus of claim 12, further comprising a latch circuit for providing a value from the memory to the dead-time implementation stage.14.根据权利要求13所述的设备，其中所述锁定电路包括增减计数器。14. The apparatus of claim 13, wherein the lockout circuit comprises an up-down counter.15.根据权利要求14所述的设备，其中所述处理器包括用于在选定时间更新存储在所述存储器中的值以使死区时间期间的功耗最小化的装置，并且其中所述计数器对来自所述存储器的值进行递增和递减，以确定大于或者小于来自所述存储器的值的值是否产生更低的功耗。15. The apparatus of claim 14 , wherein the processor includes means for updating values stored in the memory at selected times to minimize power consumption during dead times, and wherein the A counter increments and decrements the value from the memory to determine whether values greater or less than the value from the memory result in lower power consumption.16.根据权利要求15所述的设备，其进一步包括电路，用于将对应于所实现的死区时间的功耗的值提供给所述处理器。16. The apparatus of claim 15, further comprising circuitry to provide a value corresponding to the power consumption of the implemented dead time to the processor.17.根据权利要求2所述的设备，其中所述用于更新存储在所述存储器中的值的装置包括用于确定与死区时间关联的功耗并且使与死区时间关联的功耗最小化的装置。17. The apparatus of claim 2, wherein said means for updating a value stored in said memory comprises a method for determining and minimizing power consumption associated with dead time device.18.根据权利要求17所述的设备，其中所述用于确定功耗的装置监视提供给所述两个开关中至少一者的PWM信号的占空比。18. The apparatus of claim 17, wherein the means for determining power consumption monitors a duty cycle of a PWM signal provided to at least one of the two switches.19.根据权利要求17所述的设备，其中所述用于确定功耗的装置监视误差信号输出，所述误差信号输出提供调制输入给用于产生提供给所述两个开关中至少一者的PWM信号的电路。19. The apparatus of claim 17, wherein said means for determining power consumption monitors an error signal output that provides a modulation input for generating Circuit of PWM signal.20.根据权利要求17所述的设备，其中所述装置周期性地更新所述存储器中的值。20. The apparatus of claim 17, wherein the means periodically updates a value in the memory.21.根据权利要求20所述的设备，其中所述死区时间实现级实现对一个所述开关的控制信号的可变关闭以及对所述一个开关的控制信号的可变开启。21. The apparatus of claim 20, wherein said dead-time implementing stage implements variable closing of a control signal to one of said switches and variable opening of a control signal of said one switch.22.根据权利要求21所述的设备，其中所述一个开关执行同步整流功能并且另一个开关为控制开关。22. The apparatus of claim 21, wherein the one switch performs a synchronous rectification function and the other switch is a control switch.23.根据权利要求21所述的设备，其中所述装置包括在对应于第一和第二死区时间的时间内的选定瞬间采样所述脉冲宽度调制信号的模块；以及用于控制所述采样的定时的处理器。23. The apparatus according to claim 21 , wherein said means comprises means for sampling said pulse width modulated signal at selected instants of time corresponding to first and second dead times; and for controlling said Sampled timing processor.24.根据权利要求23所述的设备，其中所述死区时间实现级包括由所述处理器控制的第一和第二可变延迟电路。24. The apparatus of claim 23, wherein the dead time implementation stage includes first and second variable delay circuits controlled by the processor.25.根据权利要求24所述的设备，其中所述第一和第二可变延迟电路从所述处理器接收数字输入，所述处理器选择所述一个开关的开启和关闭的延迟时间量。25. The apparatus of claim 24, wherein the first and second variable delay circuits receive digital input from the processor that selects an amount of delay time for opening and closing of the one switch.26.根据权利要求2所述的设备，其中所述装置通过改变可变开启延迟而改变死区时间，并且在所述改变之后监视选定参数以确定功耗是否更低，如果功耗更低，则实现所述开启延迟，并且如果功耗并不更低，则恢复先前的开启延迟，并且进一步地，其中所述装置通过改变可变关闭延迟而改变死区时间，并且在所述改变之后监视选定参数以确定功耗是否更低，如果功耗更低，则实现所述关闭延迟，并且如果功耗并不更低，则恢复先前的关闭延迟。26. The apparatus of claim 2, wherein said means changes the dead time by changing the variable turn-on delay, and after said change monitors the selected parameter to determine if the power consumption is lower, if the power consumption is lower , then implement the turn-on delay, and if the power consumption is not lower, restore the previous turn-on delay, and further, wherein the device changes the dead time by changing the variable turn-off delay, and after the change Selected parameters are monitored to determine if power consumption is lower, if power consumption is lower, the shutdown delay is implemented, and if power consumption is not lower, the previous shutdown delay is restored.27.根据权利要求26所述的设备，其中所述装置传输各个第一和第二信号到所述死区时间实现级，从而在控制一个所述开关的控制信号被开启和关闭之前，分别选择另一个所述开关的控制信号的关闭延迟和开启延迟。27. The apparatus according to claim 26, wherein said means transmits respective first and second signals to said dead time implementation stage, so that before a control signal controlling one of said switches is turned on and off, respectively select A turn-off delay and a turn-on delay of a control signal of another said switch.28.根据权利要求27所述的设备，其进一步包括固定延迟级，用于延迟控制所述一个开关的控制信号。28. The apparatus of claim 27, further comprising a fixed delay stage for delaying a control signal controlling the one switch.29.根据权利要求28所述的设备，其中所述固定延迟级允许所述死区时间实现级实现正的和负的死区时间量。29. The apparatus of claim 28, wherein the fixed delay stage allows the deadtime implementing stage to implement positive and negative deadtime amounts.30.根据权利要求1所述的设备，其中所述处理器包括数字信号处理器、微处理器、微控制器或者逻辑电路中的任何一者。30. The apparatus of claim 1, wherein the processor comprises any one of a digital signal processor, a microprocessor, a microcontroller, or a logic circuit.31.根据权利要求1所述的设备，其中所述两个开关包括半导体开关。31. The apparatus of claim 1, wherein the two switches comprise semiconductor switches.32.根据权利要求31所述的设备，其中所述两个开关包括MOSFET。32. The apparatus of claim 31, wherein the two switches comprise MOSFETs.33.一种设置连接到电源电压的功率转换器电路内的两个串联开关的开启时间之间的死区时间的方法，所述方法包括：33. A method of setting a dead time between the turn-on times of two series switches within a power converter circuit connected to a supply voltage, the method comprising:监视功率转换器电路参数并且提供对应于所述电路参数的输出；monitoring a power converter circuit parameter and providing an output corresponding to the circuit parameter;通过与所述输出相关的信号对存储器进行寻址，所述存储器中存储了关于所述死区时间以及与所述电路参数的值关联的值；addressing a memory by a signal associated with said output, said memory storing therein a value associated with said dead time and associated with a value of said circuit parameter;提供与所述电路参数的值关联的存储器输出以设置对应于存储在所述存储器中的值的死区时间；以及providing a memory output associated with the value of the circuit parameter to set a dead time corresponding to the value stored in the memory; and根据所述存储器的输出而实现所述死区时间。The dead time is implemented based on the output of the memory.34.根据权利要求33所述的方法，其进一步包括在选定时间更新存储在所述存储器中的值，以使死区时间期间的功耗最小化。34. The method of claim 33, further comprising updating values stored in the memory at selected times to minimize power consumption during dead times.35.根据权利要求33所述的方法，其进一步包括在所述转换器电路设计期间在所述存储器中存储所述值。35. The method of claim 33, further comprising storing the value in the memory during the converter circuit design.36.根据权利要求33所述的方法，其进一步包括在查找表中存储所述值。36. The method of claim 33, further comprising storing the value in a lookup table.37.根据权利要求33所述的方法，其进一步包括在所述转换器电路首次连接到负载并且提供电源给所述转换器电路时，将所述值存储在所述存储器中，由此通过将所述值映射到所述转换器电路的工作范围内的电路参数而将所述值存储在所述存储器中。37. The method of claim 33, further comprising storing the value in the memory when the converter circuit is first connected to a load and power is supplied to the converter circuit, whereby The values are stored in the memory mapped to circuit parameters within an operating range of the converter circuit.38.根据权利要求33所述的方法，其中所述电路参数包括经过一个所述开关的电流、所述功率转换器电路的输入电压或者至少一个所述开关的温度。38. The method of claim 33, wherein the circuit parameters include current through one of the switches, input voltage to the power converter circuit, or temperature of at least one of the switches.39.根据权利要求38所述的方法，其中一个所述开关为同步整流器，并且所述电路参数包括经过所述一个开关的电流。39. The method of claim 38, wherein one of said switches is a synchronous rectifier, and said circuit parameter includes a current through said one switch.40.根据权利要求39所述的方法，其中所述监视步骤包括监视经过所述一个开关的电流。40. The method of claim 39, wherein the monitoring step includes monitoring current through the one switch.41.根据权利要求40所述的方法，其中所述监视步骤包括感测通过与所述开关串联的感测电阻的电流，或者使用所述功率转换器电路的输出电感两端的平均DC电压。41. The method of claim 40, wherein the monitoring step includes sensing current through a sense resistor in series with the switch, or using an average DC voltage across an output inductor of the power converter circuit.42.根据权利要求33所述的方法，其中所述监视步骤包括提供对应于所述电路参数的数字值。42. The method of claim 33, wherein the monitoring step includes providing a digital value corresponding to the circuit parameter.43.根据权利要求42所述的方法，其进一步包括提供所述数字值以对所述存储器进行寻址，从而所述存储器产生与存储在其中的死区时间关联的、对应于所述电路参数的值。43. The method of claim 42, further comprising providing the digital value to address the memory such that the memory generates a value corresponding to the circuit parameter associated with the dead time stored therein. value.44.根据权利要求43所述的方法，其进一步包括在选定时间更新所述存储在存储器中的值，以使死区时间期间的功耗最小化，并且其进一步包括对来自所述存储器的值进行递增和递减，以确定大于或者小于来自所述存储器的值的值是否产生更低的功耗。44. The method of claim 43, further comprising updating the value stored in memory at selected times to minimize power consumption during dead times, and further comprising Values are incremented and decremented to determine whether values greater or less than the value from the memory result in lower power consumption.45.根据权利要求44所述的方法，其进一步包括确定对应于为实现死区时间的功耗的值。45. The method of claim 44, further comprising determining a value corresponding to power consumption for dead time implementation.46.根据权利要求34所述的方法，其中所述更新存储在所述存储器中的值的步骤包括确定与死区时间关联的功耗并且使与死区时间关联的功耗最小化。46. The method of claim 34, wherein the step of updating the value stored in the memory includes determining and minimizing power consumption associated with dead time.47.根据权利要求46所述的方法，其中所述确定功耗的步骤包括监视提供给所述两个开关中至少一者的PWM信号的占空比。47. The method of claim 46, wherein the step of determining power consumption includes monitoring a duty cycle of a PWM signal provided to at least one of the two switches.48.根据权利要求46所述的方法，其中所述确定功耗的步骤包括监视误差信号输出，所述误差信号输出提供调制输入给用于产生提供给所述两个开关中至少一者的PWM信号的电路。48. The method of claim 46, wherein said step of determining power consumption includes monitoring an error signal output that provides a modulation input to a PWM used to generate a PWM signal to at least one of said two switches. signal circuit.49.根据权利要求46所述的方法，其中所述更新步骤包括周期性地更新所述存储器中的值。49. The method of claim 46, wherein said updating step includes periodically updating a value in said memory.50根据权利要求49所述的方法，其中所述实现死区时间的步骤包括实现对一个所述开关的控制信号的可变关闭以及对所述一开关的控制信号的可变开启。50. The method of claim 49, wherein said step of implementing a dead time includes implementing a variable turn off of a control signal to one of said switches and a variable turn on of a control signal to said one switch.51.根据权利要求50所述的方法，其中所述一个开关执行同步整流功能并且另一个开关为控制开关。51. The method of claim 50, wherein the one switch performs a synchronous rectification function and the other switch is a control switch.52.根据权利要求34所述的方法，其中所述更新存储在所述存储器中的值的步骤包括通过改变可变开启延迟而改变死区时间，并且在所述改变之后监视选定参数以确定功耗是否更低，如果功耗更低，则实现所述开启延迟，并且如果功耗并不更低，则恢复先前的开启延迟，并且进一步包括通过改变可变关闭延迟而改变死区时间，并且在所述改变之后监视选定参数以确定功耗是否更低，如果功耗更低，则实现所述关闭延迟，并且如果功耗并不更低，则恢复先前的关闭延迟。52. The method of claim 34, wherein said step of updating a value stored in said memory comprises changing a dead time by changing a variable turn-on delay, and monitoring a selected parameter after said changing to determine whether the power consumption is lower, if the power consumption is lower, implement said turn-on delay, and if the power consumption is not lower, restore the previous turn-on delay, and further include changing the dead time by changing the variable turn-off delay, And monitoring selected parameters after said change to determine if power consumption is lower, implementing said shutdown delay if power consumption is lower, and reverting to previous shutdown delay if power consumption is not lower.53.一种使与连接到电源电压的功率转换器电路内的两个串联开关的开启时间之间的死区时间关联的功耗最小化的设备，所述设备包括：53. An apparatus for minimizing power dissipation associated with dead time between the turn-on times of two series switches within a power converter circuit connected to a supply voltage, the apparatus comprising:控制装置，用于监视与所述转换器的死区时间期间的功耗关联的选定参数；control means for monitoring selected parameters associated with power consumption during dead times of said converter;所述控制装置将死区时间从第一死区时间改变到第二死区时间，比较与所述第一和第二死区时间的所述选定参数关联的功耗，并且确定与所述两个死区时间关联的功耗哪个更小；The control means changes the dead time from a first dead time to a second dead time, compares the power consumption associated with the selected parameter of the first and second dead time, and determines the Which of the two dead time associated power consumption is smaller;死区时间实现级，用于实现所述两个死区时间；以及a dead time implementation stage for implementing the two dead times; and所述控制装置选择与所述更小的功耗关联的死区时间并且提供信号给所述死区时间实现级以设置所选择的死区时间，并且其中所述选定参数包括来自误差放大器的误差信号输出，所述误差信号输出提供调制输入给用于产生提供给所述两个开关中至少一者的PWM信号的电路。The control means selects a dead time associated with the smaller power consumption and provides a signal to the dead time implementation stage to set the selected dead time, and wherein the selected parameter comprises a An error signal output providing a modulation input to circuitry for generating a PWM signal provided to at least one of the two switches.

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