CN100576496C - Formation method of dual damascene structure - Google Patents

Abstract

Translated fromChinese

一种双镶嵌结构的形成方法，包括：提供一半导体基底，在所述半导体基底中形成有金属导线层；在所述半导体基底上形成含氮的高应力介质层；在所述含氮的高应力介质层上形成介电层；在所述介电层中形成开口。该方法形成的器件中金属导线沿介质层不会发生电击穿的问题。

A method for forming a dual damascene structure, comprising: providing a semiconductor substrate in which a metal wire layer is formed; forming a nitrogen-containing high-stress dielectric layer on the semiconductor substrate; A dielectric layer is formed on the stress dielectric layer; an opening is formed in the dielectric layer. In the device formed by the method, the problem of electric breakdown does not occur along the dielectric layer of the metal wire.

Description

Translated fromChinese

双镶嵌结构的形成方法Formation method of dual damascene structure

技术领域technical field

本发明涉及半导体制造技术领域，特别涉及一种双镶嵌结构的形成方法。The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a double damascene structure.

背景技术Background technique

随着半导体工艺线宽的逐渐减小，业界选用铜作为后段的互连材料，相应的，选用低介电常数材料作为绝缘材料。由于铜难以刻蚀且极易扩散，引入双镶嵌工艺，克服难以刻蚀的缺点，并引入阻挡层阻挡铜在低介电常数材料中的扩散，作为阻挡层的材料可以是金属材料，例如，钛、氮化钛等，也可以是介质材料，例如氧化硅等。专利申请号为02106882.8的中国专利公开了一种双镶嵌工艺。图1至图4为述公开的双镶嵌工艺的制造方法剖面示意图。With the gradual reduction of the line width of the semiconductor process, the industry chooses copper as the interconnection material in the back stage, and accordingly, the low dielectric constant material is used as the insulating material. Since copper is difficult to etch and easily diffuses, a dual damascene process is introduced to overcome the disadvantage of being difficult to etch, and a barrier layer is introduced to prevent the diffusion of copper in low dielectric constant materials. The material of the barrier layer can be a metal material, for example, Titanium, titanium nitride, etc. may also be dielectric materials, such as silicon oxide, etc. Chinese patent application No. 02106882.8 discloses a dual damascene process. 1 to 4 are schematic cross-sectional views of a manufacturing method of the disclosed dual damascene process.

如图1所示，提供一具有金属导线层的基底100，所述金属导线层材质可以是铜。在所述基底100上形成第一介质层102，所述第一介质层102用于覆盖基底100中的金属导线层的铜表面，以避免所述铜表面曝露于空气中或其它腐蚀性化学制程中，其形成的方法为等离子体增强化学气相沉积(PECVD)，其厚度为30至100nm。As shown in FIG. 1 , asubstrate 100 having a metal wire layer is provided, and the material of the metal wire layer may be copper. Forming a firstdielectric layer 102 on thesubstrate 100, the firstdielectric layer 102 is used to cover the copper surface of the metal wiring layer in thesubstrate 100, so as to avoid the copper surface from being exposed to air or other corrosive chemical processes Among them, the method of its formation is plasma enhanced chemical vapor deposition (PECVD), and its thickness is 30 to 100 nm.

在所述第一介质层102上形成第二介质层104，所述第二介质层104为低介电常数材料。在所述第二介质层104上形成一抗反射层106，所述抗反射层106可以是有机或无机材料。在所述抗反射层106上形成一光刻胶层108，通过曝光显影形成连接孔开口图案110。A seconddielectric layer 104 is formed on the firstdielectric layer 102, and the seconddielectric layer 104 is a low dielectric constant material. Ananti-reflection layer 106 is formed on the seconddielectric layer 104, and theanti-reflection layer 106 may be an organic or inorganic material. Aphotoresist layer 108 is formed on theantireflection layer 106 , and a connectionhole opening pattern 110 is formed by exposure and development.

如图2所示，以所述光刻胶层108为罩幕，通过刻蚀将所述连接孔开口图案110转移到所述抗反射层106和第二介质层104中形成连接孔110a，所述连接孔110a底部露出所述第一介质层102表面。As shown in FIG. 2, using thephotoresist layer 108 as a mask, the connectionhole opening pattern 110 is transferred to theanti-reflection layer 106 and the seconddielectric layer 104 by etching to form aconnection hole 110a, so The bottom of theconnection hole 110a exposes the surface of the firstdielectric layer 102 .

在所述连接孔110a中和抗反射层106上旋涂光刻胶并形成沟槽图案，通过刻蚀将所述沟槽图案转移到所述抗反射层106和第二介质层104中，形成如图3所示的沟槽112。并移除所述抗反射层106。Spin-coat photoresist in theconnection hole 110a and on theanti-reflection layer 106 to form a groove pattern, transfer the groove pattern to theanti-reflection layer 106 and the seconddielectric layer 104 by etching, and formGroove 112 as shown in FIG. 3 . And remove theanti-reflection layer 106 .

如图4所示，通过刻蚀移除所述连接孔110a底部的第一介质层102。As shown in FIG. 4 , the firstdielectric layer 102 at the bottom of theconnection hole 110 a is removed by etching.

在所述沟槽112和连接孔110a中填充导电材料例如铜即形成铜双镶嵌结构。Filling thetrench 112 and theconnection hole 110 a with conductive material such as copper forms a copper dual damascene structure.

上述双镶嵌结构的制造工艺中，引入材料为氮化硅的第一介质层102作为基底中铜表面的覆盖层和刻蚀停止层。所述形成所述氮化硅的反应气体为氨气(NH₃)、硅烷(SiH₄)，由于上述氨气和硅烷反应的另一种生成物氢气大量被束缚在氮化硅薄膜中，使的生成的氮化硅薄膜特性蜕化，抗击穿能力下降。如图5所示，在所述基底100中形成有第一铜导线100a和第二铜导线100b，所述第一铜导线100a和第二铜导线100b之间电绝缘，在器件的制造过程中，引入材料为氮化硅作的第一介质层102作为第一铜导线100a和第二铜导线100b上表面的覆盖层，以避免铜表面被氧化。上述结构形成的器件后在工作时，第一铜导线100a和第二铜导线100b会沿着所述第一介质层102发生电击穿，有击穿电流101从所述第一介质层102中流过，造成器件电性失败。In the manufacturing process of the above-mentioned dual damascene structure, the firstdielectric layer 102 made of silicon nitride is introduced as a covering layer and an etching stop layer on the copper surface in the substrate. The reaction gases for forming the silicon nitride are ammonia (NH₃ ) and silane (SiH₄ ). Since hydrogen gas, another product of the reaction between ammonia and silane, is bound in a large amount in the silicon nitride film, the The characteristics of the formed silicon nitride film deteriorate, and the breakdown resistance decreases. As shown in FIG. 5, afirst copper wire 100a and asecond copper wire 100b are formed in thesubstrate 100, and thefirst copper wire 100a and thesecond copper wire 100b are electrically insulated. During the manufacturing process of the device A firstdielectric layer 102 made of silicon nitride is introduced as a covering layer on the upper surfaces of thefirst copper wire 100a and thesecond copper wire 100b, so as to prevent the copper surface from being oxidized. When the device formed by the above structure is in operation, thefirst copper wire 100a and thesecond copper wire 100b will undergo electrical breakdown along the firstdielectric layer 102, and abreakdown current 101 will flow from the firstdielectric layer 102. over, resulting in electrical failure of the device.

发明内容Contents of the invention

因此，本发明的目的在于提供一种双镶嵌结构的形成方法，以解决现双镶嵌结构中不同金属导线间发生电击穿的问题。Therefore, the object of the present invention is to provide a method for forming a dual damascene structure to solve the problem of electrical breakdown between different metal wires in the existing dual damascene structure.

为达到上述目的，本发明提供的一种双镶嵌结构的形成方法，包括：In order to achieve the above object, a method for forming a dual damascene structure provided by the present invention includes:

提供一半导体基底，在所述半导体基底中形成有金属导线层；在所述半导体基底上形成含氮的高应力介质层；在所述高应力介质层上形成介电层；在所述介电层中形成开口。A semiconductor substrate is provided, in which a metal wiring layer is formed; a high-stress dielectric layer containing nitrogen is formed on the semiconductor substrate; a dielectric layer is formed on the high-stress dielectric layer; a dielectric layer is formed on the dielectric Openings are formed in the layer.

所述金属导线层材质包括铜、铝、钛、氮化钛、钨中的一种或其组合。所述高应力介质层包括氮化硅、碳氮硅化合物、氧氮硅化合物中的一种或其组合。The material of the metal wire layer includes one of copper, aluminum, titanium, titanium nitride, tungsten or a combination thereof. The high stress dielectric layer includes one of silicon nitride, silicon carbonitride, silicon oxynitride or a combination thereof.

所述高应力介质层的形成方法包括物理气相沉积、等离子体增强化学气相沉积、低压化学气相沉积、高密度等离子体化学气相沉积、原子层沉积中的一种。The method for forming the high stress dielectric layer includes one of physical vapor deposition, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, high density plasma chemical vapor deposition and atomic layer deposition.

形成所述氮化硅的反应气体包括硅烷和氨气。形成所述氮化硅的射频源功率为800至960瓦。所述硅烷流量为420至490sccm，氨气流量为100至200sccm。形成所述氮化硅的反应气体包括氮气，氮气的流量为15000至20000sccm。形成所述氮化硅的环境压力为3至5托，温度为300至600℃。The reaction gas for forming the silicon nitride includes silane and ammonia. The power of the radio frequency source for forming the silicon nitride is 800 to 960 watts. The silane flow rate is 420 to 490 sccm, and the ammonia gas flow rate is 100 to 200 sccm. The reaction gas for forming the silicon nitride includes nitrogen, and the flow rate of nitrogen is 15000 to 20000 sccm. The ambient pressure for forming the silicon nitride is 3 to 5 Torr, and the temperature is 300 to 600°C.

所述介电层包括黑钻石、氟硅玻璃、磷硅玻璃、硼硅玻璃、硼磷硅玻璃、氧化硅、氮化硅、碳化硅中的一种或其组合。The dielectric layer includes one of black diamond, fluorosilicate glass, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, silicon oxide, silicon nitride, silicon carbide or a combination thereof.

该方法进一步包括：在所述开口中填充金属材料。The method further includes: filling the opening with a metal material.

与现有技术相比，本发明具有以下优点：本发明在形成介质层时，增加反应物中氮气或含氮反应物的流量，使得生成的含氮的高应力介质层中氮的含量较高，氮气有助于抑止所述氮化硅膜层中载流子迁移，增加介电常数，减小漏电流；同时，通过在氮化硅膜层中束缚氮气可将反应的生成物之一氢气从氮化硅膜层中赶出来，提高氮化硅膜层的击穿电压；由于氢气在氮化硅膜层中可使膜层特性蜕化，降低膜层的内部应力，降低击穿电压，因而通过在氮化硅膜层中束缚氮气一方面减少或消除了降低膜层击穿电压的氢气，同时提高氮化硅膜层氮的含量又可以进一步提高膜层的击穿电压。从而提高了形成的器件的耐压能力和稳定性。Compared with the prior art, the present invention has the following advantages: when forming the dielectric layer, the present invention increases the flow rate of nitrogen or nitrogen-containing reactants in the reactants, so that the nitrogen content in the generated nitrogen-containing high-stress dielectric layer is relatively high , nitrogen helps to suppress carrier migration in the silicon nitride film layer, increases the dielectric constant, and reduces leakage current; at the same time, hydrogen gas, one of the products of the reaction, can be bound by nitrogen in the silicon nitride film layer Drive out from the silicon nitride film layer to increase the breakdown voltage of the silicon nitride film layer; because hydrogen gas in the silicon nitride film layer can degrade the film characteristics, reduce the internal stress of the film layer, and reduce the breakdown voltage, so By trapping nitrogen in the silicon nitride film, on the one hand, the hydrogen gas that reduces the breakdown voltage of the film is reduced or eliminated, and at the same time, increasing the nitrogen content of the silicon nitride film can further increase the breakdown voltage of the film. Therefore, the withstand voltage capability and stability of the formed device are improved.

附图说明Description of drawings

图1至图4为现有一种双镶嵌工艺的制造方法剖面示意图；1 to 4 are schematic cross-sectional views of a conventional manufacturing method of a dual damascene process;

图5为现有双镶嵌工艺制造方法制造的器件在介质层中产生电击穿的剖面示意图；5 is a schematic cross-sectional view of an electrical breakdown in a dielectric layer of a device manufactured by an existing dual damascene manufacturing method;

图6为本发明双镶嵌结构制造方法的流程图；6 is a flowchart of a method for manufacturing a dual damascene structure of the present invention;

图7至图16为根据本发明实施例的双镶嵌结构制造方法剖面示意图。7 to 16 are schematic cross-sectional views of a method for manufacturing a dual damascene structure according to an embodiment of the present invention.

具体实施方式Detailed ways

为使本发明的上述目的、特征和优点能够更加明显易懂，下面结合附图对本发明的具体实施方式做详细的说明。In order to make the above objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings.

由于铜易扩散和易被氧化的特点，在沉积铜之后需要在金属铜之上覆盖阻挡材料，以避免铜曝露在外部环境中被氧化或铜直接与低介电常数材料接触而发生扩散。同时，所述阻挡材料也可以作为制造下层互连结构的刻蚀停止层，所述刻蚀停止层作为金属间介质层的一部分被保留在器件中。本发明中通过在具有金属层的基底上形成含氮的高应力介质层作为金属铜的阻挡材料，以此提高形成器件的击穿电压，从而提高器件的稳定性及寿命。Due to the characteristics of easy diffusion and oxidation of copper, it is necessary to cover the metal copper with a barrier material after copper deposition to prevent copper from being exposed to the external environment and being oxidized or copper is directly in contact with low dielectric constant materials to cause diffusion. At the same time, the barrier material can also be used as an etching stop layer for fabricating the underlying interconnection structure, and the etching stop layer is retained in the device as a part of the intermetallic dielectric layer. In the present invention, a nitrogen-containing high-stress dielectric layer is formed on the substrate with a metal layer as a barrier material for metal copper, so as to increase the breakdown voltage of the formed device, thereby improving the stability and life of the device.

图6为本发明双镶嵌结构制造方法的流程图。FIG. 6 is a flow chart of the manufacturing method of the dual damascene structure of the present invention.

如图6所示，首先，提供一半导体基底，在所述半导体基底中形成有金属导线层(S200)。所述半导体基底可以是多晶硅、单晶硅、非晶硅、绝缘层上硅(SOI)、砷化稼、硅锗化合物等材料，所述金属导线层材料可以是铜、铝、钛、氮化钛、钨中的一种或其组合。As shown in FIG. 6 , first, a semiconductor substrate is provided, in which a metal wiring layer is formed ( S200 ). The semiconductor substrate can be polycrystalline silicon, monocrystalline silicon, amorphous silicon, silicon-on-insulator (SOI), gallium arsenide, silicon-germanium compound, etc., and the metal wire layer material can be copper, aluminum, titanium, nitride One or a combination of titanium and tungsten.

在所述半导体基底上形成含氮的高应力介质层(S210)。所述高应力介质层包括氮化硅、碳氮硅化合物、氧氮硅化合物中的一种或其组合。所述高应力介质层的形成方法为物理气相沉积、等离子体增强化学气相沉积、低压化学气相沉积、高密度等离子体化学气相沉积、原子层沉积中的一种。A nitrogen-containing high-stress dielectric layer is formed on the semiconductor substrate (S210). The high stress dielectric layer includes one of silicon nitride, silicon carbonitride, silicon oxynitride or a combination thereof. The formation method of the high-stress dielectric layer is one of physical vapor deposition, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, high density plasma chemical vapor deposition and atomic layer deposition.

在所述含氮的高应力介质层上形成介电层(S220)。所述介电层为黑钻石、氟硅玻璃、磷硅玻璃、硼硅玻璃、硼磷硅玻璃、氧化硅、氮化硅、碳化硅中的一种或其组合。形成所述介电层的方法为物理气相沉积、化学气相沉积中的一种或其组合。A dielectric layer is formed on the nitrogen-containing high-stress dielectric layer (S220). The dielectric layer is one of black diamond, fluorosilicate glass, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, silicon oxide, silicon nitride, silicon carbide or a combination thereof. The method of forming the dielectric layer is one of physical vapor deposition, chemical vapor deposition or a combination thereof.

在所述介电层中形成开口，所述开口为连接孔和沟槽(S230)。Openings are formed in the dielectric layer, the openings being connection holes and trenches (S230).

下面结合实施例对本发明双镶嵌结构的制造方法进行详细描述。The manufacturing method of the dual damascene structure of the present invention will be described in detail below with reference to the embodiments.

图7至图16为根据本发明实施例的制造方法剖面示意图。7 to 16 are schematic cross-sectional views of a manufacturing method according to an embodiment of the present invention.

如图7所示，提供一半导体基底200，在所述半导体基底200中形成有器件层和金属导线层200a、200b。所述半导体基底200可以是多晶硅、单晶硅、非晶硅、绝缘层上硅(SOI)、砷化稼、硅锗化合物等材料，所述器件层可以是金属氧化物半导体晶体管。所述金属导线层200a、200b材料可以是铜、铝、钛、氮化钛、钨中的一种或其组合。本实施例中所述金属导线层200a、200b材料为铜。As shown in FIG. 7 , asemiconductor substrate 200 is provided, in which device layers andmetal wire layers 200a, 200b are formed. Thesemiconductor substrate 200 may be polycrystalline silicon, single crystal silicon, amorphous silicon, silicon-on-insulator (SOI), gallium arsenide, silicon-germanium compound, etc., and the device layer may be a metal oxide semiconductor transistor. The material of themetal wire layers 200a, 200b may be one of copper, aluminum, titanium, titanium nitride, tungsten or a combination thereof. In this embodiment, the material of themetal wire layers 200a, 200b is copper.

如图8所示，首先，对所述具有器件层的半导体基底200进行等离子体表面预处理。通过等离子体表面预处理可以减少或消除基底表面的污染物，改善所述半导体基底200表面材质的性质，增强后续工艺形成的介质层和所述半导体基底200表面的粘附性，同时，通过氨气等离子体可以去除金属导线层200a、200b表面的氧化铜。本实施例中选用氨气作为形成等离子的源气体，同时通入辅助气体氮气。将所述半导体基底200送入真空的工艺腔，并向腔室中通入氨气和氮气，打开射频源并调节至合适的功率，在射频源的作用下氨气电离，生成氨气等离子体。氨气等离子体在电场的加速下作用于所述半导体基底200表面。通过氨气等离子体表面预处理可以将半导体基底200表面由于曝露于外部环境而吸收的污染物、水气去除，有利于半导体基底200表面和后续工艺中沉积的其它膜层之间的粘附。所述氨气等离子体射频源功率可以是100至500瓦，氨气的流量为100至200sccm。氨气等离子体表面预处理的时间为10至30s，所述工艺腔的真空度为3至6托。本实施例中，所述氨气等离子体射频源功率可为300瓦，氨气的流量为160sccm。氨气等离子体表面预处理的时间为20s，所述工艺腔的真空度为4.2托。氮气流量为18000sccm。As shown in FIG. 8 , firstly, plasma surface pretreatment is performed on thesemiconductor substrate 200 having the device layer. The pollutants on the surface of the substrate can be reduced or eliminated by plasma surface pretreatment, the properties of the surface material of thesemiconductor substrate 200 can be improved, and the adhesion between the dielectric layer formed in the subsequent process and the surface of thesemiconductor substrate 200 can be enhanced. The gas plasma can remove the copper oxide on the surface of themetal wire layer 200a, 200b. In this embodiment, ammonia gas is selected as the source gas for forming plasma, and the auxiliary gas nitrogen is introduced at the same time. Thesemiconductor substrate 200 is sent into a vacuum process chamber, and ammonia gas and nitrogen gas are introduced into the chamber, the radio frequency source is turned on and adjusted to a suitable power, ammonia gas is ionized under the action of the radio frequency source, and ammonia gas plasma is generated . The ammonia gas plasma acts on the surface of thesemiconductor substrate 200 under the acceleration of the electric field. The ammonia plasma surface pretreatment can remove pollutants and moisture absorbed by the surface of thesemiconductor substrate 200 due to exposure to the external environment, which is beneficial to the adhesion between the surface of thesemiconductor substrate 200 and other film layers deposited in subsequent processes. The power of the ammonia plasma radio frequency source can be 100 to 500 watts, and the flow rate of ammonia gas is 100 to 200 sccm. The time for ammonia plasma surface pretreatment is 10 to 30 s, and the vacuum degree of the process chamber is 3 to 6 Torr. In this embodiment, the power of the ammonia plasma radio frequency source may be 300 watts, and the flow rate of the ammonia gas is 160 sccm. The ammonia gas plasma surface pretreatment time is 20s, and the vacuum degree of the process chamber is 4.2 Torr. The nitrogen flow rate is 18000 sccm.

在完成对所述半导体基底200表面的等离子体预处理后，在所述半导体基底200表面上沉积一含氮的高应力介质层202。沉积所述含氮的高应力介质层202的方法为物理气相沉积、低压化学气相沉积、等离子体增强化学气相沉积、高密度等离子体化学气相沉积、原子层沉积中的一种。所述沉积含氮的高应力介质层202的反应气体为氨气、硅烷、TEOS、二氯二氢硅、氧化二氮、氮气中的一种或其组合。所述含氮的高应力介质层202为氮化硅、氮硅氧化合物、掺氮碳化硅中的一种或其组合。所述沉积的含氮的高应力介质层202厚度为20至80nm。After the plasma pretreatment of the surface of thesemiconductor substrate 200 is completed, a nitrogen-containing high-stress dielectric layer 202 is deposited on the surface of thesemiconductor substrate 200 . The method for depositing the nitrogen-containing high-stress dielectric layer 202 is one of physical vapor deposition, low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, high-density plasma chemical vapor deposition, and atomic layer deposition. The reaction gas for depositing the nitrogen-containing high-stress dielectric layer 202 is one of ammonia, silane, TEOS, dichlorodihydrosilane, nitrous oxide, nitrogen or a combination thereof. The nitrogen-containing high-stress dielectric layer 202 is one of silicon nitride, nitrogen-silicon-oxygen compound, nitrogen-doped silicon carbide, or a combination thereof. The deposited nitrogen-containing high-stress dielectric layer 202 has a thickness of 20 to 80 nm.

所述含氮的高应力介质层202的沉积可以和前述氨气等离子体表面预处理在同一个腔室(chamber)中进行，以所述含氮的高应力介质层202为氮化硅为例，当所述半导体基底200完成氨气等离子体表面处理后，向工艺腔中通入生成含氮的高应力介质层202的反应气体例如氨气和硅烷，调节硅烷和氨气的流量，同时通入氮气作为辅助气体，使得生成的氮化硅薄膜具有较高的含氮量。本实施例中，所述硅烷的流量为硅烷流量为420至490sccm，氨气流量为100至200sccm。氮气的流量为15000至20000sccm。形成所述氮化硅的环境压力为3至5托，温度为300至600℃。射频源功率为800至960瓦，反应时间约为10至30秒。The deposition of the nitrogen-containing high-stress dielectric layer 202 can be carried out in the same chamber (chamber) as the aforementioned ammonia gas plasma surface pretreatment, taking the nitrogen-containing high-stress dielectric layer 202 as an example of silicon nitride , after thesemiconductor substrate 200 has finished the surface treatment with ammonia gas plasma, feed the reaction gas such as ammonia and silane into the process chamber to form the nitrogen-containing high-stress dielectric layer 202, adjust the flow of silane and ammonia, and simultaneously pass Nitrogen gas is used as an auxiliary gas, so that the formed silicon nitride film has a higher nitrogen content. In this embodiment, the flow rate of the silane is 420 to 490 sccm for the silane, and 100 to 200 sccm for the ammonia gas. The flow rate of nitrogen is 15000 to 20000 sccm. The ambient pressure for forming the silicon nitride is 3 to 5 Torr, and the temperature is 300 to 600°C. The RF source power is 800 to 960 watts and the response time is about 10 to 30 seconds.

在同一腔室中进行所述氨气等离子体表面预处理和沉积所述含氮的高应力介质层202的详细步骤如下：打开腔室，将所述半导体基底200送入工艺腔，调节腔室温度为400℃，环境的压力为3至5托；向工艺腔中通入氨气和氮气，所述氨气的流量为160sccm，氮气的流量为18000sccm；调节射频源功率为100至500瓦，腔室温度保持不变，保持氨气的流量为160sccm，氮体的流量为18000sccm。保持环境的压力为3至5托，氨气等离子体表面处理的时间为10至30秒；向反应腔室中通入硅烷，硅烷的流量为420至490sccm，保持氨气和氮气的流量不变，保持腔室温度，提高射频源功率为800至960W，所述硅烷和氨气反应生成氮化硅，由于反应过程中氮气的流量较大，多余的氮气部分被束缚在所述氮化硅膜层中，氮气有助于抑止所述氮化硅膜层中载流子迁移，增加介电常数，减小漏电流；同时，通过在氮化硅膜层中束缚氮气可将反应的生成物之一氢气从氮化硅膜层中赶出来，提高氮化硅膜层的击穿电压；由于氢气在氮化硅膜层中可使膜层特性蜕化，降低膜层的内部应力，并降低击穿电压，因而通过在氮化硅膜层中束缚氮气一方面减少或消除了降低膜层击穿电压的氢气，同时提高氮化硅膜层氮的含量又可以进一步提高了膜层击穿电压。The detailed steps of performing the ammonia plasma surface pretreatment and depositing the nitrogen-containing high-stress dielectric layer 202 in the same chamber are as follows: open the chamber, send thesemiconductor substrate 200 into the process chamber, and adjust the chamber The temperature is 400°C, the ambient pressure is 3 to 5 torr; ammonia and nitrogen are introduced into the process chamber, the flow rate of the ammonia gas is 160 sccm, and the flow rate of the nitrogen gas is 18000 sccm; the power of the radio frequency source is adjusted to 100 to 500 watts, The temperature of the chamber was kept constant, and the flow rate of ammonia gas was kept at 160 sccm, and the flow rate of nitrogen gas at 18000 sccm. Keep the pressure of the environment at 3 to 5 torr, and the time of ammonia plasma surface treatment is 10 to 30 seconds; feed silane into the reaction chamber, the flow of silane is 420 to 490 sccm, and keep the flow of ammonia and nitrogen constant , keep the chamber temperature, increase the power of the radio frequency source to 800 to 960W, the silane and ammonia react to form silicon nitride, due to the large flow of nitrogen in the reaction process, the excess nitrogen is partly bound in the silicon nitride film In the silicon nitride film layer, nitrogen helps to suppress carrier migration in the silicon nitride film layer, increases the dielectric constant, and reduces leakage current; at the same time, by binding nitrogen gas in the silicon nitride film layer, one of the reaction products - Hydrogen gas is driven out from the silicon nitride film layer to increase the breakdown voltage of the silicon nitride film layer; because hydrogen gas in the silicon nitride film layer can degrade the film characteristics, reduce the internal stress of the film layer, and reduce the breakdown voltage Therefore, by trapping nitrogen in the silicon nitride film, on the one hand, the hydrogen gas that reduces the breakdown voltage of the film is reduced or eliminated, and at the same time, increasing the nitrogen content of the silicon nitride film can further increase the breakdown voltage of the film.

如图9所示，在所述含氮的高应力介质层202上形成介电层204。所述介电层204为黑钻石、氟硅玻璃、磷硅玻璃、硼硅玻璃、硼磷硅玻璃、氧化硅、氮化硅、碳化硅中的一种或其组合。形成所述介电层204的方法为物理气相沉积或化学气相沉积。所述介电层204可以是一层或多层。As shown in FIG. 9 , adielectric layer 204 is formed on the nitrogen-containing high-stress dielectric layer 202 . Thedielectric layer 204 is one of black diamond, fluorosilicate glass, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, silicon oxide, silicon nitride, silicon carbide or a combination thereof. The method of forming thedielectric layer 204 is physical vapor deposition or chemical vapor deposition. Thedielectric layer 204 can be one or more layers.

形成所述介电层204后，需要在所述介电层204中形成沟槽和连接孔，形成沟槽和连接孔的方法包括：先行成沟槽后形成连接孔，先形成连接孔后形成沟槽。本实施例以先形成连接孔后形成沟槽的情况为例进行说明。After forming thedielectric layer 204, it is necessary to form grooves and connecting holes in thedielectric layer 204. The method for forming the grooves and connecting holes includes: first forming the grooves and then forming the connecting holes, first forming the connecting holes and then forming the connecting holes. groove. This embodiment is described by taking the case of forming the connection holes first and then forming the grooves as an example.

如图10所示，在所述介电层204上旋涂抗反射层206，在所述抗反射层206上旋涂第一光刻胶层208，通过曝光显影等工艺形成连接孔图案210。如图11所示，以所述第一光刻胶层208为阻挡材料，刻蚀所述抗反射层206和介电层204，在所述介电层204中形成连接孔210a，所述连接孔210a底部露出所述含氮的高应力介质层202表面。As shown in FIG. 10 , ananti-reflection layer 206 is spin-coated on thedielectric layer 204 , afirst photoresist layer 208 is spin-coated on theanti-reflection layer 206 , and aconnection hole pattern 210 is formed by exposure and development. As shown in FIG. 11, using thefirst photoresist layer 208 as a barrier material, theanti-reflection layer 206 and thedielectric layer 204 are etched to form aconnection hole 210a in thedielectric layer 204, and the connection The bottom of thehole 210a exposes the surface of the nitrogen-containing high-stress medium layer 202 .

如图12所示，通过灰化(Ashing)、清洗等工艺去除所述第一光刻胶层208和抗反射层206。如图13所示，在所述连接孔210a中和介电层204上旋涂牺牲层212，所述牺牲层212可以是光刻胶、抗反射材料等。在所述牺牲层212上旋涂第二光刻胶层214，并曝光显影生成沟槽图案216。As shown in FIG. 12 , thefirst photoresist layer 208 and theanti-reflection layer 206 are removed by ashing, cleaning and other processes. As shown in FIG. 13 , asacrificial layer 212 is spin-coated in theconnection hole 210 a and on thedielectric layer 204 , and thesacrificial layer 212 may be photoresist, anti-reflection material, or the like. Asecond photoresist layer 214 is spin-coated on thesacrificial layer 212 , exposed and developed to generate agroove pattern 216 .

如图14所示，通过刻蚀将所述沟槽图案216转移到所述介电层204上形成沟槽216a，去除所述第二光刻胶层214和牺牲层212。如图15所示，刻蚀所述连接孔210a底部的含氮的高应力介质层202至所述金属导线层200a、200b表面露出。如图16所示，在所述连接孔210a和沟槽216a中填充金属材料，例如铜。本发明中通过在形成膜层202时提高氮的含量，减少氢的含量，提高了膜层的应力从而提高了膜层的击穿电压。进一步的，提高了形成的器件的耐压能力和稳定性。As shown in FIG. 14 , thetrench pattern 216 is transferred to thedielectric layer 204 by etching to form atrench 216 a, and thesecond photoresist layer 214 and thesacrificial layer 212 are removed. As shown in FIG. 15 , the nitrogen-containing high-stress medium layer 202 at the bottom of theconnection hole 210 a is etched to expose the surface of the metal wire layers 200 a and 200 b. As shown in FIG. 16 , the connection holes 210 a and thegrooves 216 a are filled with metal materials, such as copper. In the present invention, by increasing the content of nitrogen and reducing the content of hydrogen when forming thefilm layer 202, the stress of the film layer is increased, thereby increasing the breakdown voltage of the film layer. Further, the withstand voltage capability and stability of the formed device are improved.

本发明虽然以较佳实施例公开如上，但其并不是用来限定本发明，任何本领域技术人员在不脱离本发明的精神和范围内，都可以做出可能的变动和修改，因此本发明的保护范围应当以本发明权利要求所界定的范围为准。Although the present invention is disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make possible changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection should be based on the scope defined by the claims of the present invention.

Claims (10)

1, a kind of formation method of dual-damascene structure comprises:

The semiconductor substrate is provided, in the described semiconductor-based end, is formed with metal carbonyl conducting layer;

To carrying out the plasma surface preliminary treatment in the described semiconductor-based end;

Carry out after the described plasma surface preliminary treatment, on the described semiconductor-based end, form nitrogenous heavily stressed dielectric layer;

On described heavily stressed dielectric layer, form dielectric layer;

In described dielectric layer, form opening;

Wherein, described heavily stressed dielectric layer is a silicon nitride, and the reacting gas that forms described silicon nitride comprises silane, ammonia and nitrogen;

Described silane flow rate is 420 to 490sccm, and ammonia flow is 100 to 200sccm;

The flow of nitrogen is 15000 to 20000sccm.

2, the formation method of dual-damascene structure as claimed in claim 1 is characterized in that: described metal carbonyl conducting layer material comprises a kind of or its combination in copper, aluminium, titanium, titanium nitride, the tungsten.

3, the formation method of dual-damascene structure as claimed in claim 1 is characterized in that: the formation method of described heavily stressed dielectric layer comprises a kind of in physical vapour deposition (PVD), plasma enhanced chemical vapor deposition, low-pressure chemical vapor deposition, high density plasma CVD, the ald.

4, the formation method of dual-damascene structure as claimed in claim 3 is characterized in that: the radio frequency source power that forms described silicon nitride is 800 to 960 watts.

5, the formation method of dual-damascene structure as claimed in claim 1 is characterized in that: the ambient pressure that forms described silicon nitride is 3 to 5 holders, and temperature is 300 to 600 ℃.

6, the formation method of dual-damascene structure as claimed in claim 1 is characterized in that: described dielectric layer comprises a kind of or its combination in black diamond, fluorine silex glass, phosphorosilicate glass, Pyrex, boron-phosphorosilicate glass, silica, silicon nitride, the carborundum.

7, the formation method of dual-damascene structure as claimed in claim 1, it is characterized in that: this method further comprises: fill metal material in described opening.

8, the formation method of dual-damascene structure as claimed in claim 1 is characterized in that, to carrying out in the pretreated step of plasma surface at the described semiconductor-based end, the source gas that forms plasma is ammonia.

9, the formation method of dual-damascene structure as claimed in claim 8 is characterized in that, to carrying out in the pretreated step of plasma surface at the described semiconductor-based end, the assist gas that forms plasma comprises nitrogen.

10, as the formation method of the described dual-damascene structure of the arbitrary claim of claim 1 to 9, it is characterized in that: the step that carried out the pretreated step of plasma surface and form nitrogenous heavily stressed dielectric layer on the described semiconductor-based end at the described semiconductor-based end is carried out at same chamber.

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