CN100561729C - Fabrication method of dual damascene structure - Google Patents

Abstract

Translated fromChinese

一种双镶嵌结构的制造方法，包括：提供一表面具有第一介质层的半导体衬底；在所述第一介质层中形成金属互连线；在所述第一介质层和所述导电结构层表面形成覆盖层；在所述覆盖层上形成第二介质层并在所述第二介质层中形成连接孔；在所述第二介质层上形成底部抗反射层、遮挡层和光致抗蚀剂层；刻蚀所述底部抗反射层、遮挡层和光致抗蚀剂层，以及所述覆盖层直至露出所述金属互连线；填充金属材料形成双镶嵌结构。本发明的方法在第二介质层上覆盖的底部抗反射层表面淀积一层致密的遮挡层，这层遮挡层能够阻止覆盖层中的氮离子与光致抗蚀剂接触，从而避免了光致抗蚀剂中毒现象的发生。

A method for manufacturing a dual damascene structure, comprising: providing a semiconductor substrate with a first dielectric layer on the surface; forming metal interconnection lines in the first dielectric layer; A covering layer is formed on the surface of the layer; a second dielectric layer is formed on the covering layer and a connection hole is formed in the second dielectric layer; a bottom anti-reflection layer, a shielding layer and a photoresist are formed on the second dielectric layer agent layer; etching the bottom anti-reflection layer, shielding layer and photoresist layer, and the covering layer until the metal interconnection line is exposed; filling metal material to form a dual damascene structure. The method of the present invention deposits a dense shielding layer on the surface of the bottom antireflection layer covered on the second dielectric layer, and this layer of shielding layer can prevent the nitrogen ions in the covering layer from contacting the photoresist, thereby avoiding the photoresist. lead to the occurrence of resist poisoning.

Description

Translated fromChinese

双镶嵌结构的制造方法Fabrication method of dual damascene structure

技术领域technical field

本发明涉及半导体制造技术领域，特别涉及一种双镶嵌结构(dualdamascene structure)的制造方法。The invention relates to the technical field of semiconductor manufacturing, in particular to a method for manufacturing a dual damascene structure.

背景技术Background technique

当今半导体器件制造技术飞速发展，半导体器件已经具有深亚微米结构，集成电路中包含巨大数量的半导体元件。在如此大规模集成电路中，元件之间的高性能、高密度的连接不仅在单个互连层中互连，而且要在多层之间进行互连。因此，通常提供多层互连结构，其中多个互连层互相堆叠，并且层间绝缘膜置于其间，用于连接半导体元件。特别是利用双镶嵌(dual-damascene)工艺形成的多层互连结构，其预先在层间绝缘膜中形成沟槽(trench)和连接孔(via)，然后用导电材料例如铜(Cu)填充所述沟槽和连接孔。这种互连结构已经在集成电路制造中得到广泛应用。Today's semiconductor device manufacturing technology is developing rapidly, semiconductor devices already have a deep submicron structure, and integrated circuits contain a huge number of semiconductor components. In such large-scale integrated circuits, high-performance, high-density connections between components are not only interconnected in a single interconnect layer, but also interconnected between multiple layers. Therefore, a multilayer interconnection structure is generally provided in which a plurality of interconnection layers are stacked on each other with an interlayer insulating film interposed therebetween for connecting semiconductor elements. In particular, a multilayer interconnection structure formed using a dual-damascene process, which preforms a trench (trench) and a connection hole (via) in an interlayer insulating film, and then fills it with a conductive material such as copper (Cu) The grooves and connecting holes. This interconnect structure has been widely used in the manufacture of integrated circuits.

双镶嵌工艺的技术重点在于蚀刻填充导体金属用的沟槽刻蚀技术。在双镶嵌工艺的前段蚀刻工艺中，目前存在两种方法制作双镶嵌构造的沟槽，第一种方法是先在介电层的上部定义出导线沟槽，之后利用另一光刻胶层定义介层窗开口。另一种方法是首先在介电层中定义出完全穿透介电层的介层窗开口，然后利用另一光刻胶层定义导线沟槽。但无论是哪种方法，都需要在衬底表面和层间介电层(ILD)之间形成一层含氮的覆盖层。The technical focus of the dual damascene process is the trench etch technique used to etch the metal that fills the conductor. In the front-end etching process of the dual damascene process, there are currently two methods for making trenches with a dual damascene structure. The first method is to first define a wire trench on the upper part of the dielectric layer, and then use another photoresist layer to define Vial opening. Another method is to first define a via opening in the dielectric layer that completely penetrates the dielectric layer, and then use another photoresist layer to define the wiring trench. But no matter which method is used, it is necessary to form a nitrogen-containing capping layer between the substrate surface and the interlayer dielectric layer (ILD).

随着器件的特征尺寸不断缩小，衬底中器件的密集程度越来越高，对集成电路的性能尤其是射频条件下的高速处理信号的性能提出了更高的要求。为了降低射频信号在电路中的延迟，目前普遍采用低介电常数(low k)材料作为层间介电层(ILD)，以降低电路中的RC延迟。然而，由于low k材料的密度较低，低密度介电材料的大量使用对制造双镶嵌结构会带来一些负面问题。例如，申请号为200510056297.4的中国专利申请中描述了一种双镶嵌结构的制造方法。图1至图5为说明该现有制造双镶嵌结构方法的剖面示意图。如图1至图5所示，图1中，在形成双镶嵌结构时，通常要在具有互连线12a和12b的衬底10表面和ILD层14之间形成由SiCN或Si₃N₄组成的覆盖层13。该覆盖层可防止衬底中互连线12a和12b中的金属铜扩散到ILD层14中，亦可防止刻蚀过程中互连线12a和12b不被刻蚀。图2中，在ILD层14中利用光刻、刻蚀等工艺形成连接孔15a和15b，之后，在图3中，于ILD层上表面覆盖底部抗反射层(BARC)16。然后，如图4所示，在BARC层16表面涂布光致抗蚀剂，并通过曝光、显影，形成图案化的光致抗蚀剂17a和17b。在这个过程中，尤其是在后续刻蚀BARC层16以形成沟槽的过程中，如图5所示，覆盖层13中的氮离子会穿过低密度的ILD层14和BARC层16与光致抗蚀剂17a和17b发生反应，在光致抗蚀剂侧壁上形成难溶的高分子聚合物“肿块”18a和18b，本文将这种现象称为“光致抗蚀剂中毒(resist poisoning)”。光致抗蚀剂中毒现象会导致沟槽图形出现缺陷。As the feature size of devices continues to shrink, the density of devices in the substrate is getting higher and higher, which puts forward higher requirements on the performance of integrated circuits, especially the performance of high-speed signal processing under radio frequency conditions. In order to reduce the delay of radio frequency signals in the circuit, low dielectric constant (low k) materials are generally used as the interlayer dielectric layer (ILD) to reduce the RC delay in the circuit. However, due to the low density of low k materials, the extensive use of low-density dielectric materials will bring some negative problems to the fabrication of dual damascene structures. For example, Chinese patent application No. 200510056297.4 describes a method for manufacturing a dual damascene structure. 1 to 5 are schematic cross-sectional views illustrating the conventional method for manufacturing a dual damascene structure. As shown in FIGS. 1 to 5 , in FIG. 1 , when forming a dual damascene structure, it is usually necessary to form a layer composed of SiCN or Si₃ N₄ between the surface of thesubstrate 10 withinterconnect lines 12 a and 12 b and theILD layer 14 . The coveringlayer 13. The covering layer can prevent the metal copper in theinterconnection lines 12a and 12b in the substrate from diffusing into theILD layer 14, and can also prevent theinterconnection lines 12a and 12b from being etched during the etching process. In FIG. 2,connection holes 15a and 15b are formed in theILD layer 14 by photolithography, etching, etc., and then, in FIG. Then, as shown in FIG. 4 , a photoresist is coated on the surface of theBARC layer 16 , and patternedphotoresists 17 a and 17 b are formed by exposure and development. In this process, especially in the subsequent process of etching the BARClayer 16 to form a trench, as shown in FIG. The resists 17a and 17b react to form insoluble polymer "lumps" 18a and 18b on the sidewalls of the photoresist. This phenomenon is referred to as "photoresist poisoning" herein. poisoning)". The phenomenon of photoresist poisoning can cause defects in the trench pattern.

发明内容Contents of the invention

因此，本发明的目的在于提供一种双镶嵌结构的制造方法，能够消除光致抗蚀剂中毒现象的发生。Therefore, the object of the present invention is to provide a method for manufacturing a dual damascene structure, which can eliminate the phenomenon of photoresist poisoning.

为达到上述目的，本发明提供了一种双镶嵌结构的制造方法，包括：To achieve the above object, the present invention provides a method for manufacturing a dual damascene structure, comprising:

提供一表面具有第一介质层的半导体衬底；providing a semiconductor substrate with a first dielectric layer on its surface;

在所述第一介质层中形成金属互连线；forming metal interconnection lines in the first dielectric layer;

在所述第一介质层和所述导电结构层表面形成覆盖层；forming a cover layer on the surface of the first dielectric layer and the conductive structure layer;

在所述覆盖层上形成第二介质层并在所述第二介质层中形成连接孔；forming a second dielectric layer on the cover layer and forming connection holes in the second dielectric layer;

在所述第二介质层上形成三层结构；forming a three-layer structure on the second dielectric layer;

刻蚀所述三层结构和所述覆盖层直至露出所述金属互连线；etching the three-layer structure and the covering layer until the metal interconnection lines are exposed;

填充金属材料形成双镶嵌结构。The filling metal material forms a dual damascene structure.

所述三层结构包括底部抗反射层、遮挡层和光致抗蚀剂层，所述底部抗反射层覆盖所述第二介质层的表面，所述遮挡层形成于所述抗反射层表面，所述光致抗蚀剂层构图于所述遮挡层表面。The three-layer structure includes a bottom antireflection layer, a shielding layer and a photoresist layer, the bottom antireflection layer covers the surface of the second dielectric layer, the shielding layer is formed on the surface of the antireflection layer, and the The photoresist layer is patterned on the surface of the shielding layer.

所述遮挡层为利用等离子增强化学气相淀积工艺在150℃～300℃的温度范围内淀积形成。The shielding layer is formed by depositing in a temperature range of 150° C. to 300° C. by using a plasma-enhanced chemical vapor deposition process.

所述遮挡层为富硅聚合物，利用旋涂(spin-on)工艺形成，厚度为

The shielding layer is a silicon-rich polymer, formed by a spin-on process, with a thickness of

所述遮挡层为氧化硅，厚度为

The shielding layer is silicon oxide with a thickness of

所述第二介质层为碳氧化硅(SiCO)，氧化硅或氟化硅玻璃，厚度为The second dielectric layer is silicon oxycarbide (SiCO), silicon oxide or fluorinated silicon glass, with a thickness of

所述覆盖层为氮化硅或氮氧化硅或氮碳氧化硅，厚度为

The covering layer is silicon nitride or silicon oxynitride or silicon oxycarbide, with a thickness of

位于所述第二介质层表面上的所述底部抗反射层的厚度为

The thickness of the bottom anti-reflection layer located on the surface of the second medium layer is

所述光致抗蚀剂层的厚度为

The thickness of the photoresist layer is

本发明具有相同或相应技术特征的另一种双镶嵌结构的制造方法，包括：Another method for manufacturing a dual damascene structure of the present invention having the same or corresponding technical features, comprising:

提供一表面具有介质层的半导体衬底，在所述介质层中形成金属互连线；providing a semiconductor substrate with a dielectric layer on the surface, forming metal interconnection lines in the dielectric layer;

平坦化所述介质层和所述金属互连线；planarizing the dielectric layer and the metal interconnection;

在所述介质层和所述导电结构层表面形成覆盖层；forming a cover layer on the surface of the dielectric layer and the conductive structure layer;

在所述覆盖层上形成层间介电层，在所述层间介电层中形成连接孔；forming an interlayer dielectric layer on the cover layer, and forming connection holes in the interlayer dielectric layer;

在具有连接孔的层间介电层上覆盖底部抗反射层；Covering the bottom anti-reflection layer on the interlayer dielectric layer with the connection hole;

在所述底部抗反射层表面形成遮挡层；forming a shielding layer on the surface of the bottom antireflection layer;

在所述遮挡层表面涂覆光致抗蚀剂并图案化所述光至抗蚀剂以定义沟槽开口；coating a photoresist on the surface of the shielding layer and patterning the photoresist to define a trench opening;

刻蚀所述光至抗蚀剂和所述遮挡层；etching the photoresist and the masking layer;

刻蚀所述遮挡层、底部抗反射层和层间介电层；etching the blocking layer, bottom anti-reflection layer and interlayer dielectric layer;

去除剩余的底部抗反射层和沟槽底部对应所述互连线位置的覆盖层；removing the remaining bottom anti-reflection layer and the covering layer at the bottom of the trench corresponding to the position of the interconnection line;

然后向连接孔和沟槽中填充金属便形成了双镶嵌结构。Metal is then filled into the vias and trenches to form a dual damascene structure.

所述遮挡层利用等离子增强化学气相淀积工艺在150℃～300℃的温度范围内形成。The shielding layer is formed at a temperature range of 150° C. to 300° C. by using a plasma-enhanced chemical vapor deposition process.

所述遮挡层为信越(Shinetzu)公司商标为SHB的富硅聚合物利用旋涂(spin-on)工艺形成，厚度为

The shielding layer is formed by a spin-on process using a silicon-rich polymer whose trademark is SHB of Shinetzu (Shinetzu) Co., Ltd., with a thickness of

所述遮挡层为氧化硅，厚度为

The shielding layer is silicon oxide with a thickness of

所述层间介质层为应用材料(Applied Materials)公司商标为黑钻石的碳氧化硅(SiCO)、氧化硅或氟化硅玻璃，厚度为

The interlayer dielectric layer is silicon oxycarbide (SiCO), silicon oxide or silicon fluoride glass with a trademark of Applied Materials (Applied Materials) company Black Diamond, with a thickness of

所述覆盖层为氮化硅或氮氧化硅或氮碳氧化硅，厚度为

The covering layer is silicon nitride or silicon oxynitride or silicon oxycarbide, with a thickness of

位于所述第二介质层表面上的所述底部抗反射层的厚度为

The thickness of the bottom anti-reflection layer located on the surface of the second medium layer is

所述光致抗蚀剂的厚度为

The thickness of the photoresist is

与现有技术相比，本发明具有以下优点：Compared with the prior art, the present invention has the following advantages:

本发明的双镶嵌结构的制造方法在ILD上覆盖的BARC层表面淀积一层致密的遮挡层。这层遮挡层能够阻止覆盖层中的氮离子与光致抗蚀剂接触，从而防止了光致抗蚀剂中毒现象的发生。同时，该遮挡层还可作为沟槽刻蚀过程中的硬掩膜层，在利用BARC层作为刻蚀牺牲层时，结合硬掩膜层的作用，可以一次刻蚀形成双镶嵌结构。而且，光致抗蚀剂在刻蚀过程中已被去除，刻蚀后仅需去除剩余的BARC，简化了制造工艺。此外，由于上述遮挡层的硬掩膜作用，光致抗蚀剂无需涂布的很厚，有利于进一步提高刻蚀分辨率。In the manufacturing method of the double damascene structure of the present invention, a dense shielding layer is deposited on the surface of the BARC layer covered on the ILD. This shielding layer can prevent the nitrogen ions in the cover layer from contacting the photoresist, thereby preventing the occurrence of photoresist poisoning. At the same time, the shielding layer can also be used as a hard mask layer in the trench etching process. When the BARC layer is used as an etching sacrificial layer, combined with the function of the hard mask layer, a dual damascene structure can be formed by one-time etching. Moreover, the photoresist has been removed during the etching process, and only the remaining BARC needs to be removed after etching, which simplifies the manufacturing process. In addition, due to the hard mask function of the shielding layer, the photoresist does not need to be coated very thick, which is beneficial to further improve the etching resolution.

附图说明Description of drawings

图1至图5为说明现有制造双镶嵌结构方法的剖面示意图；1 to 5 are schematic cross-sectional views illustrating a conventional method for manufacturing a dual damascene structure;

图6至图10为根据本发明实施例的双镶嵌结构制造方法的剖面示意图；6 to 10 are schematic cross-sectional views of a method for manufacturing a dual damascene structure according to an embodiment of the present invention;

图11为本发明双镶嵌结构制造方法的流程图。FIG. 11 is a flow chart of the method for manufacturing the dual damascene structure of the present invention.

具体实施方式Detailed ways

为使本发明的上述目的、特征和优点能够更加明显易懂，下面结合附图对本发明的具体实施方式做详细的说明。In order to make the above objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings.

本发明的双镶嵌结构的制造方法在层间介质层上覆盖的底部抗反射层表面淀积了一层致密的遮挡层，以阻止覆盖层中的氮离子与光致抗蚀剂接触，从而防止了光致抗蚀剂中毒现象的发生。In the manufacturing method of the dual damascene structure of the present invention, a dense shielding layer is deposited on the surface of the bottom anti-reflection layer covered on the interlayer dielectric layer to prevent nitrogen ions in the covering layer from contacting the photoresist, thereby preventing The occurrence of photoresist poisoning phenomenon.

图6至图10为根据本发明实施例的双镶嵌结构制造方法的剖面示意图。首先，如图6所示，并参照图1、图2和图3，所述示意图只是实例，其在此不应过度限制本发明保护的范围。在半导体衬底10表面利用化学汽相淀积(CVD)方法形成第一介质层，也就是金属间介电层11。介电层的材料可为氧化硅。在介电层11中通过光刻、刻蚀工艺形成例如铜导线构成的导电连线12a和12b。利用化学机械研磨(CMP)工艺将介电层11和铜导电连线12a和12b表面磨平；然后，利用CVD工艺，在上述介电层11和铜导电连线12a和12b表面淀积由氮化硅组成的覆盖层13，覆盖层13可为氮化硅(Si₃N₄)或氮氧化硅(SiON)，或氮碳氧化硅(SiOCN)厚度为上述覆盖层13一方面作为导电连线12a和12b中铜的扩散覆盖层，另一方面在后续刻蚀连接孔的步骤中被当作蚀刻停止层。接着，在上述覆盖层13表面淀积形成厚度

的第二介质层，也就是层间介电层14，如图1所示。上述沉积的层间介电层14是由化学气相淀积法沉积的低介电常数的无机硅基质层(Inorganic silicon based layer)，例如应用材料(Applied Materials)公司商标为黑钻石(black diamond)的二氧化硅(SiO₂)、碳氧化硅(SiCO)或氟化硅玻璃(FSG)。6 to 10 are schematic cross-sectional views of a method for manufacturing a dual damascene structure according to an embodiment of the present invention. First, as shown in FIG. 6 , and with reference to FIG. 1 , FIG. 2 and FIG. 3 , the schematic diagram is just an example, which should not limit the protection scope of the present invention excessively. A first dielectric layer, that is, anintermetallic dielectric layer 11 is formed on the surface of thesemiconductor substrate 10 by chemical vapor deposition (CVD). The material of the dielectric layer can be silicon oxide.Conductive connections 12 a and 12 b made of, for example, copper wires are formed in thedielectric layer 11 by photolithography and etching processes. Utilize the chemical mechanical polishing (CMP) process to grind thedielectric layer 11 and thecopper conductive wiring 12a and 12b surface; Thecover layer 13 composed of silicon oxide, thecover layer 13 can be silicon nitride (Si₃ N₄ ) or silicon oxynitride (SiON), or silicon oxynitride carbon (SiOCN) with a thickness of The above-mentionedcovering layer 13 serves as a covering layer for copper diffusion in theconductive lines 12a and 12b on the one hand, and serves as an etching stop layer in the subsequent step of etching connection holes on the other hand. Next, deposit on the surface of the above-mentionedcovering layer 13 to form a thickness

The second dielectric layer, that is, theinterlayer dielectric layer 14, as shown in FIG. 1 . Theinterlayer dielectric layer 14 deposited above is an inorganic silicon base layer (Inorganic silicon based layer) with a low dielectric constant deposited by chemical vapor deposition, for example, the trademark of Applied Materials is black diamond (black diamond). silicon dioxide (SiO₂ ), silicon oxycarbide (SiCO) or fluorinated silicon glass (FSG).

利用光刻、刻蚀等工艺在层间介电层14中形成连接孔15a和15b，如图2所示。然后，在层间介电层14表面涂覆BARC层16，也就是底部抗反射层。该BARC层16填充进连接孔15a和15b中，所述BARC层在层间介电层14表面上的厚度为

本实施例优选为如图3所示。The connection holes 15 a and 15 b are formed in theinterlayer dielectric layer 14 by photolithography, etching and other processes, as shown in FIG. 2 . Then, aBARC layer 16 is coated on the surface of theinterlayer dielectric layer 14 , that is, a bottom anti-reflection layer. TheBARC layer 16 is filled into the connection holes 15a and 15b, and the thickness of the BARC layer on the surface of theinterlayer dielectric layer 14 is

This embodiment is preferably As shown in Figure 3.

随后，本发明方法在BARC层16表面淀积一层致密的遮挡层19，其厚度在

之间，如图6所示。所述遮挡层19是利用等离子增强化学气相淀积(PECVD)工艺，在低温条件下进行淀积的低温淀积氧化硅(LTO)。上述淀积低温淀积氧化物遮挡层19的工艺温度范围需控制在150℃-300℃之间，本实施例优选为200℃。此外，遮挡层19也可以由富硅聚合物材料，例如信越公司(Shinetzu)的商标为SHB的富硅聚合物材料，在BARC层16表面旋涂(spin on)工艺形成，厚度为

Subsequently, the method of the present invention deposits adense shielding layer 19 on the surface of theBARC layer 16, and its thickness is between

Between, as shown in Figure 6. Theshielding layer 19 is low temperature deposited silicon oxide (LTO) deposited under low temperature conditions by using a plasma enhanced chemical vapor deposition (PECVD) process. The temperature range of the process for depositing the low-temperature depositedoxide shielding layer 19 needs to be controlled between 150°C and 300°C, and in this embodiment, it is preferably 200°C. In addition, theshielding layer 19 can also be made of a silicon-rich polymer material, such as the silicon-rich polymer material of Shinetzu (Shinetzu) whose trademark is SHB, formed by a spin-on process on the surface of theBARC layer 16, with a thickness of

接下来，如图7所示，在遮挡层19涂布光致抗蚀剂，并利用光刻工艺，例如曝光、显影等在光致抗蚀剂的表面形成具有沟槽开口图案的光致抗蚀剂层17a和17b。本实施例中，光致抗蚀剂层17a和17b的厚度为

Next, as shown in FIG. 7, a photoresist is coated on theshielding layer 19, and a photoresist with a groove opening pattern is formed on the surface of the photoresist by using a photolithography process, such as exposure and development. etchant layers 17a and 17b. In the present embodiment, the thickness ofphotoresist layer 17a and 17b is

上述光致抗蚀剂层17a和17b、遮挡层19和BARC层16组成三层结构。遮挡层19能够防止覆盖层13中的氮离子与光致抗蚀剂17a和17b接触，从而防止了光致抗蚀剂中毒现象的发生。同时，该遮挡层19还可作为沟槽刻蚀过程中的硬掩膜层，在利用BARC层16作为刻蚀牺牲层时，结合遮挡层19的掩膜作用，可以一次刻蚀形成双镶嵌结构。而且，光致抗蚀剂17a和17b在刻蚀过程中已被去除，刻蚀后仅需去除剩余的BARC，简化了制造工艺。此外，由于上述遮挡层的硬掩膜作用，光致抗蚀剂无需涂布的很厚，有利于进一步提高刻蚀分辨率。The photoresist layers 17a and 17b, theshielding layer 19 and theBARC layer 16 constitute a three-layer structure. Theshielding layer 19 can prevent nitrogen ions in thecover layer 13 from contacting thephotoresists 17a and 17b, thereby preventing the occurrence of photoresist poisoning. At the same time, theblocking layer 19 can also be used as a hard mask layer in the trench etching process. When using theBARC layer 16 as an etching sacrificial layer, combined with the masking effect of theblocking layer 19, a dual damascene structure can be formed by one etching. . Moreover, thephotoresists 17a and 17b have been removed during the etching process, and only the remaining BARC needs to be removed after etching, which simplifies the manufacturing process. In addition, due to the hard mask function of the shielding layer, the photoresist does not need to be coated very thick, which is beneficial to further improve the etching resolution.

继续参照图8，接下来，利用反应离子刻蚀工艺(reactive ion etching；RIE)，利用光致抗蚀剂17a和17b和遮挡层19作为掩膜，经由光致抗蚀剂17a和17b限定的开口图形进行刻蚀。由于遮挡层19的硬掩膜作用，光致抗蚀剂无需涂布得很厚，有利于进一步提高刻蚀分辨率。在刻蚀过程中，刻蚀剂包括氯气Cl₂、氧气O₂、氮气N₂、氦气He和氧气O₂的混合气体，或者氦气一氧气He-O₂，以及惰性气体或其混合气体(比如氢气Ar、氖气Ne、氦气He等等)，或其组合。流量为40-80sccm，等离子源输出功率200-2000W，衬底温度控制在20℃和80℃之间，腔体压力为5-50mTorr。利用光致抗蚀剂17a和17b为掩膜刻蚀遮挡层19和BARC层16。同时RIE也刻蚀光致抗蚀剂17a和17b。当然，RIE在遮挡层19和BARC层16中的刻蚀速率，与光致抗蚀剂17a和17b中的刻蚀速率稍有差异。当光致抗蚀剂17a和17b被刻蚀到遮挡层19的表面，也就是光致抗蚀剂17a和17b被刻蚀掉时，RIE经开口图形已经将遮挡层19和BARC层16刻蚀到层间介电层14的表面。Continuing to refer to FIG. 8, next, using reactive ion etching (reactive ion etching; RIE), usingphotoresist 17a and 17b and shieldinglayer 19 as a mask, through thephotoresist 17a and 17b defined The opening pattern is etched. Due to the hard mask function of theshielding layer 19, the photoresist does not need to be coated very thick, which is beneficial to further improve the etching resolution. During the etching process, the etchant includes a mixture of chlorine Cl₂ , oxygen O₂ , nitrogen N₂ , helium He and oxygen O₂ , or helium-oxygen He-O₂ , and inert gases or their mixtures. (such as hydrogen Ar, neon Ne, helium He, etc.), or a combination thereof. The flow rate is 40-80sccm, the output power of the plasma source is 200-2000W, the substrate temperature is controlled between 20°C and 80°C, and the chamber pressure is 5-50mTorr. Theshielding layer 19 and theBARC layer 16 are etched using thephotoresists 17a and 17b as masks. At the same time RIE also etches thephotoresists 17a and 17b. Of course, the etching rate of RIE in theshielding layer 19 and theBARC layer 16 is slightly different from the etching rate of thephotoresists 17a and 17b. Whenphotoresists 17a and 17b are etched to the surface of shieldinglayer 19, that is, whenphotoresists 17a and 17b are etched away, RIE has etchedshielding layer 19 andBARC layer 16 through opening patterns to the surface of theinterlayer dielectric layer 14 .

接着，如图9所示，同时刻蚀遮挡层19和BARC层16，遮挡层19兼具掩膜的作用。利用遮挡层19的掩膜作用开始刻蚀层间介电层14。由于遮挡层19是高致密膜，RIE刻蚀对遮挡层19的刻蚀速率较低，而BARC层16为低密度材料，层间介电层14为low k材料，密度较低且质地比较软，RIE对这两种材料的刻蚀速率较高。因此，同时刻蚀遮挡层19、BARC层16和层间介电层14时，BARC层16和层间介电层14被刻蚀的量远大于遮挡层19被刻蚀的量，遮挡层19被完全刻蚀掉后BARC层16和层间介电层14已被刻蚀掉层间介电层14深接近度一半的高度。Next, as shown in FIG. 9 , theshielding layer 19 and theBARC layer 16 are simultaneously etched, and theshielding layer 19 also functions as a mask. Theinterlayer dielectric layer 14 is etched using the masking effect of theshielding layer 19 . Since theshielding layer 19 is a high-density film, the etching rate of theshielding layer 19 is relatively low by RIE etching, while theBARC layer 16 is a low-density material, and theinterlayer dielectric layer 14 is a low k material with low density and relatively soft texture. , RIE has a higher etch rate for these two materials. Therefore, when theshielding layer 19, theBARC layer 16 and theinterlayer dielectric layer 14 are etched simultaneously, the etched amount of theBARC layer 16 and theinterlayer dielectric layer 14 is much greater than the etched amount of theshielding layer 19, and theshielding layer 19 After being completely etched away, theBARC layer 16 and theinterlayer dielectric layer 14 have been etched away to approximately half the height of theinterlayer dielectric layer 14 .

在接下来的工艺步骤中，如图10所示，利用湿法腐蚀工艺或氧气等离子灰化工艺(ashing)去除层间介电层14表面和沟槽中剩余的BARC层16，以露出沟槽底部的覆盖层13。最后，利用PECVD工艺，将衬底10的介电层11中导电连线12a和12b对应的覆盖层13的部分移除，以便露出导电连线12a和12b，然后向连接孔和沟槽中填充金属便形成了双镶嵌结构。In the next process step, as shown in FIG. 10, a wet etching process or an oxygen plasma ashing process (ashing) is used to remove the surface of theinterlayer dielectric layer 14 and the remainingBARC layer 16 in the trench to expose the trench.Bottom cover layer 13. Finally, using a PECVD process, the part of thecover layer 13 corresponding to theconductive wires 12a and 12b in thedielectric layer 11 of thesubstrate 10 is removed, so that theconductive wires 12a and 12b are exposed, and then the connection holes and trenches are filled. The metal forms a dual damascene structure.

图11为本发明双镶嵌结构制造方法的流程图。如图11所示，本发明的双镶嵌结构的制造方法包括：提供一表面具有介质层的半导体衬底，在所述介质层中形成金属互连线(S101)；平坦化所述介质层和所述金属互连线(S102)；在所述介质层和所述导电结构层表面形成由氮化硅(Si₃N₄)或氮氧化硅(SiON)或氮碳化硅(SiCN)组成的覆盖层(S103)，厚度为

在所述覆盖层上形成层间介电层(S104)，层间介电层可由应用材料(AppliedMaterials)公司商标为黑钻石的碳氧化硅(SiCO)，氧化硅或氟化硅玻璃(FSG)组成，层间介电层的厚度为1000-在所述层间介电层中形成连接孔(S105)；在具有连接孔的层间介电层上覆盖底部抗反射层(S106)；在所述底部抗反射层表面淀积形成遮挡层(S107)，所述遮挡层为利用等离子增强化学气相淀积工艺在150℃～300℃的温度范围内淀积形成，或为信越(Shinetzu)公司商标为SHB的富硅聚合物利用旋涂(spin-on)工艺形成，厚度为

涂覆光致抗蚀剂并图案化所述光致抗蚀剂以定义沟槽开口(S108)；刻蚀所述光致抗蚀剂和所述遮挡层(S109)；刻蚀所述遮挡层、底部抗反射层和层间介电层(S110)；去除剩余的底部抗反射层和沟槽底部对应所述互连线位置的覆盖层(S111)，然后向连接孔和沟槽中填充金属便形成了双镶嵌结构。FIG. 11 is a flow chart of the method for manufacturing the dual damascene structure of the present invention. As shown in FIG. 11 , the manufacturing method of the dual damascene structure of the present invention includes: providing a semiconductor substrate with a dielectric layer on the surface, forming metal interconnection lines in the dielectric layer (S101); planarizing the dielectric layer and The metal interconnection line (S102); forming a covering composed of silicon nitride (Si₃ N₄ ) or silicon oxynitride (SiON) or silicon carbide nitride (SiCN) on the surface of the dielectric layer and the conductive structure layer layer (S103) with a thickness of

An interlayer dielectric layer (S104) is formed on the cover layer. The interlayer dielectric layer can be made of silicon oxycarbide (SiCO), silicon oxide or fluorinated silicon glass (FSG) trademarked as black diamond by Applied Materials. composition, the thickness of the interlayer dielectric layer is 1000- Form a connection hole in the interlayer dielectric layer (S105); cover the bottom antireflection layer on the interlayer dielectric layer with the connection hole (S106); deposit and form a shielding layer on the surface of the bottom antireflection layer ( S107), the shielding layer is formed by depositing a plasma-enhanced chemical vapor deposition process in a temperature range of 150° C. to 300° C., or is a silicon-rich polymer whose trademark is SHB of Shinetzu Co., Ltd. by spin coating. -on) process, the thickness is

coating a photoresist and patterning the photoresist to define a trench opening (S108); etching the photoresist and the shielding layer (S109); etching the shielding layer , bottom anti-reflection layer and interlayer dielectric layer (S110); remove the remaining bottom anti-reflection layer and the covering layer at the bottom of the trench corresponding to the position of the interconnect line (S111), and then fill the connection hole and the trench with metal A dual damascene structure is formed.

本发明的双镶嵌结构的制造方法通过在ILD上覆盖的BARC层表面淀积一层致密的遮挡层，能够阻止覆盖层中的氮离子与光致抗蚀剂接触，从而防止了光致抗蚀剂中毒现象的发生。同时，该遮挡层还可作为沟槽刻蚀过程中的硬掩膜层，在利用BARC层作为刻蚀牺牲层时，结合硬掩膜层的作用，可以一次刻蚀形成双镶嵌结构。The manufacturing method of the dual damascene structure of the present invention can prevent the nitrogen ions in the cover layer from contacting the photoresist by depositing a dense shielding layer on the surface of the BARC layer covered on the ILD, thereby preventing the photoresist occurrence of drug poisoning. At the same time, the shielding layer can also be used as a hard mask layer in the trench etching process. When the BARC layer is used as an etching sacrificial layer, combined with the function of the hard mask layer, a dual damascene structure can be formed by one-time etching.

本发明虽然以较佳实施例公开如上，但其并不是用来限定本发明，任何本领域技术人员在不脱离本发明的精神和范围内，都可以做出可能的变动和修改，因此本发明的保护范围应当以本发明权利要求所界定的范围为准。Although the present invention is disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make possible changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection should be based on the scope defined by the claims of the present invention.

Claims (8)

Translated fromChinese

1、一种双镶嵌结构的制造方法，包括：1. A method for manufacturing a dual damascene structure, comprising:提供一表面具有介质层的半导体衬底，在所述介质层中形成金属互连线；providing a semiconductor substrate with a dielectric layer on the surface, forming metal interconnection lines in the dielectric layer;平坦化所述介质层和所述金属互连线；planarizing the dielectric layer and the metal interconnection;在所述介质层和所述金属互连线表面形成覆盖层；forming a covering layer on the surface of the dielectric layer and the metal interconnection;在所述覆盖层上形成层间介电层，在所述层间介电层中形成连接孔；forming an interlayer dielectric layer on the cover layer, and forming connection holes in the interlayer dielectric layer;在具有连接孔的层间介电层上覆盖底部抗反射层；Covering the bottom anti-reflection layer on the interlayer dielectric layer with the connection hole;在所述底部抗反射层表面形成遮挡层；forming a shielding layer on the surface of the bottom antireflection layer;在所述遮挡层表面涂覆光致抗蚀剂并图案化所述光致抗蚀剂以定义沟槽开口；coating a photoresist on the surface of the shielding layer and patterning the photoresist to define a trench opening;用反应离子刻蚀工艺刻蚀所述光致抗蚀剂和遮挡层，继而刻蚀光致抗蚀剂和底部抗反射层，进而刻蚀所述遮挡层、底部抗反射层和层间介电层，直至遮挡层被完全刻蚀掉，此时沟槽开口部分的底部抗反射层和层间介电层已被刻蚀到层间介电层深度接近一半的高度；Etching the photoresist and the shielding layer by reactive ion etching, then etching the photoresist and the bottom antireflection layer, and then etching the shielding layer, the bottom antireflection layer and the interlayer dielectric layer, until the shielding layer is completely etched away, at this time the bottom anti-reflection layer and the interlayer dielectric layer at the opening of the trench have been etched to a height close to half the depth of the interlayer dielectric layer;用湿法腐蚀工艺或氧气等离子灰化工艺去除剩余的底部抗反射层；Remove the remaining bottom anti-reflective layer by wet etching process or oxygen plasma ashing process;去除沟槽底部对应所述互连线位置的覆盖层；removing the covering layer at the bottom of the trench corresponding to the position of the interconnection line;然后向连接孔和沟槽中填充金属便形成了双镶嵌结构。Metal is then filled into the vias and trenches to form a dual damascene structure.2、如权利要求1所述的方法，其特征在于：所述遮挡层为利用等离子增强化学气相淀积工艺在150℃～300℃的温度范围内淀积形成。2. The method according to claim 1, characterized in that: the shielding layer is formed by depositing at a temperature range of 150° C. to 300° C. by using a plasma enhanced chemical vapor deposition process.3、如权利要求1所述的方法，其特征在于：所述遮挡层为富硅聚合物，利用旋涂(spin-on)工艺形成，厚度为

3. The method according to claim 1, characterized in that: the shielding layer is a silicon-rich polymer formed by a spin-on process, with a thickness of

4、如权利要求1或2所述的方法，其特征在于：所述遮挡层为氧化硅，厚度为

4. The method according to claim 1 or 2, characterized in that: the shielding layer is silicon oxide with a thickness of

5、如权利要求1所述的方法，其特征在于：所述层间介电层为碳氧化硅(SiCO)，氧化硅或氟化硅玻璃，厚度为

5. The method according to claim 1, characterized in that: the interlayer dielectric layer is silicon oxycarbide (SiCO), silicon oxide or silicon fluoride glass, with a thickness of

6、如权利要求1所述的方法，其特征在于：所述覆盖层为氮化硅或氮氧化硅或氮碳氧化硅，厚度为

6. The method according to claim 1, characterized in that: the covering layer is silicon nitride or silicon oxynitride or silicon oxycarbide with a thickness of

7、如权利要求1所述的方法，其特征在于：位于所述层间介电层表面上的所述底部抗反射层的厚度为

7. The method of claim 1, wherein the thickness of the bottom anti-reflection layer on the surface of the interlayer dielectric layer is

8、如权利要求1所述的方法，其特征在于：所述光致抗蚀剂层的厚度为

8. The method according to claim 1, wherein the thickness of the photoresist layer is

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