CN100536259C - Method for manufacturing micro connector - Google Patents

Abstract

Translated fromChinese

本发明公开了一种制作微型连接器的方法。提供晶片，在其第一表面形成一介电层。将介电层固定于承载晶片，并进行薄化工艺。将其第二表面固定于承载晶片，并在介电层上形成导线图案。在介电层与导线图案上形成绝缘层，去除部分绝缘层暴露出导线图案，并去除部分介电层与晶片，使晶片分割为多个微型连接器。所述方法有效避免晶片薄化所造成的污染问题。

The present invention discloses a method for manufacturing a micro connector. A wafer is provided, and a dielectric layer is formed on the first surface of the wafer. The dielectric layer is fixed to a carrier wafer and subjected to a thinning process. The second surface of the wafer is fixed to a carrier wafer, and a conductor pattern is formed on the dielectric layer. An insulating layer is formed on the dielectric layer and the conductor pattern, a portion of the insulating layer is removed to expose the conductor pattern, and a portion of the dielectric layer and the wafer is removed to divide the wafer into a plurality of micro connectors. The method effectively avoids the pollution problem caused by wafer thinning.

Description

Translated fromChinese

制作微型连接器的方法How to Make Micro Connectors

技术领域technical field

本发明涉及一种制作微型连接器的方法，特别是涉及一种预先将晶片薄化至预定厚度后，再制作导线图案的方法，故可有效避免晶片薄化所造成的污染问题。The invention relates to a method for making a micro-connector, in particular to a method for making a wire pattern after pre-thinning a chip to a predetermined thickness, so that the pollution problem caused by the thinning of the chip can be effectively avoided.

背景技术Background technique

就目前电子产品的发展趋势而言，电子产品的多功能化与微型化已成为主要的方向，且其多功能的表现往往需要结合多个芯片的运作方可达成，然而各芯片之间的连接若透过印刷电路板的电路配局加以达成，势必造成电子产品的体积的增加，因此目前的封装方式均朝向系统封装(system in package，SIP)的方向进行。系统封装主要的概念利用连接器为媒介，将多个欲整合应用并互相连接的芯片装设于其上，并将上述芯片与连接器一并封装成系统封装结构，而各芯片之间则利用连接器内部所设置的导线图案加以电连接。As far as the current development trend of electronic products is concerned, the multi-functionalization and miniaturization of electronic products has become the main direction, and its multi-functional performance often needs to be achieved by combining the operation of multiple chips. However, the connection between each chip If it is achieved through the circuit layout of the printed circuit board, it will inevitably increase the volume of the electronic product. Therefore, the current packaging methods are all oriented towards the system in package (SIP) direction. The main concept of system packaging uses connectors as a medium to install multiple chips that are to be integrated and connected to each other, and package the above-mentioned chips and connectors together into a system package structure. The wire patterns provided inside the connector are electrically connected.

由于连接器的尺寸会影响系统封装结构的体积，因此现有制作连接器的方法在制作出连接器内部的导线图案后，会对连接器进行研磨工艺以降低连接器的厚度，进而缩减系统封装结构的体积。然而，此作法会增加导线图案受污染的机率，而降低工艺成品率。Since the size of the connector will affect the volume of the system package structure, the existing method of making the connector will grind the connector after making the wire pattern inside the connector to reduce the thickness of the connector, thereby reducing the system package The volume of the structure. However, this method will increase the possibility of contamination of the wire pattern and reduce the yield of the process.

发明内容Contents of the invention

本发明的目的之一在于提供一种制作高密度微型连接器的方法，以缩减系统封装结构的体积。One of the objectives of the present invention is to provide a method for manufacturing a high-density micro-connector, so as to reduce the volume of the system packaging structure.

为达上述目的，本发明提供一种制作微型连接器的方法。根据本发明的方法，首先提供晶片，该晶片包括第一表面与第二表面。接着在该晶片的该第一表面上形成介电层，并利用第一黏着层接合该介电层与承载晶片。随后进行薄化工艺，由该晶片的该第二表面薄化该晶片，再移除该第一黏着层，并将利用第二黏着层接合该晶片的该第二表面与该承载晶片。接着在该介电层上形成导线图案，并在该介电层与该导线图案上形成绝缘层。然后在该绝缘层上形成屏蔽图案，该屏蔽图案包括对应于该导线图案的多个第一开口，以及定义出切割道图案的多个第二开口。随后去除所述第一开口暴露出的该绝缘层，以暴露出该导线图案，并去除该第二开口所暴露出的该绝缘层、该介电层与该晶片，使该晶片分割为多个微型连接器。最后再移除该屏蔽图案，以及该第二黏着层。To achieve the above purpose, the present invention provides a method for making a micro connector. According to the method of the present invention, firstly, a wafer is provided, and the wafer includes a first surface and a second surface. Then a dielectric layer is formed on the first surface of the wafer, and the dielectric layer is bonded with the carrier wafer by using the first adhesive layer. Then perform a thinning process to thin the wafer from the second surface of the wafer, remove the first adhesive layer, and use the second adhesive layer to bond the second surface of the wafer and the carrier wafer. Then a wire pattern is formed on the dielectric layer, and an insulating layer is formed on the dielectric layer and the wire pattern. A shielding pattern is then formed on the insulating layer, the shielding pattern includes a plurality of first openings corresponding to the wire pattern, and a plurality of second openings defining a scribe pattern. Then remove the insulating layer exposed by the first opening to expose the wire pattern, and remove the insulating layer, the dielectric layer and the wafer exposed by the second opening, so that the wafer is divided into a plurality of micro connector. Finally, the shielding pattern and the second adhesive layer are removed.

为了进一步了解本发明的特征及技术内容，请参阅以下有关本发明的详细说明与附图。然而附图仅供参考与辅助说明用，并非用来对本发明加以限制。In order to further understand the features and technical content of the present invention, please refer to the following detailed description and accompanying drawings of the present invention. However, the drawings are only for reference and auxiliary description, and are not intended to limit the present invention.

附图说明Description of drawings

图1至图16为本发明一优选实施例制作微型连接器的方法示意图。1 to 16 are schematic diagrams of a method for manufacturing a micro connector according to a preferred embodiment of the present invention.

简单符号说明simple notation

10    晶片        12    第一表面10wafer 12 first surface

14    第二表面    16    介电层14second surface 16 dielectric layer

18    第一黏着层  20    承载晶片18 firstadhesive layer 20 carrier chip

22    第二黏着层  24    导电层22 second adhesive layer 24 conductive layer

26    屏蔽图案    28    导线图案26Shield Pattern 28 Conductor Pattern

30    绝缘层      32    屏蔽图案30insulation layer 32 shielding pattern

34    第一开口    36    第二开口34 First opening 36 Second opening

38    微型连接器38 micro connector

具体实施方式Detailed ways

请参考图1至图16。图1至图16为本发明一优选实施例制作微型连接器的方法示意图。如图1所示，首先提供晶片10，例如硅晶片，且晶片10包括第一表面12与第二表面14。如图2所示，在晶片10的第一表面12上形成介电层16。在本实施例中，介电层16为热氧化方式形成的氧化层，其作用在提供绝缘效果，以避免漏电流问题，然介电层16的形成方式与材料并不限，例如可为沉积氧化层或由其它绝缘材料所构成。Please refer to Figure 1 to Figure 16. 1 to 16 are schematic diagrams of a method for manufacturing a micro connector according to a preferred embodiment of the present invention. As shown in FIG. 1 , firstly, awafer 10 is provided, such as a silicon wafer, and thewafer 10 includes afirst surface 12 and asecond surface 14 . As shown in FIG. 2 , adielectric layer 16 is formed on thefirst surface 12 of thewafer 10 . In this embodiment, thedielectric layer 16 is an oxide layer formed by thermal oxidation, and its function is to provide an insulating effect to avoid the problem of leakage current. However, the formation method and material of thedielectric layer 16 are not limited, for example, it can be deposited The oxide layer may be made of other insulating materials.

如图3所示，对晶片10的第二表面14进行初步(preliminary)薄化工艺，例如利用粗磨(grinding)方式在不造成晶片10损坏的前提下，将晶片10的厚度迅速缩减至适当厚度。如图4所示，接着利用第一黏着层18接合介电层16与承载晶片20，使晶片10固定于承载晶片20上。在本实施例中，承载晶片20可为硅晶片、玻璃晶片、石英晶片或塑料晶片。第一黏着层18选用热释放胶带或紫外线胶带，其优点在于热释放胶带或紫外线胶带可在后续工艺中轻易利用加热或照射紫外线的方式被去除，但第一黏着层18并不限于使用上述材料，而亦可为如光致抗蚀剂、腊或聚酰亚胺(polyimide)等材料。As shown in FIG. 3 , a preliminary (preliminary) thinning process is performed on thesecond surface 14 of thewafer 10, such as using a rough grinding (grinding) method to quickly reduce the thickness of thewafer 10 to an appropriate level without causing damage to thewafer 10. thickness. As shown in FIG. 4 , thedielectric layer 16 and thecarrier chip 20 are then bonded with the firstadhesive layer 18 to fix thechip 10 on thecarrier chip 20 . In this embodiment, thecarrier wafer 20 can be a silicon wafer, a glass wafer, a quartz wafer or a plastic wafer. The firstadhesive layer 18 is selected from thermal release tape or ultraviolet tape, and its advantage is that the thermal release tape or ultraviolet tape can be easily removed by heating or irradiating ultraviolet rays in the subsequent process, but the firstadhesive layer 18 is not limited to the use of the above materials , and can also be materials such as photoresist, wax or polyimide.

如图5所示，接着进行薄化工艺，由晶片10的第二表面14全面性地薄化晶片10。薄化工艺可视晶片10的最终厚度需求、表面特性需求与应力考虑等而采用不同的方法进行。举例来说，可利用等离子体蚀刻工艺全面性地薄化晶片10，由此降低先前由于粗磨工艺所产生的应力，或利用化学蚀刻工艺蚀使晶片10的第二表面14满足对于表面粗糙度的需求，亦或是利用研磨抛光(polish)工艺使晶片10的第二表面14具有所需的表面光滑度。当然，薄化工艺并不限定单独使用上述任一方式，而可视实际状况进行上述工艺的组合，或是使用其它薄化技术，例如化学机械抛光(CMP)工艺。As shown in FIG. 5 , a thinning process is performed next, and thewafer 10 is thinned from thesecond surface 14 of thewafer 10 comprehensively. The thinning process can be performed in different ways depending on the final thickness requirements, surface property requirements, and stress considerations of thewafer 10 . For example, the plasma etching process can be used to thin thewafer 10 comprehensively, thereby reducing the stress previously generated by the rough grinding process, or the chemical etching process can be used to etch thesecond surface 14 of thewafer 10 to meet the surface roughness requirements. requirements, or thesecond surface 14 of thewafer 10 has the required surface smoothness by using a polishing process. Of course, the thinning process is not limited to use any one of the above methods alone, and the combination of the above processes may be performed according to the actual situation, or other thinning technologies, such as chemical mechanical polishing (CMP) process, may be used.

如图6所示，在薄化工艺结束后，晶片10的厚度与表面特性可符合连接器的规格要求。如图7所示，接着移除第一黏着层18，并利用第二黏着层22接合晶片10的第二表面14与承载晶片20。同样地，第二黏着层22可选用热释放胶带、紫外线胶带、光致抗蚀剂、腊或聚酰亚胺等材料。如图8所示，接着在介电层上形成导电层24，再在导电层24上形成屏蔽图案26。导电层24可为任何电性优良的材料，例如铝、金或银等，并利用电镀或沉积等方式加以形成，而屏蔽图案26则可为光致抗蚀剂图案。As shown in FIG. 6 , after the thinning process is completed, the thickness and surface characteristics of thewafer 10 can meet the specification requirements of the connector. As shown in FIG. 7 , the firstadhesive layer 18 is then removed, and thesecond surface 14 of thewafer 10 is bonded to thecarrier wafer 20 by the secondadhesive layer 22 . Likewise, the secondadhesive layer 22 can be made of materials such as thermal release tape, ultraviolet tape, photoresist, wax or polyimide. As shown in FIG. 8 , a conductive layer 24 is then formed on the dielectric layer, and then ashielding pattern 26 is formed on the conductive layer 24 . The conductive layer 24 can be any material with excellent electrical properties, such as aluminum, gold or silver, and is formed by electroplating or deposition, and theshielding pattern 26 can be a photoresist pattern.

如图9所示，接着利用屏蔽图案26作为蚀刻掩模，蚀刻导电层24以形成导线图案28，作为连接器内部的连接线路与连接垫之用。如图10所示，去除屏蔽图案26，并接着在介电层16与导线图案28上形成绝缘层30。绝缘层30的材料可为氧化硅、氮化硅、氮氧化硅、苯环丁烯(Benzocyclobutene，BCB)或聚酰亚胺等，并依据材料不同而利用沉积或涂布等方式加以形成。As shown in FIG. 9 , using theshielding pattern 26 as an etching mask, the conductive layer 24 is etched to form awire pattern 28 for connecting lines and pads inside the connector. As shown in FIG. 10 , theshielding pattern 26 is removed, and then aninsulating layer 30 is formed on thedielectric layer 16 and theconductive pattern 28 . The material of theinsulating layer 30 can be silicon oxide, silicon nitride, silicon oxynitride, benzocyclobutene (BCB) or polyimide, and can be formed by deposition or coating according to different materials.

如图11所示，在绝缘层30上形成屏蔽图案32，例如光致抗蚀剂图案。屏蔽图案32包括对应于导线图案28的多个第一开口34，以及定义出切割道图案的多个第二开口36。如图12所示，蚀刻第一开口34暴露出的绝缘层30，以暴露出导线图案28，并一并蚀刻第二开口36暴露出的绝缘层30与介电层16。随后如图13所示，经由第二开口36利用深蚀刻技术直接蚀穿晶片10，此时晶片10已被分割为多个微型连接器38，但仍通过第二黏着层22固定于承载晶片20上。As shown in FIG. 11 , ashielding pattern 32 such as a photoresist pattern is formed on theinsulating layer 30 . Theshield pattern 32 includes a plurality offirst openings 34 corresponding to thewire patterns 28, and a plurality ofsecond openings 36 defining a scribe line pattern. As shown in FIG. 12 , theinsulating layer 30 exposed by thefirst opening 34 is etched to expose thewire pattern 28 , and theinsulating layer 30 and thedielectric layer 16 exposed by thesecond opening 36 are also etched. Subsequently, as shown in FIG. 13 , thechip 10 is directly etched through the second opening 36 by deep etching technology. At this time, thechip 10 has been divided into a plurality of micro-connectors 38 , but is still fixed on thecarrier chip 20 through the secondadhesive layer 22. superior.

如图14所示，自绝缘层30的表面移除屏蔽图案32。如图15所示，自晶片10的第一表面12移除第二黏着层22。如图16所示，即制作出本发明的微型连接器38。As shown in FIG. 14 , theshield pattern 32 is removed from the surface of the insulatinglayer 30 . As shown in FIG. 15 , the secondadhesive layer 22 is removed from thefirst surface 12 of thewafer 10 . As shown in FIG. 16, themicro connector 38 of the present invention is produced.

综上所述，本发明制作微型连接器的方法利用热释放胶带或紫外线胶带作为黏着层的作法可有效避免制作完成的导线图案于后续工艺中受损，同时其易移除的特性亦可有效避免晶片于薄化后受损。此外，本发明先利用初步薄化工艺将晶片的厚度迅速缩减，并通过薄化工艺进一步缩减至最终厚度，同时使晶片的表面具有所欲的表面特性，再在晶片上制作出提供芯片间相互沟通的导线图案，因此可避免薄化晶片时可能产生的污染问题。再者，薄化工艺亦可消除初步薄化工艺中所产生应力，进而避免晶片产生翘曲等问题。另外，在暴露导线图案的过程中，可利用深蚀刻技术一并进行切割工艺，不仅可节省切割时间，亦可降低切割道的面积而提高装设于晶片上的芯片的密度。To sum up, the method of manufacturing the miniature connector of the present invention uses thermal release tape or ultraviolet tape as the adhesive layer, which can effectively prevent the finished wire pattern from being damaged in the subsequent process, and at the same time, its easy-to-remove feature can also effectively Avoid wafer damage after thinning. In addition, the present invention first uses the initial thinning process to rapidly reduce the thickness of the wafer, and further reduces the thickness to the final thickness through the thinning process. The communicating wire pattern thus avoids contamination problems that may arise when thinning the wafer. Furthermore, the thinning process can also eliminate the stress generated in the preliminary thinning process, thereby avoiding problems such as warping of the wafer. In addition, in the process of exposing the wire pattern, the deep etching technology can be used to perform the dicing process, which not only saves the dicing time, but also reduces the area of the dicing line and increases the density of the chips installed on the wafer.

以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的等同变化与修饰，皆应属本发明的涵盖范围。The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (11)

Translated fromChinese

1、一种制作微型连接器的方法，包括：1. A method of making a micro connector, comprising:提供晶片，所述晶片包括第一表面与一第二表面；providing a wafer comprising a first surface and a second surface;在所述晶片的所述第一表面上形成介电层；forming a dielectric layer on the first surface of the wafer;利用第一黏着层接合所述介电层与承载晶片；bonding the dielectric layer and the carrier wafer with a first adhesive layer;进行薄化工艺，由所述晶片的所述第二表面薄化所述晶片；performing a thinning process to thin the wafer from the second surface of the wafer;移除所述第一黏着层，并将利用第二黏着层接合所述晶片的所述第二表面与所述承载晶片；removing the first adhesive layer and bonding the second surface of the wafer to the handle wafer with a second adhesive layer;在所述介电层上形成导线图案；forming a wire pattern on the dielectric layer;在所述介电层与所述导线图案上形成绝缘层；forming an insulating layer on the dielectric layer and the conductive pattern;在所述绝缘层上形成屏蔽图案，所述屏蔽图案包括对应于所述导线图案的多个第一开口，以及定义出切割道图案的多个第二开口；forming a shielding pattern on the insulating layer, the shielding pattern including a plurality of first openings corresponding to the conductor pattern, and a plurality of second openings defining a scribe pattern;去除所述第一开口暴露出的所述绝缘层，以暴露出所述导线图案，并去除所述第二开口所暴露出的所述绝缘层、所述介电层与所述晶片，使所述晶片分割为多个微型连接器；removing the insulating layer exposed by the first opening to expose the wire pattern, and removing the insulating layer, the dielectric layer and the wafer exposed by the second opening, so that the The chip is divided into a plurality of micro connectors;移除所述屏蔽图案；以及removing the shielding pattern; and移除所述第二黏着层。removing the second adhesive layer.2、如权利要求1所述的方法，其中所述介电层为氧化层。2. The method of claim 1, wherein the dielectric layer is an oxide layer.3、如权利要求1所述的方法，其中所述第一黏着层包括热释放胶带或紫外线胶带。3. The method of claim 1, wherein the first adhesive layer comprises heat release tape or ultraviolet tape.4、如权利要求1所述的方法，其中所述承载晶片包括硅晶片、玻璃晶片、石英晶片或塑料晶片。4. The method of claim 1, wherein the handle wafer comprises a silicon wafer, a glass wafer, a quartz wafer, or a plastic wafer.5、如权利要求1所述的方法，还包括在利用所述第一黏着层接合所述介电层与所述承载晶片之前，先对所述晶片的所述第二表面进行初步薄化工艺。5. The method of claim 1, further comprising performing a preliminary thinning process on the second surface of the wafer prior to bonding the dielectric layer to the handle wafer with the first adhesive layer .6、如权利要求5所述的方法，其中所述初步薄化工艺包括粗磨工艺。6. The method of claim 5, wherein the preliminary thinning process comprises a coarse grinding process.7、如权利要求1所述的方法，其中所述薄化工艺包括等离子体蚀刻工艺。7. The method of claim 1, wherein the thinning process comprises a plasma etching process.8、如权利要求1所述的方法，其中所述薄化工艺包括化学蚀刻工艺。8. The method of claim 1, wherein the thinning process comprises a chemical etching process.9、如权利要求1所述的方法，其中所述薄化工艺包括研磨抛光工艺。9. The method of claim 1, wherein the thinning process comprises an abrasive polishing process.10、如权利要求1所述的方法，其中所述第二黏着层包括热释放胶带或紫外线胶带。10. The method of claim 1, wherein the second adhesive layer comprises heat release tape or ultraviolet tape.11、如权利要求1所述的方法，其中去除所述第二开口所暴露出的所述晶片的步骤利用深蚀刻技术加以达成。11. The method of claim 1, wherein the step of removing the wafer exposed by the second opening is accomplished using a deep etch technique.

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