CN100495576C - shift register circuit - Google Patents

Abstract

A shift register circuit having a plurality of shift registers connected in series, comprising: the grid electrode and the first source/drain electrode of the first transistor are coupled with the output signal of the previous stage shift register. A gate of the second transistor is coupled to the second source/drain of the first transistor, a first source/drain of the second transistor is coupled to the first clock signal, and a second source/drain of the second transistor is coupled to the output terminal. The first pull-down module is coupled to the output terminal and the first clock signal, and is coupled to the output terminal to a first voltage level when the output signal of the front-stage shift register and the first clock signal are at a low voltage level. And the second pull-down module is coupled with the output end and a second clock signal, and is coupled with the output end to the first voltage level when the output signal of the front-stage shift register and the second clock signal are at the low voltage level.

Description

Translated fromChinese

移位寄存器电路shift register circuit

技术领域technical field

本发明涉及一种液晶显示器的驱动电路，特别涉及一种液晶显示器的驱动电路中的移位寄存器的驱动电路。The invention relates to a driving circuit of a liquid crystal display, in particular to a driving circuit of a shift register in the driving circuit of a liquid crystal display.

背景技术Background technique

将驱动电路设计在液晶显示面板的玻璃基板上已成为未来液晶显示器的一种主要技术，其最大的优点在于节省驱动IC的成本。以薄膜晶体管显示器来说，非晶硅的工艺已成为目前的主流，但以非晶硅薄膜晶体管来说，其不稳定性，如临界电压的电压漂移，已成为电路设计上最大的问题。请参考图1，图1为一300um工艺的薄膜晶体管在80℃，不同的操作时间下，电压与电流的示意图。曲线11、12、13、14以及15分别为薄膜晶体管在使用0、2、4、6以及8小时后的电压电流曲线图。由图1可发现，薄膜晶体管使用时间越长，其临界电压的电压漂移的情形就越明显，而这种电压漂移就可能导致驱动电路上的移位寄存器输出不正确的信号，而产生液晶显示器无法正常显示的问题。Designing the driving circuit on the glass substrate of the liquid crystal display panel has become a main technology of the future liquid crystal display, and its biggest advantage lies in saving the cost of the driving IC. For thin film transistor displays, the process of amorphous silicon has become the mainstream at present, but for amorphous silicon thin film transistors, its instability, such as the voltage shift of the threshold voltage, has become the biggest problem in circuit design. Please refer to FIG. 1 . FIG. 1 is a schematic diagram of the voltage and current of a 300um process TFT at 80° C. and different operating times.Curves 11 , 12 , 13 , 14 and 15 are the voltage-current curves of the thin film transistors after 0, 2, 4, 6 and 8 hours of use, respectively. It can be found from Figure 1 that the longer the thin-film transistor is used, the more obvious the voltage drift of its critical voltage will be, and this voltage drift may cause the shift register on the drive circuit to output incorrect signals, resulting in liquid crystal display. Problems not displaying properly.

请参考图2，图2为一现有的移位寄存器的电路图。晶体管T21与T22持续接收VDD的电压而导通，使得其临界电压产生电压漂移，而造成输出端N无法维持在正常的关闭状态(off state)。请参考图3，图3为图2中移位寄存器的输出信号示意图。曲线31为图2中的移位寄存器刚开始使用时，输出端N的电压时间曲线。曲线32则为图2中的移位寄存器使用6个小时后输出端N的电压时间曲线。由曲线32可发现，现有移位寄存器在长时间使用后，其输出端信号会无法完全保持在一关闭状态，对液晶显示器来说便可能造成显示影像不正确的输出。Please refer to FIG. 2 , which is a circuit diagram of a conventional shift register. The transistors T21 and T22 are continuously turned on by receiving the voltage of VDD, so that the threshold voltages of the transistors T21 and T22 are turned on, so that the output terminal N cannot maintain a normal off state. Please refer to FIG. 3 , which is a schematic diagram of output signals of the shift register in FIG. 2 .Curve 31 is the voltage-time curve of the output terminal N when the shift register in FIG. 2 is just used.Curve 32 is the voltage-time curve of the output terminal N after the shift register in FIG. 2 has been used for 6 hours. It can be seen from thecurve 32 that after the conventional shift register is used for a long time, the signal at the output terminal cannot be completely kept in a closed state, which may cause incorrect output of the displayed image for the liquid crystal display.

发明内容Contents of the invention

本发明的目的为提供一种可减少晶体管产生的电压飘移情形的移位寄存电路。The object of the present invention is to provide a shift register circuit which can reduce the voltage drift generated by transistors.

本发明提供一种移位寄存电路，具有多个串接级的移位寄存器，包括：一第一晶体管，具有一栅极、一第一源/漏极以及一第二源/漏极，其中该第一晶体管的栅极与该第一晶体管的第一源/漏极耦接一前级移位寄存器的输出信号。一第二晶体管，具有一栅极、一第一源/漏极以及一第二源/漏极，其中该第二晶体管的栅极耦接该第一晶体管的第二源/漏极，该第二晶体管的第一源/漏极耦接一第一时钟信号，该第二晶体管的第二源/漏极耦接一输出端。一第一下拉模块，耦接该输出端与该第一时钟信号，当该前级移位寄存器的输出信号与该第一时钟信号为低电压电平时，耦接该输出端至一第一电压电平。一第二下拉模块，耦接该输出端与一第二时钟信号，当该前级移位寄存器的输出信号与该第二时钟信号为低电压电平时，耦接该输出端至该第一电压电平。The present invention provides a shift register circuit, which has a plurality of shift registers connected in series, including: a first transistor with a gate, a first source/drain and a second source/drain, wherein The gate of the first transistor and the first source/drain of the first transistor are coupled to an output signal of a previous shift register. A second transistor has a gate, a first source/drain and a second source/drain, wherein the gate of the second transistor is coupled to the second source/drain of the first transistor, and the first The first source/drain of the second transistor is coupled to a first clock signal, and the second source/drain of the second transistor is coupled to an output end. A first pull-down module, coupled to the output terminal and the first clock signal, when the output signal of the previous stage shift register and the first clock signal are at a low voltage level, the output terminal is coupled to a first voltage level. A second pull-down module, coupled to the output terminal and a second clock signal, when the output signal of the previous stage shift register and the second clock signal are at a low voltage level, the output terminal is coupled to the first voltage level.

本发明更提供一种移位寄存电路，具有多个串接级的移位寄存器，包括：一第一晶体管，具有一栅极、一第一源/漏极以及一第二源/漏极，其中，该第一晶体管的栅极与该第一晶体管的第一源/漏极耦接一前级移位寄存器的输出信号。一第二晶体管，具有一栅极、一第一源/漏极以及一第二源/漏极，其中该第二晶体管的栅极耦接该第一晶体管的第二源/漏极，该第二晶体管的第一源/漏极耦接一第一时钟信号，该第二晶体管的第二源/漏极耦接一输出端。一第三晶体管，具有一栅极、一第一源/漏极以及一第二源/漏极，其中，该第三晶体管的第一源/漏极耦接该输出端，该第三晶体管的第二源/漏极耦接该第一电压电平。一第四晶体管，具有一栅极、一第一源/漏极以及一第二源/漏极，其中，该第四晶体管的第二源/漏极耦接该第一电压电平，该第四晶体管的栅极耦接该第三晶体管的栅极，该第四晶体管的第一源/漏极耦接该第二晶体管的栅极。一第五晶体管，具有一栅极、一第一源/漏极以及一第二源/漏极，其中，该第五晶体管的栅极与该第五晶体管的第一源/漏极耦接该第二时钟信号，该第五晶体管的第二源/漏极耦接该第三晶体管的栅极。一第六晶体管，具有一栅极、一第一源/漏极以及一第二源/漏极，其中，该第六晶体管的第二源/漏极耦接该第一电压电平，该第六晶体管的栅极耦接该第一时钟信号，该第六晶体管的第一源/漏极耦接该第三晶体管的栅极。一第七晶体管，具有一栅极、一第一源/漏极以及一第二源/漏极，其中，该第七晶体管的第二源/漏极耦接该第一电压电平，该第七晶体管的栅极耦接该前级移位寄存器的输出信号，该第七晶体管的第一源/漏极耦接该第三晶体管的栅极。一第八晶体管，具有一栅极、一第一源/漏极以及一第二源/漏极，其中，该第八晶体管的第一源/漏极耦接该输出端，该第八晶体管的第二源/漏极耦接该第一电压电平。一第九晶体管，具有一栅极、一第一源/漏极以及一第二源/漏极，其中该第九晶体管的第二源/漏极耦接该第一电压电平，该第九晶体管的栅极耦接该第八晶体管的栅极，该第九晶体管的第一源/漏极耦接该第二晶体管的栅极。一第十晶体管，具有一栅极、一第一源/漏极以及一第二源/漏极，其中，该第十晶体管的栅极与该第十晶体管的第一源/漏极耦接该第一时钟信号，该第十晶体管的第二源/漏极耦接该第八晶体管的栅极。一第十一晶体管，具有一栅极、一第一源/漏极以及一第二源/漏极，其中，该第十一晶体管的第二源/漏极耦接该第一电压电平，该第十一晶体管的栅极耦接该第二时钟信号，该第十一晶体管的第一源/漏极耦接该第八晶体管的栅极。一第十二晶体管，具有一栅极、一第一源/漏极以及一第二源/漏极，其中，该第十二晶体管的第二源/漏极耦接该第一电压电平，该第十二晶体管的栅极耦接该输出端，该第十二晶体管的第一源/漏极耦接该第八晶体管的栅极。The present invention further provides a shift register circuit, which has a plurality of serially connected shift registers, including: a first transistor with a gate, a first source/drain and a second source/drain, Wherein, the gate of the first transistor and the first source/drain of the first transistor are coupled to an output signal of a previous shift register. A second transistor has a gate, a first source/drain and a second source/drain, wherein the gate of the second transistor is coupled to the second source/drain of the first transistor, and the first The first source/drain of the second transistor is coupled to a first clock signal, and the second source/drain of the second transistor is coupled to an output terminal. A third transistor has a gate, a first source/drain and a second source/drain, wherein the first source/drain of the third transistor is coupled to the output terminal, and the third transistor The second source/drain is coupled to the first voltage level. A fourth transistor has a gate, a first source/drain and a second source/drain, wherein the second source/drain of the fourth transistor is coupled to the first voltage level, and the first The gate of the four transistors is coupled to the gate of the third transistor, and the first source/drain of the fourth transistor is coupled to the gate of the second transistor. A fifth transistor has a gate, a first source/drain and a second source/drain, wherein the gate of the fifth transistor and the first source/drain of the fifth transistor are coupled to the The second clock signal, the second source/drain of the fifth transistor is coupled to the gate of the third transistor. A sixth transistor has a gate, a first source/drain and a second source/drain, wherein the second source/drain of the sixth transistor is coupled to the first voltage level, and the first The gates of the six transistors are coupled to the first clock signal, and the first source/drain of the sixth transistor is coupled to the gate of the third transistor. A seventh transistor having a gate, a first source/drain and a second source/drain, wherein the second source/drain of the seventh transistor is coupled to the first voltage level, and the first The gate of the seven transistors is coupled to the output signal of the preceding shift register, and the first source/drain of the seventh transistor is coupled to the gate of the third transistor. An eighth transistor has a gate, a first source/drain and a second source/drain, wherein the first source/drain of the eighth transistor is coupled to the output terminal, and the eighth transistor The second source/drain is coupled to the first voltage level. A ninth transistor has a gate, a first source/drain and a second source/drain, wherein the second source/drain of the ninth transistor is coupled to the first voltage level, and the ninth The gate of the transistor is coupled to the gate of the eighth transistor, and the first source/drain of the ninth transistor is coupled to the gate of the second transistor. A tenth transistor has a gate, a first source/drain and a second source/drain, wherein the gate of the tenth transistor and the first source/drain of the tenth transistor are coupled to the For the first clock signal, the second source/drain of the tenth transistor is coupled to the gate of the eighth transistor. an eleventh transistor having a gate, a first source/drain and a second source/drain, wherein the second source/drain of the eleventh transistor is coupled to the first voltage level, The gate of the eleventh transistor is coupled to the second clock signal, and the first source/drain of the eleventh transistor is coupled to the gate of the eighth transistor. a twelfth transistor having a gate, a first source/drain and a second source/drain, wherein the second source/drain of the twelfth transistor is coupled to the first voltage level, The gate of the twelfth transistor is coupled to the output terminal, and the first source/drain of the twelfth transistor is coupled to the gate of the eighth transistor.

为让本发明的上述和其它目的、特征、和优点能更明显易懂，下文特举出较佳实施例，并配合附图，作详细说明如下。In order to make the above and other objects, features, and advantages of the present invention more comprehensible, preferred embodiments are listed below and described in detail in conjunction with the accompanying drawings.

附图说明Description of drawings

图1为一300um工艺的薄膜晶体管在80℃，不同的操作时间下，电压与电流的示意图。FIG. 1 is a schematic diagram of the voltage and current of a 300um process thin film transistor at 80° C. and different operating times.

图2为一现有的移位寄存器的电路图。FIG. 2 is a circuit diagram of a conventional shift register.

图3为图2中移位寄存器的输出信号示意图。FIG. 3 is a schematic diagram of output signals of the shift register in FIG. 2 .

图4为根据本发明的第一个实施例的移位寄存器的示意图。FIG. 4 is a schematic diagram of a shift register according to a first embodiment of the present invention.

图5为根据本发明的第二个实施例的移位寄存器的示意图。FIG. 5 is a schematic diagram of a shift register according to a second embodiment of the present invention.

图6为根据本发明的第三个实施例的移位寄存器的示意图。FIG. 6 is a schematic diagram of a shift register according to a third embodiment of the present invention.

图7为根据本发明的实施例的一第一下拉模块的电路图。FIG. 7 is a circuit diagram of a first pull-down module according to an embodiment of the invention.

图8为根据本发明的实施例的一第二下拉模块的电路图。FIG. 8 is a circuit diagram of a second pull-down module according to an embodiment of the present invention.

图9为根据本发明的实施例的一第三下拉模块的电路图。FIG. 9 is a circuit diagram of a third pull-down module according to an embodiment of the present invention.

图10为根据本发明的第四个实施例的电路图。Fig. 10 is a circuit diagram according to a fourth embodiment of the present invention.

图11为图10所示的移位寄存器的时序图。FIG. 11 is a timing diagram of the shift register shown in FIG. 10 .

附图符号说明Description of reference symbols

11、12、13、14、15、31、32-曲线11, 12, 13, 14, 15, 31, 32-curves

41、51、61-第一下拉模块41, 51, 61 - first pull-down module

42、52、62-第二下拉模块42, 52, 62 - second pull-down module

53-开关装置53-Switch device

63-第三下拉模块63-Third drop-down module

T21、T22、T41、T42、T51、T52、T61、T62、T71、T72、T73、T74、T75、T81、T82、T83、T84、T85、T91、T92、T93、T94、T1、T2、T3、T4、T5、T6、T7、T8、T9、T10、T11、T12、T13、T14、T15、T16、T17-晶体管T21, T22, T41, T42, T51, T52, T61, T62, T71, T72, T73, T74, T75, T81, T82, T83, T84, T85, T91, T92, T93, T94, T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17 - Transistors

N70、N80、N1、N2、N3、N4-端点N70, N80, N1, N2, N3, N4 - endpoints

具体实施方式Detailed ways

图4为根据本发明的第一个实施例的移位寄存器的示意图。第一个实施例中利用第一下拉模块41与第二下拉模块42交替的将移位寄存器的输出信号N耦接至低电压源VSS以维持输出信号N处于关闭状态。晶体管T41的栅极与其第一源/漏极耦接前级移位寄存器的输出信号(N-1)与第一下拉模块41。晶体管T41的第二源/漏极耦接晶体管T42的栅极。晶体管T42的第一源/漏极耦接一第一时钟信号CLK，晶体管T42的第二源/漏极耦接第一下拉模块41、第二下拉模块42以及移位寄存器的输出信号N。第一下拉模块41与第二下拉模块42分别耦接第一时钟信号CLK与第二时钟信号XCLK。当前级移位寄存器的输出信号(N-1)与第一时钟信号CLK为低电压电平时，该第一下拉模块41耦接移位寄存器的输出信号N至低电压源VSS。当前级移位寄存器的输出信号(N-1)与第二时钟信号XCLK为低电压电平时，该第二下拉模块42耦接移位寄存器的输出信号N至低电压源VSS。当前晶体管T42的栅极与第一时钟信号CLK为高电压电平时，移位寄存器的输出信号N为高电压电平。FIG. 4 is a schematic diagram of a shift register according to a first embodiment of the present invention. In the first embodiment, the first pull-down module 41 and the second pull-down module 42 are used to alternately couple the output signal N of the shift register to the low voltage source VSS to maintain the output signal N in an off state. The gate of the transistor T41 and its first source/drain are coupled to the output signal (N−1) of the preceding shift register and the first pull-down module 41 . The second source/drain of the transistor T41 is coupled to the gate of the transistor T42. The first source/drain of the transistor T42 is coupled to a first clock signal CLK, and the second source/drain of the transistor T42 is coupled to the first pull-down module 41 , the second pull-down module 42 and the output signal N of the shift register. The first pull-down module 41 and the second pull-down module 42 are respectively coupled to the first clock signal CLK and the second clock signal XCLK. When the output signal (N−1) of the previous shift register and the first clock signal CLK are at low voltage levels, the first pull-down module 41 is coupled to the output signal N of the shift register to the low voltage source VSS. When the output signal (N−1) of the previous shift register and the second clock signal XCLK are at a low voltage level, the second pull-down module 42 is coupled to the output signal N of the shift register to the low voltage source VSS. When the gate of the current transistor T42 and the first clock signal CLK are at a high voltage level, the output signal N of the shift register is at a high voltage level.

图5为根据本发明的第二个实施例的移位寄存器的示意图。与图4所示的第一个实施例差异在第二个实施例增加一开关装置53，用以在移位寄存器的输出信号N为高电压电平时，关闭该第一下拉模块。晶体管T51的栅极与其第一源/漏极耦接前级移位寄存器的输出信号(N-1)与第一下拉模块51。晶体管T51的第二源/漏极耦接晶体管T52的栅极。晶体管T52的第一源/漏极耦接一第一时钟信号CLK，晶体管T52的第二源/漏极耦接第一下拉模块51、第二下拉模块52以及移位寄存器的输出信号N。第一下拉模块51与第二下拉模块52分别耦接第一时钟信号CLK与第二时钟信号XCLK。当前级移位寄存器的输出信号(N-1)与第一时钟信号CLK为低电压电平时，该第一下拉模块51耦接移位寄存器的输出信号N至低电压源VSS。当前级移位寄存器的输出信号(N-1)与第二时钟信号XCLK为低电压电平时，该第二下拉模块52耦接移位寄存器的输出信号N至低电压源VSS。当晶体管T52的栅极与第一时钟信号CLK为高电压电平时，该开关装置53关闭第一下拉模块51且移位寄存器的输出信号N为高电压电平。FIG. 5 is a schematic diagram of a shift register according to a second embodiment of the present invention. The difference from the first embodiment shown in FIG. 4 is that aswitch device 53 is added in the second embodiment to turn off the first pull-down module when the output signal N of the shift register is at a high voltage level. The gate of the transistor T51 and its first source/drain are coupled to the output signal (N−1) of the preceding shift register and the first pull-down module 51 . The second source/drain of the transistor T51 is coupled to the gate of the transistor T52. The first source/drain of the transistor T52 is coupled to a first clock signal CLK, and the second source/drain of the transistor T52 is coupled to the first pull-down module 51 , the second pull-down module 52 and the output signal N of the shift register. The first pull-down module 51 and the second pull-down module 52 are respectively coupled to the first clock signal CLK and the second clock signal XCLK. When the output signal (N−1) of the previous stage shift register and the first clock signal CLK are at low voltage levels, the first pull-down module 51 is coupled to the output signal N of the shift register to the low voltage source VSS. When the output signal (N−1) of the previous stage shift register and the second clock signal XCLK are at low voltage levels, the second pull-down module 52 is coupled to the output signal N of the shift register to the low voltage source VSS. When the gate of the transistor T52 and the first clock signal CLK are at a high voltage level, theswitch device 53 turns off the first pull-down module 51 and the output signal N of the shift register is at a high voltage level.

图6为根据本发明的第三个实施例的移位寄存器的示意图。在本实施例中，利用一次级移位寄存器的输出信号(N+1)为一电压源，用以将移位寄存器的输出信号N耦接至低电压源VSS。晶体管T61的栅极与其第一源/漏极耦接前级移位寄存器的输出信号(N-1)与第一下拉模块61。晶体管T61的第二源/漏极耦接晶体管T62的栅极。晶体管T62的第一源/漏极耦接一第一时钟信号CLK，晶体管T62的第二源/漏极耦接第一下拉模块61、第二下拉模块62以及移位寄存器的输出信号N。第三下拉模块63耦接晶体管T62的第二源/漏极、第一下拉模块61与次级移位寄存器的输出信号(N+1)。第一下拉模块61与第二下拉模块62分别耦接第一时钟信号CLK与第二时钟信号XCLK。当前级移位寄存器的输出信号(N-1)与第一时钟信号CLK为低电压电平时，该第一下拉模块61耦接移位寄存器的输出信号N至低电压源VSS。当晶体管T62的栅极与第二时钟信号XCLK为低电压电平时，该第二下拉模块62耦接移位寄存器的输出信号N至低电压源VSS。当前级移位寄存器的输出信号(N-1)晶体管T62的栅极与第一时钟信号CLK为高电压电平时，移位寄存器的输出信号N为高电压电平。当次级移位寄存器的输出信号(N+1)为高电压电平与本级移位寄存器的输出信号(N)为低电压电平时，第三模块63耦接移位寄存器的输出信号N至低电压源VSS。FIG. 6 is a schematic diagram of a shift register according to a third embodiment of the present invention. In this embodiment, the output signal (N+1) of a secondary shift register is used as a voltage source to couple the output signal N of the shift register to the low voltage source VSS. The gate of the transistor T61 and its first source/drain are coupled to the output signal (N−1) of the preceding shift register and the first pull-down module 61 . The second source/drain of the transistor T61 is coupled to the gate of the transistor T62. The first source/drain of the transistor T62 is coupled to a first clock signal CLK, and the second source/drain of the transistor T62 is coupled to the first pull-down module 61 , the second pull-down module 62 and the output signal N of the shift register. The third pull-down module 63 is coupled to the second source/drain of the transistor T62, the first pull-down module 61 and the output signal (N+1) of the secondary shift register. The first pull-down module 61 and the second pull-down module 62 are respectively coupled to the first clock signal CLK and the second clock signal XCLK. When the output signal (N−1) of the previous stage shift register and the first clock signal CLK are at a low voltage level, the first pull-down module 61 is coupled to the output signal N of the shift register to the low voltage source VSS. When the gate of the transistor T62 and the second clock signal XCLK are at a low voltage level, the second pull-down module 62 is coupled to the output signal N of the shift register to the low voltage source VSS. When the gate of the transistor T62 and the first clock signal CLK are at a high voltage level, the output signal N of the shift register is at a high voltage level. When the output signal (N+1) of the secondary shift register is at a high voltage level and the output signal (N) of the shift register at this stage is at a low voltage level, the third module 63 is coupled to the output signal N of the shift register to the low voltage source VSS.

在第4、5以及6图中，第一下拉模块41、51以及61、第二下拉模块42、52以及62、第三下拉模块63以及开关装置53可由电阻、电容、晶体管、多路复用器、逻辑门或其它类似组件所组合而成，可能为单一组件所构成或是由多个组件所组合而成的电路。为了更详细说明，下文特以较佳实施例说明，但并非将本发明限制于该实施例。In Figures 4, 5, and 6, the first pull-down modules 41, 51, and 61, the second pull-down modules 42, 52, and 62, the third pull-down module 63, and theswitching device 53 can be composed of resistors, capacitors, transistors, and multiplexers. A circuit composed of devices, logic gates, or other similar components, which may be composed of a single component or a combination of multiple components. For more detailed description, a preferred embodiment is described below, but the present invention is not limited to the embodiment.

图7为根据本发明的实施例的一第一下拉模块的电路图。图7所示的第一下拉模块的电路可适用于第一下拉模块41、51以及61。晶体管T71的第一源/漏极耦接移位寄存器的输出信号N，且其第二源/漏极耦接至一低电压源VSS。晶体管T72的第一源/漏极耦接如晶体管T42、T52以及T62的栅极，晶体管T72的第二源/漏极耦接至一低电压源VSS且其栅极耦接晶体管T71的栅极。晶体管T73的栅极与该晶体管T73的第一源/漏极耦接第二时钟信号XCLK，晶体管T73的第二源/漏极耦接该晶体管T71的栅极。晶体管T74的栅极耦接第一时钟信号CLK，晶体管T74的第一源/漏极耦接晶体管T73的第二源/漏极，晶体管T74的第二源/漏极耦接低电压源VSS。晶体管T75的栅极耦接前级移位寄存器的输出信号(N-1)，晶体管T75的第一源/漏极耦接晶体管T71的栅极，晶体管T75的第二源/漏极耦接低电压源VSS。当前级移位寄存器的输出信号(N-1)为高电压电平时，晶体管T75被导通，端点N70的电位被耦接至低电压源VSS，关闭晶体管T72与T71。当前级移位寄存器的输出信号(N-1)与第一时钟信号CLK为低电压电平时，此时第二时钟信号XCLK为高电压电平，端点N70为高电压电平，导通晶体管T72与T71，使得移位寄存器的输出信号N被耦接至低电压源VSS。FIG. 7 is a circuit diagram of a first pull-down module according to an embodiment of the invention. The circuit of the first pull-down module shown in FIG. 7 is applicable to the first pull-down modules 41 , 51 and 61 . The first source/drain of the transistor T71 is coupled to the output signal N of the shift register, and the second source/drain thereof is coupled to a low voltage source VSS. The first source/drain of the transistor T72 is coupled to the gates of the transistors T42, T52 and T62, the second source/drain of the transistor T72 is coupled to a low voltage source VSS and its gate is coupled to the gate of the transistor T71 . The gate of the transistor T73 and the first source/drain of the transistor T73 are coupled to the second clock signal XCLK, and the second source/drain of the transistor T73 is coupled to the gate of the transistor T71. The gate of the transistor T74 is coupled to the first clock signal CLK, the first source/drain of the transistor T74 is coupled to the second source/drain of the transistor T73 , and the second source/drain of the transistor T74 is coupled to the low voltage source VSS. The gate of the transistor T75 is coupled to the output signal (N-1) of the previous shift register, the first source/drain of the transistor T75 is coupled to the gate of the transistor T71, and the second source/drain of the transistor T75 is coupled to the low Voltage source VSS. When the output signal (N−1) of the front-stage shift register is at a high voltage level, the transistor T75 is turned on, the potential of the terminal N70 is coupled to the low voltage source VSS, and the transistors T72 and T71 are turned off. When the output signal (N-1) of the front-stage shift register and the first clock signal CLK are at a low voltage level, the second clock signal XCLK is at a high voltage level, the terminal N70 is at a high voltage level, and the transistor T72 is turned on. and T71 , so that the output signal N of the shift register is coupled to the low voltage source VSS.

图8为根据本发明的实施例的一第二下拉模块的电路图。图8所示的第二下拉模块的电路可适用于第二下拉模块42、52以及62。晶体管T81的第一源/漏极耦接移位寄存器的输出信号N，且其第二源/漏极耦接至一低电压源VSS。晶体管T82的第一源/漏极耦接如晶体管T42、T52以及T62的栅极，晶体管T82的第二源/漏极耦接至一低电压源VSS且其栅极耦接晶体管T81的栅极。晶体管T83的栅极与该晶体管T83的第一源/漏极耦接第一时钟信号CLK，晶体管T83的第二源/漏极耦接该晶体管T81的栅极。晶体管T84的栅极耦接第二时钟信号XCLK，晶体管T84的第一源/漏极耦接晶体管T83的第二源/漏极，晶体管T84的第二源/漏极耦接低电压源VSS。晶体管T85的栅极耦接移位寄存器的输出信号N，晶体管T85的第一源/漏极耦接晶体管T81的栅极，晶体管T85的第二源/漏极耦接低电压源VSS。当移位寄存器的输出信号N与第二时钟信号XCLK为低电压电平时，晶体管T83被导通，端点N80为高电压电平且导通晶体管T82与T81。晶体管T81被导通后，移位寄存器的输出信号N被耦接至低电压源VSS。当移位寄存器的输出信号N为高电压电平时，晶体管T85导通，端点N80被耦接至低电压源VSS，关闭晶体管T81与T82以维持移位寄存器的输出信号N为高电压电平。FIG. 8 is a circuit diagram of a second pull-down module according to an embodiment of the present invention. The circuit of the second pull-down module shown in FIG. 8 is applicable to the second pull-down modules 42 , 52 and 62 . The first source/drain of the transistor T81 is coupled to the output signal N of the shift register, and the second source/drain of the transistor T81 is coupled to a low voltage source VSS. The first source/drain of the transistor T82 is coupled to the gates of the transistors T42, T52 and T62, the second source/drain of the transistor T82 is coupled to a low voltage source VSS and its gate is coupled to the gate of the transistor T81 . The gate of the transistor T83 and the first source/drain of the transistor T83 are coupled to the first clock signal CLK, and the second source/drain of the transistor T83 is coupled to the gate of the transistor T81. The gate of the transistor T84 is coupled to the second clock signal XCLK, the first source/drain of the transistor T84 is coupled to the second source/drain of the transistor T83 , and the second source/drain of the transistor T84 is coupled to the low voltage source VSS. The gate of the transistor T85 is coupled to the output signal N of the shift register, the first source/drain of the transistor T85 is coupled to the gate of the transistor T81 , and the second source/drain of the transistor T85 is coupled to the low voltage source VSS. When the output signal N of the shift register and the second clock signal XCLK are at a low voltage level, the transistor T83 is turned on, the terminal N80 is at a high voltage level and the transistors T82 and T81 are turned on. After the transistor T81 is turned on, the output signal N of the shift register is coupled to the low voltage source VSS. When the output signal N of the shift register is at a high voltage level, the transistor T85 is turned on, the terminal N80 is coupled to the low voltage source VSS, and the transistors T81 and T82 are turned off to maintain the output signal N of the shift register at a high voltage level.

图9为根据本发明的实施例的一第三下拉模块的电路图。图9所示的第三下拉模块的电路可适用于第三下拉模块63。晶体管T91的第一源/漏极耦接次级移位寄存器输出信号(N+1)，晶体管T91的栅极耦接第一下拉模块，如图7所示的第一下拉模块电路图。晶体管T91的第二源/漏极耦接晶体管T92的第一源/漏极。晶体管T92的第二源/漏极耦接低电压源VSS，晶体管T92的栅极耦接第一时钟信号CLK。晶体管T93的的第一源/漏极耦接移位寄存器的输出信号N，且其第二源/漏极耦接至一低电压源VSS。晶体管T94的第一源/漏极耦接如晶体管T42、T52以及T62的栅极，晶体管T94的第二源/漏极耦接至一低电压源VSS且其栅极耦接晶体管T93的栅极。当次级移位寄存器输出信号(N+1)与晶体管T91栅极接收到高电压电平，且第一时钟信号CLK为低电压电平时，晶体管T93被导通，移位寄存器的输出信号N被耦接至低电压源VSS。FIG. 9 is a circuit diagram of a third pull-down module according to an embodiment of the present invention. The circuit of the third pull-down module shown in FIG. 9 is applicable to the third pull-down module 63 . The first source/drain of the transistor T91 is coupled to the output signal (N+1) of the secondary shift register, and the gate of the transistor T91 is coupled to the first pull-down module, as shown in the circuit diagram of the first pull-down module in FIG. 7 . The second source/drain of the transistor T91 is coupled to the first source/drain of the transistor T92. The second source/drain of the transistor T92 is coupled to the low voltage source VSS, and the gate of the transistor T92 is coupled to the first clock signal CLK. The first source/drain of the transistor T93 is coupled to the output signal N of the shift register, and the second source/drain of the transistor T93 is coupled to a low voltage source VSS. The first source/drain of the transistor T94 is coupled to the gates of the transistors T42, T52 and T62, the second source/drain of the transistor T94 is coupled to a low voltage source VSS and its gate is coupled to the gate of the transistor T93 . When the output signal (N+1) of the secondary shift register and the gate of the transistor T91 receive a high voltage level, and the first clock signal CLK is at a low voltage level, the transistor T93 is turned on, and the output signal N of the shift register is coupled to the low voltage source VSS.

图10为根据本发明的第四个实施例的电路图。晶体管T1的栅极与其第一源/漏极耦接一前级移位寄存器的输出信号(N-1)。晶体管T2的栅极耦接该晶体管T1的第二源/漏极，晶体管T2的第一源/漏极耦接一第一时钟信号CLK，晶体管T2的第二源/漏极耦接移位寄存器输出信号N。晶体管T3的第一源/漏极耦接移位寄存器输出信号N，晶体管T3的第二源/漏极耦接低电压源VSS。晶体管T4的第二源/漏极耦接低电压源VSS，晶体管T4的栅极耦接晶体管T3的栅极，晶体管T4的第一源/漏极耦接晶体管T2的栅极。晶体管T5的栅极与其第一源/漏极耦接第二时钟信号XCLK，晶体管T5的第二源/漏极耦接晶体管T3的栅极。晶体管T6的第二源/漏极耦接低电压源VSS，晶体管T6的栅极耦接第一时钟信号CLK，晶体管T6的第一源/漏极耦接晶体管T3的栅极。晶体管T7的第二源/漏极耦接低电压源VSS，晶体管T7的栅极耦接该前级移位寄存器的输出信号(N-1)，晶体管T7的第一源/漏极耦接晶体管T3的栅极。晶体管T8的第一源/漏极耦接移位寄存器输出信号N，晶体管T8的第二源/漏极耦接低电压源VSS。晶体管T9的第二源/漏极耦接低电压源VSS，晶体管T9的栅极耦接该晶体管T8的栅极，晶体管T9的第一源/漏极耦接晶体管T2的栅极。晶体管T10的栅极与其第一源/漏极耦接第一时钟信号CLK，晶体管T10的第二源/漏极耦接晶体管T8的栅极。晶体管T11的第二源/漏极耦接低电压源VSS，晶体管T11的栅极耦接第二时钟信号XCLK，晶体管T11的第一源/漏极耦接晶体管T8的栅极。晶体管T12的第二源/漏极耦接低电压源VSS，晶体管T12的栅极耦接移位寄存器输出信号N，晶体管T12的第一源/漏极耦接该晶体管T8的栅极。晶体管T13的栅极耦接该晶体管T3的栅极，晶体管T13的第一源/漏极耦接次级移位寄存器的输出信号(N+1)。晶体管T14的第一源/漏极耦接该晶体管T13的第二源/漏极，晶体管T14的第二源/漏极耦接低电压源VSS，晶体管T14的栅极耦接第一时钟信号CLK。晶体管T15的栅极耦接该晶体管T13的第二源/漏极，晶体管T15的第二源/漏极耦接低电压源VSS，晶体管T15的第一源/漏极耦接移位寄存器的输出信号N。晶体管T16的栅极耦接晶体管T13的第二源/漏极，晶体管T16的第二源/漏极耦接低电压源VSS，晶体管T16的第一源/漏极耦接晶体管T2的栅极。晶体管T17的栅极耦接移位寄存器的输出信号N，晶体管T17的第一源/漏极耦接晶体管T3的栅极，晶体管T17的第二源/漏极耦接低电压源VSS。Fig. 10 is a circuit diagram according to a fourth embodiment of the present invention. The gate of the transistor T1 and its first source/drain are coupled to an output signal (N−1) of a previous shift register. The gate of the transistor T2 is coupled to the second source/drain of the transistor T1, the first source/drain of the transistor T2 is coupled to a first clock signal CLK, and the second source/drain of the transistor T2 is coupled to the shift register Output signal N. The first source/drain of the transistor T3 is coupled to the shift register output signal N, and the second source/drain of the transistor T3 is coupled to the low voltage source VSS. The second source/drain of the transistor T4 is coupled to the low voltage source VSS, the gate of the transistor T4 is coupled to the gate of the transistor T3, and the first source/drain of the transistor T4 is coupled to the gate of the transistor T2. The gate of the transistor T5 and its first source/drain are coupled to the second clock signal XCLK, and the second source/drain of the transistor T5 is coupled to the gate of the transistor T3. The second source/drain of the transistor T6 is coupled to the low voltage source VSS, the gate of the transistor T6 is coupled to the first clock signal CLK, and the first source/drain of the transistor T6 is coupled to the gate of the transistor T3. The second source/drain of the transistor T7 is coupled to the low voltage source VSS, the gate of the transistor T7 is coupled to the output signal (N-1) of the previous shift register, and the first source/drain of the transistor T7 is coupled to the transistor Gate of T3. The first source/drain of the transistor T8 is coupled to the shift register output signal N, and the second source/drain of the transistor T8 is coupled to the low voltage source VSS. The second source/drain of the transistor T9 is coupled to the low voltage source VSS, the gate of the transistor T9 is coupled to the gate of the transistor T8, and the first source/drain of the transistor T9 is coupled to the gate of the transistor T2. The gate of the transistor T10 and its first source/drain are coupled to the first clock signal CLK, and the second source/drain of the transistor T10 is coupled to the gate of the transistor T8. The second source/drain of the transistor T11 is coupled to the low voltage source VSS, the gate of the transistor T11 is coupled to the second clock signal XCLK, and the first source/drain of the transistor T11 is coupled to the gate of the transistor T8. The second source/drain of the transistor T12 is coupled to the low voltage source VSS, the gate of the transistor T12 is coupled to the shift register output signal N, and the first source/drain of the transistor T12 is coupled to the gate of the transistor T8. The gate of the transistor T13 is coupled to the gate of the transistor T3, and the first source/drain of the transistor T13 is coupled to the output signal (N+1) of the secondary shift register. The first source/drain of the transistor T14 is coupled to the second source/drain of the transistor T13, the second source/drain of the transistor T14 is coupled to the low voltage source VSS, and the gate of the transistor T14 is coupled to the first clock signal CLK . The gate of the transistor T15 is coupled to the second source/drain of the transistor T13, the second source/drain of the transistor T15 is coupled to the low voltage source VSS, and the first source/drain of the transistor T15 is coupled to the output of the shift register Signal N. The gate of the transistor T16 is coupled to the second source/drain of the transistor T13, the second source/drain of the transistor T16 is coupled to the low voltage source VSS, and the first source/drain of the transistor T16 is coupled to the gate of the transistor T2. The gate of the transistor T17 is coupled to the output signal N of the shift register, the first source/drain of the transistor T17 is coupled to the gate of the transistor T3 , and the second source/drain of the transistor T17 is coupled to the low voltage source VSS.

图11为图10所示的移位寄存器的时序图。在时间t1时，前级移位寄存器的输出信号(N-1)为高电压电平，晶体管T1、T2以及T7导通，端点N1为高电压电平。此时第一时钟信号CLK为低电压电平，因此移位寄存器的输出信号N为低电压电平。第二时钟信号此时为高电压电平，晶体管T11导通，使得端点N2耦接至低电压源VSS。FIG. 11 is a timing diagram of the shift register shown in FIG. 10 . At time t1, the output signal (N−1) of the previous stage shift register is at a high voltage level, the transistors T1, T2 and T7 are turned on, and the terminal N1 is at a high voltage level. At this time, the first clock signal CLK is at a low voltage level, so the output signal N of the shift register is at a low voltage level. The second clock signal is at a high voltage level at this time, and the transistor T11 is turned on, so that the terminal N2 is coupled to the low voltage source VSS.

在时间t2时，前级移位寄存器的输出端(N-1)的讯号变成低电压电平，晶体管T1与晶体管T7被关闭，端点N1的电位因没有放电路径可供放电所以维持高电压电平，使得第二晶体管T2继续被导通。此时第一时钟信号CLK为高电压电平，而对第二晶体管T2的第一源/漏极与栅极之间形成耦合电容充电，使得端点N1的电压电平继续上升。在时间t2时，第一时钟信号为高电压电平使得移位寄存器的输出端N为高电压电平，晶体管T17导通，端点N3被耦接至低电压源VSS使得晶体管T3与T4被关闭。At time t2, the signal at the output terminal (N-1) of the previous stage shift register becomes a low voltage level, transistor T1 and transistor T7 are turned off, and the potential of terminal N1 maintains a high voltage because there is no discharge path for discharge. level, so that the second transistor T2 continues to be turned on. At this time, the first clock signal CLK is at a high voltage level, and charges the coupling capacitor formed between the first source/drain and the gate of the second transistor T2, so that the voltage level of the terminal N1 continues to rise. At time t2, the first clock signal is at a high voltage level so that the output terminal N of the shift register is at a high voltage level, the transistor T17 is turned on, and the terminal N3 is coupled to the low voltage source VSS so that the transistors T3 and T4 are turned off .

在时间t3时，移位寄存器的输出信号N为低电压电平，晶体管T17被关闭，端点N3为高电压电平使得晶体管T13被导通。此时，次级移位寄存器的输出信号(N+1)为高电压电平，因此端点N4为高电压电平，导通晶体管T15与T16，使得移位寄存器的输出信号N与晶体管T2的栅极被耦接至低电压源VSS，使得移位寄存器的输出信号N不易受到噪声的干扰而波动。At time t3, the output signal N of the shift register is at a low voltage level, the transistor T17 is turned off, and the terminal N3 is at a high voltage level so that the transistor T13 is turned on. At this time, the output signal (N+1) of the secondary shift register is a high voltage level, so the terminal N4 is a high voltage level, and the transistors T15 and T16 are turned on, so that the output signal N of the shift register and the transistor T2 The gate is coupled to the low voltage source VSS, so that the output signal N of the shift register is not easily disturbed by noise and fluctuates.

在时间t3以外，当第一时钟信号为低电压电平时，移位寄存器的输出信号N通过晶体管T3被耦接至低电压源VSS。当第二时钟信号为低电压电平时，移位寄存器的输出信号N通过晶体管T8被耦接至低电压源VSS。利用这样的下拉机制可确保移位寄存器的输出信号N保持在关闭状态，而不会受到噪声的影响。Outside time t3, when the first clock signal is at a low voltage level, the output signal N of the shift register is coupled to the low voltage source VSS through the transistor T3. When the second clock signal is at a low voltage level, the output signal N of the shift register is coupled to the low voltage source VSS through the transistor T8. Utilizing such a pull-down mechanism can ensure that the output signal N of the shift register remains in an off state without being affected by noise.

在图10的电路中，移位寄存器利用了次级移位寄存器的信号(N+1)当作电压源，用以将移位寄存器的输出信号N固定在低电压电平，避免受到噪声干扰而飘移。且第一时钟信号与第二时钟信号仅具有50％的工作周期，与图1中现有移位寄存器中晶体管T21与T22的100％工作周期相比，根据本发明的移位寄存器中晶体管的临界电压的电压飘移情形已大幅减小，且利用晶体管T15与T16更可减少移位寄存器的下降时间(falling time)。In the circuit in Figure 10, the shift register uses the signal (N+1) of the secondary shift register as a voltage source to fix the output signal N of the shift register at a low voltage level to avoid interference from noise And drift. And the first clock signal and the second clock signal only have a duty cycle of 50%, compared with the 100% duty cycle of transistors T21 and T22 in the existing shift register in FIG. 1, the transistors in the shift register according to the present invention The voltage drift of the threshold voltage has been greatly reduced, and the falling time of the shift register can be reduced by using the transistors T15 and T16.

虽然本发明已以较佳实施例揭露如上，然其并非用以限定本发明，任何熟习此技艺者，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，因此本发明的保护范围当视后附的申请专利范围所界定者为准。Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, this The scope of protection of the invention shall be defined by the scope of the appended patent application.

Claims (18)

1. a shift register circuit has a plurality of shift registers that are connected in series level, comprising:

One the first transistor has a grid, one source pole and a drain electrode, and wherein, the grid of this first transistor and the source electrode of this first transistor couple the output signal of a prime shift register;

One transistor seconds has a grid, one source pole and a drain electrode, and wherein, the grid of this transistor seconds couples the drain electrode of this first transistor, and the source electrode of this transistor seconds couples one first clock signal, and the drain electrode of this transistor seconds couples an output terminal;

One first drop-down module couples this output terminal and this first clock signal, when the output signal of this prime shift register and this first clock signal are low voltage level, couples this output terminal to one first voltage level; And

One second drop-down module couples this output terminal and a second clock signal, when the output signal of this prime shift register and this second clock signal are low voltage level, couples this output terminal to this first voltage level.

2. shift register circuit as claimed in claim 1, wherein, more comprise one the 3rd drop-down module, couple the output signal of a level shift register, when the output signal of secondary shift register is high-voltage level, couple this output terminal to this first voltage level.

3. shift register circuit as claimed in claim 1 wherein, more comprises one first switchgear, couples this output terminal and this first drop-down module, when this output terminal is high-voltage level, closes this first drop-down module.

4. shift register circuit as claimed in claim 1, wherein, the phase differential of this second clock signal and this first clock signal is 180 degree.

5. shift register circuit as claimed in claim 1, wherein, this first clock signal has for 50% work period.

6. shift register circuit as claimed in claim 1, wherein, this first drop-down module comprises:

One the 3rd transistor has a grid, one source pole and a drain electrode, and wherein, the 3rd transistorized source electrode couples this output terminal, and the 3rd transistor drain couples this first voltage level;

One the 4th transistor, have a grid, one source pole and a drain electrode, wherein the 4th transistor drain couples this first voltage level, and the 4th transistorized grid couples the 3rd transistorized grid, and the 4th transistorized source electrode couples the drain electrode of this transistor seconds;

One the 5th transistor has a grid, one source pole and a drain electrode, and wherein, the 5th transistorized grid and the 5th transistorized source electrode couple this second clock signal, and the 5th transistor drain couples the 3rd transistorized grid;

One the 6th transistor, have a grid, one source pole and a drain electrode, wherein, the 6th transistor drain couples this first voltage level, the 6th transistorized grid couples this first clock signal, and the 6th transistorized source electrode couples the 3rd transistorized grid; And

One the 7th transistor, have a grid, one source pole and a drain electrode, wherein, the 7th transistor drain couples this first voltage level, the 7th transistorized grid couples the output signal of this prime shift register, and the 7th transistorized source electrode couples the 3rd transistorized grid.

7. shift register circuit as claimed in claim 1, wherein, this second drop-down module comprises:

One the 8th transistor has a grid, one source pole and a drain electrode, and wherein, the 8th transistorized source electrode couples this output terminal, and the 8th transistor drain couples this first voltage level;

One the 9th transistor, have a grid, one source pole and a drain electrode, wherein, the 9th transistor drain couples this first voltage level, the 9th transistorized grid couples the 8th transistorized grid, and the 9th transistorized source electrode couples the drain electrode of this transistor seconds;

The tenth transistor has a grid, one source pole and a drain electrode, and wherein, the tenth transistorized grid and the tenth transistorized source electrode couple this first clock signal, and the tenth transistor drain couples the 8th transistorized grid;

The 11 transistor, have a grid, one source pole and a drain electrode, wherein, the 11 transistor drain couples this first voltage level, the 11 transistorized grid couples this second clock signal, and the 11 transistorized source electrode couples the 8th transistorized grid; And

The tenth two-transistor, have a grid, one source pole and a drain electrode, wherein, the drain electrode of the tenth two-transistor couples this first voltage level, the grid of the tenth two-transistor couples this output terminal, and the source electrode of the tenth two-transistor couples the 8th transistorized grid.

8. shift register circuit as claimed in claim 2, wherein, the 3rd drop-down module comprises:

The 13 transistor has a grid, one source pole and a drain electrode, and wherein, the 13 transistorized grid couples this first drop-down module, and the 13 transistorized source electrode couples the output signal of this secondary shift register;

The 14 transistor, have a grid, one source pole and a drain electrode, wherein, the 14 transistorized source electrode couples the 13 transistor drain, the 14 transistor drain couples this first voltage level, and the 14 transistorized grid couples this first clock signal;

The 15 transistor, have a grid, one source pole and a drain electrode, wherein, the 15 transistorized grid couples the 13 transistor drain, the 15 transistor drain couples this first voltage level, and the 15 transistorized source electrode couples this output terminal; And

The 16 transistor, have a grid, one source pole and a drain electrode, wherein, the 16 transistorized grid couples the 13 transistor drain, the 16 transistor drain couples this first voltage level, and the 16 transistorized source electrode couples the drain electrode of this transistor seconds.

9. shift register circuit as claimed in claim 3, wherein, this first switchgear is 1 the 17 transistor, have a grid, one source pole and a drain electrode, wherein, the 17 transistorized grid couples this output terminal, and the 17 transistorized source electrode couples this first drop-down module, and the 17 transistor drain couples this first voltage level.

10. shift register circuit as claimed in claim 1, wherein the output signal of this prime shift register is a sensitizing pulse signal.

11. a shift register circuit, the shift register with a plurality of serial connection levels comprises:

One the first transistor has a grid, one source pole and a drain electrode, and wherein the source electrode of the grid of this first transistor and this first transistor couples the output signal of a prime shift register;

One transistor seconds has a grid, one source pole and a drain electrode, and wherein, the grid of this transistor seconds couples the drain electrode of this first transistor, and the source electrode of this transistor seconds couples one first clock signal, and the drain electrode of this transistor seconds couples an output terminal;

One the 3rd transistor has a grid, one source pole and a drain electrode, and wherein, the 3rd transistorized source electrode couples this output terminal, and the 3rd transistor drain couples this first voltage level;

One the 4th transistor, have a grid, one source pole and a drain electrode, wherein, the 4th transistor drain couples this first voltage level, the 4th transistorized grid couples the 3rd transistorized grid, and the 4th transistorized source electrode couples the drain electrode of this transistor seconds;

One the 5th transistor has a grid, one source pole and a drain electrode, and wherein, the 5th transistorized grid and the 5th transistorized source electrode couple this second clock signal, and the 5th transistor drain couples the 3rd transistorized grid;

One the 6th transistor, have a grid, one source pole and a drain electrode, wherein the 6th transistor drain couples this first voltage level, and the 6th transistorized grid couples this first clock signal, and the 6th transistorized source electrode couples the 3rd transistorized grid;

One the 7th transistor, have a grid, one source pole and a drain electrode, wherein, the 7th transistor drain couples this first voltage level, the 7th transistorized grid couples the output signal of this prime shift register, and the 7th transistorized source electrode couples the 3rd transistorized grid;

One the 8th transistor has a grid, one source pole and a drain electrode, and wherein, the 8th transistorized source electrode couples this output terminal, and the 8th transistor drain couples this first voltage level;

One the 9th transistor, have a grid, one source pole and a drain electrode, wherein, the 9th transistor drain couples this first voltage level, the 9th transistorized grid couples the 8th transistorized grid, and the 9th transistorized source electrode couples the drain electrode of this transistor seconds;

The tenth transistor has a grid, one source pole and a drain electrode, and wherein, the tenth transistorized grid and the tenth transistorized source electrode couple this first clock signal, and the tenth transistor drain couples the 8th transistorized grid;

The 11 transistor, have a grid, one source pole and a drain electrode, wherein, the 11 transistor drain couples this first voltage level, the 11 transistorized grid couples this second clock signal, and the 11 transistorized source electrode couples the 8th transistorized grid; And

The tenth two-transistor, have a grid, one source pole and a drain electrode, wherein, the drain electrode of the tenth two-transistor couples this first voltage level, the grid of the tenth two-transistor couples this output terminal, and the source electrode of the tenth two-transistor couples the 8th transistorized grid.

12. shift register circuit as claimed in claim 11 wherein, more comprises one the 3rd drop-down module, couple the output signal of a level shift register, when the output signal of secondary shift register is high-voltage level, couple this output terminal to this first voltage level, comprising:

The 13 transistor has a grid, one source pole and a drain electrode, and wherein, the 13 transistorized grid couples the 3rd transistorized grid, and the 13 transistorized source electrode couples the output signal of this secondary shift register;

The 14 transistor, have a grid, one source pole and a drain electrode, wherein, the 14 transistorized source electrode couples the 13 transistor drain, the 14 transistor drain couples this first voltage level, and the 14 transistorized grid couples this first clock signal;

The 15 transistor, have a grid, one source pole and a drain electrode, wherein, the 15 transistorized grid couples the 13 transistor drain, the 15 transistor drain couples this first voltage level, and the 15 transistorized source electrode couples this output terminal; And

The 16 transistor, have a grid, one source pole and a drain electrode, wherein, the 16 transistorized grid couples the 13 transistor drain, the 16 transistor drain couples this first voltage level, and the 16 transistorized source electrode couples the drain electrode of this transistor seconds.

13. shift register circuit as claimed in claim 11 wherein, more comprises one first switchgear, when this output terminal is high-voltage level, closes the 3rd transistor, comprising:

The 17 transistor, have a grid, one source pole and a drain electrode, wherein, the 17 transistorized grid couples this output terminal, the 17 transistorized source electrode couples the 3rd transistorized grid, and the 17 transistor drain couples this first voltage level.

14. shift register circuit as claimed in claim 11, wherein, the phase differential of this second clock signal and this first clock signal is 180 degree.

15. shift register circuit as claimed in claim 11, wherein, this first clock signal has for 50% work period.

16. shift register circuit as claimed in claim 11, wherein, the output signal of this prime shift register is a sensitizing pulse signal.

17. shift register circuit as claimed in claim 11, wherein, described transistor is a nmos pass transistor.

18. shift register circuit as claimed in claim 11, wherein, described transistor is the TFT thin film transistor (TFT), is arranged on the glass substrate.

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