CN100419835C - Pixel circuit and display device - Google Patents

Abstract

The present invention turns on a selection TFT (20) and a correction TFT (22) to hold a data voltage of a data line in a holding capacitor (28) as a gate voltage of a driving TFT (24). After the selection TFT (20) is turned off, the voltage of the capacitor line (SC) is lowered, thereby turning on the drive TFT (24) and causing a drive current to flow through the organic EL element (26). The correction TFT (22) is turned on before the capacitance line (SC) falls and turned off during the fall. Therefore, during the gate voltage drop, the capacitance value of the correction TFT (22) changes, and the gate voltage drop gradient of the drive TFT (24) changes, whereby the gate voltage after the capacitor line (SC) drops is set in accordance with the change in the threshold value of the drive TFT (24). Particularly, by disposing the driving TFT 24 and the correcting TFT 22 adjacent to each other, the characteristics of both are brought into the same state, and correction can be performed efficiently.

Description

Translated fromChinese

像素电路及显示装置Pixel circuit and display device

技术领域technical field

本发明关于包含有机EL(Electro Luminescence：电场发光)组件等发光组件的像素电路、及将该有机EL组件配置成矩阵状的显示装置。The present invention relates to a pixel circuit including a light-emitting element such as an organic EL (Electro Luminescence) element, and a display device in which the organic EL element is arranged in a matrix.

背景技术Background technique

已知有使用有机EL组件作为发光组件的有机EL面板，且其开发也有所进展。在该有机EL面板中，将有机EL组件配置成矩阵状，个别控制该有机EL组件的发光，而执行显示。尤其在主动矩阵式有机EL面板中，每个像素都具有控制显示用的TFT，由此控制该TFT的动作，便可控制每个像素的发光，所以可以执行精度非常高的显示。An organic EL panel using an organic EL element as a light-emitting element is known, and its development is progressing. In this organic EL panel, organic EL elements are arranged in a matrix, and light emission of the organic EL elements is individually controlled to perform display. In particular, in an active matrix organic EL panel, each pixel has a TFT for controlling display, and by controlling the operation of the TFT, the light emission of each pixel can be controlled, so that very high-precision display can be performed.

图13所表示的是主动矩阵式有机EL面板的像素电路的一例。供应显示像素亮度的数据电压的数据线经由栅极连接于栅极线的n沟道的选择TFT 10，而连接于驱动TFT 12的栅极。此外，在驱动TFT 12的栅极连接有另一端连接于保持电容线SC的保持电容14的一端，并保持驱动TFT 12的栅极电压。FIG. 13 shows an example of a pixel circuit of an active matrix organic EL panel. A data line supplying a data voltage for displaying pixel luminance is connected to a gate of a drivingTFT 12 via an n-channel selection TFT 10 whose gate is connected to the gate line. In addition, the gate of the driving TFT 12 is connected to one end of theholding capacitor 14 whose other end is connected to the holding capacitor line SC, and holds the gate voltage of the drivingTFT 12.

驱动TFT 12的源极连接于EL电源线，漏极连接于有机EL组件16的阳极，有机EL组件16的阴极连接于阴极电源。The source of the driving TFT 12 is connected to the EL power supply line, the drain is connected to the anode of theorganic EL component 16, and the cathode of theorganic EL component 16 is connected to the cathode power supply.

这种像素电路被配置成矩阵状，依预定时序(timing)使设置于每个水平线的栅极线变成H电位，该行的选择TFT 10成为导通(ON)状态。在此状态下，为能对数据线依序供应数据电压，该数据电压被供应并保持于保持电容14，即便栅极线转变为L电位，仍保持该时的电压。Such pixel circuits are arranged in a matrix, and the gate lines provided on each horizontal line are set at H potential at predetermined timing, so that theselection TFT 10 of the row is turned on (ON). In this state, in order to sequentially supply data voltages to the data lines, the data voltages are supplied and held in theholding capacitor 14, and even if the gate line is changed to L potential, the voltage at that time is maintained.

然后，对应此保持电容14中所保持的电压，使驱动TFT 12产生动作，相对应的驱动电流从EL电源线经由有机EL组件16而流入阴极电源，有机EL组件16便对应数据电压而进行发光。Then, corresponding to the voltage held in thestorage capacitor 14, the drivingTFT 12 is activated, and the corresponding driving current flows from the EL power line through theorganic EL element 16 to the cathode power supply, and theorganic EL element 16 emits light corresponding to the data voltage. .

然后，将栅极线依序转为H电位，将所输入的视频信号(video signal)当作数据电压依序供应给所对应的像素，借此被配置成矩阵状的有机EL组件16便对应数据电压进行发光，执行关于视频信号的显示。Then, the gate lines are sequentially turned to H potential, and the input video signal (video signal) is sequentially supplied to the corresponding pixels as a data voltage, so that theorganic EL elements 16 configured in a matrix form correspond to The data voltage emits light, and display with respect to the video signal is performed.

但是，在此种像素电路中，配置成矩阵状的像素电路的驱动TFT，若其临限值电压不均匀的话，亮度将呈不均匀状态，而造成显示质量降低的问题发生。所以，针对构成整个显示面板的像素电路的TFT，难以将其特性变为相同状态，且难以防止其导通或关断的临限值不发生不均现象。However, in such a pixel circuit, if the threshold voltages of the drive TFTs arranged in a matrix are not uniform, the luminance will be non-uniform, resulting in a problem of degradation in display quality. Therefore, it is difficult to make the characteristics of the TFTs constituting the pixel circuits of the entire display panel into the same state, and it is difficult to prevent non-uniformity in the threshold value of their turn-on or turn-off.

所以，便期待防止驱动TFT的临限值不均对于显示造成影响。Therefore, it is desired to prevent the non-uniform threshold value of the driving TFT from affecting the display.

在此，针对用以防止对TFT临限值变动造成影响的电路，自以往便有各种方案(例如日本专利特表2002-514320号公报)。Here, conventionally, there have been various proposals for circuits for preventing the influence of fluctuations in the TFT threshold value (for example, Japanese Patent Laid-Open No. 2002-514320).

但是，在该方案中，需要设置用以进行临限值变动补偿的电路。所以，若使用这种电路的话，便会发生像素电路的组件数增加，开口率变小的问题发生。此外，当追加补偿用的电路时，将产生驱动像素电路用的外围电路必须变更的问题。However, in this scheme, it is necessary to provide a circuit for compensating for fluctuations in the threshold value. Therefore, if such a circuit is used, the number of components of the pixel circuit increases and the aperture ratio becomes smaller. In addition, when a circuit for compensation is added, there arises a problem that peripheral circuits for driving pixel circuits must be changed.

发明内容Contents of the invention

本发明提供一种以简单的变更，便可有效的补偿驱动晶体管的临限值电压变动的像素电路。The invention provides a pixel circuit capable of effectively compensating the variation of the threshold voltage of the driving transistor by simple modification.

本发明所涉及的一种像素电路，其具有：一端连接于数据线，且对控制端输入选择信号的选择晶体管；一端连接于此选择晶体管的另一端，且控制端连接于预定电压的第1电源的修正晶体管；控制端连接于此修正晶体管的另一端，一端连接于作为电流供应源的第2电源的驱动晶体管；一端连接于此驱动晶体管的控制端，另一端连接于脉冲电压线的保持电容；以及利用流通于所述驱动晶体管的电流而发光的发光组件；在利用变更所述脉冲电压线的电压值而导通所述驱动晶体管的过程中，使所述修正晶体管导通或关断，借此控制驱动晶体管导通时的控制端电压，同时所述驱动晶体管与所述修正晶体管形成邻接状态。A pixel circuit according to the present invention includes: a selection transistor whose one end is connected to a data line and a selection signal is input to a control end; The correction transistor of the power supply; the control end is connected to the other end of the correction transistor, and one end is connected to the drive transistor of the second power supply as the current supply source; one end is connected to the control end of the drive transistor, and the other end is connected to the hold of the pulse voltage line a capacitor; and a light-emitting element that emits light by using the current flowing through the driving transistor; during the process of turning on the driving transistor by changing the voltage value of the pulse voltage line, the correction transistor is turned on or off , so as to control the voltage of the control terminal when the driving transistor is turned on, and at the same time, the driving transistor and the correction transistor form an adjacent state.

再者，优选的是，所述数据线与电源线朝垂直扫描方向延伸，且所述修正晶体管形成于所述数据线与电源线之间。Furthermore, preferably, the data line and the power line extend in a vertical scanning direction, and the correction transistor is formed between the data line and the power line.

再者，所述驱动晶体管优选的是，夹着所述电源线，而形成于所述修正晶体管的相反侧。Furthermore, it is preferable that the drive transistor is formed on the opposite side of the correction transistor across the power supply line.

再者，优选的是，在将所述选择晶体管导通的状态下，对数据线供应使修正晶体管导通的数据电压，并将对应数据电压的电压保持在驱动晶体管的控制端，然后，使所述选择晶体管关断，在此状态下，使脉冲电压线的电压产生变化，且使驱动晶体管的控制端电压移位，借此使修正晶体管关断，同时使驱动晶体管导通，且使对应数据电压的电流流通于驱动晶体管。Furthermore, preferably, in the state where the selection transistor is turned on, the data line is supplied with a data voltage for turning on the correction transistor, and the voltage corresponding to the data voltage is kept at the control terminal of the driving transistor, and then, the The selection transistor is turned off. In this state, the voltage of the pulse voltage line is changed, and the voltage of the control terminal of the driving transistor is shifted, so that the correction transistor is turned off, and the driving transistor is turned on at the same time, and the corresponding The current of the data voltage flows through the driving transistor.

再者，优选的是，所述第1电源与第2电源为同一电源。Furthermore, preferably, the first power supply and the second power supply are the same power supply.

再者，所述修正晶体管与驱动晶体管是p型沟道晶体管，优选的是，所述脉冲电压线在所述选择晶体管关断之后，从高电位变化成低电位。Furthermore, the correction transistor and the driving transistor are p-type channel transistors. Preferably, the pulse voltage line changes from a high potential to a low potential after the selection transistor is turned off.

本发明的另一实施例涉及若干若干个像素排列成矩阵状的显示装置，各像素具有：对应供应电力进行动作的显示组件；第1导电区域连接于数据线，并对控制端输入选择信号的选择晶体管；第1导电区域连接于电源线，将电力供应给所述显示组件的驱动晶体管；控制端连接于预定电压的第1电源，第1导电区域连接于所述选择晶体管的第2导电区域，第2导电区域连接于所述驱动晶体管的控制端的修正晶体管；以及，第1电极连接于所述驱动晶体管的控制端与所述修正晶体管的第2导电区域，第2电极连接于脉冲电压线的保持电容。此外，所述驱动晶体管的控制端电压对应所述脉冲电压线的电压变动产生变化，而对应于此变化，所述修正晶体管对应其动作临限值来控制所述驱动晶体管成为导通状态时的所述控制端电压。另外，所述修正晶体管与所述驱动晶体管由同一导电型晶体管所构成，且所述修正晶体管与所述驱动晶体管的至少沟道区域，均由经激光退火而多结晶化的半导体层所构成，该沟道区域相互接近配置。Another embodiment of the present invention relates to a display device in which a plurality of pixels are arranged in a matrix, and each pixel has: a display component that operates corresponding to the power supply; the first conductive region is connected to the data line, and a selection signal is input to the control terminal Selection transistor; the first conductive area is connected to the power line, and power is supplied to the driving transistor of the display component; the control terminal is connected to the first power supply of a predetermined voltage, and the first conductive area is connected to the second conductive area of the selection transistor , the second conductive region is connected to the correction transistor of the control terminal of the driving transistor; and the first electrode is connected to the control terminal of the driving transistor and the second conductive region of the correction transistor, and the second electrode is connected to the pulse voltage line of hold capacitance. In addition, the control terminal voltage of the driving transistor changes in response to the voltage variation of the pulse voltage line, and corresponding to this change, the correction transistor controls the voltage when the driving transistor is turned on according to its operating threshold value. the control terminal voltage. In addition, the correction transistor and the drive transistor are composed of transistors of the same conductivity type, and at least channel regions of the correction transistor and the drive transistor are composed of semiconductor layers that have been polycrystallized by laser annealing, The channel regions are arranged close to each other.

本发明的另一实施例在所述像素电路与显示装置中，所述修正晶体管的沟道长度方向与所述驱动晶体管的沟道长度方向，配置成平行于所述多结晶化激光退火时所照射的线状脉冲激光的扫描方向，且所述修正晶体管的沟道区域与所述驱动晶体管的沟道区域，其至少一部分均位于所述脉冲激光扫描方向正交方向所拉出的同一条线上。In another embodiment of the present invention, in the pixel circuit and the display device, the channel length direction of the correction transistor and the channel length direction of the driving transistor are arranged parallel to the polycrystallization laser annealing. The scanning direction of the irradiated linear pulsed laser, and at least a part of the channel region of the correction transistor and the channel region of the driving transistor are located on the same line drawn in the direction perpendicular to the pulsed laser scanning direction superior.

在本发明另一实施例所涉及的显示装置中，所述修正晶体管与所述驱动晶体管由同一导电型晶体管所构成，且采用所述修正晶体管的主动层的至少一部分在层间夹介着绝缘层而形成在所述电源线下层位置的构造。In the display device according to another embodiment of the present invention, the correction transistor and the drive transistor are composed of transistors of the same conductivity type, and at least a part of the active layer of the correction transistor is used to interpose an insulating layer between the layers. layer to form a structure at the position of the lower layer of the power cord.

再者，本发明中，在所述显示装置中，所述第1电源兼用作电源线，也可以在所述修正晶体管的主动层与所述电源线的层间形成有连接于所述电源线的所述修正晶体管的控制端。此外，所述修正晶体管也可具备有在所述数据线与所述电源线的线间，形成至少与其中一方的线呈部分重叠状态延伸的主动层。Moreover, in the present invention, in the display device, the first power supply is also used as a power supply line, and a layer connected to the power supply line may also be formed between the active layer of the correction transistor and the power supply line. The control terminal of the correction transistor. In addition, the correction transistor may include an active layer formed between the data line and the power supply line and extending in a state of partially overlapping at least one of the lines.

本发明的另一实施例在所述显示装置中，所述修正晶体管的沟道区域具备有在其沟道长度方向，沟道宽度互异的部分。According to another embodiment of the present invention, in the display device, the channel region of the correction transistor has portions having different channel widths in the channel length direction.

如以上所述，根据本发明，在利用变更脉冲电压线的电压值而使驱动晶体管导通的过程中，变更修正晶体管的导通或关断状态，借此来控制驱动晶体管导通时的控制端电压。所以，可对应修正晶体管的临限值电压，将不同电压设定在所对应的驱动晶体管的控制端。此外，因为将驱动晶体管与修正晶体管形成邻接状态，因而可轻易将驱动晶体管与修正晶体管的临限值电压设为相同电压，而可利用修正晶体管补偿驱动晶体管的临限值电压，且可使流通于发光组件的电流量呈均匀状态。As described above, according to the present invention, during the process of turning on the driving transistor by changing the voltage value of the pulse voltage line, the on or off state of the correction transistor is changed, thereby controlling the control when the driving transistor is turned on. terminal voltage. Therefore, different voltages can be set at the corresponding control terminals of the driving transistors corresponding to the threshold voltages of the correction transistors. In addition, since the drive transistor and the correction transistor are formed adjacent to each other, the threshold voltage of the drive transistor and the correction transistor can be easily set to the same voltage, and the threshold voltage of the drive transistor can be compensated by the correction transistor, and the current flow can be made The amount of current in the light-emitting component is uniform.

再者，数据线与电源线朝垂直扫描方向延伸，并将修正晶体管形成于数据线与电源线的线间，且夹介着电源线而在修正晶体管的相反侧形成驱动晶体管等，借此可有效率的配置，而可尽可能的增大发光组件等显示组件，而实现高开口率的显示装置。Furthermore, the data line and the power line extend in the vertical scanning direction, and the correction transistor is formed between the data line and the power line, and the driving transistor is formed on the opposite side of the correction transistor with the power line interposed therebetween, thereby enabling With efficient configuration, the display components such as light-emitting components can be enlarged as much as possible, so as to realize a display device with a high aperture ratio.

例如，在电源线的下层区域，在层间夹介着绝缘层而重叠配置修正晶体管的主动层，借此可更加提升1像素内的配置自由度。此外，当将修正晶体管的控制端(栅极电极)连接于电源线时，即便修正晶体管的主动层位于电源线下方，因为仍可对其沟道区域利用控制端来施加与电源线相同的电压，所以可减小对晶体管动作的影响。For example, in the region of the lower layer of the power supply line, the active layer of the correction transistor is overlapped with an insulating layer interposed between the layers, thereby further increasing the degree of freedom of arrangement within one pixel. In addition, when the control terminal (gate electrode) of the correction transistor is connected to the power supply line, even if the active layer of the correction transistor is located below the power supply line, the same voltage as the power supply line can still be applied to the channel region by using the control terminal , so the influence on the operation of the transistor can be reduced.

再者，在修正晶体管的沟道长度方向，设置沟道宽度互异的部分，借此也可提升1像素内的各晶体管等的配置自由度。Furthermore, in the direction of the channel length of the correction transistor, a portion having a different channel width is provided, whereby the degree of freedom in the arrangement of each transistor etc. in one pixel can also be improved.

再者，由于脉冲电压线的电压变动，驱动晶体管从关断转为导通状态，且修正晶体管的导通或关断状态切换，其电容值将产生变化。所以，因应修正晶体管的临限值变化，驱动晶体管的栅极电压便变化着利用某电压来施行修正晶体管的导通或关断的切换。此外，对应脉冲电压线变化的驱动晶体管的栅极电压的变化，乃是由修正晶体管的电容值所引起的，因此对应修正晶体管的临限值变动，栅极电压将产生变动。所以，由于以抵消驱动晶体管的临限值变动的方式，使驱动晶体管的栅极电压产生变化，因此可以尽可能整合修正晶体管的特性与驱动晶体管的特性而使控制变为容易。Furthermore, due to the voltage variation of the pulse voltage line, the driving transistor turns from off to on, and the correction transistor switches from on to off, and its capacitance value will change. Therefore, in response to the change of the threshold value of the correction transistor, the gate voltage of the drive transistor is changed to use a certain voltage to switch the correction transistor on or off. In addition, the variation of the gate voltage of the driving transistor corresponding to the variation of the pulse voltage line is caused by the capacitance value of the correction transistor, so corresponding to the variation of the threshold value of the correction transistor, the gate voltage will fluctuate. Therefore, since the gate voltage of the driving transistor is varied in such a way as to cancel out the variation of the threshold value of the driving transistor, the characteristics of the correction transistor and the characteristics of the driving transistor can be integrated as much as possible to facilitate control.

所以，当修正晶体管与驱动晶体管的沟道区域，均由经激光退火而多结晶化的半导体层所构成时，至少将此沟道区域相互接近配置，借此可轻易整合特性。Therefore, when the channel regions of the trimming transistor and the driving transistor are both composed of semiconductor layers that have been polycrystallized by laser annealing, at least the channel regions are arranged close to each other, so that characteristics can be easily integrated.

例如，当采用经激光退火而多结晶化的主动层时，将修正晶体管的沟道长度方向与驱动晶体管的沟道长度方向，配置成平行于多结晶化激光退火时所照射线状脉冲激光扫描方向，借此可对晶体管的电移动度影响较大的沟道长度方向，照射若干次的激光脉冲，可降低每个像素的各晶体管特性偏差量。此外，通过将修正晶体管的沟道区域与所述驱动晶体管的沟道区域的位置，均排列成至少一部分位于所述脉冲激光扫描方向的正交方向所拉出的同一条线上，即可因为同一激光束照射此2个晶体管的沟道区域，而使其特性更加接近。For example, when using an active layer polycrystallized by laser annealing, the channel length direction of the correction transistor and the channel length direction of the driving transistor are arranged parallel to the linear pulse laser scanning irradiated during polycrystallization laser annealing. In this way, the channel length direction, which has a greater influence on the electric mobility of the transistor, can be irradiated several times with laser pulses, which can reduce the deviation of each transistor characteristic of each pixel. In addition, by arranging the positions of the channel region of the correction transistor and the channel region of the driving transistor so that at least part of them are located on the same line drawn in the direction perpendicular to the scanning direction of the pulsed laser, it is possible because Irradiating the channel regions of these two transistors with the same laser beam brings their characteristics closer together.

再者，若所述第1电源与第2电源设为同一电源的话，便不需要个别设置电源线。Furthermore, if the first power supply and the second power supply are the same power supply, there is no need to separately install a power supply line.

再者，当将修正晶体管与驱动晶体管设定为同一p型沟道晶体管时，所述脉冲电压线在所述选择晶体管关断之后，由从高电位变化成低电位，便可有效的利用p型沟道晶体管的栅极电容。Furthermore, when the correction transistor and the driving transistor are set as the same p-channel transistor, the pulse voltage line changes from a high potential to a low potential after the selection transistor is turned off, so that the p-channel can be effectively used. type channel transistor gate capacitance.

附图说明Description of drawings

图1是本发明实施例所涉及的像素电路构造图。FIG. 1 is a structural diagram of a pixel circuit involved in an embodiment of the present invention.

图2是本发明实施例中，对栅极线GL、电容线SC所施加信号的时序图。FIG. 2 is a timing diagram of signals applied to the gate line GL and the capacitor line SC in the embodiment of the present invention.

图3是本发明实施例所涉及的栅极电压Vg24变化状态图。FIG. 3 is a diagram showing the variation state of the gate voltage Vg24 involved in the embodiment of the present invention.

图4是本发明实施例所涉及的像素电路中，所存在电容的说明图。FIG. 4 is an explanatory diagram of capacitors existing in the pixel circuit according to the embodiment of the present invention.

图5是本发明实施例所涉及的像素平面构造一例图。FIG. 5 is an example diagram of a pixel plane structure involved in an embodiment of the present invention.

图6A是沿图5A-A线的概略剖视构造图。Fig. 6A is a schematic cross-sectional structural diagram along line A-A of Fig. 5 .

图6B是沿图5B-B线的概略剖视构造图。FIG. 6B is a schematic cross-sectional structural diagram along line B-B in FIG. 5 .

图7是本发明实施例中，将修正TFT多栅极化时，平均每1像素的等效电路图。FIG. 7 is an equivalent circuit diagram per one pixel when the correction TFT is multi-gated in an embodiment of the present invention.

图8是实现图7所示等效电路的布局一例概略平面图。Fig. 8 is a schematic plan view showing an example of a layout for realizing the equivalent circuit shown in Fig. 7 .

图9是本发明实施例中，将选择TFT与修正TFT二者施行多栅极化时的等效电路图。FIG. 9 is an equivalent circuit diagram when multiple gates are performed on both the selection TFT and the correction TFT in the embodiment of the present invention.

图10是实现图9所示等效电路的布局一例图。FIG. 10 is a diagram showing an example of a layout for realizing the equivalent circuit shown in FIG. 9 .

图11是图10所示布局的另一例图。FIG. 11 is another example of the layout shown in FIG. 10 .

图12是本发明实施例的另一例电路构造图。Fig. 12 is another circuit configuration diagram of the embodiment of the present invention.

图13是已知像素电路构造图。FIG. 13 is a structural diagram of a known pixel circuit.

符号说明Symbol Description

10选择TFT            12驱动TFT10Select TFT 12 Drive TFT

14保持电容           16有机EL组件14 holdingcapacitor 16 organic EL components

20选择TFT            22修正TFT20Select TFT 22 Modify TFT

24驱动TFT            26有机EL组件24drive TFT 26 organic EL components

28保持电容           30抑制漏电流TFT28hold capacitor 30 suppress leakage current TFT

100透明(绝缘)基板    102缓冲层100 transparent (insulating)substrate 102 buffer layer

104栅极绝缘膜(层)    106层间绝缘膜(层)104 gate insulating film (layer) 106 interlayer insulating film (layer)

108平面化绝缘层      110第2平面化绝缘层108Planarized insulating layer 110 The second planarized insulating layer

120半导体层          122主动层120semiconductor layer 122 active layer

124半导体层          262第1电极(阳极)124semiconductor layer 262 first electrode (anode)

264第2电极(阴极)     270发光组件层264 Second electrode (cathode) 270 Light emitting component layer

272空穴输送层        274发光层272hole transport layer 274 light emitting layer

276电子输送层        22-1第1修TFT276 Electron transport layer 22-1 1st Repair TFT

22-2第2修TFT         20c沟道区域22-22nd revision TFT 20c channel area

20d漏极区域          20g(20g1、20g2)栅极电极20d drain region 20g (20g1, 20g2) gate electrode

20s源极区域          22c沟道区域20s sourceregion 22c channel region

22d漏极区域          22g(22g1、22g2)栅极电极22d drain region 22g (22g1, 22g2) gate electrode

22s源极区域          24c沟道区域22s sourceregion 24c channel region

24d漏极区域          24e连接电极24d drain region 24e connection electrode

24g栅极              24s源极区域24g gate 24s source region

24w金属配线          28e电容电极(第1电极)24w metal wiring 28e capacitor electrode (first electrode)

Cs保持电容值        CV阴极电源Cs hold capacitor value CV cathode power supply

Cw1寄生电容         Cw2寄生电容Cw1 parasitic capacitance Cw2 parasitic capacitance

DL数据线            GL栅极线DL data line GL gate line

PL电源线            SC电容线PL power line SC capacitor line

具体实施方式Detailed ways

以下，针对本发明实施例，参照附图进行说明。Hereinafter, embodiments of the present invention will be described with reference to the drawings.

图1是实施例所涉及的1像素的像素电路构造图。在朝垂直扫描方向延伸的数据线DL，连接有n型沟道选择TFT 20的第1导电区域(漏极)。该选择TFT 20的栅极(控制端)连接于朝水平扫描方向延伸的栅极线GL，第2导电区域(源极)连接于p型沟道修正TFT 22的第1导电区域(源极)。另外，该选择TFT 20也可为p型沟道，当为p型沟道时，只要将对栅极线GL输出的选择信号(栅极信号)的极性(H电位或L电位)相反驱动便可。FIG. 1 is a diagram showing a pixel circuit configuration of one pixel according to the embodiment. The first conductive region (drain) of the n-typechannel selection TFT 20 is connected to the data line DL extending in the vertical scanning direction. The gate (control terminal) of theselection TFT 20 is connected to the gate line GL extending in the horizontal scanning direction, and the second conductive region (source) is connected to the first conductive region (source) of the p-typechannel correction TFT 22. . In addition, theselection TFT 20 may also be a p-type channel. When it is a p-type channel, the polarity (H potential or L potential) of the selection signal (gate signal) output to the gate line GL is reversely driven. You can.

修正TFT 22的控制端(栅极)连接于电源线PL(电压Pvdd)，第2导电区域(漏极)则连接于p型沟道驱动TFT 24的控制端(栅极)。此外，在驱动TFT 24的栅极连接保持电容28的一端(第1电极)，该保持电容28的另一端(第2电极)则连接于具有利用脉冲状电压驱动的脉冲电压线功能的保持电容线(以下称电容线)SC。此电容线SC如同栅极线GL，为朝水平扫描方向延伸的线。另外，设置其它电源线，并将修正TFT 22的栅极连接于其它电源线的话，便可任意调整将修TFT 22从导通(ON)切换为关断(OFF)的时序。The control terminal (gate) of thecorrection TFT 22 is connected to the power line PL (voltage Pvdd), and the second conductive region (drain) is connected to the control terminal (gate) of the p-typechannel driving TFT 24. In addition, one end (first electrode) of astorage capacitor 28 is connected to the gate of the drivingTFT 24, and the other end (second electrode) of thestorage capacitor 28 is connected to a storage capacitor functioning as a pulse voltage line driven by a pulse-shaped voltage. Line (hereinafter referred to as capacitance line) SC. The capacitance line SC is a line extending in the horizontal scanning direction like the gate line GL. In addition, if another power supply line is provided and the gate of thecorrection TFT 22 is connected to the other power supply line, the timing of switching thecorrection TFT 22 from conducting (ON) to turning off (OFF) can be adjusted arbitrarily.

驱动TFT 24的第1导电区域(源极)连接于朝垂直扫描方向延伸的电源线PL，第2导电区域(漏极)则连接于有机EL组件26的阳极。此外，有机EL组件26的阴极连接于预定低电压的阴极电源CV。在此，普通情况时，有机EL组件26的阴极将成为所有像素共通的状态，此阴极连接于阴极电源CV。The first conductive region (source) of the drivingTFT 24 is connected to the power line PL extending in the vertical scanning direction, and the second conductive region (drain) is connected to the anode of theorganic EL element 26. In addition, the cathode of theorganic EL element 26 is connected to a cathode power supply CV of a predetermined low voltage. Here, normally, the cathode of theorganic EL element 26 is common to all pixels, and this cathode is connected to the cathode power supply CV.

有机EL面板将这种像素电路呈矩阵状配置，在输入该水平线的视频信号的时序，该水平线的栅极线将转为H电位，该行的选择TFT 20便将成为导通状态。借此，修正TFT 22的源极便成为数据线DL的电位。In an organic EL panel, such pixel circuits are arranged in a matrix, and at the timing when a video signal of the horizontal line is input, the gate line of the horizontal line is turned to H potential, and theselection TFT 20 of the line is turned on. Thereby, the source of thecorrection TFT 22 becomes the potential of the data line DL.

在此，对数据线DL供应数据电压。该数据电压Vdata对应于显示对应像素的视频信号者，例如，依3至5V左右表现出从白电位至黑电位。另一方面，电源线PL的电压Pvdd设定于0V左右。所以，当导通选择TFT 20，并对修正TFT 22(在此为源极)施加数据线DL的数据电压Vdata时，修正TFT 22便将呈导通状态，数据电压Vdata便被设定于驱动TFT 24的栅极(节点Tg 24)。换句话说，在对各像素写入数据电压Vdata的期间，将3至5V左右的电压设定在驱动TFT 24的栅极。另外，此时保持电容28的另一端的电容线SC设定为+8V左右。Here, the data voltage is supplied to the data line DL. The data voltage Vdata corresponds to displaying the video signal of the corresponding pixel, for example, from white potential to black potential at about 3 to 5V. On the other hand, the voltage Pvdd of the power line PL is set at about 0V. Therefore, when the selectedTFT 20 is turned on, and the data voltage Vdata of the data line DL is applied to the correction TFT 22 (here, the source), thecorrection TFT 22 will be in the conduction state, and the data voltage Vdata will be set at the driving state. The gate of the TFT 24 (node Tg 24). In other words, a voltage of approximately 3 to 5 V is set at the gate of the drivingTFT 24 while the data voltage Vdata is being written to each pixel. In addition, at this time, the capacitance line SC at the other end of thestorage capacitor 28 is set to about +8V.

在这种数据电压Vdata的对驱动TFT 24栅极的写入结束之后，便将电容线SC的电压降低至例如-4V。据此，驱动TF T24的栅极将降低12V左右，驱动TFT 24将导通，对应于数据电压的电流便经由驱动TFT24从电源线PL供应至有机EL组件26而发光。After the data voltage Vdata is written into the gate of the drivingTFT 24, the voltage of the capacitance line SC is lowered to -4V, for example. Accordingly, the gate of the drivingTFT 24 will drop by about 12V, the drivingTFT 24 will be turned on, and the current corresponding to the data voltage will be supplied from the power line PL to theorganic EL element 26 through the drivingTFT 24 to emit light.

在此，修正TFT 22电容线SC从+8V降低至-4V左右，其漏极(节点Tg 24)的电压便从3至5V转为基本的-9V至-7V左右的负电压(如后述，此电压少许不同)，而从导通状态变化为关断状态。因为对应修正TFT 22从此导通变化为关断，修正TFT 22的栅极电容将产生变化，所以该电容的变化时序，即修正TFT 22的临限值V_th22便将左右最终的驱动TFT 24的栅极电位。所以，便可利用修正TFT 22来补偿驱动TFT 24的临限值电压V_th24的参差不齐。Here, the capacitance line SC of thecorrection TFT 22 is lowered from +8V to about -4V, and the voltage of its drain (node Tg 24 ) is changed from 3 to 5V to a basic negative voltage of about -9V to -7V (as described later) , this voltage is slightly different), while changing from the on state to the off state. Since the gate capacitance of thecorrection TFT 22 will change when thecorrection TFT 22 changes from being turned on to off, the timing of the change of the capacitance, that is, the threshold value V_th22 of thecorrection TFT 22 will affect thefinal driving TFT 24. gate potential. Therefore, thecorrection TFT 22 can be used to compensate the variation of the threshold voltage V_th24 of the drivingTFT 24 .

在此，驱动TFT 24对应于电源电压Pvdd与栅极电压V_g24之差值，即对应于Vgs24而导通而流通所对应的驱动电流。该Vgs24当大于由其TFT特性所决定的临限值电压V_th24之时，驱动TFT 24便开始流通电流，驱动电流量由栅极电压V_g24与临限值电压V_th24的差值而决定。另一方面，较难将基板上矩阵状配置的多数像素的各驱动TFT 24的临限值电压V_th24设为完全相同状态，临限值电压V难免因像素位置而多少有偏差情况。而且，由于有机EL组件26以对应于所供应的驱动电流量的亮度进行发光，因此各像素的发光亮度便将对应驱动TFT 24的临限值电压V_th24的偏差而发生变动。本实施例所涉及的构造利用修正TFT 22的电容变化，而补偿发光亮度的偏差。Here, the drivingTFT 24 is turned on corresponding to the difference between the power supply voltage Pvdd and the gate voltage V_g24 , that is, corresponding to Vgs24 , and flows a corresponding driving current. When the Vgs24 is greater than the threshold voltage_Vth24 determined by its TFT characteristics, the drivingTFT 24 starts to flow current, and the amount of driving current is determined by the difference between the gate voltage_Vg24 and the threshold voltage_Vth24 . On the other hand, it is difficult to set the threshold voltage V_th24 of each drivingTFT 24 of many pixels arranged in a matrix on the substrate to be completely the same state, and the threshold voltage V inevitably varies somewhat depending on the pixel position. Furthermore, since theorganic EL element 26 emits light with a luminance corresponding to the amount of supplied driving current, the light emission luminance of each pixel varies according to the variation of the threshold voltage V_th24 of the drivingTFT 24 . The structure according to the present embodiment compensates for variations in light emission luminance by correcting changes in the capacitance of theTFT 22 .

以下，针对发光亮度的偏差补偿原理，参照图2与图3进行说明。图3所示为图2中椭圆形所示的电容线SC下降时的放大状态。首先，如图2所示，栅极线GL当选择其行(水平线)之时，便成主动(H)电位。在此例中，选择TFT 20为n型沟道，栅极线GL设定为L电位＝-4V左右，H电位＝8V左右，当选择(主动)之际便设定为8V。Hereinafter, the principle of compensating the deviation of the light emission luminance will be described with reference to FIGS. 2 and 3 . FIG. 3 shows an enlarged state when the capacitance line SC indicated by the ellipse in FIG. 2 falls. First, as shown in FIG. 2, when the gate line GL selects its row (horizontal line), it becomes active (H) potential. In this example, theTFT 20 is selected as an n-type channel, and the gate line GL is set to L potential = about -4V, H potential = about 8V, and when selected (active), it is set to 8V.

此外，电容线SC的电压Vsc在比选择栅极线GL(H电位)的期间稍长的期间中将呈H电位。换句话说，在栅极线GL变为H电位之前便将转为H电位，在栅极线GL呈L电位之后便转为L电位。In addition, the voltage Vsc of the capacitance line SC has the H potential for a period slightly longer than the period of the selection gate line GL (H potential). In other words, before the gate line GL becomes the H potential, it becomes the H potential, and after the gate line GL becomes the L potential, it becomes the L potential.

在栅极线GL为H电位的期间，对应于该栅极线GL的选择TFT 20与修正TFT 22将导通，此时对数据线DL输出的数据电压Vdata，便将透过选择TFT 20与修正TFT 22而施加给节点Tg 24。即，驱动TFT24的栅极电压Vg 24将被设定为数据电压Vdata。During the period when the gate line GL is at the H potential, theselection TFT 20 and thecorrection TFT 22 corresponding to the gate line GL will be turned on. At this time, the data voltage Vdata output to the data line DL will pass through theselection TFT 20 and thecorrection TFT 22.Modification TFT 22 is applied tonode Tg 24. That is, the gate voltage Vg24 of the drivingTFT 24 will be set as the data voltage Vdata.

在栅极线GL转为L电位，且数据电压Vdata写入之后，电容线SC的电压便下降，对应此情况，节点Tg 24的电位便将降低，不久之后修正TFT 22便将关断。驱动TFT 24的栅极电压V_g24对应电容线SC的降低部分(在此例中为从8V至-4V的12V)，转为仅较数据电压Vdata降低预定电压的较低电压，并流通对应此电压的驱动电流。After the gate line GL turns to L potential and the data voltage Vdata is written, the voltage of the capacitor line SC drops, corresponding to this situation, the potential of thenode Tg 24 drops, and thecorrection TFT 22 turns off shortly thereafter. The gate voltage_Vg24 of the drivingTFT 24 is changed to a lower voltage corresponding to the lowered portion of the capacitance line SC (in this example, 12V from 8V to -4V) by a predetermined voltage lower than the data voltage Vdata, and flows corresponding to this. voltage drive current.

修正TFT 22设置于每个像素，且形成邻接此像素的驱动TFT 24状态，且经由与驱动TFT 24相同步骤而制成。特别如后所述，当包含选择TFT 20，例如作为驱动TFT 24与修正TFT 22的主动层，采用将非晶硅施行激光退火而多结晶化所获得的多晶硅时等，由对驱动TFT24与修正TFT 22的主动层区域，同时照射进行多结晶化用的相同激光脉冲，便可整合TFT特性。此外，植入主动层的杂质浓度也可几乎相同。所以，修正TFT 22与驱动TFT 24便形成连临限值电压也大致相同的状态。另外，因为修正TFT 22的栅极连接于电源线PL(在此Pvdd＝0V)，因此随着节点Tg 24的电压V_g24的降低，而从导通变化成关断状态。Thecorrection TFT 22 is provided at each pixel, and forms the state of the drivingTFT 24 adjacent to this pixel, and is fabricated through the same steps as the drivingTFT 24 . In particular, as will be described later, when polysilicon obtained by performing laser annealing and polycrystallization of amorphous silicon is used as the active layer of the drivingTFT 24 and thecorrection TFT 22 including theselection TFT 20, thedrive TFT 24 and thecorrection TFT 24 are selected. The active layer region of theTFT 22 is simultaneously irradiated with the same laser pulse for polycrystallization, so that TFT characteristics can be integrated. In addition, the impurity concentration of the implanted active layer can also be almost the same. Therefore, thecorrection TFT 22 and the drivingTFT 24 are in a state where even the threshold voltage is substantially the same. In addition, since the gate of thecorrection TFT 22 is connected to the power supply line PL (here, Pvdd=0V), it changes from the on state to the off state as the voltage V_g24 of thenode Tg 24 decreases.

依此，当电容线SC下降时，为p型沟道TFT的修正TFT 22从导通变化为关断状态，另外，驱动TFT 24则从关断变化为导通状态。TFT的栅极电容值Cg会随导通或关断的状态而进行变化。所以，驱动TFT24的栅极电压V_g24的变化受到2个TFT 22、24的导通或关断状态变化的影响。换句话说，TFT具体而言，在TFT导通状态时，Cg较大，在关断状态时则较小。因为电容在导通时将较大于关断时，因此电压变化状态便将受电容变化的影响。Accordingly, when the capacitance line SC falls, thecorrection TFT 22 which is a p-channel TFT is turned from on to off, and the drivingTFT 24 is turned from off to on. The gate capacitance Cg of the TFT changes with the state of being turned on or off. Therefore, the change of the gate voltage V_g24 of the drivingTFT 24 is affected by the change of the on or off state of the twoTFTs 22 and 24 . In other words, specifically, for a TFT, Cg is large when the TFT is in an on state, and is small when it is in an off state. Since the capacitance will be larger when turned on than when turned off, the voltage change state will be affected by the change in capacitance.

换句话说，若修正TFT 22从导通转为关断，其栅极电容值C_g22变小的话，电压V_g24降低的斜率α便将变大。In other words, if thecorrection TFT 22 is turned from on to off, the gate capacitance C_g22 becomes smaller, and the slope α of the voltage V_g24 decreases becomes larger.

所以，当某像素的修正TFT 22从导通状态切换为关断状态的切换电压为如图3的(切换电压A)的情况时，节点Tg 24的电压(栅极电压V_g24)便如图中实线所示的进行变化。即，在到达切换电压A之前，栅极电压V_g24将从暂时设定的数据电压V_data，依第1斜率α₁进行变化(降低)，在到达切换电压A之后，便依第2斜率α₂进行变化(降低)。然后，若驱动TFT 24转成导通的话，便依第3斜率α₃进行变化(降低)，当电容线SC的电压呈L电位并经过预定期间之后，电压V_g24便被设定为修正电压VcA。Therefore, when the switching voltage of thecorrection TFT 22 of a certain pixel is switched from the on state to the off state as shown in Figure 3 (switching voltage A), the voltage of the node Tg 24 (gate voltage V_g24 ) is as shown in Changes are made as indicated by the solid line. That is, before reaching the switching voltage A, the gate voltage V_g24 will change (decrease) from the temporarily set data voltage V_data according to the first slope α₁ , and after reaching the switching voltage A, it will change (decrease) according to the second slope α₂ Make a change (decrease). Then, when the drivingTFT 24 is turned on, it changes (decreases) according to the third slope_α3 , and when the voltage of the capacitance line SC becomes L potential and a predetermined period elapses, the voltage V_g24 is set as the correction voltage VcA.

在此，修正TFT 22从导通变化为关断的切换电压，如上所述，若为修正TFT 22栅极电压的电源电压Pvdd＝0的话，便由其源极电压的差V_gs22来决定。所以，切换电压A、B等于电源电压Pvdd加上修正TFT 22的临限值电压V_th22绝对值之后的电压(Pvdd+|V_th22|)。Here, the switching voltage at which thecorrection TFT 22 changes from on to off is determined by the difference V_gs22 of the source voltage if the power supply voltage Pvdd of the gate voltage of thecorrection TFT 22 is 0 as described above. Therefore, the switching voltages A and B are equal to the voltage (Pvdd+|V_th22 |) obtained by adding the power supply voltage Pvdd and correcting the absolute value of the threshold voltage V_th22 of theTFT 22 .

另外，当修正TFT 22的临限值电压V_th22为较低于[切换电压A]的[切换电压B]时，栅极电压V_g24便如图3中的虚线所示进行变化。即，栅极电压V_g24在从暂时设定的数据电压Vdata，到达切换电压B之前，将依第1斜率α₁进行变化(降低)，在到达之后起便依第2斜率α₂进行变化(降低)，若驱动TFT24导通的话，便依第3斜率α₃进行变化(降低)，当电容线SC的电压呈L电位并经预定期间之后，电压V_g24便被设定为修正电压VcB。In addition, when the threshold voltage V_th22 of thecorrection TFT 22 is [switching voltage B] lower than [switching voltage A], the gate voltage V_g24 changes as shown by the dotted line in FIG. 3 . That is, the gate voltage V_g24 changes (decreases) according to the first slope_α1 before reaching the switching voltage B from the temporarily set data voltage Vdata, and then changes according to the second slope_α2 ( decrease), if the driving TFT24 is turned on, it changes (decreases) according to the third slope_α3 , and when the voltage of the capacitor line SC becomes L potential for a predetermined period, the voltage_Vg24 is set as the correction voltage VcB.

借此方式，对于节点Tg 24，即便最初供应相同的数据电压Vdata，最后的驱动TFT 24的栅极电压V_g24便将形成临限值电压越低，便被设定于越高的修正电压Vc。In this way, for thenode Tg 24, even if the same data voltage Vdata is initially supplied, the gate voltage_Vg24 of thefinal drive TFT 24 will form a higher correction voltage Vc as the threshold voltage is lower. .

如上述，驱动TFT 24的临限值电压V_th24对应于修正TFT 22的临限值电压V_th22。所以，若驱动TFT 24的临限值电压V_th24为[V_th24A]的话，栅极电压V_g24便将成为对应于临限值电压V_th24A的修正电压VcA，若为[V_th24B]的话，栅极电压V_g24便将设定为对应于该临限值电压V_th24B的修正电压VcB。在此例子中，临限值电压V_th24与修正后的栅极电压V_g24之差，不管临限值电压为V_th24A的情况、或临限值电压为V_th24B的情况均为相同。换句话说，依照修正TFT 22的尺寸、电源电压值Pvdd、驱动TFT 24的尺寸、保持电容28的电容值Cs等的设定，若数据电压Vdata为相同的话，即便驱动TFT 24的临限值电压V_th24依每个像素而异，临限值电压V_th24与栅极电压V_g24的差将可呈一定状态，而可排除受驱动TFT 24的临限值电压V_th24偏差情况的影响。As described above, the threshold voltage V_th24 of the drivingTFT 24 corresponds to the threshold voltage V_th22 of thecorrection TFT 22 . Therefore, if the threshold voltage V_th24 of the drivingTFT 24 is [V_th24 A], the gate voltage V_g24 will become the corrected voltage VcA corresponding to the threshold voltage V_th24 A, if it is [V_th24 B] If so, the gate voltage V_g24 is set to be the corrected voltage VcB corresponding to the threshold voltage V_th24 B. In this example, the difference between the threshold voltage V_th24 and the corrected gate voltage V_g24 is the same regardless of whether the threshold voltage is V_th24 A or the threshold voltage is V_th24 B. In other words, according to the setting of the size of thecorrection TFT 22, the power supply voltage value Pvdd, the size of the drivingTFT 24, the capacitance value Cs of thestorage capacitor 28, etc., if the data voltage Vdata is the same, even the threshold value of the drivingTFT 24 The voltage V_th24 is different for each pixel, and the difference between the threshold voltage V_th24 and the gate voltage V_g24 can be in a certain state, and the influence of deviation of the threshold voltage V_th24 of the drivingTFT 24 can be eliminated.

在此为能执行如上述的补偿，优选的是，依第2斜率α₂为第1斜率α₁的2倍的方式进行条件设定。针对此条件设定，根据图3所示进行说明。如图3所示，当修正TFT 22为导通状态的情况时，因为其电容值C_g22较大于关断时，因此栅极电压V_g24的变化便将抑制因脉冲驱动电压变化所产生的影响，斜率α₁便将变小。此外，当修正TFT 22为关断状态的情况时，电容值C_g22较小，因为脉冲驱动电压变化所产生影响较大，因此斜率α₂较大。此外，因为将条件设定成斜率α₂为斜率α₁的2倍大小，因此脉冲驱动电压达L电位时的栅极电压V_g24的减少部分，便将形成修正TFT 22呈关断状态时为导通状态时的2倍。Here, in order to perform the compensation as described above, it is preferable to set the condition so that the second slope_α2 is twice the first slope_α1 . For this condition setting, it will be explained based on what is shown in Figure 3. As shown in FIG. 3 , when theTFT 22 is turned on, because its capacitance C_g22 is larger than when it is turned off, the change of the gate voltage V_g24 will suppress the influence caused by the change of the pulse driving voltage. , the slope α₁ will become smaller. In addition, when thecorrection TFT 22 is in the off state, the capacitance value C_g22 is small because the influence of the change of the pulse driving voltage is large, so the slope_α2 is large. In addition, since the condition is set such that the slope_α2 is twice as large as the slope_α1 , the reduced part of the gate voltage_Vg24 when the pulse driving voltage reaches the L potential will form 2 times that of the on state.

换句话说，依2个驱动TFT 24的临限值电压的差ΔV_th24等于2个修正TFT 22的临限值电压的差ΔV_th22的方式，构成TFT，由将修正TFT 22从导通变为关断时的斜率设为2倍，便成为ΔV_th22＝ΔV_th24，2个修正电压(VcA、VcB)的差ΔVc便满足ΔVc＝ΔV_th24。In other words, the TFT is constructed in such a way that the difference ΔV_th24 of the threshold voltages of the twodrive TFTs 24 is equal to the difference ΔV_th22 of the threshold voltages of the twocorrection TFTs 22, and thecorrection TFT 22 is turned from on to off. When the slope at turn-off is doubled, ΔV_th22 =ΔV_th24 , and the difference ΔVc between the two correction voltages (VcA, VcB) satisfies ΔVc=ΔV_th24 .

即，在图3中，下述(i)至(iv)将全部相等：That is, in Figure 3, the following (i) to (iv) will all be equal:

(i)2个修正TFT 22的切换电压A与B之差(ΔV_th22)、(i) The difference between the switching voltages A and B of the two correction TFTs 22 (ΔV_th22 ),

(ii)切换电压B(切换时序较迟缓者：在此为较低的电压)，与此像素之节点Tg 24B在到达切换电压B之时，具备切换电压A之修正TFT 22的像素之节点Tg 24B的电压V_g24A间的差(ΔV_th22′)；(ii) Switching voltage B (slower switching timing: a lower voltage here), when the node Tg 24B of this pixel reaches the switching voltage B, the node Tg of the pixel with thecorrection TFT 22 of switching voltage A The difference between the voltage V_g24 A of 24B (ΔV_th22 ′);

(iii)2个驱动TFT 24的切换电压的差(ΔV_th24)；(iii) the difference (ΔV_th24 ) of the switching voltages of the twodrive TFTs 24 ;

(iv)修正电压VcA、VcB的差(ΔVc)。(iv) The difference (ΔVc) between the voltages VcA and VcB is corrected.

另外，即使在作为数据电压Vdata而写入之电压的取样(sampling)电压产生变化的情况下，由于斜率仍无变化，因此切换电压差ΔV_th22与修正电压差ΔVc相等的状况将无变化，而可经常补偿临限值电压的变动。In addition, even when the sampling voltage of the voltage written as the data voltage Vdata changes, since the slope does not change, there is no change in the fact that the switching voltage difference ΔV_th22 is equal to the correction voltage difference ΔVc. Changes in the threshold voltage can often be compensated for.

再者，根据实验，数据电压的电位差在补偿动作后的修正电压中，将被放大为2倍。所以，可缩小数据电压的范围，而保持足够的驱动TFT 24的栅极电压差，具有可获得轻易制作缩小供应数据电压的电路的负荷的效果。Furthermore, according to experiments, the potential difference of the data voltage is doubled in the corrected voltage after the compensation operation. Therefore, the range of the data voltage can be reduced while maintaining a sufficient difference in the gate voltage for driving theTFT 24, and the effect of reducing the load of the circuit supplying the data voltage can be easily fabricated.

另外，如上述，在电容线SC的电压下降之际，驱动TFT 24的栅极电压变化特别会受修正TFT 22栅极电容值C_g22、驱动TFT 24的栅极电容值C_g24、保持电容28的电容值Cs、及配线的寄生电容Cw的影响。In addition, as mentioned above, when the voltage of the capacitance line SC drops, the gate voltage change of the drivingTFT 24 is affected particularly by the gate capacitance C_g22 of thecorrection TFT 22 , the gate capacitance C_g24 of the drivingTFT 24 , and thestorage capacitance 28 . The capacitance value Cs of the wire and the influence of the parasitic capacitance Cw of the wiring.

关于上述V_g24变化的机制，根据电荷移动量进行说明。在此将保持电容28的电容值设为Cs、将修正TFT 22的栅极电容设为C_g22、将驱动TFT 24的栅极电容设为C_g24、将修正TFT 22的临限值电压设为V_th22、将驱动TFT 24的临限值电压设为V_th24，且设定为保持电容28的电容值Cs＝修正TFT 22的栅极电容C_g22。The mechanism of the change in V_g24 described above will be described based on the amount of charge transfer. Here, let the capacitance value of the holdingcapacitor 28 be Cs, the gate capacitance of thecorrection TFT 22 be C_g22 , the gate capacitance of thedrive TFT 24 be C_g24 , and the threshold voltage of thecorrection TFT 22 be V_th22 , set the threshold voltage of the drivingTFT 24 as V_th24 , and set the capacitance Cs of thestorage capacitor 28 = the gate capacitance C_g22 of thecorrection TFT 22 .

(i)首先，若从驱动TFT 24栅极电压V_g24＝Vdata的状态，将电容线SC下降12V的话，节点Tg 24的电压V_g24也应下降12V。若将仅考虑此变化的V_g24表示为V_g24′的话，便成为：(i) First, if the capacitance line SC is lowered by 12V from the state where the gate voltage of the drivingTFT 24 is_Vg24 =Vdata, the voltage_Vg24 of the node Tg24 should also be lowered by 12V. If V_g24 considering only this change is expressed as V_g24 ′, it becomes:

V_g24′＝Vdata-12V_g24 ′=Vdata-12

(ii)若将修正TFT 22的栅极电容设为C_g22的话，从此修正TFT 22所流出，并流入保持电容28中的电荷量Q_f22便为：(ii) Assuming that the gate capacitance of thecorrection TFT 22 is C_g22 , the amount of charge Q_f22 that flows out of thecorrection TFT 22 and flows into thestorage capacitor 28 is:

Q_f22＝C_g22×(Vdata-|V_th22|)Q_f22 ＝C_g22 ×(Vdata-|V_th22 |)

在此，本实施例中，如上述C_g22＝Cs，节点Tg 24的电压V_g24仅上升(Vdata-|V_th22|)。所以，经考虑此上升部分的电压V_g24″便成为Here, in the present embodiment, the voltage V_g24 of thenode Tg 24 rises only by (Vdata-|V_th22 |) as described above for C_g22 =Cs. Therefore, the voltage V_g24 ″ of this rising part becomes

V_g24″＝2Vdata-12-|V_th22|V_g24 ″=2Vdata-12-|V_th22 |

(iii)然后，也从驱动TFT 24的栅极流入电荷至保持电容28。此电荷量Q_f24将驱动TFT 24的最终栅极电压设为V_g24，而成为(iii) Then, charges also flow from the gate of the drivingTFT 24 to the holdingcapacitor 28 . This amount of charge Q_f24 sets the final gate voltage of the drivingTFT 24 to V_g24 , and becomes

Q_f24＝-C_g24′×(V_g24+|V_th24|)Q_f24 ＝-C_g24 ′×(V_g24 +|V_th24 |)

其中，C_g24′驱动TFT 24为关断时与导通时的电容差，采用以SPICE(SPICE仿真器)的MEYER式所计算出的C_g24′＝C_g24×2/3的值。Wherein, C_g24 ′ drives theTFT 24 as the capacitance difference between the off state and the on state, and adopts the value of C_g24 ′=C_g24 ×2/3 calculated by the MEYER formula of SPICE (SPICE simulator).

(iv)驱动TFT 24的栅极电压V_g24仅要设定为偏移电荷Q_f24流入保持电容28中的份量的电压便可。所以，(iv) The gate voltage V_g24 of the drivingTFT 24 needs only to be set to a voltage that offsets the amount of charge Q_f24 flowing into thestorage capacitor 28 . so,

V_g24＝V_g24″+Q_f24/C_g22V_g24 ＝V_g24 ″+Q_f24 /C_g22

＝V_g24″-C_g24′(V_g24+|V_th24|)/C_g22=V_g24 ″-C_g24 ′(V_g24 + |V_th24 |)/C_g22

若将此式重新整理的话，最终V_g24便为下式：If this formula is rearranged, the final V_g24 is the following formula:

(1+C_g24′/C_g22)V_g24(1+C_g24 ′/C_g22 )V_g24

＝2Vdata-12-|V_th22|-(C_g24′/C_g22)|V_th24|=2Vdata-12-|V_th22 |-(C_g24 ′/C_g22 )|V_th24 |

若V_th22＝V_th24＝V_th的话，便为下式：If V_th22 ＝V_th24 ＝V_th , then it is the following formula:

V_g24＝-|V_th|+(2Vdata-12)/(1+C_g24′/C_g22)V_g24 ＝-|V_th |+(2Vdata-12)/(1+C_g24 ′/C_g22 )

此式的右边第二项乃因为依布局尺寸所产生的固定值，因此V_g24由仅偏离V_th的话，即便驱动TFT 24的临限值电压V_th有偏离，也可对其进行补偿。The second term on the right side of this formula is a fixed value due to the layout size. Therefore, if V_g24 only deviates from V_th , even if the threshold voltage V_th of the drivingTFT 24 deviates, it can be compensated.

另外，严格的说，针对配线的寄生电容也必须考虑，考虑此情况进行设定的话便可。此外，当电源电压Pvdd非为0V的情况时，若考虑此数值的话便可。In addition, strictly speaking, the parasitic capacitance of the wiring must also be considered, and it is only necessary to set it in consideration of this fact. In addition, when the power supply voltage Pvdd is not 0V, it is sufficient to consider this value.

再者，当修正TFT 22的临限值电压V_th22、与驱动TFT 24的临限值电压V_th24不同的情况时，优选的是，其栅极电压V_g24仅偏移驱动TFT 24的临限值电压V_th24。所以，若调整上式中的C_g24′/C_g22便可。但是，较难进行太大的调整，优选的是，尽可能依V_th22＝V_th24的方式形成TFT。Furthermore, when the threshold voltage V_th22 of thecorrection TFT 22 is different from the threshold voltage V th24 of the drivingTFT 24, it is preferable that the gate voltage V_g24 is only shifted from the threshold voltage V_th24 of the drivingTFT 24. value voltage V_th24 . Therefore, it is sufficient to adjust C_g24 ′/C_g22 in the above formula. However, it is difficult to adjust too much, and it is preferable to form the TFT in such a manner that V_th22 =V_th24 as much as possible.

接着，针对本发明实施例所涉及的像素电路中各种电容的关系，参照图4进行说明。本实施例的像素电路除保持电容Cs之外，也连接有上述修正TFT 22的栅极电容C_g22、驱动TFT 24栅极电容C_g24、及各种寄生电容。例如，如图4所示，修正TFT 22的漏极与驱动晶体管24的栅极的连接点(节点)Tg 24与电源线PL之间，存在有寄生电容C_w1，在修正TFT 22的源极与选择TFT 20的源极的连接部与电源线PL之间存在有寄生电容C_w2。这些寄生电容与图3的节点Tg 24的电压V_g24降低的斜率α的关，在图3中，从数据电压Vdata到达切换电压(A或B)时的斜率α₁便可以下式表示：Next, the relationship among various capacitances in the pixel circuit according to the embodiment of the present invention will be described with reference to FIG. 4 . In addition to the holding capacitor Cs, the pixel circuit of this embodiment is also connected to the gate capacitor C_g22 of thecorrection TFT 22 , the gate capacitor C_g24 of the drivingTFT 24 , and various parasitic capacitors. For example, as shown in FIG. 4 , there is a parasitic capacitance C_w1 between the connection point (node)Tg 24 between the drain of thecorrection TFT 22 and the gate of the drivingtransistor 24 and the power supply line PL, and at the source of the correction TFT 22 A parasitic capacitance C_w2 exists between the connection to the source of theselection TFT 20 and the power supply line PL. These parasitic capacitances are related to the slope α that the voltage V_g24 of thenode Tg 24 in FIG. 3 decreases. In FIG. 3 , the slope_α1 when the data voltage Vdata reaches the switching voltage (A or B) can be expressed by the following formula:

α₁＝Cs/(C_w1+C_w2+Cs+C_g22)α₁ =Cs/(C_w1 +C_w2 +Cs+C_g22 )

该等寄生电容(C_w1、C_w2、C_g22)全部从分别充电一定电荷的状态起，使电荷流入保持电容Cs，所以，栅极电压V_g24降低的斜率α₁便以此式表示。These parasitic capacitances (C_w1 , C_w2 , C_g22 ) all flow into the storage capacitor Cs from the state of being charged with a certain amount of charge, so the slope α₁ of the decrease of the gate voltage V_g24 is expressed by this formula.

接着，在图3中，到达切换电压之后，直到驱动TFT 24导通为止的期间内的节点Tg 24的电压V_g24降低的斜率α₂以下式表示：Next, in FIG. 3, after reaching the switching voltage, the slope_α2 at which the voltage V_g24 of thenode Tg 24 decreases during the period until thedrive TFT 24 is turned on is expressed by the following equation:

α₂＝Cs/(Cs+C_w1)α₂ =Cs/(Cs+C_w1 )

因为在到达切换电压之后，修正TFT 22将呈关断，其栅极电容C_g22、及其源极与电源线PL间的寄生电容C_w2，将电性地从保持电容28(电容值Cs)切离。Because thecorrection TFT 22 will be turned off after reaching the switching voltage, its gate capacitance C_g22 and the parasitic capacitance C_w2 between its source and the power line PL will be electrically removed from the holding capacitor 28 (capacitance value Cs). Cut off.

在此，如上所述，设定为α₂＝2×α₁。所以，由依满足Cs＝C_g22-C_w1+C_w2的方式设定保持电容28的电容Cs，当电容线SC的电压下降之际，藉由修正TFT 22从导通切换到关断，便可将驱动TFT 24的栅极电压V_g24下降的斜率α₂设定为α₁的2倍，且可执行驱动TFT 24的临限值电压变动的适当补偿。Here, as described above, it is set to α₂ =2×α₁ . Therefore, by setting the capacitance Cs of thestorage capacitor 28 in such a manner as to satisfy Cs=C_g22 −C_w1 +C_w2 , when the voltage of the capacitor line SC drops, the switching of theTFT 22 from on to off can be corrected. The slope_α2 at which the gate voltage_Vg24 of the drivingTFT 24 falls is set to be twice the value of_α1 , and appropriate compensation for fluctuations in the threshold voltage of the drivingTFT 24 can be performed.

再者，图3所示的驱动TFT 24导通后的斜率α₃，将以下式表示：Furthermore, the slope α₃ after the drivingTFT 24 is turned on shown in FIG. 3 is expressed by the following formula:

α₃＝Cs/(Cs+C_w1+C_g24)α₃ =Cs/(Cs+C_w1 +C_g24 )

C_g24如上所述为驱动TFT 24的栅极电容，由导通驱动TFT 24，此电容C_g24连接于保持电容28，电压下降的斜率α₃也将受此电容C_g24的影响。此驱动TFT 24导通的时序t_on244如上所述，并不因驱动TFT 24的切换电压，也即临限值电压V_th24而异，各像素均为同时。具体而言，利用对应各修正TFT 22其临限值电压V_th22偏差的时序，分别设为关断，在各像素电路中，栅极电压V_g24将以同时到达的时序从电源电压Pvdd仅降低各自V_th24所对应份的较低电压。As mentioned above, C_g24 is the gate capacitance of the drivingTFT 24, and the drivingTFT 24 is turned on. This capacitor C_g24 is connected to the holdingcapacitor 28, and the slope_α3 of the voltage drop will also be affected by this capacitor C_g24 . As mentioned above, the timing t_on24 4 of the drivingTFT 24 is not different due to the switching voltage of the drivingTFT 24, that is, the threshold voltage V_th24 , and all pixels are at the same time. Specifically, by using the timing corresponding to the deviation of the threshold voltage V_th22 of eachcorrection TFT 22, each of them is turned off, and in each pixel circuit, the gate voltage V_g24 will only decrease from the power supply voltage Pvdd at the same timing. The lower voltage corresponding to the respective V_th24 .

接着，针对具备这种像素电路的像素布局(layout)，参照图5与第6A图、第6B图进行说明。图5所示为1个像素的概略平面构造图，图6A与图6B分别显示沿图5的A-A线、B-B线的概略剖面构造。Next, a pixel layout (layout) including such a pixel circuit will be described with reference to FIG. 5 , FIG. 6A , and FIG. 6B . FIG. 5 is a schematic plan view of a pixel, and FIG. 6A and FIG. 6B respectively show a schematic cross-sectional structure along the lines A-A and B-B of FIG. 5 .

在玻璃等透明绝缘基板100上形成缓冲层102，形成在其上方且由多晶硅所构成的各TFT主动层以及构成电容电极的半导体层(120、124、28e)，在图5中由虚线所示。此外，在图5中，形成于较上述半导体层更上方，采用Cr等高融点金属材料的栅极线GL、电容线SC、及修正TFT 22的栅极22g、及驱动TFT 24的栅极24g由虚实相见的线表示。另外，形成于较半导体层、上述GL、SC更上方，采用Al等低电阻金属材料的数据线DL、电源线PL、与这些为同层的金属配线24w以实线表示。Abuffer layer 102 is formed on a transparent insulatingsubstrate 100 such as glass, and each TFT active layer formed of polysilicon and the semiconductor layer (120, 124, 28e) forming a capacitor electrode are formed above it, as shown by dotted lines in FIG. . In addition, in FIG. 5, the gate line GL, the capacitance line SC, thegate 22g of thecorrection TFT 22, and thegate 24g of thedrive TFT 24 are formed above the above-mentioned semiconductor layer and are made of high-melting-point metal materials such as Cr. Represented by lines where virtual and real meet. In addition, the data line DL, the power line PL, and themetal wiring 24w on the same layer as these formed above the semiconductor layer and the above-mentioned GL and SC using a low-resistance metal material such as Al are indicated by solid lines.

在图5所示的布局中，各像素的构成位于沿显示装置的水平扫描(H)方向所形成的栅极线GL的行间的位置处，以及大概沿显示装置的垂直扫描(V)方向所形成的数据线DL的行间的位置处。此外，电源线PL形成于与数据线DL大致并排并朝垂直扫描方向(矩阵的列方向)，在各像素区域内，通过数据线DL、与连接于此数据线DL的像素的有机EL组件26之间。然后，如后述，选择TFT 20、修正TFT 22及保持电容28配置于数据线DL与电源线PL之间，驱动TFT与有机EL组件26配置于电源线PL与相邻列的数据线DL之间。In the layout shown in FIG. 5, the configuration of each pixel is located at a position between rows of gate lines GL formed along the horizontal scanning (H) direction of the display device, and approximately along the vertical scanning (V) direction of the display device. The position between the rows of the formed data line DL. In addition, the power line PL is formed approximately in parallel with the data line DL and faces the vertical scanning direction (column direction of the matrix), and in each pixel area, passes through the data line DL and theorganic EL element 26 of the pixel connected to the data line DL. between. Then, as described later, theselection TFT 20, thecorrection TFT 22, and thestorage capacitor 28 are disposed between the data line DL and the power line PL, and the driving TFT and theorganic EL element 26 are disposed between the power line PL and the data line DL of the adjacent column. between.

选择TFT 20形成于栅极线GL与数据线DL的交叉点附近。从栅极线GL朝像素区域形成突出部，在层间夹介着栅极绝缘膜104，并以横跨沿栅极线GL延伸的半导体层120的一部分的方式予以覆盖。从此栅极线GL突出的突出部便成为TFT 20的栅极电极20g，半导体层120的被此栅极电极20g覆盖的区域将成为沟道区域。Theselection TFT 20 is formed near the intersection of the gate line GL and the data line DL. A protrusion is formed from the gate line GL toward the pixel region, and covers a part of thesemiconductor layer 120 extending along the gate line GL with thegate insulating film 104 interposed therebetween. The protrusion protruding from the gate line GL becomes thegate electrode 20g of theTFT 20, and the region of thesemiconductor layer 120 covered by thegate electrode 20g becomes the channel region.

连接于选择TFT 20的修正TFT 22在由数据线DL与电源线PL所包夹的区域中，配置成在其沟道长度方向沿数据线DL的延伸方向(垂直扫描方向)的状态。此外，该修正TFT 22的主动层以部分重叠于数据线DL的方式，形成于数据线DL的下层。在该修正TFT 22、与靠近下一行栅极线GL所配置的电容线SC之间，更具体而言，沿该电容线SC配置保持电容28。此外，驱动TFT 24夹介着电源线PL而配置于与修正TFT 22形成区域为相反侧区域(有机EL组件区域26侧)，构成其主动层的半导体层124的至少沟道区域24c配置成尽可能接近修正TFT22的沟道区域22c状态而加以布局。Thecorrection TFT 22 connected to theselection TFT 20 is arranged such that its channel length direction is along the extending direction of the data line DL (vertical scanning direction) in the region surrounded by the data line DL and the power line PL. In addition, the active layer of thecorrection TFT 22 is formed in the lower layer of the data line DL so as to partially overlap the data line DL. Between thecorrection TFT 22 and the capacitance line SC disposed close to the gate line GL of the next row, more specifically, a holdingcapacitor 28 is disposed along the capacitance line SC. In addition, thedrive TFT 24 is arranged in a region opposite to the region where thecorrection TFT 22 is formed (on the side of the organic EL element region 26) with the power supply line PL interposed therebetween, and at least thechannel region 24c of thesemiconductor layer 124 constituting the active layer thereof is arranged as far as possible. It is possible to arrange the layout close to the state of thechannel region 22c of thecorrection TFT 22 .

在此，于本实施形态中，选择TFT 20的主动层、修正TFT 22的主动层、及保持电容28的电容电极28e利用单一半导体层120而一体化形成(当然，也可各为独立层，且分别依预定配线进行电性连接)。Here, in this embodiment, the active layer of theselection TFT 20, the active layer of thecorrection TFT 22, and thecapacitor electrode 28e of thestorage capacitor 28 are integrally formed by using a single semiconductor layer 120 (of course, each may be an independent layer, and are electrically connected according to predetermined wiring).

在选择TFT 20的形成区域中，数据线DL与半导体层120在贯穿栅极绝缘膜104与层间绝缘膜106而形成的接触孔(contact hole)中连接。然后，该半导体层120从数据线DL的下层区域(与数据线DL的接触区域)，沿栅极线GL延伸至与电源线PL重叠的位置处，并从重叠位置将电源线PL的下层沿电源线PL的延伸方向，朝垂直扫描方向延伸。此外，此半导体层120在修正TFT 22的栅极22g与电源线PL的接触附近前方，从电源线PL的下层位置起，朝平行于栅极线GL延伸方向的方向弯曲，并朝数据线DL延伸。In the formation region of theselection TFT 20, the data line DL is connected to thesemiconductor layer 120 in a contact hole formed through thegate insulating film 104 and theinterlayer insulating film 106. Then, thesemiconductor layer 120 extends from the region of the lower layer of the data line DL (contact region with the data line DL) along the gate line GL to a position overlapping with the power line PL, and from the overlapping position the lower layer of the power line PL is extended along the gate line GL. The extending direction of the power line PL extends in the vertical scanning direction. In addition, thissemiconductor layer 120 is bent in a direction parallel to the extending direction of the gate line GL from the position of the lower layer of the power line PL in front of the contact vicinity of thegate 22g of thecorrection TFT 22 and the power line PL, and is bent toward the data line DL. extend.

另外，在选择TFT 20的形成区域中，半导体层120，连接于数据线DL的杂质植入区域构成第1导电区域(例如：漏极区域20d)，重叠于栅极20g的无杂质植入的本征区域(intrinsic range)将构成沟道区域20c，在夹介着此沟道区域20c的相反侧，构成经植入与第1导电区域相同导电型之杂质的第2导电区域(例如源极区域20s)。In addition, in the formation region of theselection TFT 20, thesemiconductor layer 120, the impurity-implanted region connected to the data line DL constitutes the first conductive region (for example: thedrain region 20d), and the impurity-implanted region overlapping thegate 20g The intrinsic region (intrinsic range) will constitute thechannel region 20c, and on the opposite side sandwiching thechannel region 20c, the second conductive region (such as the source electrode) implanted with impurities of the same conductivity type as the first conductive region will be formed.area 20s).

从电源线PL的下层朝数据线DL延伸的半导体层120，在与数据线DL再度交叉的附近(选择TFT 20的第1导电区域20d附近)，将朝数据线DL延伸方向弯曲，且至少一部分重叠于电源线PL形成区域(在此例中，与数据线DL均部分重叠)，并将数据线DL与电源线PL间的区域，朝垂直扫描方向延伸至电容线SC形成区域为止。Thesemiconductor layer 120 extending from the lower layer of the power line PL toward the data line DL will bend toward the extending direction of the data line DL in the vicinity of the crossing with the data line DL again (near the firstconductive region 20d of the selection TFT 20), and at least a part It overlaps with the area where the power line PL is formed (in this example, partially overlaps with the data line DL), and extends the area between the data line DL and the power line PL to the area where the capacitor line SC is formed in the vertical scanning direction.

再者，半导体层120沿数据线DL配置的区域构成修正TFT 22的主动层，在夹介着该主动层的栅极绝缘膜104的上方配置有修正TFT22的栅极电极22g，该栅极电极22g透过形成于层间绝缘膜106的接触孔而连接于电源线PL。该栅极电极22g从与电源线PL的接触位置朝数据线DL延伸，并在与半导体层120(修正TFT22的主动层)重叠的位置处弯曲，朝数据线DL的延伸方向延伸，并覆盖半导体层120的上层，且依部分重叠数据线DL与电源线PL的方式，形成于该等的下层。Furthermore, the region of thesemiconductor layer 120 arranged along the data line DL constitutes the active layer of thecorrection TFT 22, and thegate electrode 22g of thecorrection TFT 22 is disposed above thegate insulating film 104 sandwiching the active layer. 22g is connected to the power supply line PL through a contact hole formed in theinterlayer insulating film 106 . Thegate electrode 22g extends from the position in contact with the power line PL toward the data line DL, bends at a position overlapping with the semiconductor layer 120 (the active layer of the correction TFT 22), extends toward the extending direction of the data line DL, and covers thesemiconductor layer 120. The upper layer of thelayer 120 is formed on the lower layer in such a manner as to partially overlap the data line DL and the power line PL.

半导体层120的被栅极电极22g覆盖的区域形成修正TFT 22的未施行杂质掺杂的沟道区域22c，夹介着沟道区域22c而在选择TFT20侧形成经植入与该选择TFT 20不同导电型的杂质的第1导电区域(在此，例如源极区域22s)，在电容线SC侧形成经植入与第1导电区域22s为相同杂质的第2导电区域(在此为漏极区域22d)。另外，数据线DL、电源线PL、及此修正TFT 22的至少沟道区域22c，将与这些线部分重叠，并形成于该等的下层，借此可有效率的将修正TFT 22配置于数据线DL与电源线PL之间非常狭窄的区域内。此外，通过将栅极电极22g配置于该沟道区域22c及数据线DL与电源线PL的层间，沟道区域22c便将电性屏蔽于数据线DL，可防止修正TFT 22的动作受到施加于数据线DL的数据信号的影响。此外，因为至少修正TFT 22的栅极电极22g连接于电源线PL，因此即便该修正TFT 22的主动层，特别沟道区域22c配置成重叠于电源线PL的状态，对沟道区域22c所施加的电压与覆盖栅极电极22g的情况无实质变化。所以，便可将修正TFT 22的主动层的大半区域形成于电源线PL的下层，依照这种配置的话，在1个像素内的开口率，即有助于发光的有机EL组件26的形成面积便可形成最大极限。The region of thesemiconductor layer 120 covered by thegate electrode 22g forms thechannel region 22c of thecorrection TFT 22 that is not doped with impurities, and forms an implanted TFT different from theselection TFT 20 with thechannel region 22c interposed therebetween. The first conductive region (here, for example, thesource region 22s) of the impurity of the conductivity type is formed on the capacitor line SC side by implanting the second conductive region (here, the drain region) with the same impurities as the firstconductive region 22s. 22d). In addition, the data line DL, the power line PL, and at least thechannel region 22c of thecorrection TFT 22 will partially overlap with these lines and be formed in the lower layer of these lines, thereby efficiently disposing thecorrection TFT 22 on the data line. In a very narrow area between the line DL and the power line PL. In addition, by disposing thegate electrode 22g between thechannel region 22c and the layer between the data line DL and the power line PL, thechannel region 22c will be electrically shielded from the data line DL, which can prevent the action of thecorrection TFT 22 from being affected. influence on the data signal of the data line DL. In addition, since at least thegate electrode 22g of thecorrection TFT 22 is connected to the power supply line PL, even if the active layer of thecorrection TFT 22, especially thechannel region 22c is arranged to overlap the power supply line PL, thechannel region 22c is The voltage of is not substantially changed from the case of covering thegate electrode 22g. Therefore, most of the active layer of thecorrection TFT 22 can be formed in the lower layer of the power line PL. According to this arrangement, the aperture ratio in one pixel, that is, the formation area of theorganic EL element 26 that contributes to light emission A maximum limit can be formed.

半导体层120从修正TFT 22的第2导电区域形成区域朝电容线SC延伸，在与电容线SC交叉的位置处弯曲，在朝电容线SC的延伸方向即水平扫描方向，依此电容线SC与其间夹介着栅极绝缘膜104并重叠的方式施行图案化处理(patterning)，半导体层120的重叠于电容线SC的区域便具有电容电极(第1电极)28e的功能，电容线SC(第2电极)与该电容电极28e，在其间夹介栅极绝缘膜104而相对向配置的区域便形成保持电容28。Thesemiconductor layer 120 extends from the second conductive region forming region of the correctingTFT 22 toward the capacitor line SC, and bends at a position where it intersects with the capacitor line SC. Patterning is performed in such a way that thegate insulating film 104 is interposed therebetween and overlapped, the region of thesemiconductor layer 120 overlapping the capacitor line SC functions as a capacitor electrode (first electrode) 28e, and the capacitor line SC (first electrode) 2 electrode) and thecapacitor electrode 28e are arranged opposite to each other with thegate insulating film 104 interposed therebetween to form thestorage capacitor 28.

在修正TFT 22的第2导电区域22d与保持电容28的电容电极28e间，透过形成于层间绝缘膜106与栅极绝缘膜104的接触孔，连接金属配线24w。该金属配线24w沿电容线SC的延伸方向形成，在形成于层间绝缘膜106的接触孔中，与驱动TFT 24的栅极电极24g相连接。Between the secondconductive region 22d of thecorrection TFT 22 and thecapacitor electrode 28e of thestorage capacitor 28, themetal wiring 24w is connected through a contact hole formed in theinterlayer insulating film 106 and thegate insulating film 104. Themetal wiring 24w is formed along the extending direction of the capacitance line SC, and is connected to thegate electrode 24g of the drivingTFT 24 in a contact hole formed in theinterlayer insulating film 106.

驱动TFT 24的栅极电极24g从其和金属配线24w的连接区域沿自行的栅极线GL的形成方向(图中为朝上方向)延伸，并在中途横跨电源线PL的下层，于电源线PL的有机EL组件26侧沿该电源线PL的延伸方向形成。Thegate electrode 24g of the drivingTFT 24 extends from the connection area between it and themetal wiring 24w along the direction in which the gate line GL is formed (upward direction in the figure), and crosses the lower layer of the power line PL on the way. Theorganic EL element 26 side of the power line PL is formed along the extending direction of the power line PL.

在此，电源线PL将从与修正TFT 22的栅极电极22g的接触区域附近起，弯曲接近数据线DL，在上述金属配线24w附近，朝有机EL组件26侧弯曲迂回该形成区域，并从与构成驱动TFT 24的主动层的半导体层124相接触附近起，朝下一行像素延伸于垂直扫描方向。然后，驱动TFT 24通过电源线PL靠近数据线DL侧，而形成有机EL组件26间的隔间(space)。Here, the power line PL bends from the vicinity of the contact area with thegate electrode 22g of thecorrection TFT 22 to approach the data line DL, and bends around the formation area near themetal wiring 24w toward theorganic EL element 26 side, and From the vicinity of contact with thesemiconductor layer 124 constituting the active layer of the drivingTFT 24, it extends in the vertical scanning direction toward the next row of pixels. Then, thedrive TFT 24 is driven to the side of the data line DL through the power line PL to form a space between theorganic EL elements 26.

构成驱动TFT 24的主动层的半导体层124，在上方被栅极电极24g所覆盖的区域形成有沟道区域24c，与电源线PL的连接侧形成有第1导电区域(在此为源极区域24s)，更在与有机EL组件26的连接侧形成第2导电区域(在此为漏极区域24d)。沟道区域24c未掺杂杂质的本征区域，形成于其两侧的第1与第2导电区域(24s与24d)，则掺杂与上述修正TFT 22为相同导电型的杂质。另外，驱动TFT 24的第1导电区域24s在形成于层间绝缘膜106与栅极绝缘膜104的接触孔中，与电源线PL相连接。此外，驱动TFT 24的第2导电区域24d在形成于层间绝缘膜106与栅极绝缘膜104的接触孔中，与例如由与上述电源线PL等为相同材料所构成的连接电极24e相连接。In thesemiconductor layer 124 constituting the active layer of the drivingTFT 24, achannel region 24c is formed in a region covered by thegate electrode 24g above, and a first conductive region (here, a source region) is formed on the side connected to the power supply line PL. 24s), further forming a second conductive region (here, thedrain region 24d) on the side connected to theorganic EL element 26. Thechannel region 24c is an intrinsic region not doped with impurities, and the first and second conductive regions (24s and 24d) formed on both sides thereof are doped with impurities of the same conductivity type as the above-mentioned modifiedTFT 22. In addition, the firstconductive region 24s of the drivingTFT 24 is connected to the power supply line PL in a contact hole formed in theinterlayer insulating film 106 and thegate insulating film 104. In addition, the secondconductive region 24d of the drivingTFT 24 is connected to aconnection electrode 24e made of, for example, the same material as the above-mentioned power line PL, etc., in a contact hole formed in theinterlayer insulating film 106 and thegate insulating film 104. .

再者，如图6A及图6B所示，在覆盖数据线DL、电源线PL、上述金属配线24w、连接电极24e的基板整面上，形成有用以使上面平而化的由有机树脂等构成的平面化绝缘层108。然后，在该平面化绝缘层108中，于连接于上述驱动TFT 24的连接电极24e形成区域中形成接触孔，并透过该接触孔，将形成于该平面化绝缘层108上的有机EL组件26的第1电极262(在此为阳极)与连接电极24e相连接。另外，当未设置连接电极24e的情况时，在驱动TFT 24的第2导电区域24d形成区域中，形成贯穿平面化绝缘层108、层间绝缘膜106、与栅极绝缘膜104的接触孔，直接将有机EL组件26的第1电极262与第2导电区域24d连接。Furthermore, as shown in FIG. 6A and FIG. 6B, on the entire surface of the substrate covering the data line DL, the power line PL, the above-mentionedmetal wiring 24w, and theconnection electrode 24e, a layer made of organic resin or the like is formed to flatten the upper surface. The planarizedinsulating layer 108 formed. Then, in theplanarization insulating layer 108, a contact hole is formed in the formation region of the connectingelectrode 24e connected to the drivingTFT 24, and through the contact hole, the organic EL element formed on theplanarization insulating layer 108 The first electrode 262 (here, an anode) of 26 is connected to theconnection electrode 24e. In addition, when theconnection electrode 24e is not provided, in the formation region of the secondconductive region 24d of the drivingTFT 24, a contact hole penetrating theplanarization insulating layer 108, theinterlayer insulating film 106, and thegate insulating film 104 is formed, Thefirst electrode 262 of theorganic EL element 26 is directly connected to the secondconductive region 24d.

如图6B所示，有机EL组件26形成于基板侧，且对于连接于驱动TFT 24的每个像素，在各自图案的第1电极262与第2电极264之间，设有发光组件层270。第1电极262可采用如ITO(Indium Tin Oxide)等透明导电性金属氧化物等所形成，在此具有阳极(空穴植入电极)的功能。第2电极264由如Al、Ag等功函数(仕事関数)较小的金属材料，或这种金属材料与上述ITO等的积层构造所构成，在此具有阴极(电子植入电极)的功能。另外，将每个像素形成各自图案的第1电极262的边缘部分，利用形成在平面化绝缘层108更上层的第2平面化绝缘层110而覆盖，以防止在形成非常薄的发光组件层270上所形成的第2电极264与此第1电极262间发生短路现象。As shown in FIG. 6B, theorganic EL element 26 is formed on the substrate side, and for each pixel connected to the drivingTFT 24, a light emittingelement layer 270 is provided between thefirst electrode 262 and thesecond electrode 264 of the respective pattern. Thefirst electrode 262 can be formed by using transparent conductive metal oxides such as ITO (Indium Tin Oxide), etc., and has the function of an anode (hole implantation electrode) here. Thesecond electrode 264 is made of a metal material with a small work function (work function) such as Al or Ag, or a laminated structure of such a metal material and the above-mentioned ITO, etc., and functions as a cathode (electron implantation electrode) here. . In addition, the edge portion of thefirst electrode 262 where each pixel is formed with its own pattern is covered by the secondplanarization insulating layer 110 formed on the upper layer of theplanarization insulating layer 108 to prevent the formation of a very thin light emitting element layer 270 A short circuit occurs between thesecond electrode 264 formed above and thefirst electrode 262.

发光组件层270在这个例子中为空穴输送层272、发光层274、电子输送层276等3层构造。不仅限于3层构造，随所使用的有机材料等，可为具备发光功能的单层，可为双层，可为4层以上的积层构造。当发光组件层270采多层构造的情况时，可全层形成各像素共通的情况，也可以多层中的一部分或全层，例如图6B所示，仅发光层274形成如同第1电极262，依每个像素设定个别图案。In this example, the light-emittingelement layer 270 has a three-layer structure including ahole transport layer 272 , a light-emittinglayer 274 , and anelectron transport layer 276 . Not limited to the three-layer structure, depending on the organic material used, etc., it can be a single layer with a light-emitting function, a double layer, or a laminated structure of four or more layers. When the light-emittingcomponent layer 270 adopts a multi-layer structure, all layers can be formed in common with each pixel, and a part or all of the layers can also be used. For example, as shown in FIG. 6B, only the light-emittinglayer 274 is formed like thefirst electrode 262. , to set individual patterns for each pixel.

这种构造的有机EL组件26，在本实施例中从电源线PL经由驱动TFT 24供应给第1电极262的电流在与第2电极264之间流通，并以对应电流量的辉度，在发光组件层中引起发光。另外，发光是通过从第1电极262所植入的空穴、与从第2电极264所植入的电子，在发光组件层中再结合，借此被激发的发光分子在返回基层状态之际便进行发光而得的，在本例中，辨识到光穿透过透明的第1电极262与基板100，并从基板射出于外部。In theorganic EL element 26 of such a structure, in this embodiment, the current supplied from the power supply line PL to thefirst electrode 262 via the drivingTFT 24 flows between thesecond electrode 264, and the luminance corresponding to the amount of current flows in the Luminescence is induced in the light-emitting component layer. In addition, light is emitted through the recombination of holes implanted from thefirst electrode 262 and electrons implanted from thesecond electrode 264 in the light-emitting element layer, whereby the excited light-emitting molecules return to the base layer state It is obtained by emitting light. In this example, it is recognized that the light passes through the transparentfirst electrode 262 and thesubstrate 100 , and is emitted from the substrate to the outside.

在本实施例中，如上述，夹介着电源线PL且上述修正TFT 22与驱动TFT 24配置成尽可能靠近的布局。特别修正TFT 22的沟道区域22c与驱动TFT 24的沟道区域24c，其沟道区域的至少一部分在垂直扫描方向上形成相互并排的状态。In this embodiment, as described above, thecorrection TFT 22 and the drivingTFT 24 are arranged as close as possible to each other with the power supply line PL interposed therebetween. In particular, thechannel region 22c of thecorrection TFT 22 and thechannel region 24c of the drivingTFT 24 are arranged in a state where at least a part of the channel regions are aligned with each other in the vertical scanning direction.

在本实施例中，形成于像素内的各TFT的主动层，对于利用电浆CVD等所形成的非晶硅层，将整形为线状(line)的脉冲激光(参照图5)设定成其长度方向在水平扫描方向为一致的状态，在其宽度方向相隔预定间距偏移并依序施行照射，而使用经多结晶化退火所获得的低温多晶硅(LTPS)层。激光束的扫描方向此激光束的宽度方向，且使其与数据线DL等的延伸方向即垂直扫描方向相一致。如图5所示，修正TFT 22与驱动TFT 24的各沟道区域22c、24c配置成其沟道长度方向一致于数据线DL等的延伸方向，即一致于激光束的扫描方向的状态。所以，通过将激光束的扫描间距设为小于修正TFT 22与驱动TFT 24的沟道长度，便可对任一沟道区域22c、24c，在其沟道长度方向中，依横跨沟道的方式(沟道宽度方向)，必定照射若干次激光束。借此，即便在各激光束的能量产生偏差的情况下，因为对任一沟道区域22c、24c照射若干次激光束，因此便可在任何像素中，将所有沟道长度方向中所接收到的能量总量的偏差缩小。In this embodiment, the active layer of each TFT formed in the pixel is set to a pulsed laser beam shaped into a line (see FIG. 5 ) for an amorphous silicon layer formed by plasma CVD or the like. Its length direction is in the same state in the horizontal scanning direction, and its width direction is shifted at predetermined intervals and sequentially irradiated, and a low-temperature polysilicon (LTPS) layer obtained by polycrystallization annealing is used. The scanning direction of the laser beam is the width direction of the laser beam, and is made to coincide with the extending direction of the data lines DL, ie, the vertical scanning direction. As shown in FIG. 5 , thechannel regions 22c and 24c of thecorrection TFT 22 and thedrive TFT 24 are arranged such that the channel length direction thereof coincides with the extending direction of the data line DL etc., that is, coincides with the scanning direction of the laser beam. Therefore, by setting the scanning pitch of the laser beam to be smaller than the channel lengths of thecorrection TFT 22 and the drivingTFT 24, anychannel region 22c, 24c can be positioned in the channel length direction according to the distance across the channel. method (channel width direction), the laser beam must be irradiated several times. In this way, even if the energy of each laser beam varies, since the laser beam is irradiated several times to any one of thechannel regions 22c and 24c, it is possible to capture all the received signals in the channel length direction in any pixel. The deviation of the total amount of energy is reduced.

再者，当将利用所谓激光退火而形成的多晶硅层使用在TFT的主动层的情况时，便依将同一脉冲激光束同时照射在构成修正TFT 22与驱动TFT 24的沟道区域22c、24c的区域的方式，将沟道区域22c、24c相靠近配置，借此可轻易地在两个TFT上，同等的形成对TFT特性(特别临限值)具有颇大影响的多结晶化状态。Furthermore, when the polysilicon layer formed by so-called laser annealing is used as the active layer of the TFT, the same pulsed laser beam is simultaneously irradiated on thechannel regions 22c and 24c constituting thecorrection TFT 22 and thedrive TFT 24. By arranging thechannel regions 22c and 24c close to each other by means of regions, it is easy to equally form a polycrystalline state that greatly affects TFT characteristics (especially threshold values) on both TFTs.

其中，经整形为线状的脉冲激光的1个照射区域，例如脉冲长度方向为10cm至30cm的长度，其脉冲宽度为300μm左右。然后，这种大小的脉冲激光的扫描间距例如以25μm左右，即，一边以每隔25μm偏移脉冲激光的照射位置，一边将非晶硅进行多结晶化。此外，将修正TFT 22的沟道区域22c、与驱动TFT 24的沟道区域24c，不仅相靠近的配置，且通过在朝交叉于垂直扫描方向的方向可拉出的同一直线，至少一部分配置成并排的状态，借此可将同一脉冲激光照射于各沟道区域22c、24c。此外，将修正TFT 22与驱动TFT 24的双方，都设定为其沟道长度至少在30μm以上，优选的是40μm以上，借此可将如上述大小的脉冲激光依如上所述的间距，沿像素的垂直扫描方向对沟道形成区域进行扫描，借此便可确实的将至少1个以上的同一脉冲激光照射于2个TFT的沟道区域22c、24c。Among them, one irradiated region of the pulsed laser light shaped into a line has a length of, for example, 10 cm to 30 cm in the pulse length direction, and its pulse width is about 300 μm. Then, the scanning pitch of the pulsed laser light of such a size is, for example, about 25 μm, that is, the amorphous silicon is polycrystallized while shifting the irradiation position of the pulsed laser light every 25 μm. In addition, thechannel region 22c of thecorrection TFT 22 and thechannel region 24c of the drivingTFT 24 are not only arranged adjacently, but also at least partially arranged on the same straight line that can be drawn in a direction crossing the vertical scanning direction. In a side-by-side state, the same pulsed laser light can be irradiated to eachchannel region 22c, 24c. In addition, both thecorrection TFT 22 and the drivingTFT 24 are set to have a channel length of at least 30 μm or more, preferably 40 μm or more, so that the pulsed laser light of the above-mentioned size can be transmitted along the above-mentioned pitch. By scanning the channel formation region in the vertical scanning direction of the pixel, it is possible to reliably irradiate at least one or more identical pulsed laser light to thechannel regions 22c and 24c of the two TFTs.

再者，同一导电型的杂质以各栅极22g、24g为屏蔽(mask)，而同时植入于半导体层120与124，因为形成位置非常接近，因此便可整合杂质植入条件(植入浓度、植入能量等)，由此观点来看也可修正TFT 22与驱动TFT 24的特性使其相等。Furthermore, the impurities of the same conductivity type are implanted into the semiconductor layers 120 and 124 at the same time using thegates 22g and 24g as masks. Since the formation positions are very close, the impurity implantation conditions (implantation concentration) can be integrated. , implantation energy, etc.), from this point of view, the characteristics of theTFT 22 and the drivingTFT 24 can also be corrected to be equal.

通过将像素区域内形成如上述所说明的布局，在像素区域的水平扫描方向的单侧区域(图5的像素左侧)配置数据线DL、电源线、及TFT20、22、24等电路组件，在剩下的单侧(图5的像素右侧)配置有机EL组件26，整体便可形成有效率的配置。具体而言，通过这种布局，便可在各像素区域内将有机EL组件26尽量形成较大，且有助于提升作为显示装置的开口率。此外，当考虑发光效率及需求亮度时，依每个发光颜色切换像素面积，而整合各像素的寿命的情况时，也可不须变更TFT 20、22、24、保持电容28等的面积或布局，即可仅轻易变更有机EL组件26的面积，而可达到提升设计效率的效果。By forming the layout as described above in the pixel area, the data line DL, power line, and TFT20, 22, 24 and other circuit components are arranged in the single-side area (the left side of the pixel in FIG. 5 ) in the horizontal scanning direction of the pixel area, Theorganic EL element 26 is arranged on the remaining side (the right side of the pixel in FIG. 5 ), so that an efficient arrangement can be formed as a whole. Specifically, through this layout, theorganic EL element 26 can be formed as large as possible in each pixel area, and it helps to increase the aperture ratio of the display device. In addition, when considering the luminous efficiency and required brightness, switching the pixel area according to each luminous color, and integrating the life of each pixel, it is not necessary to change the area or layout of theTFT 20, 22, 24, holdingcapacitor 28, etc. Only the area of theorganic EL element 26 can be changed easily, and the design efficiency can be improved.

再者，如图5所示的布局，矩阵配置的像素采取每行的同色像素位置仅朝水平扫描方向偏移预定间距的所谓三角形(デルタ)排列，当一条数据线DL为将数据信号Vdata供应给同色像素的情况时，如图5所示，数据线DL朝矩阵的列方向蛇行延伸，并连接于在线的左右交错配置的同色像素的选择TFT 20。通过采用这种布局，在图5所示的像素的下一行像素中，上述有机EL组件26与图5相反的配置于像素左侧，TFT 20、22、24等则配置于像素右侧。当然，在上述说明的布局中，不仅限于三角形排列，也可为直线排列，在这种情况下，每行的有机EL组件、与用以控制该有机EL组件的TFT等的位置关并没有左右反转。Furthermore, in the layout shown in FIG. 5 , the pixels of the matrix configuration adopt a so-called delta arrangement in which the positions of pixels of the same color in each row are only offset by a predetermined distance in the horizontal scanning direction. When a data line DL is used to supply the data signal Vdata In the case of pixels of the same color, as shown in FIG. 5 , the data line DL snakes along the column direction of the matrix, and is connected to theselection TFT 20 of the pixels of the same color arranged staggered left and right on the line. By adopting this layout, in the next row of pixels of the pixel shown in FIG. 5, the above-mentionedorganic EL element 26 is arranged on the left side of the pixel opposite to that in FIG. 5, and theTFTs 20, 22, 24, etc. are arranged on the right side of the pixel. Of course, in the layout described above, it is not limited to the triangular arrangement, but also can be arranged in a straight line. In this case, the organic EL components in each row are not related to the positions of the TFTs used to control the organic EL components. reverse.

在此，本实施例所涉及的修正TFT 22如图5所示，由半导体层所构成的沟道区域22c的宽度(沟道宽度)在其沟道长度方向发生变化。具体而言，在图5中，越靠近选择TFT 20(图中上侧)宽度越宽，在保持电容28与驱动TFT 24的连接侧(图中下侧)宽度将变狭窄。依此修正TFT 22的沟道宽度在其沟道长度方向，设置至少不同于其它的部分，便可增加修正TFT 22的配置自由度。另外，修正TFT 22的特性可考虑以最狭窄的沟道宽度为基准。依此，通过提高修正TFT 22的配置自由度，便可有效的执行其它电路组件的驱动TFT 24的栅极24g的布局等。此外，为求能增加配置的自由度，优选的是，变更形成沟道区域的半导体层的宽度(沟道宽度方向)，也可变更其它选择TFT 20、驱动TFT 24等的沟道宽度，更加提高配置的自由度。Here, in thecorrection TFT 22 according to this embodiment, as shown in FIG. 5, the width (channel width) of thechannel region 22c formed of the semiconductor layer changes in the direction of the channel length. Specifically, in FIG. 5, the width becomes wider toward the selection TFT 20 (upper side in the figure), and becomes narrower on the connection side (lower side in the figure) of thestorage capacitor 28 and thedrive TFT 24. According to this, the channel width of the modifiedTFT 22 is set at least different from other parts in the channel length direction, so that the degree of freedom in the configuration of the modifiedTFT 22 can be increased. In addition, the characteristics of the modifiedTFT 22 can be considered based on the narrowest channel width. Accordingly, by increasing the degree of freedom in the arrangement of thecorrection TFT 22, the layout of thegate 24g of the drivingTFT 24, etc. of other circuit components can be effectively performed. In addition, in order to increase the degree of freedom of arrangement, it is preferable to change the width (channel width direction) of the semiconductor layer forming the channel region, and it is also possible to change the channel width ofother selection TFT 20, driveTFT 24, etc., more Improve configuration freedom.

再者，如上所述，实施形例所涉及的像素电路配置成矩阵状，而构成显示装置。多数情况在玻璃基板上，形成包含有机EL组件的像素区域，以及在其外围用以驱动各像素的外围驱动电路，形成的顺序是，首先在基板上形成像素区域中有机EL组件以外的电路组件与外围驱动电路，然后，在这些电路组件的上方形成有机EL组件，再从组件侧使封装基板覆盖玻璃基板100并粘着，而获得有机EL面板。另外，实施例所涉及的像素电路并不仅限于这种有机EL面板，可适用于其它各种显示装置。特别当适用于在各像素中形成电流驱动型显示组件与控制此组件的电路(TFT)的情况时，仍可获得相同的效果。Furthermore, as described above, the pixel circuits according to the embodiment are arranged in a matrix to form a display device. In most cases, on a glass substrate, a pixel area including an organic EL element is formed, and a peripheral drive circuit for driving each pixel is formed on its periphery. The order of formation is first to form circuit elements other than the organic EL element in the pixel area on the substrate Then, an organic EL module is formed on these circuit components, and the package substrate is covered with theglass substrate 100 from the module side and adhered to obtain an organic EL panel. In addition, the pixel circuits involved in the embodiments are not limited to such organic EL panels, and can be applied to other various display devices. Especially when applied to the case where a current-driven type display element and a circuit (TFT) for controlling this element are formed in each pixel, the same effect can be obtained.

接着，在本实施例中，优选的是，选择TFT 20、修正TFT 22多栅极化。这是因为特别将多晶硅层作为主动层使用的TFT，可有效减少较多的漏电流之故。漏电流在本实施例中，当修正TFT 22、选择TFT 20为关断时，透过这些TFT，流向数据线DL的电流，通过将这些TFT多栅极化，便可抑制漏电流。如图7所示，也可以仅将修正TFT 22施行多栅极化，或者也可仅将选择TFT 20施行多栅极化。当然，也可如图9所示，将二者施行多栅极化。Next, in this embodiment, it is preferable to select theTFT 20 and modify theTFT 22 to be multi-gated. This is because especially the TFT using the polysilicon layer as the active layer can effectively reduce a lot of leakage current. Leakage Current In this embodiment, when theTFT 22 is modified and theTFT 20 is selected to be off, the current flowing to the data line DL through these TFTs can be suppressed by multi-gate these TFTs. As shown in FIG. 7, only thecorrection TFT 22 may be multi-gated, or only theselection TFT 20 may be multi-gated. Of course, as shown in FIG. 9 , both of them can be multi-gated.

图7所示将修正TFT 22多栅极化时的等效电路，图8所示为实现该等效电路布局的一例的平面图。在图7的例子中，修正TFT 22采用所谓的双栅极构造。具体而言，在节点Tg24与选择TFT 20之间设置：漏极连接于节点Tg24的第1修正TFT 22-1，以及设置在此第1修正TFT 22-1与选择TFT 20之间的第2修正TFT 22-2等二组件。第1与第2修正TFT 22-1、22-2的栅极均连接于电源线PL，第1与第2修正TFT22-1、22-2的源极漏极电性串联连接于选择TFT 20与节点Tg24之间。由此形成这种连接关系，以提高驱动TFT 24与选择TFT 20之间的非导通漏电流耐性，而可有效防止保持于保持电容28的驱动TFT24的栅极电压V_g24泄漏于数据线DL而发生从适当数值偏移的变动的效果。FIG. 7 shows an equivalent circuit when thecorrection TFT 22 is multi-gated, and FIG. 8 is a plan view showing an example of the layout of the equivalent circuit. In the example of FIG. 7, thecorrection TFT 22 employs a so-called double gate structure. Specifically, between the node Tg24 and theselection TFT 20, a first modification TFT 22-1 whose drain is connected to the node Tg24, and a second modification TFT 22-1 provided between the first modification TFT 22-1 and theselection TFT 20 are provided between the node Tg24 and theselection TFT 20. Correct the second components such as TFT 22-2. The gates of the first and second correction TFTs 22-1 and 22-2 are connected to the power line PL, and the source and drain electrodes of the first and second correction TFTs 22-1 and 22-2 are electrically connected in series to theselection TFT 20 and node Tg24. This connection relationship is thus formed to improve the non-conduction leakage current resistance between the drivingTFT 24 and theselection TFT 20, and effectively prevent the gate voltage V_g24 of the drivingTFT 24 held in thestorage capacitor 28 from leaking to the data line DL. Instead, a shifted effect from the appropriate value occurs.

具体说明的话，通过分割修正TFT 22，在第1与第2修正TFT 22-1与22-2的连接点，将选择TFT 20的源极侧的电压V_s20(修正TFT 22-2的源极电压V_d22-2)与节点Tg24的电压V_g24予以分压，其间的数值的电压V_m便成为第1修正TFT 22-1的源极电压。TFT的非导通漏电流当TFT的漏极源极间电压Vds降低1V时，便将降低约1位数。所以，通过将修正TFT 22分割，便可将漏极连接于节点Tg24的第1修正TFT22-1的漏极源极间电压Vds缩小，而降低非导通漏电流。Specifically, by dividing thecorrection TFT 22, at the connection point of the first and second correction TFTs 22-1 and 22-2, the voltage V_s20 on the source side of the selection TFT 20 (the source of the correction TFT 22-2 The voltage V_d22-2 ) is divided by the voltage V_g24 of the node Tg24, and the voltage V_m having a value in between becomes the source voltage of the first correction TFT 22-1. The non-conducting leakage current of the TFT will decrease by about 1 digit when the voltage Vds between the drain and the source of the TFT decreases by 1V. Therefore, by dividing thecorrection TFT 22, the drain-source voltage Vds of the first correction TFT 22-1 whose drain is connected to the node Tg24 can be reduced to reduce the non-conduction leakage current.

另外，如图7所示，当将修正TFT 22多栅极化时，其导电区域(在此为漏极)连接于驱动TFT 24的栅极的第1修正TFT 22-1，其沟道区域尺寸未必要与另一方例如第2修正TFT 22-2的沟道区域尺寸相同。In addition, as shown in FIG. 7, when thecorrection TFT 22 is multi-gated, its conductive region (here, the drain) is connected to the first correction TFT 22-1 that drives the gate of theTFT 24, and its channel region The size is not necessarily the same as that of the channel region of the other, for example, the second modification TFT 22-2.

例如，将第1修正TFT 22-1的沟道区域尺寸设为较小于第2修正TFT 22-2的沟道区域尺寸，借此可减小第1修正TFT 22-1的栅极电容Cg22-1。当修正TFT 22为关断时，若从此栅极电容Cg22流入于保持电容28的电荷量较多时，节点Tg24的电位经长时间仍可维持于较高状态，随电容线SC下降的电压下降速度将变迟缓。所以，通过缩小第1修正TFT 22的沟道尺寸，在关断时，流入保持电容28的来自第1修正TFT 22-1的栅极电容Cg22-1的电荷量将减少，而可迅速降低节点Tg24的电压。在这种情况下，若将第1修正TFT 22-1的沟道区域的沟道长度设为L1、沟道宽度设为W1、将第2修正TFT  22-2的沟道区域的沟道长度设为L2、沟道宽度设为W2时，优选的是，满足W1×L1＜W2×L2。For example, setting the channel region size of the first modified TFT 22-1 to be smaller than the channel region size of the second modified TFT 22-2, thereby reducing the gate capacitance Cg22 of the first modified TFT 22-1 -1. When thecorrection TFT 22 is turned off, if there is a large amount of charge flowing from the gate capacitor Cg22 into thestorage capacitor 28, the potential of the node Tg24 can still be maintained at a high state for a long time, and the voltage drop rate decreases with the capacitor line SC will become sluggish. Therefore, by reducing the channel size of the first modifiedTFT 22, the amount of charge flowing into thestorage capacitor 28 from the gate capacitance Cg22-1 of the first modified TFT 22-1 at the time of turn-off is reduced, and the node can be rapidly reduced. The voltage of Tg24. In this case, if the channel length of the channel region of the first modified TFT 22-1 is set to L1, the channel width is set to W1, and the channel length of the channel region of the second modified TFT 22-2 is set to When L2 is used and the channel width is W2, it is preferable to satisfy W1×L1<W2×L2.

第1修正TFT 22-1的沟道长度L1，在满足降低非导通漏电流要求的最低极限程度的前提下，尽可能的缩短，沟道宽度W1则在布局限制所容许的范围内，尽可能的加宽。第2修正TFT 22-2的沟道长度L2越长，虽可使从此第2修正TFT 22-2的栅极电容Cg22-2流入节点Tg24的电荷的流出迟缓，但是如此一来，TFT的导通电阻将变大，数据写入时间将拉长。所以，优选的是，依L2/W2的值变小的方式，即L2增长份量恰为宽度W2加宽份量。由此观点来看，优选的是，满足上述W1×L1＜W2×L2。The channel length L1 of the first modified TFT 22-1 is shortened as much as possible under the premise of meeting the minimum limit of the non-conduction leakage current requirement, and the channel width W1 is within the allowable range of layout restrictions, as much as possible. possible widening. The longer the channel length L2 of the second modified TFT 22-2 is, the longer the outflow of charges flowing into the node Tg24 from the gate capacitance Cg22-2 of the second modified TFT 22-2 can be slowed down. The on-resistance will become larger, and the data writing time will be longer. Therefore, preferably, according to the way that the value of L2/W2 becomes smaller, that is, the amount of increase of L2 is exactly the amount of widening of the width W2. From this point of view, it is preferable that the above W1×L1<W2×L2 is satisfied.

图8所示如上述，将修正TFT 22多栅极化时的布局的一例平面构造。在图8的例子中，选择TFT 20的主动层与修正TFT 22的主动层，利用同一半导体层而一体形成，但为方便说明，对于构成第1修正TFT22-1、22-2的主动层的半导体层标注图标符号122。该半导体层122如同上述图5的布局，沿数据线DL并朝相邻行方向(图中下方)延伸。FIG. 8 shows an example of the planar structure of the layout when the modifiedTFT 22 is multi-gated as described above. In the example of FIG. 8, the active layer of theTFT 20 and the active layer of the modifiedTFT 22 are selected to be integrally formed using the same semiconductor layer. The semiconducting layer is marked withreference numeral 122 . Thesemiconductor layer 122 is similar to the layout of FIG. 5 , extending along the data line DL and toward the direction of the adjacent row (downward in the figure).

修正TFT 22-1、22-2的栅极22g(22g1、22g2)共通的在电源线PL的下层区域与该电源线PL相连接。所以，该栅极电极22g便从接触于电源线PL的位置起，朝数据线DL延伸于水平扫描方向，横跨主动层122上方的区域将构成第2修正TFT 22-2的栅极电极22g2，从此处更延伸至数据线DL的形成区域，在刚横跨数据线DL之后便返折，而钻入数据线DL下方。在钻入数据线DL后的附近，栅极电极22g将依再覆盖主动层122上方的方式，沿数据线DL的延伸方向朝下一行像素方向延伸，在此重叠于主动层122的区域便成为第1修正TFT 22-1的栅极电极22g1。另外，此第1修正TFT 22-1的栅极电极22g1形成于电源线PL与主动层122的层间，主动层122便电性阻隔形成于其上方的电源线PL与数据线DL。Thecommon gates 22g (22g1, 22g2) of the correction TFTs 22-1, 22-2 are connected to the power supply line PL in the lower region of the power supply line PL. Therefore, thegate electrode 22g extends from the position in contact with the power line PL to the data line DL in the horizontal scanning direction, and the area above theactive layer 122 will constitute the gate electrode 22g2 of the second modified TFT 22-2. , extending from here to the formation area of the data line DL, and turning back just after crossing the data line DL, and drilling under the data line DL. In the vicinity of the drilled data line DL, thegate electrode 22g will extend along the extension direction of the data line DL toward the direction of the next row of pixels in such a way as to cover the top of theactive layer 122 again, and the area overlapping theactive layer 122 here becomes The gate electrode 22g1 of the first correction TFT 22-1. In addition, the gate electrode 22g1 of the first modified TFT 22-1 is formed between the power line PL and theactive layer 122, and theactive layer 122 electrically isolates the power line PL and the data line DL formed above it.

依此，将栅极电极22g返折成U形图案，借此可覆盖沿数据线DL朝垂直扫描方向延伸的半导体层122上方例如2个地方，可在分别被栅极电极22g所覆盖的位置各自形成沟道区域22c2、22c1。半导体层122从连接于第2修正TFT22-2的选择TFT20的源极区域20s侧起，依序形成源极区域22s2、沟道区域22c2(栅极电极22g2的下层区域)、第2修正TFT 22-2的漏极区域22d2及第1修正TFT 22-1的源极区域22s1、沟道区域22c1(栅极电极22g1的下层)、及第1修正TFT 22-1的漏极区域22d1。然后，第1修正TFT 22-1的漏极区域22d1连接保持电容28的电容电极28e(同一半导体层)，且透过金属配线24w与驱动TFT 24的栅极电极24g相连接。According to this, thegate electrode 22g is folded back into a U-shaped pattern, thereby covering, for example, two places above thesemiconductor layer 122 extending along the data line DL toward the vertical scanning direction, and the positions covered by thegate electrode 22g can be respectively Channel regions 22c2, 22c1 are formed respectively. In thesemiconductor layer 122, a source region 22s2, a channel region 22c2 (a region under the gate electrode 22g2), and asecond correction TFT 22 are sequentially formed from thesource region 20s side of theselection TFT 20 connected to the second correction TFT 22-2. -2 drain region 22d2, source region 22s1 of the first correction TFT 22-1, channel region 22c1 (under the gate electrode 22g1), and drain region 22d1 of the first correction TFT 22-1. Then, the drain region 22d1 of the first correction TFT 22-1 is connected to thecapacitor electrode 28e (same semiconductor layer) of the holdingcapacitor 28, and is connected to thegate electrode 24g of the drivingTFT 24 through themetal wiring 24w.

若采用图8所示布局的话，即便将修正TFT 22多栅极化(在此为[双栅极化])，仍可极力抑制其设置面积的增加。If the layout shown in FIG. 8 is adopted, even if thecorrection TFT 22 is multi-gated (here, [double-gated]), the increase in its installation area can be suppressed as much as possible.

图9所示的不仅修正TFT 22，就连上述选择TFT 20页施行多栅极化情况时的电路构造例。此外，图10所示是采用图9所示电路构造时的实际布局一例平面图。在图9的例子中，由串联连接于数据线DL的2个选择TFT20-1、20-2构成选择TFT。另外，2个选择TFT 20-1、20-2的栅极均连接于栅极线GL。Fig. 9 shows not only thecorrection TFT 22, but also an example of the circuit configuration when multi-gate is implemented on the above-mentioned selectedTFT 20 page. In addition, FIG. 10 is a plan view showing an example of the actual layout when the circuit configuration shown in FIG. 9 is adopted. In the example of FIG. 9, the selection TFT is comprised by two selection TFT20-1, 20-2 connected in series to the data line DL. In addition, the gates of the two selection TFTs 20-1 and 20-2 are both connected to the gate line GL.

为将选择TFT 20施行多栅极化，对如图5等所示的选择TFT 20的单栅极构造布局，施加简单的变更便可轻易的对应。例如图10所示，构成选择TFT 20的主动层的半导体层120在选择TFT 20的形成区域附近，形成从数据线DL在电源线PL处返折为U形(ㄈ形)的形状。所以，仅要将从栅极线GL突出形成的栅极电极20g的图案，形成如图10中虚线所示，更进一步的延长并重叠于从电源线PL返折的半导体层120上层状态的话便可。依此延伸栅极电极20g，在靠近返折呈U形的半导体层120的栅极线GL附近侧，与返折侧的2个地方形成栅极电极20g1、20g2，并通过在各自下层形成沟道区域20c1、20c2，便可轻易地形成其主动层电性串联连接于数据线DL的双栅极型选择TFT20。此外，再如图10所示，从栅极电极20g中途更朝水平扫描方向设置突出部，便可由将主动层的U形底边部分的上层覆盖此突出部的方式，获得3个主动层串联连接于数据线DL的三栅极型选择TFT 20。In order to implementmulti-gate selection TFT 20, it is possible to easily correspond to the single-gate structure layout ofselection TFT 20 as shown in FIG. 5 and the like. For example, as shown in FIG. 10, thesemiconductor layer 120 constituting the active layer of theselection TFT 20 is formed in a U-shape (ㄈ shape) from the data line DL at the power line PL near the formation region of theselection TFT 20. Therefore, it is only necessary to form the pattern of thegate electrode 20g protruding from the gate line GL, as shown by the dotted line in FIG. Can. In this way, thegate electrode 20g is extended, and the gate electrodes 20g1 and 20g2 are formed on the side close to the gate line GL of theU-shaped semiconductor layer 120 and the two places on the side of the folded back. The channel regions 20c1 and 20c2 can easily form adouble-gate selection TFT 20 whose active layer is electrically connected in series with the data line DL. In addition, as shown in FIG. 10, a protrusion is provided from thegate electrode 20g toward the horizontal scanning direction, and the upper layer of the U-shaped bottom part of the active layer can cover the protrusion, so that three active layers can be connected in series. A tri-gatetype selection TFT 20 connected to the data line DL.

图11所示修正TFT 22的多栅极(双栅极)化的另一布局例。在图11的布局中，从朝水平扫描方向延伸的栅极线GL，由与数据线DL的接触区域起，沿该栅极线GL朝水平扫描方向配置半导体层120，朝该半导体层120并排突出形成2个栅极电极20g1、20g2。在该例子中，多栅极的选择TFT 20的沟道区域20c1、20c2并排配置于栅极线GL的延伸方向即水平扫描方向。Another layout example of multi-gate (double gate)correction TFT 22 shown in FIG. 11 . In the layout of FIG. 11 , from the gate line GL extending in the horizontal scanning direction, from the contact area with the data line DL, thesemiconductor layer 120 is arranged in the horizontal scanning direction along the gate line GL, and thesemiconductor layer 120 is arranged side by side. Two gate electrodes 20g1 and 20g2 are protrudingly formed. In this example, the channel regions 20c1 and 20c2 of themulti-gate selection TFT 20 are arranged side by side in the direction in which the gate line GL extends, that is, the horizontal scanning direction.

如上述图9及图10、或图11所示，不仅修正TFT 22，甚至将选择TFT 20多栅极化，借此可更有效的抑制非导通漏电流。As shown in FIG. 9 and FIG. 10, or FIG. 11 above, not only theTFT 22 is modified, but even the selectedTFT 20 is multi-gated, so that the non-conduction leakage current can be more effectively suppressed.

图12所示为另一电路构造例。在图12所示的平均1个像素的等效电路构造中，在一端(第1导电区域：例如漏极)连接于数据线DL的选择TFT 20的另一端(第2导电区域：例如源极)与上述修正TFT 22的第1导电区域(例如源极)之间，更具备有栅极连接于电容线SC的抑制漏电流TFT 30。此抑制漏电流TFT 30是n沟道型，与修正TFT 22呈相反极性。Fig. 12 shows another circuit configuration example. In the equivalent circuit structure of an average pixel shown in FIG. ) and the first conductive region (for example, the source) of thecorrection TFT 22, there is also a leakagecurrent suppression TFT 30 whose gate is connected to the capacitance line SC. This leakagecurrent suppression TFT 30 is of an n-channel type, and has an opposite polarity to that of thecorrection TFT 22.

该抑制漏电流TFT 30电容线SC呈H电位时便导通，呈L电位时便关断。所以，栅极线GL在H电位期间导通，在关于将数据线DL的数据电压Vdata写入于驱动TFT 24的栅极方面，均不致发生问题。此外，在资料写入结束之后，因为电容线SC降低为L电位，因而关断。即，当电容线SC下降，驱动TFT 24的栅极电位转为低电压的情况时，该抑制漏电流TFT 30便维持关断状态，便可有效的抑制从此时的数据线DL朝驱动TFT 24的栅极流通的漏电流。所以，将可更加提升显示装置内的若干像素的各发光辉度的均匀状况。另外，在图12所示构造中，虽可更将修正TFT 22多栅极化，便可更加降低非导通漏电流，但是电路组件的增加将导致开口率下降。所以，在开口率取最大极限，且可达各像素发光辉度均匀的范围内，决定是否更进一步将修正TFT多栅极化较为适合。The leakagecurrent suppressing TFT 30 capacitance line SC is turned on when the electric potential is H, and is turned off when the electric potential is L. Therefore, the gate line GL is turned on during the H potential period, and there is no problem in writing the data voltage Vdata of the data line DL to the gate of the drivingTFT 24. In addition, after data writing is completed, the capacitive line SC is lowered to L potential, and thus turned off. That is, when the capacitance line SC drops and the gate potential of the drivingTFT 24 turns to a low voltage, the leakagecurrent suppressing TFT 30 will maintain an off state, which can effectively suppress the current from the data line DL to the drivingTFT 24. The leakage current flowing through the gate. Therefore, the uniformity of the luminance of each pixel in the display device can be further improved. In addition, in the structure shown in FIG. 12, although thecorrection TFT 22 can be multi-gated, the non-conduction leakage current can be further reduced, but the increase of circuit components will lead to a decrease in aperture ratio. Therefore, in the range where the aperture ratio is at the maximum limit and the luminance of each pixel can be uniform, it is more appropriate to determine whether to further multi-gate the correction TFT.

产业上之可利用性Industrial availability

可利用在各像素具有显示组件的显示装置等。A display device or the like having a display element in each pixel can be used.

Claims (19)

1. image element circuit is characterized in that it has:

One end is connected in data line, and by the selection transistor of control end input select signal;

One end is connected in the transistorized other end of described selection, and control end is connected in the correction transistor of the 1st power supply of predetermined voltage;

Control end is connected in the transistorized other end of described correction, and an end is connected in the driving transistors as the 2nd power supply of electric current source of supply;

One end is connected in the control end of described driving transistors, and the other end is connected in the maintenance electric capacity of Pulse Electric line ball; And

Utilization circulates in the electric current of described driving transistors and luminous luminescence component;

At the magnitude of voltage that utilizes the described Pulse Electric line ball of change and in the process of the above-mentioned driving transistors of conducting, make described correction transistor turns or shutoff, control end voltage when controlling described driving transistors conducting whereby, described driving transistors and described correction transistor abut to form simultaneously.

2. image element circuit according to claim 1 is characterized in that,

Under state with described selection transistor turns, supply makes the data voltage of revising transistor turns to data line, and the voltage of corresponding data voltage remained on the control end of driving transistors, then, described selection transistor is turn-offed, under this state, the voltage of Pulse Electric line ball is changed, and make the control end voltage shift of driving transistors, make whereby and revise the transistor shutoff, make the driving transistors conducting simultaneously, and the current flowing that makes corresponding data voltage is in driving transistors.

3. image element circuit according to claim 1 is characterized in that, described the 1st power supply and the 2nd power supply are same power supply.

4. image element circuit according to claim 1 is characterized in that, described correction transistor AND gate driving transistors is the p channel transistor, and described Pulse Electric line ball is varied to electronegative potential from noble potential after described selection transistor turn-offs.

5. image element circuit according to claim 1 is characterized in that, the active layers of described correction transistor and described driving transistors constitutes by the many crystal semiconductors that obtained through the multiple crystallization laser annealing,

The orientation of transistorized orientation of described correction and described driving transistors, the direction of scanning of the linear pulse laser that is shone when being configured to be parallel to described multiple crystallization laser annealing, and the channel region of transistorized channel region of described correction and described driving transistors, its at least a portion all are positioned on the crisscross same straight line of pulling out in described pulse laser direction of scanning.

6. image element circuit according to claim 1 is characterized in that described data line and power lead extend towards vertical scanning direction, and described correction transistor is formed between described data line and the power lead.

7. image element circuit according to claim 6 is characterized in that, described driving transistors presss from both sides the described power lead that is being situated between, and is formed at the transistorized opposition side of described correction.

8. image element circuit according to claim 6, it is characterized in that, under state with described selection transistor turns, supply makes the data voltage of revising transistor turns to data line, and the voltage of corresponding data voltage is remained on the control end of driving transistors, then, described selection transistor is turn-offed, under this state, the voltage of Pulse Electric line ball is changed, and make the control end voltage shift of driving transistors, make whereby and revise the transistor shutoff, make the driving transistors conducting simultaneously, and the current flowing that makes corresponding data voltage is in driving transistors.

9. image element circuit according to claim 6 is characterized in that, described the 1st power supply and the 2nd power supply are same power supply.

10. image element circuit according to claim 6 is characterized in that, described correction transistor AND gate driving transistors p channel transistor, and described Pulse Electric line ball is varied to electronegative potential from noble potential after described selection transistor turn-offs.

11. image element circuit according to claim 6 is characterized in that, the active layers of described correction transistor and described driving transistors constitutes by the many crystal semiconductors that obtained through the multiple crystallization laser annealing,

The orientation of transistorized orientation of described correction and described driving transistors, the direction of scanning of the linear pulse laser that is shone when being configured to be parallel to described multiple crystallization laser annealing, and the channel region of transistorized channel region of described correction and described driving transistors, its at least a portion all are positioned on the crisscross same straight line of pulling out in described pulse laser direction of scanning.

Be arranged in rectangular display device 12. a display device, described display device are plurality of pixels, it is characterized in that, each pixel has:

The display module that the corresponding electric power of being supplied moves;

The 1st conductive region is connected in data line, and to the selection transistor of control end input select signal;

The 1st conductive region is connected in power lead, electric power supply is given the driving transistors of described display module;

Control end is connected in the 1st power supply of predetermined voltage, and the 1st conductive region is connected in transistorized the 2nd conductive region of described selection, and the 2nd conductive region is connected in the correction transistor of the control end of described driving transistors; And,

The 1st electrode is connected in the control end and transistorized the 2nd conductive region of described correction of described driving transistors, and the 2nd electrode is connected in the maintenance electric capacity of Pulse Electric line ball;

Corresponding its action threshold value of described correction transistor, and the variation in voltage of corresponding described Pulse Electric line ball change the control end voltage of described driving transistors, in view of the above and the described control end voltage of control when described driving transistors is conducting state;

The described driving transistors of described correction transistor AND gate is made of same conductive-type transistor;

And the channel region at least of the described driving transistors of described correction transistor AND gate, by through laser annealing and the semiconductor layer of multiple crystallization constitutes, this channel region is mutually near configuration.

13. display device according to claim 12, it is characterized in that, the orientation of transistorized orientation of described correction and described driving transistors, the direction of scanning of the linear pulse laser that is shone when being configured to be parallel to described multiple crystallization laser annealing, and the channel region of transistorized channel region of described correction and described driving transistors, its at least a portion all are positioned on the same straight line that described pulse laser direction of scanning orthogonal directions pulled out.

14. display device according to claim 12 is characterized in that, the transistorized channel region of described correction possesses to be had in its orientation, the part of channel width inequality.

15. display device according to claim 12 is characterized in that, described correction transistor possesses to be had between the line of described data line and described power lead, extends in partly overlapping mode with a side line wherein at least and the active layers that forms.

Be arranged in rectangular display device 16. a display device, described display device are plurality of pixels, it is characterized in that, each pixel has:

The display module that corresponding supply electric power moves;

The 1st conductive region is connected in data line, and to the selection transistor of control end input select signal;

The 1st conductive region is connected in power lead, electric power supply is given the driving transistors of described display module;

Control end is connected in the 1st power supply of predetermined voltage, and the 1st conductive region is connected in transistorized the 2nd conductive region of described selection, and the 2nd conductive region is connected in the correction transistor of the control end of described driving transistors; And,

The 1st electrode is connected in the control end and transistorized the 2nd conductive region of described correction of described driving transistors, and the 2nd electrode is connected in the maintenance electric capacity of Pulse Electric line ball;

Corresponding its action threshold value of described correction transistor, and the variation in voltage of corresponding described Pulse Electric line ball change the control end voltage of described driving transistors, in view of the above and the described control end voltage of control when described driving transistors is conducting state;

The described driving transistors of described correction transistor AND gate is made of same conductive-type transistor;

And at least a portion of the transistorized active layers of described correction is pressed from both sides the lower floor position that is being situated between insulation course and is being formed at described power lead at interlayer.

17. display device according to claim 16 is characterized in that,

Described the 1st power supply dual-purpose power lead,

Interlayer at transistorized active layers of described correction and described power lead is formed with the transistorized control end of described correction that is connected in described power lead.

18. display device according to claim 16 is characterized in that,

The transistorized channel region of described correction possesses to be had in its orientation, the part of channel width inequality.

19. display device according to claim 16 is characterized in that,

Described correction transistor possesses to be had between the line of described data line and described power lead, extends in partly overlapping mode with a side line wherein at least and the active layers that forms.

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