CN100411153C

Movatterモバイル変換

Info

Publication number: CN100411153C
Application number: CNB2006101006496A
Authority: CN
Inventors: 陈信铭
Original assignee: Toppoly Optoelectronics Corp
Current assignee: TPO Displays Corp
Priority date: 2003-01-10
Filing date: 2003-01-10
Publication date: 2008-08-13
Anticipated expiration: 2023-01-10
Also published as: CN1901168A

Abstract

A method for manufacturing a thin film transistor array and a driving circuit includes: providing a substrate, and sequentially forming a polycrystalline silicon layer and a doped thin film of a first conductive type; performing a first photomask process to form a plurality of island-shaped structures; performing a second photomask process, and implanting a doped region of a second conductivity type into the doped film of the first conductivity type; forming a first conductor layer on the obtained structure, and performing a third photomask process to form a source electrode, a drain electrode and a lower electrode of the storage capacitor; forming a first dielectric layer and a second conductor layer on the obtained structure, and performing a fourth photomask process to form a stacked structure of a gate insulating layer and a gate electrode, and simultaneously forming a dielectric layer and an upper electrode of a storage capacitor; forming a protective layer on the resultant structure, and performing a fifth photomask process to form openings exposing the respective source and drain electrodes and the upper electrode of the storage capacitor; a conductive layer is formed on the resulting structure, and a sixth photomask process is performed to form a conductive line and a pixel electrode.

Description

Translated fromChinese

薄膜晶体管阵列及其驱动电路的制造方法Thin film transistor array and its driving circuit manufacturing method

本申请是第03101633.2号发明专利申请的分案申请。This application is a divisional application of No. 03101633.2 patent application for invention.

技术领域technical field

本发明涉及一种薄膜晶体管阵列及其驱动电路的制造方法，且特别是一种以六道光掩模工艺即可完成的薄膜晶体管阵列及其驱动电路的制造方法。The invention relates to a manufacturing method of a thin film transistor array and its driving circuit, in particular to a manufacturing method of the thin film transistor array and its driving circuit which can be completed by six photomask processes.

背景技术Background technique

针对多媒体社会的急速进步，多半受惠于半导体元件或人机显示装置的飞跃进步。就显示器而言，阴极射线管(Cathode Ray Tube，CRT)因具有优异的显示品质与其经济性，一直独占近年来的显示器市场。然而，对于个人在桌上操作多数终端机/显示器装置的环境，或是以环保的观点切入，若以节省能源的潮流加以预测阴极射线管因空间利用以及能源消耗上仍存在很多问题，而对于轻、薄、短、小以及低消耗功率的需求无法有效提供解决的方法。因此，具有高画质、空间利用效率佳、低消耗功率、无辐射等优越特性的薄膜晶体管液晶显示器(TFT-LCD)已逐渐成为市场的主流。The rapid progress of the multimedia society is mostly due to the rapid progress of semiconductor components or man-machine display devices. As far as the display is concerned, the cathode ray tube (Cathode Ray Tube, CRT) has been monopolizing the display market in recent years because of its excellent display quality and economy. However, for the environment where individuals operate most terminals/display devices on the table, or from the perspective of environmental protection, if the trend of energy saving is used to predict that cathode ray tubes still have many problems in terms of space utilization and energy consumption, and for The demands of lightness, thinness, shortness, smallness and low power consumption cannot effectively provide a solution. Therefore, thin film transistor liquid crystal displays (TFT-LCDs) with superior characteristics such as high image quality, good space utilization efficiency, low power consumption, and no radiation have gradually become the mainstream of the market.

我们所熟知的薄膜晶体管大致上可分为非晶硅薄膜晶体管与多晶硅薄膜晶体管两种。低温多晶硅(LTPS)技术有别于一般传统的非晶硅(a-Si)技术，其电子迁移率可以达到200cm2/V-sec以上，因此可使薄膜晶体管的尺寸更小，具有增加显示器的开口率(aperture ratio)、减少功率消耗等功能。此外，低温多晶硅制造工艺可以将部份驱动电路随同薄膜晶体管制造工艺一并制造于基板上，大幅提升液晶显示面板的特性及可靠度，故制造成本大幅降低。The well-known thin film transistors can be roughly divided into two types: amorphous silicon thin film transistors and polycrystalline silicon thin film transistors. Low-temperature polysilicon (LTPS) technology is different from the general traditional amorphous silicon (a-Si) technology. Its electron mobility can reach more than 200cm2/V-sec, so it can make the size of thin-film transistors smaller and increase the opening of the display. rate (aperture ratio), reduce power consumption and other functions. In addition, the low-temperature polysilicon manufacturing process can manufacture part of the driving circuit on the substrate together with the thin film transistor manufacturing process, which greatly improves the characteristics and reliability of the liquid crystal display panel, so the manufacturing cost is greatly reduced.

图1(A)至图1(H)绘示为已有薄膜晶体管阵列以及驱动电路制造工艺的剖面图。请参照图1A，首先提供一基板100，并于基板100上形成一多晶硅层(polysilicon layer)，接着以第一道光掩模工艺(Mask 1)定义此多晶硅层，以使其形成多个多晶硅材料的岛状结构102a、102b、102c。FIG. 1(A) to FIG. 1(H) are cross-sectional views of the manufacturing process of the conventional thin film transistor array and the driving circuit. Please refer to FIG. 1A , first provide asubstrate 100, and form a polysilicon layer (polysilicon layer) on thesubstrate 100, and then define the polysilicon layer with the first photomask process (Mask 1), so that it forms a plurality of polysilicon layers Islands ofmaterial 102a, 102b, 102c.

岛状结构102a是用以形成薄膜晶体管(TFT)，而岛状结构102b以及岛状结构102c是用以形成驱动电路，如互补金属氧化物半导体(CMOS)。由于岛状结构102a是用以形成薄膜晶体管，故岛状结构102a通常是以阵列方式排列于基板100上，而岛状结构102b以及岛状结构102c则通常是配置于基板100的边缘或其他区域。Theisland structure 102a is used to form a thin film transistor (TFT), and theisland structure 102b and theisland structure 102c are used to form a driving circuit, such as a complementary metal oxide semiconductor (CMOS). Since theisland structure 102a is used to form a thin film transistor, theisland structure 102a is usually arranged on thesubstrate 100 in an array, while theisland structure 102b and theisland structure 102c are usually arranged on the edge or other areas of thesubstrate 100 .

接着请参照图1(B)，于形成有岛状结构102a、102b、102c的基板100上依序形成一第一介电层104以及一导体层(图中未绘)。接着再以第二道光掩模工艺(Mask 2)定义此导体层，以于岛状结构102a、102b、102c上分别形成栅极106a、106b、106c，并于基板100的适当位置上形成存储电容器的下电极108。Next, referring to FIG. 1(B), a firstdielectric layer 104 and a conductive layer (not shown in the figure) are sequentially formed on thesubstrate 100 formed with theisland structures 102a, 102b, 102c. Then define the conductor layer with the second photomask process (Mask 2) to formgates 106a, 106b, 106c on theisland structures 102a, 102b, 102c respectively, and form storage capacitors at appropriate positions on thesubstrate 100. Thelower electrode 108.

接着请参照图1(C)，以第三道光掩模工艺(Mask 3)决定N+掺杂区域110、112的位置，以于岛状结构102a中形成N+掺杂区域110，而于岛状结构102c中形成N+掺杂区域112。其中，岛状结构102a中的N+掺杂区域110是分布于栅极106a的两侧，而岛状结构102c中的N+掺杂区域112则是分布于栅极106c的两侧。Then please refer to FIG. 1(C), the positions of the N+ dopedregions 110 and 112 are determined by the third photomask process (Mask 3), so as to form the N+ dopedregion 110 in theisland structure 102a, and in the island structure N+ dopedregion 112 is formed in 102c. Wherein, the N+ dopedregion 110 in theisland structure 102a is distributed on both sides of thegate 106a, and the N+ dopedregion 112 in theisland structure 102c is distributed on both sides of thegate 106c.

接着请参照图1(D)，接着以第四道光掩模工艺(Mask 4)决定N-掺杂区域的位置，以于岛状结构102a中形成N-掺杂区域114，而于岛状结构102c中形成N-掺杂区域116。其中，岛状结构102a中的N-掺杂区域114是分布于栅极106a与N+掺杂区域110之间，而岛状结构102c中的N-掺杂区域116则是分布于栅极106c与N+掺杂区域112之间。Then please refer to FIG. 1(D), and then determine the position of the N-doped region by the fourth photomask process (Mask 4), so as to form the N-doped region 114 in theisland structure 102a, and in the island structure N-doped region 116 is formed in 102c. Wherein, the N-doped region 114 in theisland structure 102a is distributed between thegate 106a and the N+ dopedregion 110, while the N-doped region 116 in theisland structure 102c is distributed between thegate 106c and the N+ dopedregion 110. between N+ dopedregions 112 .

接着请参照图1(E)，以第五道光掩模工艺(Mask 5)决定P+掺杂区域的位置，以于岛状结构102b中形成P+掺杂区域118。其中，岛状结构102b中的P+掺杂区域110是分布于栅极106b的两侧。Next, referring to FIG. 1(E), the position of the P+ doped region is determined by the fifth photomask process (Mask 5), so as to form the P+ dopedregion 118 in theisland structure 102b. Wherein, the P+ dopedregion 110 in theisland structure 102b is distributed on both sides of thegate 106b.

接着请参照图1(F)，形成一第二介电层120覆盖于基板100上，接着以第六道光掩模工艺(Mask 6)定义第一介电层104以及第二介电层120，以决定第一介电层104以及第二介电层120的图案。1(F), a seconddielectric layer 120 is formed to cover thesubstrate 100, and then the sixth photomask process (Mask 6) is used to define the firstdielectric layer 104 and the seconddielectric layer 120, To determine the patterns of the firstdielectric layer 104 and the seconddielectric layer 120 .

第一介电层104以及第二介电层120中具有开口122a、开口122b以及开口122c。其中，开口122a是将N+掺杂区域110暴露，开口122b是将P+掺杂区域118暴露，而开口122c则是将N+掺杂区域112暴露。The firstdielectric layer 104 and the seconddielectric layer 120 have anopening 122 a , an opening 122 b and an opening 122 c therein. Theopening 122 a exposes the N+ dopedregion 110 , the opening 122 b exposes the P+ dopedregion 118 , and the opening 122 c exposes the N+doped region 112 .

接着请参照图1(G)，形成一导体层(图中未绘)覆盖于第二介电层120上，接着再以第七道光掩模工艺(mask 7)定义上述的导体层以形成源极/漏极124。其中，源极/漏极124是藉由开口122a、开口122b以及开口122c而分别与N+掺杂区域110、P+掺杂区域118暴露以及N+掺杂区域112电性连接。Then please refer to FIG. 1(G), a conductive layer (not shown in the figure) is formed to cover the seconddielectric layer 120, and then the seventh photomask process (mask 7) is used to define the above-mentioned conductive layer to form the source pole/drain 124. The source/drain 124 is electrically connected to the N+ dopedregion 110 , the exposed P+ dopedregion 118 and the N+ dopedregion 112 through theopening 122 a , the opening 122 b and the opening 122 c .

接着请参照图1(H)，形成一平坦层126覆盖于已形成有源极/漏极124的基板100上，接着再以第八道光掩模工艺(Mask 8)定义平坦层126，以决定平坦层126的图案。其中，平坦层126具有开口128，此开口128是用以将源极/漏极124a暴露。Then referring to FIG. 1(H), aflat layer 126 is formed to cover thesubstrate 100 on which the source/drain 124 has been formed, and then the eighth photomask process (Mask 8) is used to define theflat layer 126, so as to The pattern of theplanarization layer 126 is determined. Wherein, theflat layer 126 has anopening 128 for exposing the source/drain 124a.

在以第八道光掩模工艺(Mask 8)定义平坦层126之后，接着会形成一导电层(图中未绘)于基板100上，此导电层通常是氧化铟锡等透明材料。最后再以第九道光掩模工艺(Mask 9)定义上述的导电层，以形成像素电极130。After the eighth photomask process (Mask 8) is used to define theplanar layer 126, a conductive layer (not shown in the figure) is formed on thesubstrate 100, and the conductive layer is usually a transparent material such as ITO. Finally, the above-mentioned conductive layer is defined by the ninth photomask process (Mask 9) to form thepixel electrode 130.

同样请参照图1(H)，由图1(H)左侧可以得知，岛状结构102c中的N-掺杂区域116及N+掺杂区域112、栅极106c以及源极/漏极124c是构成一N型金属氧化物半导体(NMOS)。岛状结构102b中的P+掺杂区域118、栅极106b以及源极/漏极124b是构成一P型金属氧化物半导体(PMOS)。而由上述N型金属氧化物半导体(NMOS)以及P型金属氧化物半导体(PMOS)即可构成一互补金属氧化物半导体(CMOS)，此互补金属氧化物半导体(CMOS)于面板上所扮演的角色为一内藏的驱动电路(driving circuit)，用以驱动图1H右侧薄膜晶体管(TFT)，进而控制像素的显示。Please also refer to FIG. 1(H), as can be seen from the left side of FIG. 1(H), the N-doped region 116 and the N+ dopedregion 112, thegate 106c, and the source/drain 124c in theisland structure 102c It constitutes an N-type metal oxide semiconductor (NMOS). The P+ dopedregion 118 , thegate 106 b and the source/drain 124 b in theisland structure 102 b constitute a P-type metal oxide semiconductor (PMOS). A complementary metal oxide semiconductor (CMOS) can be formed by the above-mentioned N-type metal oxide semiconductor (NMOS) and P-type metal oxide semiconductor (PMOS). The role is a built-in driving circuit, which is used to drive the thin-film transistor (TFT) on the right side of FIG. 1H to control the display of the pixels.

由图1(H)右侧可以得知，岛状结构102a中的N-掺杂区域110及N+掺杂区域114、栅极106a以及源极/漏极124a是构成一多晶硅型态的薄膜晶体管(Poly-TFT)。其中，薄膜晶体管藉由上述互补金属氧化物半导体(CMOS)的驱动来控制写入像素电极130的数据(data)。It can be known from the right side of FIG. 1(H) that the N-doped region 110 and the N+ dopedregion 114, thegate 106a and the source/drain 124a in theisland structure 102a constitute a polysilicon type thin film transistor (Poly-TFT). Wherein, the thin film transistor is driven by the complementary metal oxide semiconductor (CMOS) to control the data written into thepixel electrode 130 .

图2绘示为已有薄膜晶体管阵列以及驱动电路的制作流程图。请参照图2，已有薄膜晶体管阵列以及驱动电路的制作流程主要是由定义多晶硅层S200、定义栅极&存储电容的下电极S202、定义N+掺杂区域S204、定义N-掺杂区域S206、定义P+掺杂区域S208、定义第一介电层的图案S210、定义源极/漏极&存储电容的上电极S212、定义第二介电层的图案S214，以及定义像素电极的图案S216等步骤所构成。FIG. 2 is a flow chart showing the manufacturing process of the existing thin film transistor array and driving circuit. Please refer to FIG. 2, the manufacturing process of the existing thin film transistor array and driving circuit is mainly defined by defining the polysilicon layer S200, defining the lower electrode S202 of the gate & storage capacitor, defining the N+ doped region S204, defining the N-doped region S206, Define the P+ doped region S208, define the pattern S210 of the first dielectric layer, define the upper electrode S212 of the source/drain & storage capacitor, define the pattern S214 of the second dielectric layer, and define the pattern S216 of the pixel electrode, etc. constituted.

已有薄膜晶体管阵列及其驱动电路结构，在制作上所需的光掩模数目较多，通常需要八道(不包含N-掺杂区域114、116的制作)或是九道光掩模工艺才能够完成，使得制造工艺成本难以降低。此外，由于所需的光掩模数目较多，使得面板制作的时间无法有效缩短，且良率难以提升。The existing thin-film transistor array and its driving circuit structure require a large number of photomasks for fabrication, usually eight (not including the fabrication of N-dopedregions 114 and 116 ) or nine photomask processes are required. Can be completed, making it difficult to reduce the cost of the manufacturing process. In addition, due to the large number of photomasks required, the time for panel fabrication cannot be effectively shortened, and the yield rate is difficult to improve.

发明内容Contents of the invention

本发明的目的是提出一种薄膜晶体管阵列及其驱动电路的制造方法，其仅需以六道光掩模工艺即可制作完成。The purpose of the present invention is to propose a manufacturing method of a thin film transistor array and its driving circuit, which can be completed by only six photomask processes.

为达到本发明的上述目的，提出一种薄膜晶体管阵列以及驱动电路的制造方法，包括以下步骤：提供一基板，并依次形成多晶硅层和第一导电类型的掺杂薄膜；执行第一光掩模工艺，以对该多晶硅层和第一导电类型的掺杂薄膜构图，形成包括该多晶硅层和该第一导电类型的掺杂薄膜的多个岛状结构，其中，该多个岛状结构包括用于形成薄膜晶体管阵列的第一岛状结构和用于形成驱动电路的第二岛状结构；执行第二光掩模工艺，以在至少一部分所述第二岛状结构的部分或全部区域上在第一导电类型的掺杂薄膜中注入第二导电类型的掺杂区域；在所得结构上形成第一导体层，并且执行第三光掩模工艺，以对该第一导体层构图，在各个岛状结构的该第一导电类型的掺杂薄膜、该第二导电类型的掺杂区域上分别形成源极和漏极，并在基板上形成存储电容器的下电极，并且在该第三光掩模工艺中，用同样的光掩模对位于该第一导体层下方的该第一导电类型的掺杂薄膜和第二导电类型的掺杂区域进行构图，从而该源极和该漏极与其下方的该第一导电类型的掺杂薄膜或第二导电类型的掺杂区域具有相同的图案；在所得结构上形成第一介电层和第二导体层，并执行第四光掩模工艺，以对该第一介电层和该第二导体层构图，在各个岛状结构的该多晶硅层之上形成栅绝缘层和栅极的堆叠结构，同时，在对应于所述存储电容器的下电极的位置形成存储电容器介电层和上电极；在所得结构上形成保护层，并执行第五光掩模工艺，以对该保护层构图，形成暴露各个所述源极和漏极以及存储电容器的上电极的开口；在所得结构上形成导电层，并执行第六光掩模工艺，以对该导电层构图，形成导线和像素电极。In order to achieve the above object of the present invention, a method for manufacturing a thin film transistor array and a driving circuit is proposed, comprising the following steps: providing a substrate, and sequentially forming a polysilicon layer and a doped film of the first conductivity type; performing a first photomask process, to pattern the polysilicon layer and the doped film of the first conductivity type to form a plurality of island structures comprising the polysilicon layer and the doped film of the first conductivity type, wherein the plurality of island structures include A first island structure for forming a thin film transistor array and a second island structure for forming a driving circuit; performing a second photomask process to cover at least part of a part or all of the second island structure Implanting a doped region of a second conductivity type into a doped film of a first conductivity type; forming a first conductor layer on the resulting structure, and performing a third photomask process to pattern the first conductor layer, forming a pattern on each island A source electrode and a drain electrode are respectively formed on the doped thin film of the first conductivity type and the doped region of the second conductivity type, and the lower electrode of the storage capacitor is formed on the substrate, and the third photomask In the process, the same photomask is used to pattern the doped film of the first conductivity type and the doped region of the second conductivity type under the first conductor layer, so that the source and the drain and the underlying The doped film of the first conductivity type or the doped region of the second conductivity type has the same pattern; a first dielectric layer and a second conductor layer are formed on the resulting structure, and a fourth photomask process is performed to The first dielectric layer and the second conductor layer are patterned, and a stacked structure of a gate insulating layer and a gate is formed on the polysilicon layer of each island structure, and at the same time, at a position corresponding to the lower electrode of the storage capacitor forming a storage capacitor dielectric layer and an upper electrode; forming a protective layer on the resultant structure, and performing a fifth photomask process to pattern the protective layer to form an upper electrode exposing each of said source and drain electrodes and the storage capacitor openings; forming a conductive layer on the resulting structure, and performing a sixth photomask process to pattern the conductive layer to form wires and pixel electrodes.

根据本发明的薄膜晶体管阵列及其驱动电路结构，适于配置于一基板上，该结构包括：多个扫描配线，配置于该基板上；多个信号配线，配置于该基板上；多个薄膜晶体管，该些薄膜晶体管是藉由该些扫描配线与该些信号配线驱动，每一该些薄膜晶体管包括：一多晶硅层，配置于该基板上；一源极/漏极，配置于该多晶硅上方；一N+掺杂薄膜，配置于该多晶硅层与该源极/漏极之间；一栅极，配置于该多晶硅上方；一栅极绝缘层，配置于该多晶硅与该栅极之间；多个像素电极，对应于该些薄膜晶体管配置：多个存储电容，对应于该些像素电极配置；以及多个互补金属氧化物半导体，每一该些互补金属氧化物半导体包括一N型金属氧化物半导体与一P型金属氧化物半导体，所述栅极绝缘层包括：一第一介电层；以及一第二介电层，配置于该第一介电层上。The thin film transistor array and its driving circuit structure according to the present invention are suitable for being arranged on a substrate, and the structure includes: a plurality of scanning wirings arranged on the substrate; a plurality of signal wirings arranged on the substrate; a thin film transistor, the thin film transistors are driven by the scanning wirings and the signal wirings, each of the thin film transistors includes: a polysilicon layer configured on the substrate; a source/drain configured above the polysilicon; an N+ doped film disposed between the polysilicon layer and the source/drain; a gate disposed above the polysilicon; a gate insulating layer disposed between the polysilicon and the gate Between; a plurality of pixel electrodes, corresponding to the thin film transistor configurations: a plurality of storage capacitors, corresponding to the pixel electrode configurations; and a plurality of complementary metal oxide semiconductors, each of which includes a N Type metal oxide semiconductor and a P type metal oxide semiconductor, the gate insulation layer includes: a first dielectric layer; and a second dielectric layer, configured on the first dielectric layer.

根据本发明的薄膜晶体管阵列及其驱动电路结构，适于配置于一基板上，其主要是由多个扫描配线、多个信号配线、多个薄膜晶体管、多个像素电极、多个存储电容以及多个互补金氧半晶体管所构成。According to the thin film transistor array and its drive circuit structure of the present invention, it is suitable to be arranged on a substrate, which is mainly composed of a plurality of scanning wiring, a plurality of signal wiring, a plurality of thin film transistors, a plurality of pixel electrodes, a plurality of memory Capacitors and a plurality of complementary metal-oxide-semiconductor transistors.

本发明中，薄膜晶体管主要是由一多晶硅层、一源极/漏极、一N+掺杂薄膜、一栅极以及一栅极绝缘层。其中，多晶硅层是配置于基板上，源极/漏极配置于多晶硅上方，N+掺杂薄膜配置于多晶硅层与源极/漏极之间，栅极配置于多晶硅上方，而栅极绝缘层则配置于多晶硅与栅极之间。In the present invention, the thin film transistor is mainly composed of a polysilicon layer, a source/drain, an N+ doped film, a gate and a gate insulating layer. Among them, the polysilicon layer is arranged on the substrate, the source/drain is arranged above the polysilicon, the N+ doped thin film is arranged between the polysilicon layer and the source/drain, the gate is arranged above the polysilicon, and the gate insulating layer is It is arranged between the polysilicon and the gate.

本发明中，像素电极以及存储电容是对应于薄膜晶体管而配置于基板上。In the present invention, the pixel electrodes and storage capacitors are arranged on the substrate corresponding to the thin film transistors.

本发明中，互补金属氧化物半导体是由一N型金属氧化物半导体与一P型金属氧化物半导体所构成。N型金属氧化物半导体主要是由一多晶硅层、一源极/漏极、一N+掺杂薄膜、一栅极以及一栅极绝缘层所构成。其中，多晶硅层配置于基板上，源极/漏极配置于多晶硅上方，N+掺杂薄膜配置于多晶硅与源极/漏极之间，栅极配置于多晶硅上方，而栅极绝缘层则配置于多晶硅层与栅极之间。In the present invention, the complementary metal oxide semiconductor is composed of an N-type metal oxide semiconductor and a P-type metal oxide semiconductor. The NMOS is mainly composed of a polysilicon layer, a source/drain, an N+ doped film, a gate and a gate insulating layer. Among them, the polysilicon layer is arranged on the substrate, the source/drain is arranged above the polysilicon, the N+ doped thin film is arranged between the polysilicon and the source/drain, the gate is arranged above the polysilicon, and the gate insulating layer is arranged on the between the polysilicon layer and the gate.

此外，N型金属氧化物半导体中，栅极与源极/漏极之间的多晶硅层内更包括一N-掺杂区域。In addition, in the NMOS, the polysilicon layer between the gate and the source/drain further includes an N-doped region.

P型金属氧化物半导体主要是由一多晶硅层、一源极/漏极、一P+掺杂薄膜、一栅极以及一栅极绝缘层所构成。其中，多晶硅层配置于基板上，源极/漏极配置于多晶硅上方，P+掺杂薄膜配置于多晶硅与源极/漏极之间，栅极配置于多晶硅上方，而栅极绝缘层则配置于多晶硅层与栅极之间。The P-type metal oxide semiconductor is mainly composed of a polysilicon layer, a source/drain, a P+ doped film, a gate and a gate insulating layer. Among them, the polysilicon layer is arranged on the substrate, the source/drain is arranged above the polysilicon, the P+ doped film is arranged between the polysilicon and the source/drain, the gate is arranged above the polysilicon, and the gate insulating layer is arranged on the between the polysilicon layer and the gate.

上述栅极绝缘层例如是由至少一第一介电层所构成，其中，第一介电层的材料例如为氧化硅、氮化硅、含氢的介电层等。此外，栅极绝缘层亦可由至少一第一介电层以及一第二介电层构成，其中，第一介电层的材料包括氧化硅、氮化硅、含氢的介电层等，而第二介电层的材料例如为一感光性树脂。The above-mentioned gate insulating layer is composed of at least one first dielectric layer, wherein the material of the first dielectric layer is, for example, silicon oxide, silicon nitride, a hydrogen-containing dielectric layer, and the like. In addition, the gate insulating layer may also be composed of at least a first dielectric layer and a second dielectric layer, wherein the material of the first dielectric layer includes silicon oxide, silicon nitride, a hydrogen-containing dielectric layer, etc., and The material of the second dielectric layer is, for example, a photosensitive resin.

本发明中，栅极的材料例如为铝/钼、铝/钛等，源极/漏极的材料例如为铝/钼、钼等。In the present invention, the material of the gate is, for example, aluminum/molybdenum, aluminum/titanium, etc., and the material of the source/drain is, for example, aluminum/molybdenum, molybdenum, etc.

针对穿透式面板而言，导体层的材料可选用氧化铟锡等透明的导体。针对反射式面板而言，导体层的材料可以选用金属等具有良好反射特性的材料。此外，以反射式面板为例，导体层(通常为具有良好反射能力的金属)下方保护层的表面例如一凹凸的表面，以增进导体层反射光线的效果。For the transmissive panel, the material of the conductor layer can be a transparent conductor such as indium tin oxide. For the reflective panel, the material of the conductor layer can be selected from materials with good reflective properties such as metal. In addition, taking the reflective panel as an example, the surface of the protective layer under the conductive layer (usually a metal with good reflective ability) is for example a concave-convex surface, so as to enhance the light reflection effect of the conductive layer.

为让本发明的上述目的、特征、和优点能更明显易懂，特举一优选实施例，并配合所附图式，作详细说明如下。In order to make the above objects, features, and advantages of the present invention more comprehensible, a preferred embodiment will be described in detail as follows in conjunction with the accompanying drawings.

附图说明Description of drawings

图1(A)至图1(H)为已有薄膜晶体管阵列以及驱动电路制造工艺的剖面图；1(A) to 1(H) are cross-sectional views of the manufacturing process of the existing thin film transistor array and driving circuit;

图2为已有薄膜晶体管阵列以及驱动电路的制作流程图；Fig. 2 is the fabrication flowchart of existing thin film transistor array and drive circuit;

图3(A)至图3(I)为依照本发明一优选实施例薄膜晶体管阵列以及驱动电路制造工艺的剖面图；3(A) to FIG. 3(I) are cross-sectional views of a thin film transistor array and a driving circuit manufacturing process according to a preferred embodiment of the present invention;

图4为依照本发明一优选实施例薄膜晶体管阵列以及驱动电路的制作流程图；FIG. 4 is a flow chart of manufacturing a thin film transistor array and a driving circuit according to a preferred embodiment of the present invention;

图5为依照本发明一优选实施例互补金属氧化物半导体(CMOS)的布局(layout)示意图；以及FIG. 5 is a schematic layout diagram of a complementary metal oxide semiconductor (CMOS) according to a preferred embodiment of the present invention; and

图6为依照本发明一优选实施例像素的布局示意图。FIG. 6 is a schematic diagram of a pixel layout according to a preferred embodiment of the present invention.

具体实施方式Detailed ways

图3(A)至图3(I)为依照本发明一优选实施例薄膜晶体管阵列以及驱动电路制造工艺的剖面图。请参照图3(A)，首先提供一基板300，并依序于基板300上形成一多晶硅层以及一N+掺杂薄膜，接着一第一道光掩模工艺(Mask 1)定义上述的多晶硅层以及N+掺杂薄膜，以形成多个由多晶硅层302a、302b、302c以及N+掺杂薄膜304a、304b、304c堆叠而成的岛状结构。3(A) to 3(I) are cross-sectional views of the manufacturing process of the thin film transistor array and the driving circuit according to a preferred embodiment of the present invention. Please refer to FIG. 3(A), first provide asubstrate 300, and sequentially form a polysilicon layer and an N+ doped film on thesubstrate 300, and then a first photomask process (Mask 1) defines the above-mentioned polysilicon layer and N+ doped thin films to form a plurality of island structures formed by stackingpolysilicon layers 302a, 302b, 302c and N+ dopedthin films 304a, 304b, 304c.

上述多晶硅层的形成方式例如是先形成一非晶硅薄膜(a-Si)于基板300上，接着再对此非晶硅层进行一准分子激光退火工艺(Excimer LaserAnnealing，ELA)，以使得非晶硅层结晶成为多晶硅层。而N+掺杂薄膜的形成方法例如是直接以化学气相沉积的方式沉积一具有N+掺杂的非晶硅薄膜于基板300上；或是先形成一非晶硅薄膜于基板300上，的后再对此非晶硅进行N型离子掺杂，以形成N+掺杂薄膜。The above-mentioned polysilicon layer is formed by, for example, first forming an amorphous silicon film (a-Si) on thesubstrate 300, and then performing an Excimer Laser Annealing (ELA) process on the amorphous silicon layer, so that the non-crystalline The crystalline silicon layer is crystallized into a polysilicon layer. The formation method of N+ doped film is, for example, directly depositing an N+ doped amorphous silicon film on thesubstrate 300 by chemical vapor deposition; or first forming an amorphous silicon film on thesubstrate 300, and then The amorphous silicon is doped with N-type ions to form an N+ doped film.

岛状结构302a是用以形成薄膜晶体管(TFT)，而岛状结构302b以及岛状结构302c是用以形成驱动电路，如互补金属氧化物半导体(CMOS)。由于岛状结构302a是用以形成薄膜晶体管，故岛状结构302a例如是以阵列方式排列于基板300上，而岛状结构302b以及岛状结构302c则例如是配置于基板300的边缘或其他区域。Theisland structure 302a is used to form a thin film transistor (TFT), and theisland structure 302b and theisland structure 302c are used to form a driving circuit, such as a complementary metal oxide semiconductor (CMOS). Since theisland structure 302a is used to form a thin film transistor, theisland structure 302a is, for example, arranged in an array on thesubstrate 300, while theisland structure 302b and theisland structure 302c are, for example, disposed on the edge or other regions of thesubstrate 300. .

接着请参照图3(B)与图3(C)，以第二道光掩模工艺(Mask 2)决定P+掺杂区域306的位置，藉由P型离子的掺杂的动作而于N+掺杂薄膜304b的全部区域(如图3(B)所绘示)或是部份区域(如图3(C)所绘示)中形成P+掺杂区域306。Next, please refer to FIG. 3(B) and FIG. 3(C), the position of the P+ dopedregion 306 is determined by the second photomask process (Mask 2), and the N+ is doped by the doping action of P-type ions The P+ dopedregion 306 is formed in the entire region (as shown in FIG. 3(B) ) or a part of the region (as shown in FIG. 3(C )) of thethin film 304b.

接着请参照图3(D)，于基板300上形成一第一导体层(图中未绘示)，接着再以第三道光掩模工艺(Mask 3)定义上述的第一导体层，以于N+掺杂薄膜304a、P+掺杂区域306以及N+掺杂薄膜304c上分别形成源极/漏极308a、308b、308c。并于基板300的适当位置上形成存储电容器的下电极310。Then please refer to FIG. 3(D), a first conductor layer (not shown in the figure) is formed on thesubstrate 300, and then the third photomask process (Mask 3) is used to define the above-mentioned first conductor layer, so as to Source/drain electrodes 308a, 308b, 308c are respectively formed on the N+ dopedfilm 304a, the P+ dopedregion 306 and the N+ dopedfilm 304c. And thelower electrode 310 of the storage capacitor is formed on a proper position of thesubstrate 300 .

然而，在定义第一导体层时，第三道光掩模工艺可以同时定义位于第一导体层下方的N+掺杂薄膜304a、304b、304c或是P+掺杂区域306(图3(B)、3(C)所示)。因此，源极/漏极308a会与其下的N+掺杂薄膜304a具有相同的图案；源极/漏极308b会与其下的P+掺杂区域306具有相同的图案；而源极/漏极308c也会与其下的N+掺杂薄膜304c具有相同的图案。However, when defining the first conductor layer, the third photomask process can simultaneously define the N+ dopedfilms 304a, 304b, 304c or the P+ dopedregions 306 located below the first conductor layer (Fig. 3(B), 3 (C) shown). Therefore, the source/drain 308a will have the same pattern as the underlying N+ dopedfilm 304a; the source/drain 308b will have the same pattern as the underlying P+ dopedregion 306; and the source/drain 308c will also have the same pattern. will have the same pattern as the underlying N+ dopedfilm 304c.

接着请参照图3(E)，于基板300上依序形成一第一介电层(图中未绘示)以及一第二导体层(图中未绘示)，接着以第四道光掩模工艺(Mask 4)定义上述介电层以及第二导体层，以于多晶硅层302a、302b、302c上分别形成栅极绝缘层312a、312b、312c与栅极314a、314b、314c的堆叠结构。Next, please refer to FIG. 3(E), a first dielectric layer (not shown in the figure) and a second conductor layer (not shown in the figure) are sequentially formed on thesubstrate 300, and then a fourth photomask The process (Mask 4) defines the above-mentioned dielectric layer and the second conductive layer to form stacked structures ofgate insulating layers 312a, 312b, 312c andgates 314a, 314b, 314c on thepolysilicon layers 302a, 302b, 302c respectively.

本实施例中，栅极绝缘层312a、312b、312c形成之后例如可对栅极绝缘层312a、312b、312c进行一快速热工艺(Rapid Thermal Process，RTP)，以使得栅极绝缘层312a、312b、312c的品质更为提升。In this embodiment, after thegate insulating layers 312a, 312b, 312c are formed, for example, a rapid thermal process (Rapid Thermal Process, RTP) can be performed on thegate insulating layers 312a, 312b, 312c, so that thegate insulating layers 312a, 312b , The quality of 312c is further improved.

栅极绝缘层312a、312b、312c例如是由至少一第一介电层所构成，其中第一介电层的材料例如为氧化硅、氮化硅、含氢的介电层等。而栅极绝缘层312a、312b、312c亦可由至少一第一介电层以及一第二介电层构成，其中第一介电层的材料包括氧化硅、氮化硅、含氢的介电层等，而第二介电层的材料例如为一感光性树脂。此外，栅极314a、314b、314c的材料例如为铝/钼、铝/钛等，而源极/漏极308a、308b、308c的材料例如为铝/钼、钼等。Thegate insulating layers 312 a , 312 b , and 312 c are, for example, composed of at least one first dielectric layer, wherein the material of the first dielectric layer is, for example, silicon oxide, silicon nitride, a hydrogen-containing dielectric layer, and the like. Thegate insulating layers 312a, 312b, and 312c can also be composed of at least one first dielectric layer and a second dielectric layer, wherein the material of the first dielectric layer includes silicon oxide, silicon nitride, and a hydrogen-containing dielectric layer. etc., and the material of the second dielectric layer is, for example, a photosensitive resin. In addition, the materials of thegates 314a, 314b, 314c are, for example, aluminum/molybdenum, aluminum/titanium, etc., while the materials of the source/drain electrodes 308a, 308b, 308c are, for example, aluminum/molybdenum, molybdenum, etc.

同样请参照图3(E)，第四道光掩模工艺(Mask 4)中会于下电极310上形成一介电层316以及一上电极318，下电极310、介电层316以及上电极318即构成一存储电容器。此外，第四道光掩模工艺(Mask 4)中会于基板300的适当位置上形成介电层320以及配线322的堆叠结构。Please also refer to FIG. 3(E), in the fourth photomask process (Mask 4), adielectric layer 316 and anupper electrode 318 will be formed on thelower electrode 310, thelower electrode 310, thedielectric layer 316 and theupper electrode 318 That is, a storage capacitor is formed. In addition, in the fourth photomask process (Mask 4), a stacked structure of thedielectric layer 320 and thewiring 322 will be formed on a proper position of thesubstrate 300.

然而，熟习该项技术的应能轻易理解栅极314a、314b、314c与源极/漏极308a、308b、308c的制作顺序可因应制造工艺而有所调整。也就是，本实施例中并不限定源极/漏极308a、308b、308c以及栅极314a、314b、314c的制作顺序。However, those skilled in the art should easily understand that the fabrication sequence of thegates 314a, 314b, 314c and the source/drains 308a, 308b, 308c can be adjusted according to the fabrication process. That is, in this embodiment, the fabrication sequence of the source/drain 308a, 308b, 308c and thegate 314a, 314b, 314c is not limited.

接着请参照图3(F)，形成一保护层324于基板300上，接着再以第五道光掩模工艺(Mask 5)定义保护层324，以决定保护层324的图案。保护层324中例如具有开口326a、326b、326c、326d、326e。其中，开口326a是用以将源极/漏极308a暴露，开口326b是用以将源极/漏极308b暴露，开口326c是用以将源极/漏极308c暴露，开口326d是用以将存储电容器的上电极318暴露，而开口326e是用以将配线322暴露。3(F), aprotective layer 324 is formed on thesubstrate 300, and then the fifth photomask process (Mask 5) is used to define theprotective layer 324 to determine the pattern of theprotective layer 324. For example, theprotective layer 324 hasopenings 326 a , 326 b , 326 c , 326 d , and 326 e therein. Wherein, theopening 326a is used to expose the source/drain 308a, theopening 326b is used to expose the source/drain 308b, theopening 326c is used to expose the source/drain 308c, and theopening 326d is used to expose Theupper electrode 318 of the storage capacitor is exposed, and theopening 326e is used to expose thewiring 322 .

接着请参照图3(G)，在以第五道光掩模工艺(Mask 5)定义保护层324之后，接着形成一导电层(图中未绘示)于基板300上，此导电层通常是氧化铟锡等透明材料。最后再以第六道光掩模工艺(Mask 6)定义上述的导电层，以形成导线328以及像素电极330。Then please refer to FIG. 3(G), after defining theprotective layer 324 with the fifth photomask process (Mask 5), a conductive layer (not shown in the figure) is then formed on thesubstrate 300. This conductive layer is usually oxidized Indium tin and other transparent materials. Finally, the above-mentioned conductive layer is defined by the sixth photomask process (Mask 6) to form thewire 328 and thepixel electrode 330.

接着请参照图3(H)及图3(I)，其绘示与图3(F)及3(G)类似，为其差异在于一为穿透式面板(图3(H)及图3(I))，而另一为反射式面板(图3(F)及图3(G))。图3(H)及图3(I)中的保护层324具有一凹凸表面332，且配置于凹凸表面332上的像素电极334例如是选用一些具有良好效果的导体。藉由保护层324上的凹凸表面332将可增进像素电极334(反射电极)反射光线的效果。Then please refer to Fig. 3(H) and Fig. 3(I), which are similar to Fig. 3(F) and 3(G), except that one is a penetrating panel (Fig. 3(H) and Fig. (I)), and the other is a reflective panel (Fig. 3(F) and Fig. 3(G)). Theprotection layer 324 in FIG. 3(H) and FIG. 3(I) has a concave-convex surface 332, and thepixel electrodes 334 disposed on the concave-convex surface 332 are, for example, selected conductors with good effects. The light reflection effect of the pixel electrode 334 (reflective electrode) can be enhanced by the concave-convex surface 332 on theprotective layer 324 .

接着请同时参照图3(G)以及图3(I)，由图3(G)以及图3(I)左侧可以得知，多晶硅层302c、N+掺杂薄膜304c、源极/漏极308c、栅极绝缘层312c以及栅极314c是构成一N型金属氧化物半导体(NMOS)。多晶硅层302b、P+掺杂薄膜306、源极/漏极308b、栅极绝缘层312b以及栅极314b是构成一P型金属氧化物半导体(PMOS)。而由上述N型金属氧化物半导体(NMOS)以及P型金属氧化物半导体(PMOS)即可构成一互补金属氧化物半导体(CMOS)，此互补金属氧化物半导体于面板上所扮演的角色为一内藏的驱动电路，用以驱动图3(G)以及图3(I)右侧薄膜晶体管，进而控制像素的显示。Then please refer to FIG. 3(G) and FIG. 3(I) at the same time. From the left side of FIG. 3(G) and FIG. , thegate insulating layer 312c and thegate 314c constitute an N-type metal oxide semiconductor (NMOS). Thepolysilicon layer 302b, the P+ dopedthin film 306, the source/drain 308b, thegate insulating layer 312b and thegate 314b constitute a P-type metal oxide semiconductor (PMOS). A complementary metal oxide semiconductor (CMOS) can be formed by the above-mentioned N-type metal oxide semiconductor (NMOS) and P-type metal oxide semiconductor (PMOS). The role played by the complementary metal oxide semiconductor on the panel is a The built-in driving circuit is used to drive the thin film transistors on the right side of FIG. 3(G) and FIG. 3(I), and then control the display of the pixels.

由图3(G)以及图3(I)右侧可以得知，多晶硅层302a、N+掺杂薄膜304a、源极/漏极308a、栅极绝缘层312a以及栅极314a是构成一多晶硅型态的薄膜晶体管。其中，薄膜晶体管是藉由上述互补金属氧化物半导体的驱动来控制写入像素电极330或是像素电极334中的数据。3(G) and the right side of FIG. 3(I), it can be seen that thepolysilicon layer 302a, the N+ dopedfilm 304a, the source/drain 308a, thegate insulating layer 312a and thegate 314a constitute a polysilicon type thin film transistors. Wherein, the thin film transistor controls the data written into thepixel electrode 330 or thepixel electrode 334 by driving the CMOS.

图4绘示为依照本发明一优选实施例薄膜晶体管阵列以及驱动电路的制作流程图。请参照图4，本实施例薄膜晶体管阵列以及驱动电路的制作流程主要是由定义多晶硅层S400、定义P+掺杂区域S402、定义源极/漏极&N+掺杂薄膜回蚀&存储电容的下电极S404、定义栅极&存储电容的上电极S406、定义保护层的图案S408，以及定义像素电极&导线的图案S410等步骤所构成。由S400至S410总共需要六道光掩模工艺。然而，若在驱动电路中的N型金属氧化物半导体(NMOS)中制作N-掺杂区域(轻掺杂区域)的话，则需要再增加一道光掩模工艺。FIG. 4 is a flow chart illustrating the fabrication of a thin film transistor array and a driving circuit according to a preferred embodiment of the present invention. Please refer to FIG. 4, the manufacturing process of the thin film transistor array and the driving circuit in this embodiment is mainly defined by defining the polysilicon layer S400, defining the P+ doped region S402, defining the source/drain & N+ doped film etch back & the lower electrode of the storage capacitor S404, defining the upper electrode of the gate & storage capacitor S406, defining the pattern of the protective layer S408, and defining the pattern of the pixel electrode & wire S410. A total of six photomask processes are required from S400 to S410 . However, if an N-doped region (lightly doped region) is formed in the N-type metal oxide semiconductor (NMOS) in the driving circuit, another photomask process needs to be added.

图5绘示为依照本发明一优选实施例驱动电路中互补金属氧化物半导体的布局示意图。请参照图5，分别施加电压Vin、Vdd以及Vss于接点504、506以及508上，由于接点504与栅极500及栅极502电性连接，因此施加于接点504上的Vin可用以控制N型金属氧化物半导体与P型金属氧化物半导体通道层的导通与否，而N型金属氧化物半导体与P型金属氧化物半导体通道层的导通与否则会直接影响到互补金属氧化物半导体由接点510的输出Vout，而由接点510输出的Vout值可能为Vdd或是Vss其中之一。FIG. 5 is a schematic diagram of a CMOS layout in a driving circuit according to a preferred embodiment of the present invention. Please refer to FIG. 5, apply voltages Vin, Vdd, and Vss to thecontacts 504, 506, and 508 respectively. Since thecontact 504 is electrically connected to thegate 500 and thegate 502, Vin applied to thecontact 504 can be used to control the N-type Whether the conduction of the metal oxide semiconductor and the P-type metal oxide semiconductor channel layer is conducted, and whether the conduction of the N-type metal oxide semiconductor and the P-type metal oxide semiconductor channel layer will directly affect the complementary metal oxide semiconductor. The output Vout of thecontact 510, and the value of Vout output by thecontact 510 may be one of Vdd or Vss.

然而，图5中所绘示的驱动电路仅为一的互补金属氧化物半导体单元的布局示意图，而熟习该项技术的应能了解面板上的驱动电路可由上述的互补金属氧化物半导体搭配其他电路或元件而构成，以驱动面板上的像素阵列。However, the driving circuit shown in FIG. 5 is only a schematic layout diagram of a CMOS unit, and those who are familiar with this technology should understand that the driving circuit on the panel can be composed of the above-mentioned CMOS with other circuits. or elements to drive the pixel array on the panel.

图6绘示为依照本发明一优选实施例像素的布局示意图。请参照图6，由上述图3(A)至图3(I)的六道光掩模工艺所制作出的像素结构主要包括一扫描配线600、一信号配线602、一薄膜晶体管604、一存储电容器606以及一像素电极330(334)所构成。其中，薄膜晶体管604主要是由多晶硅层302a、栅极314a、N+掺杂薄膜304a以及源极/漏极308a所构成。此外，扫描配线600与薄膜晶体管604中的栅极314a连接，以控制其下通道层(多晶硅层302a)的开关，而所欲写入的数据则是经由信号配线602传输以及薄膜晶体管604的控制而写入像素电极330(334)中。FIG. 6 is a schematic diagram of a pixel layout according to a preferred embodiment of the present invention. Please refer to FIG. 6 , the pixel structure produced by the six photomask processes in FIG. 3(A) to FIG. 3(I) mainly includes ascanning wiring 600, asignal wiring 602, athin film transistor 604, a Thestorage capacitor 606 and a pixel electrode 330 (334) are formed. Wherein, theTFT 604 is mainly composed of apolysilicon layer 302a, agate 314a, an N+ dopedfilm 304a, and a source/drain 308a. In addition, thescan wiring 600 is connected to thegate 314a of thethin film transistor 604 to control the switch of the lower channel layer (polysilicon layer 302a), and the data to be written is transmitted through thesignal wiring 602 and thethin film transistor 604 It is written into the pixel electrode 330 (334) under the control.

综上所述，本发明薄膜晶体管阵列及其驱动电路结构至少具有下列优点：In summary, the thin film transistor array and its driving circuit structure of the present invention have at least the following advantages:

1.本发明薄膜晶体管阵列及其驱动电路结构，仅需六道光掩模即可完成，使其制作成本大幅降低。1. The thin film transistor array and its driving circuit structure of the present invention can be completed with only six photomasks, so that the manufacturing cost is greatly reduced.

2.本发明薄膜晶体管阵列及其驱动电路结构，其所使用的光掩模数目较少，使得面板制作的时间缩短许多。2. The thin film transistor array and its drive circuit structure of the present invention use fewer photomasks, which greatly shortens the time for panel fabrication.

3.本发明薄膜晶体管阵列及其驱动电路结构，其所使用的光掩模数目较少，有助于面板优良率的提升。3. The thin film transistor array and its driving circuit structure of the present invention use fewer photomasks, which contributes to the improvement of panel yield.

虽然本发明已以一优选实施例揭露如上，然其并非用以限定本发明。Although the present invention has been disclosed above with a preferred embodiment, it is not intended to limit the present invention.