CA2236181A1 - Multiple electronic purse parking meter - Google Patents

Description

MULTIPLE ELECTRONIC PURSE PARKING METER
BACKGROUND OF THE IhTVENTION
Field of the Invention This invention is concerned with electronic purse displays (EPD) and in particular with a multiple electronic purse paJ-king meter.
Desc:ri~tion of the Related Art There are some problems associated with the utilization of coin vending machines, including mechanical parking meters. ( 1 ) Motorists have to make sure they have the right change before buying parking time. (2) The person collecting money from the meter must walk to each meter and manually empty the coins. (3) Coin acceyting parking meters are snore vulnerable; to vandalism.
In the past, unattended vending or dispensing machines were generally limited to relatively inexpensive items. The expansion of the vending machines to more sophisticated and higher priced articles, usually exceeds the average consumer's 1 S pocket or purse change. An limited solution has been provided by the introduction of a bill changer in the proximity of the coin operated vending machines. Still, there are problems that affect both the potential purchaser and the owner of a vending machine, like for example the cost of a bill changer located in the proximity of a vending machine, potential loss by the use of counteri:eit currency, and security concerns associated with unattended vending machine:>.
Consumers are becoming more comfortable making unattended purchases with non-currency devices like a card of some type having a Personal Identification Number (PIN) which allows fir a faster paced lifestyle with the potential of 24-hour acce:es. Such access is becoming common for unattended bank teller machines, public transportation systems including parking meters, and in many other cases.
Electronic parking meters accepting credit cards avoid the above mentioned inconveniencies because the accumulated parking time and sales can be stored within electronic memory. Transaction systems, including parking meters, using vend disposable or reprogrammable; pre-paid card:>, axe presently widely used. The user may vary the amount of time ipurchased on the meter by using his debit card.
An auditor is used to program the parking meter and /or to extract data from the parking meter using a hand-held device directly connected to the parking meter.
Integrated circuit (IC) cards, or smart cards, have a significant advantage over magnetic stripe cards as they ~~re more secure; especially when used with stand alone terminals which are not connected to the remote central computer during each transaction. The memory size of the smart c~~rd is not big enough therefore, another device having a much larger memory than the smart card is dedicated to interface with the s mart card. To change the memory size of this additional device, or certain other features of the unit, typically requires redesigning the device. Generally, stand alone terminals can accept only one kind of smart card which can be identified by the terminal. At some point in tune, the card will be discharged and needs to be repla ced/recharged.
US 4,880,097 issued disclosing a park card having a memory to be used with an electronic parking meter. Coins, paper bills, special park cards are accepted by this parking meter. A hand-held auditor can be used with the parking meter through a cable; or an infrared transmission system for gathering data from the parking meter.
The ;~~arking meter uses one processor and does not include a card security access mod~.~le.
US 5,614,892 issued disclosing an auditing system capable of processing and storing data derived from a vending machine, or a parking meter. A purchaser can vary the time purchased on the meter either by using his debit card or by inserting coins. This parking meter usea one processor and an "Alcatel" card receptor mechanism for reading an IC card.
US 5,500517 issued disclosing a hams held device for collecting data recorded on a smart card terminal and transferring same to a remote computer. The prepaid money value can be subtracted from the card, or can be charged to the card owner's account. This smart card terniinal uses one processor and no description is provided for the smart card security access module.
There are problems associated with mechanical meters, as well as electronic meters that cannot support internal security modules. Non-electronic-purse parking meters can typically accept simple, logic or memory cards which offer lower security.

Users are limited in having cash tied up in a dedicated card that can only be spent on parking. Messaging and instn:~ctions are limited and not easily understood from simple 7 segment displays.
Accordingly, there is a need for a cashless, multiple electronic purse pay and display machine using credit cards and displaying easy-to-read information.
Due to the large inventory of existing coin accepting machines, it is an addit~.onal need for retrofitting any improvements to the devices within the existing coin machine structures.
SUMMARY OF THE INVENTION
The invention solves the above problems by providing an electronic parking meter which uses a plurality of credit cards.
The parking meter with multiple-electronic-purse (Mufti-E-Purse) of the present invention consists of a Card Reader Module (CRM), a Graphic Display Module (GDM) and a Motherboard Board Module (MBM).
It is an object of the present invention to provide a card reader module including a Security Access Module (SAM) capable of validating a plurality of ISO
compliant Storage Value Cards. In the case when one card is expired or has defective contacts, another credit card rnay be used to purchase parking time.
It is another object of the present invention to provide a fully electronic drop-in replacement module which fits existing MacKay or other industry standard meter casing models, or to be used with any on-street Electronic Purse Devices (EPD) like electronic parking meters (EP1VI), pay and display machines (PDM), or electronic purse; terminals (EPT).
It is still another objecvt of the present invention to use a custom designed, intelligent mixed-mode graphics and icon based LCD module.
It is a further object of the present invention to provide a Mufti-E-Purse meter which supports three different memory areas: one for primary data, another for a mirror image of the current data being collected, and a third axea which holds the previous collection data.
Advantageously, the custom designed ASIC within the master microprocessor prov ides a great deal of functionality. While not all the functions are necessarily used, their existence allows for possible upgrades and improvements without major re-engineering.
BRII.F DESCRIPTION OF 'THE DRAWINGS
The present invention will be better understood from the following description with reference to the drawings where:
Figure 1 is a block diagram of the electronic parking meter of the present invention;
Figure 2 is a front viev~~ of the GDM and the MBM modules of the EPM;
Figure 3 is an exploded view of the housing of the CRM of the EPM;
Figure 4 is a block dia~;ram of the MBM and of the GDM;
Figure 5 is a view of th.e front glass of the LCD display viewed from the user side;
Figure 6 is a view of floe back glass of the LCD display viewed from the curbside;
Figure 7 is an exploded view of the LCD display;
Figure 8 is a front view of the back glass of the LCD display displaying icons;
Figure 9 is a front view of the front glass of the LCD display displaying graplucs and icons;
Figure 10 is electrical diagram of the card reader overcurrent and over voltage monitor circuitry;
Figure 11 is a map representing of the main processor memory and the flash memory;
Figure 12 is a functional block diagram of the EPM;
Figure 13 is an block diagram of the smart card management according to the invention;
Figure 14 is a block diagram of the CRM overcurrent monitor protection circuit;
Figure 15 is a block diagram of the event management according to the present invention;

Figure 16 is an electrical diagram of the power management according to the invention; and Figure 17 is a chart showing the steps required to maintain a scrolling LCD
display.
DET~~ILED DESCRIPTION OF THE DRAWINGS
Figure 1 shows the three major components or modules, the card reader module (CRM) 40, the motherboard module (MBM) 30, and the intelligent graphic display module (GDM) 20. Module 30 comprises the operating system, the transaction records memory, a.tld the Security Access Modules (SAM).
As shown in Figure 2, the CRM 40 is connected to the MBM 30 via a 10 pin connector 14, while the GDM :ZO is connected to the MBM 30 via an 18 pin hardwired wishbone connector 12. The C'RM 40 accepts the customers cash card waking the GDM 20, which powers up the MBM 30, which in turn handles the smart card transaction. Once the customer has selected an appropriate amount of parking time, the MBM 30 sends a command sequence to the GDM 30 to handle the timing and display functions. When the meter stands idle the low power GDM 20 will continue to display messages while the rest of the meter is powered off. The CRM 40 and the MBM: 30 may be lumped together logically as their functions are intimately connected.
Figure 3 shows a card acceptor slot 16 for receiving the customer's smart card and a push-button switch (key) 47 is used to set parking time, accept a transaction, or confirm a split payment (payment from more than one cash card). All information is displayed on the graphic/icon I~CD display 1S and indicator LED's 72, 74 and (shown in Figure 6). The card acceptor slot 16 and push-button 47 are placed in such a manner that no modification to the existing MacKay MKV77 or other industry stand~~rd meter casings are necessary.
In a preferred embodiment, the three major components may use the following circuit boards:
CRM 40 : a 2 layer, 0.062 inch. thick, FR4 epoxy & glass, gold clad, over 1 ox.
copper;

MBM: 30 : a 2 layer, 0.062 inch thick, FR4 epoxy & glass, gold clad, over 1 ox.
copper;
GDM 20 : a 2-layer, 0.031 inch thick, FR4 epoxy & glass, gold clad, over 1 ox.
copper.
Figure 4 is a block diagram of the MBM and GDM. The intelligent graphic display module (GDM) 20 handles all of the timing and display functions within the parking meter. The GDM 20 is a custom designed module which includes a very low poweo microcontroller 22, an L,CD controller 21, a memory 24, a forward facing (user side) mixed-mode graphic and. icon based LC'.D display 25 with a backlight 26, and an icon based red/silver backglass~ indicator LCD 27 for the curbside. All timing functions are handled by a combination of hardware and software within the low power microcontroller 22.
Memory 24 is a 8192 byte low power serial IZC EEPROM is used to store LCD display messages, display scripts, meter configuration data and some smart card transz~ction data. Memory 24 communicates over a 2 wire IZC bus with both the graphic display microcontroller 24 and with the motherboard microprocessor 34, and is capable of storing 4 variable length, bit mapped messages which are hard coded at program load time. A total message length of approximately 100, 16 x 16 characters is possible. Display scripts, wlhich describe what and how messages are displayed on the L~~D display 15, are also sl;ored in this memory. The following is a simple display script example:
~ fast scroll message 3 (static display of time for 5 seconds) ~ slow scroll message 2 ~ repeat (i.e. go to beginning of script) ~EEPROM 8K Bytes Graphic Display Module Low Power IZC serial EEPROM
- 7.Sk Bytes 1,000,000 Write Cycles - O.Sk Bytes 10,000,000 Write Cycles The low power microcontroller 22 handles all LCD graphic display updates, real time clock/calendar and alarm functions, LED indicator functions, and is the driver for all icons on both the graphics display module 25 and the backglass 27. The single; chip microcontroller 22 has the following functions:
Low Power RISC CPU
Instruction Program Space Stored in OTP EPROM
192 bytes RAM
Watchdog, Power-up, Oscillator Start-up and Power-on Timers User Timer Modules ~ Timer 0 - 8 bit timer/counter with prescaler.
~ Timer 1 - 16 bit timer/c;ounter with prescaler. Driven by an external Xtal/Clock for a real time clock while the CPU is in sleep mode.
~ Timer 2 - 8 bit timer/counter with period register, prescaler, and postscaler ~ I/O Pins with 25 ma Sink/Source drive capability ~ IZC Serial Communications Port ~ Channel , 8 bit AD converter The LCD controller 21 is a very low power integrated circuit which functions as the LnD display 15 refresh driver. The controller contains 80 x 33 (2640) bits of display RAM: which provides two pages of display space. Each bit in a selected page of RAM
corre;~ponds to an individual pixel, bit on (1) = pixel on, bit off (0) =
pixel off. Paging allov~~s the system to draw th.e next screen of data completely before displaying it.
Control registers control display scrolling, blanking, paging, inverse video, and RAM
address control. A parallel port is used to interface the controller 21 to the graphic displ~~y microcontroller 22.
LCD Driver ( Recommended Seiko SED1526) 16 x 80(min) pixel display High speed onicroprocessor compatible R/W parallel lbus interface.
Dual display RAM with bank switching for smoother scrolls.

RTC Clock input 32KHzt'~

lFormat YY/MM/DD/l~-I/MM/SS, day of week, and leap year correction through year 2083 lE~esolution 1 second llnterface lzC bus Calendar .Jan l, 1984 to Dec 31, 2083 l:.atched clock Double buffered time clock to ensure accuracy.
.Alarm HH:MM:SS and DOW flexible wakeup alarm system Serial EEPROM 24 ( Recommended Microchip 24LC65-I/SM) Size 8kbytes 'Write cycles 1,000,000 and 10,000,000 for high endurance area (512 bytes) Est. Usage Display buffer (4x20x16x16/8=2560 bytes) Graphics display language (GDL) program store (<121 bytes) 'Visa Cash (<1600 bytes) lVon-volatile storage and additional display buffer (3912 bytes) Microcontroller 22 1 Recommended Microchip PIC 16LCxx) System Clock 4.OMHz l:nternal RAM 128 Bytes in LPM + 170 bytes in ROM/OTP 4K instructions 1:/0 22+

l:nternal timerst'~ Maintain RTC.

'Wake up LPM at up to 64Hz for screen/RTC
updates and PDO pulses IZC bus Data rates 100KBaud (min) - lMHz(max) LPM master reading i:rom EEPROM:

ti7KBaud (max) ASIC master with LPM, or EEPROM

A 20 bit programmable divide by n counter can provide adjustment for up to t0.5ppm accuracy from a 32KHz clock source.
z A flow the LPM to sleep betweew screen updates and PDO pulses. This is done to reduce total system power consumption.

The GDM 20 determines what to do based on a Graphic Display Language (GDL) scripts stored in a memory 24. The MBM 30 uses the IZC bus to program GDL
scripts and access the GDM 20 intenlal registers. A rivo-wire handshake is used to control access to the IZC bus. GDM 20 also maintains a real-time clock/calendar 28, with leap year correction through to the ;year 2083.
Placement - Two solid ;?4 AWG wire, 9-pin, 0.1" pitch, single line, herring bone connectors positioned in the bottom corners of the board on a 0.1" pitch. The GDM
pinout is arranged as shown below in Table 1.
SDOLTT Left Input Modulated IR serial data output (IR
Tx) SDIN Left OutputModulated IR serial data input (IR
Rx) VBA7~ Left Input Bab:ery voltage Left Input 3I5'J Supply GND Left Input Ground RESET Left Input Reset Normally high, stays low while reset button pressed p~()N Left OutputPovrer on Normally low ,47K pull-down., high to bring up SV power supply RightInput Analog input (Over current detect) $R RightInput Bus Request Normally low, high when requested BG RightOutputBus Grant Normally low, 47K pull-down., raised high when granted/ready.

SDA RightI/O IzC Data Normally high, 20K pull-up. Low when GDM in reset SCL Right1/0 I2C Clock Nomally high, 20K pull-up. Low when GDM in reset GDINT RightOutputGraphics Display Event Interrupt Normally low, 47K pull-down., remains high until reset by ASIfC-GDM command or power down request EXTIi~ITRightOutputPulse Detected External Interrupt Normally low, 47K pull-down., remain high until cleared by ASIfC-GDM command or power down request.

PDO RightOutputPulsed Detect Output Normally high, pulsed low for 120us at 64Hz rate.

S PDI RightInput Pulsed Detect Input GDM generates external event (EXTINT) if high when PDO low.

Table 1: Pin Description LCD DISPLAY
The EPM utilizes a custom designed GDM 20. As shown in Figures 5 and 6, GDM: 20 consists of a mixed-rr~ode LCD 15 with icons and graphics. The 16 x 80 pixel graphic forward facing display 25 is capable of displaying up to five 16 x 16 pixel chara~;,ters or ten 8 x 16 pixel cl';raracters at one time. Display 25 can scroll messages in at least two directions, or switch between static messages at a programmable rate.
Figures 8 and 9 show icons are used to indicate error conditions such as low battery, out of order, invalid coin, invalid card, and no parking. The rear side or curbside display 27 utilizes a dual color silver/red LCD. Icons like the international "no parking"
symbol or the word "EXPIRED" in one or more languages may be displayed.
The EPM utilizes a custom designed intelligent mixed-mode graphics 25 and icon based backlit LCD module 27. The GDM 20 also contains a real time clock and calendar 28 for system timing functions as well as an EEPROM module 24 used to store the LCD
messages and system configuration data.
The LCD display 15 is illustrated in Figure 7. The front LCD display 25 (user side) is a mixed-mode display utilizing both pixel and icon based graphics.
It's featwes include the following:

~ Graphic display area ( 14 mm x 43 mm viewable) capable of displaying graphics or text.
Examples as follows:
Graphics 1 screen of 16 x 80 pixels Symbols, pictures, etc.
Text 1 line of 5 16 x 16 pixel Chinese characters Text 1 line of 7 16 x 12 pixel English characters Text 2 lines of 10 8 x 8 pixel English characters ~ More independent controlled icons located above graphic display area may optionally be used to indicate the message like:
N~o Parking (English. character message) International No Parking (Character P with the symbol a over it) N~o Parking (Second language character message) ~ An LCD backlight 26 lights momentarily when a customer is interacting with the perking meter. It may be configured to operate only through a range of night time hours.
The curbside LCD module 27 is a dual color (red and silver) icon based display used to indicate for example:
~ N~o Parking with a flashing red international no parking symbol.
~ Time Expired with a flashing red "EXPIRED" in two or more languages.
~ The remaining background area in red (Rc;d Flag).
Backlight 26 Front glass 25 Color Blue/green Coverage 7,otal active area (min) Back glass 27 None LCD display 15 is a custom designed, intelligent, low power, LCD module featuring:

~ A 14 mm x 43 mm, 16 x 81) pixel graphic front display 25 capable of displaying five 16 x 16 pixel Chinese, English or other language characters. Icons for no perking symbol plus 2 no parking messages.
~ A red/silver curbside LCD 27 with an international no parking icon and the word "I?xpired" in at least two languages. The whole curbside display 27 can be set to Red (red flag).
~ A backlight 26 on graphic front display LCD 25.
~ A low power microcontrol:ler 22 with real time clock 28 and IZC
communications port.
~ An 8K byte serial EEPROPvI 24 capable of storing four 20 character messages.
~ A 2 LED indicator driver 2,8, 1 bicolor red/green LED 74 and 1 yellow LED
72.
LCDs F~°ont Glass:
Color Black/Transflective Operating Temp. -20°C to +85°C
Size Not to exceed GDM board size.
Fit in MacKay zinc without interference.
Active area 46 x. 25mm (min) Graphic area Resolution 16x80 Graphics size l4mm x 43mm (min) Icon Shape International Low Battery (Picture of a battery) International No Parking ('P' in a circle with a slash through it) Invalid Coin (Circle with an 'X' through it) Invalid Card (Rectangle with an 'X' through it) Size Recommended: 8mm x 43mm Placement See Figure 4a Back Glass:
Color Red/Silver reflective Operating Temp -20°C to +85°C
Size Not to exceed GDM board size.
Fit in MacKay zinc without interference.

Active area 46 x: 25mm (min) Icon shapes International no parking ('P' in a circle with a slash through it) Expired (English & Chinese linked as one icon.) Remaining background area LEDs LED's 72, 74, and 68 acre used to indicate park running time, time expired, and low battery. GDM 20 provides three high current outputs to flash LEDs 68, 72, 74 at rates of O.SHz, lHz, and 2Hz. One led is a bi-color red/green LEDs 68, 74, and the other is a yellow LED 72.
Three LED's (light emitting diodes) 68, 72, 74, are provided on the meter, two on th~~ front side and one on the backside. These status indicators are configured as follows:
LED Functions: LEI) 1 74 Front, right side of LCD display.
Dual color (red/green) 'super bright' LED
Time Expired Red Running Time Green LED 2 72 Front, left side of LCD display.
Single color (yellow) 'super bright' LED
Low Battery Yellow LED 3 68 Back, left side of LCD display.
Dual color (red/green) 'super bright' LED
Time Expired Red Running Time Green LED Flash Rate: Individual LED flash rates are preset at design time to one of the following rates:
Slow 0.5 Hz (2 Seconds) Medium 1.0 Hz (1 Seconds) Fast: 2.0 Hz (0.5 Seconds) LED Flash Time: The flash on time for any LED is fixed at 8 ms.
LED

Bi-color LED 74, 68 (Rec;ommended Toshiba TLRAG178,T0226AA

Kingbright 59RSGC-CA) Color Red and Green Intensity 4.SmA for 8ms regardless of flash rate or supply voltage Location As defined by zinc. . See Fig 5.

Number One on front, and one on back Yellow LED 72 (Rec;ommended Kingbright L93YT

Stanley HPY5066X) Color Yellow Intensity 4.SmA for 8ms regardless of flash rate or supply voltage Location As defined by zinc. . See Fig 5 Number One on front IR Transmitter 76 (Rec;ommended Siemens LD275-3 Siemens SFH41 ~-U) Color TBD nm Intensity TBD

Location As defined by zinc. . See Figure 5 Number One on front IR Rc;ceiver 76 (Recommended Siemens SFH20~) Color TBD nm Intensity TBD

Location As defined by zinc. . See Figure 5 Number One on front Card Reader Module (CRMI

The system is operational with a "smart card" and can optionally accept coins.
The c:.ser interface to the meter is either through the insertion of a card a coin, or through a simple push button I~'7. Either event will generate an interrupt signal to the continuously running low power microcontroller 28 on the GDM 20. When the card is inserted in the Card Reader Module 40, an interrupt is generated which wakes up the G:DM 20 before the MBM operating system, including the main processor 34 are powe.~ed up, for low power consumption. MBM 30 is powered up through a high-efficiE~ncy switching power supply 60. CRM 40 comprises an acceptor module 18 and attacl:.ed PCB. The CRM 40 includes a module connector readers, logic and protection circuitry 45. Module 40 becomes a sacrificial component for protecting the memory and the processors against high current drain and high voltage cause by intentional tampering/vandalisam.
The GDM 20 provides a variety of graphic displays due to the dedicated microprocessor 22 provided therefor. Graphics in two or more languages and a number of icons can be displayed on the GDM screen 15.
The card reader modulE; 40 consists of an acceptor module 18 with an attached printed circuit board containing a module connector and an overcurrent monitor circuitry 45. As shown in Fig. 10, the overcurrent monitor circuitry 45 includes an over-voltage crowbar protection diodes 44, and fusible resistors 48. Module 40 becornes a sacrificial component in order to protect the rest of the parking meter electronics from high voltage tampering and/or vandalism.
Input Interface The operator input interface consists of one momentary push-button switch t7 placed near the right, top area of the smart card slot.
Button Dimension: 12 nun. diameter Button Travel: 4 mrn. maximum The low cost card reader circuit board contains a low number of components making it easy to repair or replace should the need arise.
The Protection circuit 45 consists of low resistance 1/10 watt thin film resistors 48 placed in series with all electrical connections within the card reader socket 42. Crowbar protection diodes 44 are used to clamp any high voltages entering the c~~rd reader 40 to +5 volts or ground causing any excessive currents to blow the thin film resistors 48 thus making them fusible links.

A card insertion switch 49 in the card acceptor module 18 is plastic, and electrically isolated from the acrd connector so there is no need for protection circui~:ry.
The card acceptor module 18 is physically open allowing most debris inserted into the card slot to either fall through into the main parking meter housing or to be easily cleared from the mechanism.
Card reader module 40 is susceptible to vandalism by people shoving objects into the card acceptor slot. If the object is metallic there is a good possibility that tl-~e card power supply could draw excessive current. To prevent this the current consumption of the interface circuitry, both power and I/O, is monitored by the GDM
whenever the card acceptor module 18 is powered up. Excessive current drain will result in the card acceptor module 18, the power being shut down and an error flagged. The detection circuit 45 has a programmable over current setpoint (up to 300 m.a).
15 Mothc;rboard Module (MBM) The motherboard module 30 shown in Figure 4 contains the primary microprocessor 34, memory 35 and operating system. All cash card transactions and audits are handled by the MBM 30 while timing and display functions are dispatched to the GDM 20. CPU 34, a Z80 microprocessor, is embedded in a custom designed 20 Application Specific Integrated. Circuit (ASIC) 36. Motherboard 30 utilizes a large 1 megabyte flash memory module 35 used to store a predetermined number of cash card transaction records as well as the operating system. A memory bank switching system 38 is used to handle the large amount of memory attached to the 8 bit processor 34. In a pref erred embodiment, three security access modules 41 - 43 are supported.
MBM 30 utilizes a custom designed ASIC 36 which contains a great deal of functionality and while all of the functions are not necessarily required for the EPM, their existence allows for possible future upgrades and improvements without major re-engineering. The following functions are available on the motherboard module:

1. The Z80 Microprocessor 34 is modelled after the CMOS Z84C00. It is fully static, low power, non-multiplexed address and data buses, with 16 bit arithmetic instructions. It is a mature device fully supported for software development.
Operational temperature range: -40 ° C to +85 ° C
-ASIC: Operating Voltage: 3 to 6 Volts -160 I3ytes Internal Ram -40 memory mapped I/O registers for all other ASIC function blocks, timers, etc.
2. The I'-C ("I Squared C" ) interface is a standard industrial serial interface used to cor.:~municate with multiple devices on a two wire bus. This bus is used to comrrmnicate with the intelligent graphic display module (GDM) 20 which also contains an IZC EEPROM 24. This port is implemented in software as the speed of the microprocessor 34 allows tile software driver to communicate at baud rates of appro:Kimately 35K Baud. A bus request and bus grant control structure has been added to allow the microprocessor 34 to quickly gain control of the IZC bus in order to comrrmnicate to the GDM 20.
The LED controller consists of two programmable pulse rate generators.
These two generator outputs are used in conjunction with a few logic gates to create a 3 LEI) driver 28. Driver 28 outputs are programmable for logic off, logic on, or a flash rate of 0.5 Hz, 1 Hz, or 2 Hz. When an output is in flash mode the output ON
time is set to a fixed 8 ms. in on~der to conserve power due to the high power nature of LED's 68, 72 and 74.
The LCD controller 21 is capable of driving up to 36 LCD outputs. The LCD
segments can be programmed to flash at a programmable rate of 0.5 Hz, 1 Hz, or Hz. Eight of the LCD segments can be programmed to flash at an independent flash rate.
A low power 32 kHz timekeeping oscillator runs constantly within the ASIC
36. It is the source for both the: internal real time counters and a 60 second counter.
A real-time clock or RTC 28 (hours and minutes only) is implemented in hardware within the ASIC 36. It has a time-of day alarm and an independent 60 second counter. The CPU 34 c;an directly access the counter and alarm registers.
There is a maskable time-of day alarm interrupt and a non-maskable midnight roll-over interrupt. The 60 second counter may be set to cause an interrupt at intervals of between 1 and 60 seconds.
A Watchdog Timer is provided. The Watchdog Timer is a 6 bit (0-63) counter incremented at a 1 second rate. If the timer is not reset by microprocessor 34 within 64 seconds the microprocessor reset will be activated. This prevents processor 34 and ultim;~tely the parking meter from "locking-up" due to a glitch.
Watchdog time-out period 64 seconds Watchdog reset when Bus Request (BR) changes from low to high.
If no positive BR transition in the timeout period then the GDM 20:
- display the out of order message "-- -- -- -- --", - turns on the out of order icon (if present), and - cycles the power off and on again using the PWRON pin.
If there is still no BR transition within the timeout period the meter will turn the power off, and go to sleep. Only a manual reset or battery replacement will restart the m eter.
Suggested Operation Protocol GDM PDO/PDI Wakeup 1) Either GD or EXT interrupt occurs.
lb) IzC BG, SDA and SCL powered off (generate IzC start) 2) GDM 20 asserts the PfVRON pin that wakes up the ASIC 36 3) After a lus delay GDNf 20 asserts GDINT/BXTINT and power IZC SDA and SCL (generate IZC stop) 4) ASIC 36 determines source of wakeup 5) If ASIC 36 needs to access screen 15/EEPROM 24/RTC 28 then:
a) ASIC 36 outputs bus request (BR), b) LPM 22 aborts IZC activity and outputs bus grant (BG) in < 1 ms, c) ASIC 36 issues IZC commands to LPM 22/RTC 281EEPROM 24, d) LPM 22 will dessert BG when it is processing commands and not able to accept input, e) ASIC 36 releases bus request (BR), and LPM 22 resumes screen updates.
Note: ASIC 36 may release and retake the IZC bus repeatedly as desired.

6) ASIC 36 processes and resets all events 7) ASIC 36 requests power down by clearing PWRON, GDINT and EXTINT
lines.
This does not clear interrupt flags so that pending interrupts will wakeup the meter on the the next 64Hz tick.
GDM 20 Reset Wakeup 1 ) Reset button released.
lb) IZC BG, SDA and SCL powered off (generate I'-C start) 2) GDM 20 asserts the PV~RON pin that wakes up the ASIC 36 3) After a lus delay GDM: 20 asserts GDINT and power IZC SDA and SCL
(generate IZC stop) IZC BG is raised.
4) ASIC 36 determines reset wakeup 5) ASIC 36 accesses IzC bus a) ASIC 36 outputs bus request (BR), b) ASIC issues IZC commands to LPM 22/RTC 28/EEPROM 24, c) LPM 22 will dessert BG when it is processing commands and not able to accept input, d) ASIC 36 releases bus request (BR), and LPM resumes screen updates.
Note: ASIC may release and retake the IZC bus repeatedly as desired.

6) ASIC 36 processes and resets all events 7) ASIC requests power down by clearing PWRON, GDINT and EXTINT lines.
This does not clear interrupt flags so that pending interrupts will wakeup the meter on the the next 6~lHz tick.
Achieving ~O.Sppm Clock Accuracy A programmable clock frequency correction can be achieved by using a 1 MHz crystal and Timerl on a PIC microcontroller.
A 1 MHz crystal with t20ppm manufacturing tolerance can be corrected with adjusl;able capacitors by "frequency pulling". Stop watch manufacturers use this method to achieve ~6ppm accuracy. A clock can also be frequency corrected by counting the number of oscillations per second and setting that into a programmable dividf; by n counter. For a IMEIz oscillator a 20bit counter would be required for t0.5ppm.
The accuracy no longer depends on manufacturing tolerance but temperature compensation which could be calculated and corrected using the same technique.
The table below shows the values for several frequency ranges.
Frequency range Max Error Counter Output Max Error In value Out 999,!)79.5-999,980.5- 20 ppm 999,980 1Hz t 0.5 ppm 999,!98.5-999,999.5- 1.5 ppm 999,999 1 Hz t 0.5 ppm 999,!)99.5-1,000,000.5f 0.5 ppm 1,000,1)001 Hz t 0.5 ppm 1,000,000.5-1,000,001.5t 1.5 ppm 1,000,0001 Hz t 0.5 ppm 1,000,019.5-1,000,020.5+ 20 ppm 1,000,020[ 1 Hz I t 0.5 ppm Calculating the value to program into the counter can be done in three steps, with two short measurement cycles, since the conversion from start value to final value; is just a ratio.

Step l : Set the counter to 1.,000,000. Average the clock for several seconds to increase accuracy and remove fitter.
Step 2 : Apply the following formula to create program value.
Step =~: Program and verify by repeating the above steps.
FCnew = FCold * F or FCnew = FCold / T
where: FCnc:w is the final frequency correction value FCold is the start frequency correction value (1,000,000) F is the frequency in Hz produced by FCold T is the time: in seconds for an output cycle with FCold To correct for temperature requires a temperature measurement on a regular basis ;approximately every 15 minutes for a parking meter) and correction applied.
Fox crystals have maximum -0.04ppm/CZ so a correction of -0.02ppm/CZ would be optimum without individually characterizing each crystal. Fully temperature tuning each crystal is not feasible.
This method may also be achieved with a 32KHz clock and fractional counting. The GDM 24 bit counter is initializedinitailized to 16777216 (22a).
By using a stabilized or frequently corrected clock, on street frequency calibration can be performed. The FC~,u,~ can be calculatedcaluculated by the controlling device as follo~rs with the averaging being optional.
FC'~W = PDR Meter ~'h X FCpLD~W , FCi,,Ew = FCpLD + FC',,,EW
MeterPDR (T 2 Range checking on the :MBM will limit valuesvaules of FC to crystal tolerance of -389ppm to +20ppm, or +6224 to -320 Using the PIC as a RTC'. and LCD Backplane Driver Since timed will continue to run when the PIC is asleep it can be used for a low power clock. The LCD b,ackplane and pulse detect wakeup require a 64Hz wake:up. The accuracy of this wakeup is negligible as will be shown later.
Using the prescaler would not be acceptable since the RTC 28 relies on the ability to resolve to 0.5ppm to adjust for clock tolerance. The l6bit counter of Timerl is nov long enough to count for one second, but will do the 15.625ms required for 64H2:. An additional register is required to store the top 4 bits of the 20bit frequency correction value.
Designing the RTC 28 software and interrupt structure is tricky, but achievable. If Timerl was always set to the same value it would produce an accurate 64Hz~ ~20ppm clock, but then the RTC would not be correct. The way to do it is to take t:he frequency correction (FC) number stored in EEPROM 24 and using 1/64 (FCcnt/64) of that value for 63 cycles and then one cycle with the remainder (FCcnt%64). This will produce a slight fitter in refresh time, but it will be (0.4°io), and not visible to the e;ye. This is less than the j fitter caused by different code execution times for the graphica refresh.
A word of warning must be given to the firmware developer when using Timerl with no prescaler and ~Nith a 1:1 ratio between the timer clock and the operating clock. Even though they are the same clock the cycles taken in responding to the overflow will have to be calculated and subtracted from timer when it is reset.
Time continues to run even as the LPM wakes up to service the rollover. An additional correction in timing is required to take into account the difference in interrupt latency between an LPM that is already awake and one that must first wakeup.
A universal asynchronous receiver transmitter (DART) is available for data communications. Programmable baud rates of 600, 1200, 2400, and 9600 baud (bits per se cond) are available. A lr.~odulator/demodulator is also available which allows the UART to be used as an infrared communications link at baud rates of 600, 1200, and 2400 baud. The modulation/ demodulation frequency is a fixed 32,768 Hz.

A 8192 byte low power static RAM 37 is used for the operating system soft~~are stack, variable storage, and temporary code space.
Figure 11 shows the 1 megabyte low power EEPROM flash memory device 35 used for system bootup, the; operating system software, and transaction record S stora,e. This device has a hardware secure boot block to protect the system from boot code loss. This memory device has a 10,000 erase cycle limit which translates to an absolute minimum lifespan of 27 years based on an unlikely daily meter audit cycle.
A non-volatile memory 35 of this size is required to store redundant and multiple copies of the smart c~erd transaction records. The transaction record storage area of the flash memory 35 is partitioned into 128k byte blocks. Flash memory 3~ is block: erasable only so extra blocks must be available in order to accommodate new transaction records before the ~old transaction records can be released for erasure.
In addition to the 16 programmable I/O pins available on the ASIC 36, of which 8 can be reserved for future use, two 8 bit output ports and one 8 bit input port may lie added to the motherboard 30 to handle banked memory switching, security access module (SAM) 41 - 43 switching, and power supply control. Bank switching can be accomplished by adding 5 bits from one output port to the address bus.
These 5 bits select one of thirty-two 32k byte memory blocks.
Power Su~plv The EPM is powered by a 3 "C" cell alkaline battery pack 52 located in a battery compartment 58 the lower backside of the meter module. The replacement procedure is quick and simple. A backup capacitor maintains the meter operating system for the short period of time it takes to replace the battery.
Most of the time the GDM 20 is in a low power sleep mode. GDM 20 and some interrupt circuitry on the MBM 30 are powered directly from the battery pack 52. When the EPM wakes up ,~ high efficiency switching regulator 60, located on the MBNI 30, is switched on by the GDM 20, powering the whole meter at 5 volts. A
low battery detector circuit in the CTDM 20 flags the operating system software when the battery is nearing the end of it's useful life.

Three inexpensive 1.5 volt alkaline "C:" cell batteries, rated at 7 Ahr (Amperes per hour), will power the EPM for at least six months. Alkaline batteries are capable of operating over the specified EPM operating temperature range. To increase product reliability and serviceability, batteries 52 are supplied in welded and shrink wrapped packs with an attached waterproof automotive type connector.
Maximum ratings Vcc DC Supply voltage -0.5 to +7.OV
Icc DC Supply current (sleep) 600uW @ 3V
DC Supply current (awake) TBD @ SV
Supply voh:age 2.SV-6V
Expansion Port Connector A 10 pin, "RJ" type Expansion port Connector is provided on the main board assembly. When assembled, this connector protrudes through the meter from allowing access without disassembly of the meter. The connector is normally covered with a dust/environmental cap/'plug when not in use. The Expansion Port Connector provides for future expansion by providing appropriate signal at this connector. They include power/ground, bi-directional TTL level serial signals (RX/TX), a full IZC
implementation (SDA/SCL), as well as, an external interrupt line.
In a preferred embodirr~ent, up to three Security Access Modules (SAMs) 41 -43 are; supported in the EPM for receiving a variety of credit cards. Modules are placed behind battery 52 in the battery compartment 55 for easy access.
Switching circuitry allows the operating system to select: which security module 41 - 43 or Smart Card it currently requires. This switching circuit handles all of the I/O
ports plus the clock; required by these modules.
Security Access Modules 41 - 43 specification:
~Fully compliant to IS07816-1.,3,4 TO/T1 protocols;
~Card. acceptor 18 is mechanically open to allow debris to pass through.
~Gold plated electrical contacts;

~Over current shutdown protection 45 against metallic object insertion;
~Over voltage protection against vandalism;
~Esti:mated contact life of > 4 ;years using worst case card usage.
EPM eration The operations performed by the EPM can be broken down into the following functions as shown in Figure 12:
~Smart Card Management (Transactions) (also shown in Figure 13) ~Mernory Management (Transaction Storage) ~Time and Display Management ~Event Management (Interrupla) ~Power Management ~Card Reader Module Protection Scheme 45 A typical smart card transaction triggers the following actions:
1. The customer selects tree required amount of parking time by pressing the meter's push button ~7. For each button press the accumulated amount of time and accumulated crash value required is displayed on the LCD 15.
2. The customer then inserts his/her cash card and authorizes the transaction by pressing the push button ~7.
3. The transaction data is stored redundantly in the transaction storage area of the flash memory 35 on the, motherboard module 30.
4. The GDM 20 displays l:he remaining parking time on it's LCD 15 until the time is zero or another 'transaction takes place.
During this time intem~pts (events) are taking place on button ~7 presses, card insertions, and communications between the motherboard 30 and the graphic display module (GPM) 20. Depending; upon what function is being performed the system turns power on or off, and/or wakes/sleeps different parts of the meter in order to conserve power.

Smart Card Management The EPM supports up to three internal security access modules (SAMs) 41 -43 and one external ISO card reader 40 shown in Figure 13. Communications between a SAM 41 - 43 and a Cash Card may be synchronous and/or asynchronous and i s intermediated by the motherboard microprocessor 34. For a transaction to take place the motherboard module 30 will wake up on card insertion, perform a powerup and reset on the card to deterniine what type of card is inserted, then connect the appropriate SAM 41 - 43 to the microprocessor 34.
As shown in Figure 14, SAM's power, clock, and I/O lines must be applied in sequence with the I/O lines resistively pulled-up to Vdd in order to meet the proper powerup conditions. The external card reader interface is powered by a separate current monitored power supply (CDVDD). When a card is inserted an interrupt is generated (CDDETN) which wakes the GDM 20 which in turn enables the power supply on the motherboard module 30. Current to the card reader 45 is monitored by the GDM 20 when powered up and is disabled and an error flagged if excessive current is detected. The SAM modules 41 - 43 are not current monitored but current limiting resistors 48 are used be prevent excessive current flow if the SAM is improperly installed.
The following five tables define the motherboard input and output ports used to control SAM1 41, SAM2 4:!, SAM3 43, arid the Smart Card Reader 40. Three ports are I/O expansion ports, 'the other two are located within the ASIC 36.
Bank & Card Select Register OUT_ PORTO Address A000 - AFFF (Write Only) msb (bit 7) lsb (bit 0) SSI~L1 SSELO CDPWEZ A19 A18 A17 A16 A15 7- SSEL1 SAM Select 1 (Power & Data Switch Select) 6- SSELO SAM Select 0 (Power & Data Switch Select) 5- CDPWR Card Reader Power Enable 4- A19 Memory Bank Address 3- A18 Memory Bank Address 2- A 17 Memory Bank Address 1- A 16 Memory Bank Address 0- A15 Memory Bank Address Card Output Register OUT PORT1 Address B000 - BFFF~ (Write Only) msb (bit 7) lsb (bit 0) CDRST CDPROG CDIO CLCLK SRST SPROG SSEL SLCLK~
7- CDRST Card Reader Reset 6- CDPROG Card Reader Program 5- CDOUT Card Reader Data Output (Z80 to Card Reader) 4- DLCLK Card Reader Low Speed Clock 3- SRST SAM Reset 2- SPROG SAM Program 1- SCSEL SAM Clock Select (SAM1, SAM2, or SAM3) 0- SLCLK SAM Low Speed Clock General Purpose Input Register IN-PORTO Address A000 - BFFF' (Read Only) msb (bit 7) lsb (bit 0) CDRMV CDIN ~CDDET~BG GDINT KEYINT --- EXTINT
7- CDRMV Card Power Input / Card Removed 6- CDIN Card Reader Data Input (Card Reader to Z80) 5- CDDETN Card Detect Input (Inverted) 4- BG IzC Bus Grant 3- GDINT Graphic Display Module Flag Input 2- KEYINT KeyButton Input 1 _ ___ 0- EXTINT Graphic Display Module External Input ASIC I/O Control/Status Register (Low) IO DATA REG_LO Address C013 (Read/Write Programmable) msb (bit 7) lsb (bit 0) --- MEMEl --- MF:MEO DCSEL SIO --- --7- BR IZC Bus Request 6- MEMEl Memory Enable 1 (Output for address decoding) 5- --- Reserved 4- MEMEO Memory Enable 0 (Output for address decoding) 3- DCSEL Card Reader D Clock Select (Output) 2- SIO SAM 1, 2, & 3 Data I/O (Bi-directional) 1- --- Reserved 0- --- Reserved ASIC I/O Control/Status Register (Hi.gh) IO DATA REG_HI Address C014 (Read/Write Programmable) msb (bit 7) lsb (bit 0) ALSCL --- ALSDA ~--- --- --- OCD ---7- ALSCL Anti-Latchup Protected IZC Clock (Bi-directional) 6- --- Reserved 5- ALSDA Anti-Latchup Protected IZC Serial Data (Bi-directional) 4- --- Reserved 3- --- Reserved 2- --- Reserved 1- --- Reserved 0- --- Reserved Memory Management As shown in Figure 4, the motherboard microprocessor 34 is embedded within the ASIC 36. Microprocessor 34 is an 8 bit processor with a 32k byte program code space (OOOOh - 7FFFh). Another 8k byte space is separately decoded for static RAM
37. Bank switching 38 is used to access the 1M byte FLASH memory 35 used for both code and transaction record storage. Code memory is decoded into thirty-two 32k byte blocks by adding 5 additional address lines (A 15 - A 19) for a total code address space of 1 M bytes. These 5 address lines are derived from the output expansion port. See Table 2 Bank & Card Select Register. An Intel PA28F008BVB
FLASH memory module which is block erasable only may be used. There are 11 memory blocks described in Table 2 below:
Block SizePhysical Function Address 1 16 00000-03FFFHardware protected boot block for k startup &

initialization code.

2 8 04000-OSFFFDownloader #l. Code for updating software k and data.

3 8 06000-07FFFMeter ID and version information k 4 96 08000-1FFFFBlacklist data /additional code space.
k 5 128 20000-3FFFFApplication code space.

k 6 128 40000-SFFFFTransaction record space.

k 7 128 60000-7FFFFTraJZSaction record space.

k 8 128 80000-9FFFFTransaction record space.

k 9 128 A0000- Transaction record space.

k BFFFF

10 128 C0000- Trmsaction record space.

k DFFFF

11 128 E0000- Traalsaction record space.

k FFFFF

Table 2: Flash Memory Module Block Size & Function Block erase time: 0.8 seconds typical ( 7.0 sec. max.) for blocks 1, 2, & 3 1.9 seconds typical (14.0 sec. max.) for blocks 4 thru 11 Block write time: 1.4 seconds typical for 128k block Write or "Program" time is approximately 8 us per byte. There is no block write capability. All times are specified for 5 volt read and writes over the commercial temperature range.
Time and Display Management All time and display management is handled by the Graphic Display Module (GDM) 20. GDM 20 will be connectf;d to the MBM 30 via a fine pitch 18 pin ribbon cable 14. Both the GDM 20 and MBM 30 will be mounted to the meter casing with self taping machine screws.

Even; Management The EPM waits in a low power mode most of the time. The motherboard module (MBM) 30 is powered off and the graphic display module (GDM) 20 is waking momentarily then sleeping every 1/64 second. The following events S (interrupts) take place which rc;quire the EPM to take action:
Customer push button (key) press Graphic Display Module interrupt Cash Card insertion cJraphic Display Module interrupt Graphic Display Module service request Motherboard Module interrupt Real 'Time Clock Tick 1164 second l:nterrupt internal to GDM
Figure 15 shows a block diagram of the event management according to the invention. A customer key ~7 press or cash card insertion generates a PDI
interrupt which wakes and/or alerts the graphic display module 20 which in turn powers up the MBM 30, 5 volt power supply via the PWRON output. GDM 20 waits for MBM 30 power up stabilization then asserts an external alert (EXTINT) to tell microprocessor 34 to immediately determine vrhich interrupt, key t7 press or card insertion, woke it up.
When GDM 20 requires service from MBM 30 it first checks it's power on (PWF:ON) flag to see if MBM 30 is powered up. If not GDM 20 sets PWRON to power up MBM 30, waits for power up stabilization, then asserts GDINT. The Z80 wake, checks for a GDINT, and if asserted queries the GDM 20 via the I2C
serial bus for the interrupt source. Because the interrupt query takes place over a serial communications port the event response is slower than a standard interrupt.
GDM 20 is constantly :running a real time clock 28 which uses a 32 kHz crystal controlled counter/timer internal to the microcontroller 22. This timer interrupts the microcontroller 22 every 15.625 ms. (1/64 second). This interrupt rate forms the basic timer for functions being performed by microcontroller 22.
Power Management Figure 16 shows an electrical diagram. of the power management according to the irmention. A high-efficiency (~ 85%) switching power supply 60 on the motherboard module (MBM) ?.0 supplies 5 volts to the EPM when powered up.
When powered down GDM 20~ and some event detection circuitry on the MBM 30 continue to run at a reduced unregulated voltage supplied directly from the battery pack.
The EPM is powered by 3 standard alkaline "C" cell batteries 52 (VEDA 14A) with a nominal output voltage of 4.5 volts. Alkaline "C" cell batteries 52 have an energy rating of 7000 ma/hr. 7,able 3 is an estimated energy audit assuming a week (6 month) battery life.
Function Current _ Time ma/hrs EPIVI Idle 0.2 ma 24 hr/day * 7 day/wk * 26 wks 874 = 4368 hrs.

LE:D 5.0 ma 8 ms/sec * 24 hr/day * 7 day/wk175 Indicator * 26 wks = 35 hrs.

Transactions150.0 8 sec/trans * 450 trans/wk * 3900 ma 26 wks = 26 hrs.

Ba<;klight 5.0 ma 5 sec/trans * 450 trans/wk * 81 26 wks =
16.25 hrs.

Audits 150.0 120 sec/audit * 1 audit/wk * 130 ma 26 wks =
0..87 hrs Total milliamp/hour 5160 Table 3: EPM Energy Audit Estimate The total audit of 5160 ma/hrs represents a conservative 74% battery utiliz~~tion over 6 months or an extended battery life of approximately 8 months.
It is recommended standard operating procedure to replace the EPM batteries 52 at the beginning of the cold season as battery capacity suffers at low temperatures.
The graphic display module 20 handles all events. Key ~7 press and card insertion events originating from the event detection circuitry 31 on the motherboard module 30 are passed on to the: GDM 20 whi<;h in turn wakes the motherboard 30 by turning on the switching power supply 60.

GDM 20 monitors battery voltage once per hour and if it consistently detects a low battery threshold for 24 hours the low battery condition is flagged and the EPM is placed in an out of order state. This allows the system to ignore temporary low battery conditions due to heavrr usage, and/or low temperatures. If at any time the battery voltage drops below an unacceptable operating limit it will immediately go into a low battery status or, oul: of order state.
The motherboard microprocessor 34 manages power to the Security Access Modules (SAM's) 41 - 43 and the Card Reader Module (CRM) 40. Field Effect Transistor (FET) switches 44, directly driven by the Bank & Card Select Register 38, supply power to SAM 41 - 43. Another FET 49 switch driven by the card removal detect circuit supplies 5 volts to the CRM 40.
As illustrated in Figure 14, an over current detection circuit 45 monitors card reade r 40 current consumption. The power supply 50 feed for the card reader (CDVDD) has an in line current sense resistor 58. An analog to digital converter located on the GDM 20 is used to measure this current.
Analog input (AIN) An analog voltage from the main board is supplied to the AIN input. This voltage is converted by the LPM A/D using VDD as the reference high voltage, and ground as the low reference. The main board requests AIN be sampled by setting the AINf flag in the AINCFG register in the LPM. The data that is to be stored in the A1NI)ATA register in the LPM is set by the type bits (AINT1/AINTO). The data may be thf: latest sample, the minimum or maximum value converted. The sample rate is set b)~ the rate bits (AINR4-AINRO).
EPNf Specifications Motherboard Processor 34 Z80 equivalent embedded in a custom designed ASIC
System Clock - 3.58 MHz resonator.
Timekeeping Clock - 32.768 k:Hz crystal.

Mem~~ry 35:
RAM: 8K Bytes Motherboard RAM: 160 Bytes lvlotherboard, internal to Z80 FLASH 1M Bytes lvlotherboard Boot Block Protected Flash Memory 10,000 Write Cycles Environmental Limits Oper;~ting Temperature Range: 0 - +70" C
Storage Temperature Range: -55 - +120° C
Humidity: 0 - 99% non-condensing EMI: Not effected by cellular phone placed within 0.1 meter of the unit when installed in an industry standard MacKay MKV77 housing.
Briti:oh Standards: Damp Heat BS2011 Part 2.1 Test DB
60 °C for 16 hours Vibration BS2011 Part 2 Test Fc, Procedure B3 5 Hz to 60 Hz sweep at 0.75 mm.
for 6 hours :Driving Rain BS2011 Part 2.1R Test Rb3 12.5 t 1 dmZ / minute for 1 minute Bump Test BS EN60068-2-29 Peak acceleration 98 m/secz Pulse duration 16 ms Corresponding velocity change 1000 m/s Number of bumps 1000 Solar Radiation BS2011 Part 2 Test Sa, Procedure A

40 °C with 1.12 kW/m2 solar radiation Minimum basic requirf;ments are as follows:
1) - Operational temperabu~e range -40°C', to +85°C
(+55°C for backlight);
2) - Quiescent power consumption (sleep mode): <600uW;
3) - Operating voltage: 3-6V;
4) - Large area programmable dot matrix LCD technology with backlight;
5) - Aat least 16x16 pixel Chinese character or other languages font;
6) A- at least 8x16 pixel English character font;
7) - The height of the graphics display area shall not be less than 12 mm;
8) - The display buffer shall not be less than 20 Chinese characters;
9) - It shall be capable of assigning portions of the buffer to the real time clock or meter clock;.
10) - The LCD panel shall be capable of statically displaying at least 4 Chinese characters and dynamically moving through the buffer to provide a scrolling message;
11 ) - A paged mode shall be provided to allow alternate displaying of different portions of the 20 character display buffer, e.g. the display can be flipped back and forth between the meter time and a short scrolling message; and 12) - It shall be capable of cycling through at least four different 20 character display buffers in sequence by the EPM, each one allowing the above features (desirable part of the EPM specification).
To ensure that the tem~aerature specifications are met, all electronic components will be selected with the above temperature range. Other environmental factors such as humidity will be addressed with conformal coating during manufacture. In order to improve the coating process, ICs will be surface-mounted where possible and all electronic devices will be exposed for coating.
Physical Dimensions Board size Provide approx. size, thickness = 0.031 Mounting requirements Be a self contained unit. Fit in the MacKay zinc case without interference. Use existing two mounting holes. Align with main board jumper.
Maintaining_the Scrolling Displ~
The GDL supports a scrolling graphics bit map with overlapping RTC 28 clock paste. The scrolling bit map can be divided into top and bottom sections for scrolling. The RTC paste routine supports fixed screen RTC 28 and a scrolling RTC
28. The RTC 28 can be either HH:MM:SS or HH:MM, in either of the two font sizes.
Colons may be on, off, or flashing at O.SHz. 'The colons are placed on top of the boundary between the RTC digits.
As shown in Figure 17., scrolling graphics requires the following steps:
1. Copy of the current graphic image, blanking unknown portions. This is best accomplished by reading and writing directly from the active graphics display controller (GDC) RAlVf area to be inactive GDC RAM while applying the bit shifts required.
2 Retrieve unknown portion from EEPROM 24 and replace the inactive GDC
RAM areas.
3. If the RTC 28 was displayed screen relative then update the unknown portion that were below the RT'C 28 and then update the RTC 28 past area.
4. If the RTC 28 was scrolling just update the RTC 28 if necessary. It will have to be updated if the time being displayed has changed.
5. Make the inactive GDC: RAM the active display RAM.3 NOTE: 1. Switching between pages on the SED1526 precludes the use of the 17th line of graphics. ~Chese 10 bytes can be used for additional general purpose storage space.
Switching between pages on the SED1526 precludes the use of the 17th line of graphics. These to bytes can be used for additional general purpose storage space The card insertion switch in the card acceptor 18 is plastic and electrically isolated from the card connector so there is no need for protection circuitry.
Grat~uics Display Language All screen graphics bit maps, fonts, and display instructions are stored in the IZC EEPROM 24 in a format to be referred to as the graphics display language (GDL).
The start address of the GDL script is O 1 FE-O 1 FF. The LPM 22 only reads from the EEPF:OM 24 and uses the data to update the display. TSTAMP is also stored in the EEPF;OM 24 at 01 FB-O 1 FD.
GDL Instruction Format The GDL script consists of a list of consecutive 123 byte instructions. Each GDL instruction will be follovred by the next instruction except the last instruction.
The last instruction is marked with ENDOP=1. The script is then restarted at the beginning. Undefined values should be initialized to 0.
The (JDL instructions are formatted as follows:
CTYPE SDIRI SDIRO (:PE1 CPEO PCFMT ENDOP

RCI. CLSZ TOPS BOTS C;NTE STEPSZ

CCI~ CCFGO LZS SGN --- PG PRATE PRATED

SCRDLY

CNTL

CNTH

STARTL

STARTH

STOPL

STOPH

CLOCKL

CLOCKH
Reserved for future expansion CLOCKH
General purpose configuration bits.

VdAKE Cause wakeup when done. Normally 0 except for last step in script 0 Do not indicate when done 1 Cause GD event when done (set GDF flag) CTYPE Counter type 0 Counter is number of times to scroll 1 Counter is number of 1/16 seconds to scroll S DIR1/SDIRO Scroll direction 00 Scroll left O1 Scroll right (future option) 10 Scroll up (future option) 11 Scroll down (future option) CPE1/CPEO Clo<:k paste enable 00 Display graphics data only O1 Paste RTC value over graphics data.

10 Paste SECTIMER value over graphics data.

11 Reserved for future use PCFMT Paste clock format4 If AMIPM, YYY/MM/DD, or day of week we desired they will have to be updated in the graphics bitmap at noon and midnight by the main boards application software.

ENDOP End of script operation. Normally 0 except for last step in script 0 Proceed with next instruction 1 Restart at beginning of GDL buffer Scroll buffer configuration bits.

RCL Relative clock location (Pixels from start of buffer/screen) 0 Scrolleen buffer relative. Clock paste buffer will scroll with graphics.

1 Screen location relative. Clock paste buffer will stay in fixed location on the screen.

C:LSZ Clock font size 0 6x8font 1 12 x 16 font TOPS Scroll top half of graphics 0 Static top message 1 Scroll top half B~~TS Scroll bottom half of graphics 0 Static bottom message 1 Scroll bottom half C:~1TE Counter Enable.

0 Counter value ignored 1 Counter value significant Enabling the counter for a static script with a counter value of 0 will cause the GDM to constantly update the static 2~ display.

S~CEPSZ Scroll step size 000 Static display 001 1 (pixel) 010 8(small font) 011 12(RTC) 100 16(large font) 1 O 1 80(screen) 110 80(screen) 111 80(screen) Paste block configuration bits.
C'.CFGI/CCFGO Colon configuration 00 Off O1 On 10 Off 11 Blink~sl Colon is added on the boundaryboundry between the HM
and MS
Colon dots are 2x2 pixels in small font Colon dots are 4x4 pixels in large font L,ZS Leading Zero Suppression (TENS of hours) 0 Display zero 1 Zero suppression s When enabled the colon will blink at IHz, colon on if 1/2 seconds is even, and off if 1/2 seconds is odd.

S(JN6 Display negative sign in placeinplace of MSD (TENS of hours) 0 No 1 Yes Only negative '-' sign shown, positive values use blank instead of '+'.
Negative times can result from displaying SECTIMER
value less than less than 00:00:00.
Page buffer configuration tits.
PG Page; (80 pixel scroll) the nonscrolling line (Optional) 0 Nonscrolling top or bottom line is static 1 If TOPS=0 top will page (80 pixel scroll) If BOTS=0 bottom will page (80 pixel scroll) Note: If TOPS=0 and BOTS=0 then paging of top and bottom can be enabled with this bit.
Note;: The storage fol~nat for PG=1 is 16 bit.
PI~ATE1/PRATEO Page; scroll rate (Optional) 00 Static O1 O.SHz 10 1Hz 11 2Hz This bit may l;~e dropped in the future if a foot is developed to allow a full '-'HH:MM:SS time to be displayed on a single screen.

Scroll buffer configuration bytes.
SI~RDLY Scroll delay 0 Static display 1-255 1(fastest)-255(slowest) (approx.approx 1/l6sec) CNTH/CNTL Cownter 0 forever 1-65535 defined by CNTP as buffers/seconds to scroll S'CARTH/STARTL Stars: address of screen buffer S'COPH/STOPL Stop address+1 of screen buffer' P~~ste block configuration bytes.
CLOCKH/CLOCKL Clock location. Only valid if CPE1/CPEOo00.
0-81914095 If RCL=0 this is the EEPROM address in the scroll buffer area where thecolumn location of the left column side of the clock paste block is to start replacing the graphics.
0-159 If RCL=1 and CLSZ=0 (small font) then this is the screen column location of the left side of the clock paste buffer. Top row will be 0-79 and bottom row will be 80-159.
0-7f If RCL=l and CLSZ=1 then this is the screen column location of the left side of the clock paste block.
See section 6.2.1 for details Graphics Storage Format The two graphics stora;;e formats are 8-bit and 16-bit. The storagestrorage format used is determined by the TOPS, BOT'S and PG bits of the GDL
instruction as shown below.
TOf BOTS PG S t o r S a g a Format 0 0 0 8-Bit 0 1 0 8-Bit 1 0 0 8-Bit 1 1 0 16-bit x x 1 16-Bit Both formats are vertical column oriented. The first byte of each format contains the state of the top 8 pixels in the left most column. The LSB of the first byte is the top left most pixel.
Graphics Format (8-bit) The first byte of the 8-bit format controls the top 8 bits in the left most column. The LSB of the first byte is the top left most pixel. The second byte defines the state of the top 8 pixels in l:he second column and so on to the end of the buffer (GDh stop address - 1).
If TOPS=1 and we are using the 8-bit format (BOTS=0) then the top buffer ends 80 bytes before the GDL stop address. 'Che bottom buffer is the last 80 bytes before the stop address.

If TOPS=0 and we are using the 8-bit format with BOTS=1 then the first 80 bytes are the top buffer and GDL instructions stop address is one past the end of the bottom buffer which starts immediately after the top buffer.
If TOPS=0 and we are using the 8-bit format with BOTS=0 then the first 80 S bytes are the top buffer and GDL inst~~uctions stop address is one past the end of the bottom buffer which is the last 80 bytes before the stop address. The stop address must be 160 larger than the start address if TOPS=0, BOTS=0 and PG=0.
Graphics Format ( 16-bit) The first byte of the 16-bit format controls the top 8 bits in the left most column. The LSB of the first byte is the top left most pixel. The second byte defines the state of the bottom 8 pixels in the first column. The bytes alternate top and bottom to the end of the buffer (GDL stop address - 1 ).
Clock Storage and Display Formats There are three registers to store time values: RTC, CMP, and SECTIMER. .
All three clocks are decremented by 24:00:00 by the GDM at midnight.
The RTC is a YY:MM:DD:HH:MM:SS free running real time clock with statistical frequency correction. The RTC is stored in the format described in ~7.1.
The CMP value is an HH:MM:SS value stored in the GDM. If the RTCW
wakeup bit is set in WAKEUPO then the GDM will cause a wakeup when the HH:MM:SS of CMP and RTC match. The storage format for CMP supports setting wakeups up to 100 hours in the future by storing values up to 124 (100+24 midnight).
The storage of CMP hours is binary and the RTC hours is BCD, so a conversion must take place before times are compared.
The SECTIMER is an HH:MM:SS time value that is may be used instead of the RTC for displaying time. The SECTIMER can either count up or down based on the count direction. (SEC CDIR bit of SECTIMER FMT) The storage format for the second timer is a ones magnitude. Several examples are shown in the table below:

Time SECTIMER HR SECTIMER MIN SECTIMER SEC

99:59:59 99 = 0x63 59 = Ox3B 59 = Ox3B

O 1:02:03 O 1 = 0x01 02 = 0x02 03 = 0x03 00:00:00 00 = Ox00~8~ 00 = 0x00 00 = 0x00 - 01:02:03- O1 = 0x80 ~ 0x0102 = 0x02 03 = 0x03 = 0x81 - 99:59:59- 99 = 0x80 ~ 0x6359 = Ox3B 59 = Ox3B
= OxE3 To count down valid park time; the MBM would write a GDL script to display SECTIMER with a count down direction. After 00:00:00 the time would become negative and continuecontiue to count down. The SECTIMER can count from 99:59:59 to -99:59:59, and rollover to 0 at the end of these counts. The SECTIMER
has the same accuracy and frequency calibration as the RTC.
The card reader module 40 is capable of accepting standard ISO Card, as well as, a Smart Card Interface device which is attached to a Parking Data Retriever (PDR), as it will be described later. This establishes a communications link between a PDR and the EPM. The communications protocol is standard asynchronous RS232 at 9600 Baud, with TTL logic levels.
A PDR is provided as a powerful platform for the EPM application. It utilizes flash ROM for BIOS, SETUP, & Communication utilities. The main user RAM
memory acts as the user disk, and can be upgraded to l3Mbyte. Additional storage 78.
s can be provided via standard PC-cards installed in the PCMCIA slot. There is an optional integrated microphone and speaker. For communications there are 2 serial ports, (1 IR 76 and 1 Lemo connector) as well as a fully IrDA compliant optical port Time 00:00:00 could be marked as negative, but will be always be stored as positive The PDR is used to replace manual collection of physical money by retrieving the electronic cash. The PDR is also used for meter configuration, meter firmware maintenance, and for interfacing with a Central Computer System (CCS). The PDR
is a ruggedized, hand held DOS computer, collecting transaction data for uploading the CCS. The PDR is dropped into th.e CCS cradle and it both charges and has its data off loaded by a program running on the CCS computer. The PDR is a simple carrier of data and makes no decision about the data integrity. These decisions are made by the CCS. The CCS can identify whether two cards having the same number have been used in two different parking lots, signals when a withdrawn card is used, and can compare authorized signatures for signed transactions.
A smart card interface interfaces between the parking meter and the PDR. The electronic cash transactions stored on the serial port can be downloaded and loaded to an ISO 7816 compliant Central Computer.
The keyboard has 51 multi-function keys, 5 function keys, cursor and ESC
key. The keys have tactile feedback as well as programmable audible feedback.
The LCD is 200 x 200 pixels, backlit and temperature compensated. It can display CGA
compatible text and graphics.
A windowed carrying case may be provided with each PDR unit. The sturdy nylon/plastic carrying case allows the PDR to be carried on a belt, or with an included shoulder harness. In addition to offering additional protection from driving rain, dirt, and dust, it allows the operator to carry out all key presses, and view the LCD display through a clear plastic window.
The battery recharging automatically takes place when the PDR is placed into the communication/charging cradle. Each cradle is powered by it's own individual AC adapter. The cradles are interconnected in a daisy chained network via a 4 wire cable. Each chain or network can have up to 30 cradles connected in a series arrangement. Each chain connects to a master unit, which in turn is connected via a serial cable to an available communication port on the PC. The cradles are individually numbered/addressed, and can be selected by the supplied PC
3 0 communications software. At the CC S site all PDR data/file transfers, including date/time adjustments can be remotely accomplished using the program running on the PC in conjunction with the internal COM program resident and running on each individual PDR.
Each PDR will require it's own charger communications cradle which can be wall mounted with a wall mount kit. .A 220VAC adapter (12VDC @ 800mA) is provided with each cradle. A short R:f cable is included with each unit, to allow for PDR interconnection of each wall mounted cradle. A supplied 50 ohm termination resistor must terminate the last cradle if the cradles are connected via the PDR
network. A master unit is required fox each group of cradles attached to a PC.
A
master cradle can be master to a maximum of 30 slave cradles.
The PDR may be a Microflex PC9800 with l OMb of installed user memory and the PCMCIA option included. The operating system is MS-DOS 6.22, and the standard communications software COM.EXE is embedded in the flash BIOS. IrDA
capability and drivers are provided with the product for future use, but are not utilized in either phase one or two.
The PDRs communicate and transfer data to the CCS equipment via supplied software. When the PDRs are dropped into the cradles at the end of th2e day, the resident PDR software is first instructed by a menu selection to "LINK to CCS". This menu choice will call or execute the PDR's internal COM.EXE program. In this way, the PDR becomes a slave to the software running on the PC. When data and files are remotely transferred from each PDR, the program can terminate the PDR from the slave program.
The unit is international in that the displays are j ust treated as static or scrolling bitmaps with the special ability to overwrite the display graphics with the meter time or the real time clock (RTC).
All data moved to/from the EPDs is done so by means of the PDR and an attached Smart Card Interface (SCI) device. The SCI provides a direct connection to the card reader contacts through a "card like" sleeve that is inserted into the EPD card slot. The insertion of the card should generate a response from the EPD, and the PDR
3 0 software will provide the proper response and command to the EPD
challenge. Data will be transferred using an established protocol that is compliant to the particular EPD (EPM, PDM & EPT). The data transfer rate will be approx. 9600baud.
Revenue collection, meter configuration, and meter firmware maintenance are accomplished via a communications link established by inserting a portable data terminal interface card into the meter's card acceptor slot 16. In a prffered embodiment, the communication protocol is a standard asynchronous RS232 at Baud, with TTL logic levels.
The SCI is a serial communication device, is provided with a smart card sleeve that plugs into the EPD. It has it's own interface circuit encased in the plastic case that the sleeve protrudes from. The circuit is powered from the EPD during any communications/data transfer. The device connects to the PDR via an attached cable that plugs into the PDR's LEMO port; connector. The cable is approx. 1.4M in length.

I' C Address 1VIAP
When communicating with the ASIC the LPM will be configured as an IZC slave device at 7bit address O I 10011. The EEPROM is I'C device 1010000. Since there are different device addresses there will be no confusion as to which device is to respond:
There are only four commands to communicate on the IZC bus: start, read byte(s), write byte(s), and stop.
All communications is done by reading and writing LPM and EEPROM addresses.
For the proposed PIC microcontroller there are 256 memory locations (00-F'F) including 36 special purpose registers identified in the micracontroller user manual. Not all memory locations are valid.
All registers are available) but some area are nor. useful. Consult the PIC
and SED 1526 users manual for purpose of each memory location. The RTC and SED 1526 are accessed through the LPM.

I'C LPM Address I~IAP
LPM internal addresses 0000-0005Reserved for GDM

0006 PWRON Bit field 0007-OOABReserved for GDM

OOAC RTC_SEC BCD format OOAD RTC_NIIN BCD format OOAE RTC_HR BCD format OOAF RTC_DAY_DATE BCD format OOBO RTC_MONTH BCD format OOB I RTC_YEAR BCD format OOB2-OOB7Reserved for GDM

OOB8 WAKEUPO Bit field--OOB9 EVENTO Bit field OOBA EVENT1 Bit field OOBB LEDO Bit field OOBC LED1 Bit field OOBD ENUM Bit field OOBE ENU1~I0 Bit field OOBF ENU1~I1 Bit field OOCO LBATVAL Integer format OOC 1 Reserved for GDM

OOC2 AL~ICFG Bit field OOC3 AINDATA Integer format OOC4 Reserved for GDM

OOCS BATREAD Bit field OOC6 BATDATA Inte er format OOC7 Reserved for GDNI

OOCB Reserved for GDM

OOC9 CMP_SEC BCD format OOCA CMP_MIN BCD format OOCB CMP_HR Unsigned integer format 00CC SEC'I'11VIER_SECBCD format OOCD SECTI1VIER_MIN BCD format OOCE SECTIMER_HR Signed integer format OOCF SECTT1VIER_FMT Bit field DODO-00D Reserved for I GDNI

OOD8 LCD contrast MSB bit, 5 bit inte er OOD9-OOE7Reserved for GDM

ThP fnllnwinQ SFD1526 addresses are translated by the LPM
0100-014FSED1526_BITMAPO Gra h_ics bit map page 0 top (visable) 0200-024FPO Grahics bit ma -page 0 SED1526_BITNIA bottom (visable) 0300-034F_ Gra hics bit ma a a 1 to SED1526_BIT'MAP1(hidden) 0400-044FSED1526_BITNL~P1Gra hics bit ma age 1 bottom (hidden) 0500-0509SED1526_ICONMAP Gra hics bit ma ,icons 0600-TBD SED1526 STAT Gra hics statuslcontrol CNTL

0006 PWRDN (read/write) GLED RLED PLED BACK PWRON GDIN'f EXTIyT VICC
GLED Green LED drive pin (Use LEDO/LED 1 to control LED) BLED Red LED drive pin (Use LEDO/LED 1 to control LED) YLED Yellow LED drive pin (Use LEDO/L.ED 1 to control LED) BACK Backlight drive pin I',Use LEDO/LED1 to control backlight) PWRON POWON drive pin (0 to power dawn MBM) GDINT GDINT drive pin (0 when powering down I~IBVI) GD11~1T' EXTINT drive pin (0 when powering down MB M) VICC I''C drive pin (iVlust be left high) Set this register to OxOI to power down the LVIBM. GDML~('I' and EXTINT pins are lowered by the MBM by clearing them in this register. Clearing GDINT, EXTINT, and PWRON pin and power dawn regardless of the respective interrupt status flags.
Ignored interrupt flags reboot the ASIC on the next clack tick (64Hz). The GDiVI will set VICC to 1 whenever it finds a watchdog event just incase The VICC bit was cleared.
OOAC RTC_SEC (BCD format 0-59 seconds) TENS ONES
TENS tens of seconds digit ONES ones of seconds digit OOAD RTC MII''t (BCD format 0-~9 minutess) TENS ONES
TENS tens of minutes digit ONES ones of minutes digit OOAE RTC HR (BCD format 0-23 hourss) -TENS ONES
TENS tens of hours digit ONES ones of hours digit OOAF RTC~A
DATE
DATE obit date of month code (1-28/Z9130/31) p p 0 0 MONTH
MO~ Sbit month of year (0000 for Tanuary . . . 1011 for December) OOB 1 RTC YEAR Year (0-99) RTC_YEAR
RTC_YEAR Year 0 is 1986 OOB2 RTC DOW Da of week RTC DOW
DAy 3bit day code (000 for Sunday . . . I IO far Saturday) This register is incremented every midnight and rolls over from 6 to 0. If the DOW is set incorrectly the GDM will not calculate and correct it.

OOB8 WAI~EUPO (read/write NIIDN Nlidni~ht wakeup enable NOON Noon wakeup enable RTCW Real time clock wakeup enable GDW Graphics script wakeup enable PDOW Pulsed detect wakeup enable PDOE Pulsed detect output enable 0 Disabled, PDO stays high) and PDI input is ignored.
1 Enabled, PDO pulsed low for 120us every. If PDI goes high during PDO pulse then PDOF flag is set.
PDOL PDI interrupt detect level Generate PDOF flag if detection enabled and PDI matches this bit just before PDO is raised. Only one sample of PDI is required.
OOB9 EVENTO (read*/write MIDF Midnight wakeup occured. Produces GDINT.
NOONFNoon wakeup occurred. Produces GDINT.
RTCF Real time clack wakeup occurred. Produces GDINT.
GDF Graphics script wakeup occurred. Produces GDP~ 1T
PDOF Pulsed detect wakeup occurred. Produces EXTINT. (Flag not useful) RESF Indicates GDM reset. Produces GI7INT.
WDTF Indicates watchdog timer expired. Produces GDINT.
*Whenever this byte is read by the main processing board it is cleared by the GDM.
OOBA EVENT1 (read/write) BATF GDLF L,BCNT
BATF Battery was changed llag. Produces GDIl~(T.
GDLF Graphics display language error. Produces GDINT.
LBCNT Count of consecutive low battery readings(6-bit) Battery reading taken every hour. Counter reset if good battery detected.
Meter low battery symbol displayed and yellow LED blink slow if counter o 0.
If LBCNT = 24 the GDM causes a GDINT.
If LBCNT = 24 then the GDNI will display out of order and go to ultra low currnet made) not responding to internal or external events.
In ultra low current mode the only activity is: the RTC is updated, the low battery indicator flashes at the programmed rate. The I2C and graphics display are disabled.
The only way to come out of ultra low current mode is a hard reset.
*Whenever this byte is read by the MBM it is clears the BATE and GDLF flags.
LBCNT
is not effected by a read.

OOBB LEDO (read/write) xLBE Red/~reen LED low battery indicator 0 LED not used for low battery indicator 1 LED on/flashino if low battery This status takes precedent over the individual programmable flash rates xLED2 Red/~reen LED state 0 off 1 on xLED lhtLEDO Red/~reen LED flash rate OD LED on solid O L LED ZHz I 0 LED I Hz I1 LED O.SHz OOBC LEDI (read/write BACK Backlight on/off LBFI/LBFOLow battery flash rate 00 on solid O1 ZHz 10 1Hz I I O.SHz YLBE YellowLED low battery indicator YLED2 LED state Yellow 0 off 1 on YLED 1/YLEDOYellow LED flash :rate 00 on solid 01 2Hz 10 IHz 11 0.5Hz OOBD ENUiVI
FGNP Front glass no parking symbol FGNPE Front glass no parking in English FGNPC Front glass no parking in Chineese BGBG Back glass background BGNPS Back glass no parking symbol BGNPC Back glass no parking in English & Chineese OOBE ENLIi~IO
xl/x0 ICON flash rate 00 on solid Ol 2Hz 10 1Hz 11 O.SHz OOBF ENU1~I1 (read/write) 1 ~ ~o ~ ___ ~ ___ ~ ~s cN 1 ~ FB cN0 ~ FB cD 1 ~ FB cDo xl/x0 ICON flash rate 00 on solid O1 2Hz 10 1Hz I I O.~Hz 00C0 LBATVAL (read/write) Threshold level for hourly low battery Level checks. A battery reading Iessthan this value is considered low battery level.
OOCZ AINCFG (read/write) AINF ~ HINT 1 ~ AINTO ~ AINRATE
AINF Analog input conversion enable 0 disabled 1 enabled AINT1/AP~ 1T0 Analog data type to store 00 no change O1 maximum miminum 11 latest AINRATE Analog conversion rate (1/I6 ticks) 0 1/16 second 1 1/8 second 2 t/4 second 4 0.~ Hz 8 1 Hz 16 2 Hz OOC3 A11YDATA (read/write) AINDATA I
Unsigned data supplied by LPNI AID. This register is cleared by the main board, and does not need to be initialized by the LPM prior to minimum and maximum sample configurations.
OOCS BATREAD (read/write) ___ ___ ___ ___~ ___ ___ ___ BATREAD
A bit set in this register will cause battery reading to be taken and stored in BATDATA
on the next l6Hz tick after the MBivI has been powered down.
OOC6 BATDATA (read_write) Latest AID reading of battery voltage 00C9 CvIP SEC (BCD format 0-59 seconds) TENS ~ ONES
TENS tens of seconds digit ONES ones of seconds digit OOCA CMP NIIN (BCD format 0-59 minutes) TENS O NES
TENS tens of minutes digit ONES ones of minutes digit OOCB CMP_HR (B inary format 0-255 hours) OOCC SECThIER SEC (BCD format ranges 0-59 seconds) TENS ~ ONES

TENS tens of seconds digit ONES ones of seconds digit OOCD SECTIMER_VII~~1 (BCD format ranges 0-59 minutes) TENS ONES

TENS tens of minutes di;it ONES ones of minutes digit OOCE SECTIibIER
HR (Ones com le_ment binary format ranges -127 to 127 hours) SIGN ST HR

SIGN Sign of Timer 0 Positive time 1 Display negative if SGN bit of GDL script is enabled ST_HR 0-99, 7 bit integer hour OOCF SECTIyIER_FMT

___ _ __ ___ ___ ___ ___ ___ SEC_CDIR

SEC_CDIR Second Timer count direction 0 Count down I Count up DODO TCALO
TcALo TCALZ

0100-014F _SED1526 BITVIAPO (read/~a~rite) Top 8 rows of LCD display The first address is the left most column, One byte is used for each column.
The MSB of the data is the bottom dot on the screen Consult SED1~26 Date Sheet for mapping of bits to pixels 0200-024F SED p26 BITI~IrIPO (read/~urite) Bottom 8 rows of LCL) display The first address is the left most column, One byte is used for each column.
The MSB of the data is the bottom dot on the screen Consult SED1~Z6 Date Sheet for mapping of bits to pixels 0300-034FSED1526_BITI~fAPI (read/write) Hidden top 8 rows of LCD display (scratch pad area) Consult SED1~26 Date Sheet for mapping of bits to pixels 0400-404FSED1526 BITivIAPI (read/write) Hidden bottom 8 rows of LCD display (scratch pad area) Consult SEDl~26 Date Sheet for mapping of bits to pixels 000-009 SED1~26_ICONS (read/write) Consult SED 126 Date Sheet for mapping of bits to pixels 0600-06xx _SED1~26_STATUS CFG (read/write) Consult SED1~26 Date Sheet for mapping of bits to pixels I'C EEPROyI Address yI~P
The application software on the main board maintains the memory map for the serial EEPROM.
Other than the fixed addresses below the LP!~I only determines how memory is mapped by processin' the GDL script.
The first 512 bytes have extended write capability (10 million cycles) and are used for frequently modified data such as GDL script address. Other fixed addresses as noted below:
Final address specification to be defined by F'rior Data Sciences. The high endurance block location, determined by Prior Data Sciences, is conf~ured dur-in' assembly by the GDM
manufacturer. The table below uses bank 0 a;t the hijh endurance block.
EnduranceAddress Variable Pur ose ~

_ High 0000-O1FD TBD b a lication High OIFE GDLADDR_LO Low Address of GDL scri t High O1FF GDLADDR_HI High Address of GDL scri t Low 0200 GDNf_VER GDM Version Number Low 0201 GDM_SERNO Low GDNI Serial Number Low 0202 GD1~I_SERN1 High GDM Serial Number Low 0203 GDM PCB GDM PCB Version Number Low 0204 GDL_VER GDL Version Number Low 0205 FCO Fre uenc Correction Ultra Low (Not used) Low 0206 FCl Fre uenc Correction Low Low 0207 FC2 Fre uenc Correction Medium Low 0208 FC3 Fre uenc Correction High Low 0209 FC4 Fre uenc Correction Ultra High Low 020A RSTWAKEUPO Default WAKEL'P0 value (OxOE) Low 020B RSTEVENTO Default EVENTO value (0x02) Low 020C RSTEVENT1 Default EVENTI value (0x00) Low 020D RSTLEDO Default LEDO value (0x00) Low 020E RSTLED1 Default LED1 value (0x38) Low 020F RSTENUM Default ENUM value (OxBE) Low 0210 RS'TElYUMO Default E'~IUMO value (0x00) Low 0211 RSTENITVII Default EYUM1 value (0x00) Low 0212 RSTLBATVAL Default LBATVAL value (OxC7) Low 0213-0214RTC_FONT Address of font table. If 0000 use internal LPM font for RTC. (Not im lemented) Low 0215-055F TBD b a Lication Low 0560-OSFFSYS ERROR S stem failure message Low 0600-1FFF TBD b a lication Default Frequency correction value is 16777216 decimal or 0x1000000. FCO is not used.
FC 1 = 0x00 FC2 = 0x00 FC:3 = 0x00 FC4 = 0x01 The SYS ERROR system failure message is a 160 byte static graphic that is displayed after a watchdog event. Clearing the WDTF bit deactivates displaying this message.

Claims (10)

1. A multiple purse electronic parking meter, comprising:
input/output means;
a low power microcontroller for generating an interrupt signal defining a parking; meter event;
an LCD display for displaying a mixed-mode graphics and icons;
a first memory means for storing display functions including a plurality of graphic display languages, and to maintain scrolling messages on said LCD
display;
a real time continuously running clock for generating a preset interrupt tick rate forming the basic timer for said low power microcontroller;
processing means for waking up on receipt of said interrupt signal, for determining the source of said interrupt signal, and to control said LCD
display, said first memory means, and said clock;
second memory means for storing code data and customer data;
a memory switching system for accessing said second memory means whenever said event occurs and said processing means has woke up.

2. A parking meter according to claim 1, wherein said input/output means comprises a card reader module for accepting a plurality of ISO compliant cards.

3. A parking meter according to claim 2, wherein said input/output means further comprises a security access module for validating one of said plurality of ISO
compliant cards and for generating a card access signal.

4. A parking meter according to claim 2, wherein said input/output means further comprises a system protection means for continuously monitoring the current supplied to said card reader module.

5. A parking meter according to claim 3, wherein said input/output means further comprises actuating means on said card reader module for initializing said security access module and for selecting the amount of parking time purchased whenever said card is inserted and said actuating means is operated.

6. A parking meter according to claim 4, wherein said system protection means is an overcurrent/overvoltage protection circuitry.

7. A parking meter according to claim 5, wherein said amount of parking time can be purchased directly or through a split payment.

8. A parking meter according to claim 1, further comprising a smart card interface for insertion in said input means to interface with a portable data retriever.

9. A parking meter according to claim 1, wherein said customer data comprise current transaction data and previous transaction data.

10. A multiple purse electronic parking meter, comprising:
a card reader module for accepting a plurality of ISO compliant cards;
a security access module for validating one of said plurality of ISO compliant cards and for generating a card access signal;
a low power microcontroller for generating an interrupt signal defining a parking meter event;
an LCD display for displaying a mixed-mode graphics and icons;
a first memory means for storing display functions including a plurality of graphic display languages, and to maintain scrolling messages on said LCD
display;

a real time continuously running clock for generating a preset interrupt tick rate forming the basic timer for said low power microcontroller;
processing means for waking up on receipt of said interrupt signal, for determining the source of said interrupt signal, and to control said LCD
display, said first memory means, and said clock;
second memory means for storing code data and customer data;
a memory switching system for accessing said second memory means whenever said event occurs and said processing means has woke up;
system protection means for continuously monitoring the current supplied said card reader module; and actuating means on said card reader module for initializing said security access module and for selecting the amount of parking time purchased whenever said card is inserted and said actuating means is operated, whereby when said card is validated said processing means is powered up for a short period of time to identify the event and to instruct recordation of the event in said second memory means, and said low power microcontroller and said first memory means continuously maintain scrolling messages and display the remaining parking time on said LCD display.