AU8298491A - Random access cache memory - Google Patents

Info

Publication number: AU8298491A
Authority: AU; Australia
Prior art keywords: random access; cache memory; access cache; memory; random
Prior art date: 1990-06-27
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Abandoned

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

MOS Electronics Corp

Original Assignee

MOS Electronics Corp

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1991-04-01Priority claimed from US07/678,912external-prioritypatent/US5488709A/en

1991-06-24Application filed by MOS Electronics CorpfiledCriticalMOS Electronics Corp

1992-01-23Publication of AU8298491ApublicationCriticalpatent/AU8298491A/en

StatusAbandonedlegal-statusCriticalCurrent

Classifications

- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0888—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0877—Cache access modes
- G06F12/0879—Burst mode
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
- G06F12/0835—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means for main memory peripheral accesses (e.g. I/O or DMA)

Landscapes

Engineering & Computer Science (AREA)
Theoretical Computer Science (AREA)
Physics & Mathematics (AREA)
General Engineering & Computer Science (AREA)
General Physics & Mathematics (AREA)
Memory System Of A Hierarchy Structure (AREA)

AU82984/91A1990-06-271991-06-24Random access cache memoryAbandonedAU8298491A (en)

Applications Claiming Priority (6)

Application Number	Priority Date	Filing Date	Title
US678912		1984-12-06
US54607190A	1990-06-27	1990-06-27
US546071		1990-06-27
US67891491A	1991-04-01	1991-04-01
US678914		1991-04-01
US07/678,912US5488709A (en)	1990-06-27	1991-04-01	Cache including decoupling register circuits

Publications (1)

Publication Number	Publication Date
AU8298491Atrue AU8298491A (en)	1992-01-23

Family

ID=27415469

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
AU82984/91AAbandonedAU8298491A (en)	1990-06-27	1991-06-24	Random access cache memory

Country Status (2)

Country	Link
AU (1)	AU8298491A (en)
WO (1)	WO1992000590A1 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
DE69327633T2 (en)*	1992-11-13	2000-08-10	National Semiconductor Corp., Richardson	Microprocessor with address area configuration system and method for controlling memory system operations using address areas
JP3886189B2 (en)*	1995-12-18	2007-02-28	テキサスインスツルメンツインコーポレイテツド	Microprocessor device supporting burstable and non-cacheable memory access
US6947748B2 (en)	2000-12-15	2005-09-20	Adaptix, Inc.	OFDMA with adaptive subcarrier-cluster configuration and selective loading
WO2004045228A1 (en)*	2002-11-07	2004-05-27	Broadstorm Telecommunications, Inc.	Method and apparatus for adaptive carrier allocation and power control in multi-carrier communication systems
US7573851B2 (en)	2004-12-07	2009-08-11	Adaptix, Inc.	Method and system for switching antenna and channel assignments in broadband wireless networks
JP5462068B2 (en)*	2010-05-12	2014-04-02	アダプティックスインコーポレイテッド	Adaptive carrier allocation and power control method and apparatus in multi-carrier communication system

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US4403288A (en)*	1981-09-28	1983-09-06	International Business Machines Corporation	Methods and apparatus for resetting peripheral devices addressable as a plurality of logical devices
US4577293A (en)*	1984-06-01	1986-03-18	International Business Machines Corporation	Distributed, on-chip cache

1991
- 1991-06-24AUAU82984/91Apatent/AU8298491A/ennot_activeAbandoned
- 1991-06-24WOPCT/US1991/004484patent/WO1992000590A1/enunknown

Also Published As

Publication number	Publication date
WO1992000590A1 (en)	1992-01-09

Publication	Publication Date	Title
AU690462B2 (en)	1998-04-23	Optical random access memory
EP0593152A3 (en)	1995-10-04	Random access memory design
GB9205551D0 (en)	1992-04-29	Cache memory
EP0450285A3 (en)	1992-12-30	Cache memory
GB2225657B (en)	1992-07-01	Random access memory system
GB2260429B (en)	1995-05-24	Versatile cache memory
EP0657819A3 (en)	1996-08-07	Cache memory.
EP0487288A3 (en)	1992-10-21	Synchronous dynamic random access memory
AU7043494A (en)	1994-12-20	Dynamic random access memory system
EP0514017A3 (en)	1993-10-06	Serial access memory
EP0438211A3 (en)	1992-08-05	Cache memory system
EP0412245A3 (en)	1992-01-29	Cache memory
DE69016094D1 (en)	1995-03-02	Video random access memory.
EP0594347A3 (en)	1994-08-24	Synchronous static random access memory
EP0470742A3 (en)	1994-09-28	Dynamic random access memory
EP0486794A3 (en)	1994-12-28	Dram having extended refresh time
GB2254487B (en)	1995-06-21	Full CMOS type static random access memories
GB2297398B (en)	1999-11-24	Accessing cache memories
EP0447051A3 (en)	1992-01-22	Random access memory with access on bit boundaries
GB9103954D0 (en)	1991-04-10	Random access memory built-in write buffer
EP0499853A3 (en)	1993-11-18	Memory access scheme
GB2277390B (en)	1997-02-26	Random access memory
EP0468453A3 (en)	1992-11-19	Multiport cache memory
KR970008600B1 (en)	1997-05-27	Memory access system
GB2223127B (en)	1992-03-25	Static random access memory

Movatterモバイル変換

AU8298491A - Random access cache memory - Google Patents

Info

Links

Classifications

Landscapes

Applications Claiming Priority (6)

Publications (1)

Family

ID=27415469

Family Applications (1)

Country Status (2)

Families Citing this family (6)

Family Cites Families (2)

Also Published As

Similar Documents