AU2000228229A1 - Method for operating a parallel arrangement of power semiconductor switches - Google Patents

Abstract

The invention relates to a method for statically balancing the loading of power semiconductor switches (S<SUB>1</SUB>, S<SUB>2</SUB>, S<SUB>3</SUB>) in a parallel circuit ( 1 ). To achieve this in prior art, switching instants of individual switches (S<SUB>1</SUB>, S<SUB>2</SUB>, S<SUB>3</SUB>) are adapted in the case of GTOs and current amplitudes of individual switches are adapted in the case of IGBTs. According to the invention, a primary pattern ( 4 ) of frame-switching pulses is predetermined for a total current (i) through the parallel circuit ( 1 ) and a secondary pattern ( 51, 52, 53 ) comprising more or fewer pulses than the primary pattern ( 4 ) is generated for at least one switch (S<SUB>1</SUB>, S<SUB>2</SUB>, S<SUB>3</SUB>). In contrast in conventional methods, the asynchronicity of the pulses enables a rapid redistribution of the loading between the parallel switches (S<SUB>1</SUB>, S<SUB>2</SUB>, S<SUB>3</SUB>), thus reducing or obviating the need for inductive suppressor circuits for limiting the current. The method is compatible with methods for the dynamic synchronization of transient switching and is suitable for "latching" and amplitude-controlled power semiconductor switches (S<SUB>1</SUB>, S<SUB>2</SUB>, S<SUB>3</SUB>). The examples relate to the addition or omission of subordinate switching pulses during long or short frame-switching pulses and to an active control ( 6 ) of the number of subordinate switching pulses, depending on the loading of the switches (S<SUB>1</SUB>, S<SUB>2</SUB>, S<SUB>3</SUB>).