Gate Resizer
Contents
Gate Resizer#
Gate Resizer commands are described below. Theresizer commands stop whenthe design area is-max_utilizationutil percent of the core area.utilis between 0 and 100. Theresizer stops and reports an error if the maxutilization is exceeded.
Commands#
Note
Parameters in square brackets
[-paramparam]are optional.Parameters without square brackets
-param2param2are required.
Set Don’t Use#
Theset_dont_use command removes library cells from consideration bytheresizer engine and theCTS engine.lib_cells is a list of cells returned byget_lib_cellsor a list of cell names (wildcards allowed). For example,DLY* says donot use cells with names that begin withDLY in all libraries.
set_dont_uselib_cellsUnset Don’t Use#
Theunset_dont_use command reverses theset_dont_use command.
unset_dont_uselib_cellsReset Don’t Use#
Thereset_dont_use restores the default dont use list.
reset_dont_useReport Don’t Use#
Thereport_dont_use reports all the cells that are marked as dont use.
report_dont_useSet Don’t Touch#
Theset_dont_touch command prevents the resizer commands frommodifying instances or nets.
set_dont_touchinstances_netsUnset Don’t Touch#
Theunset_dont_touch command reverse theset_dont_touch command.
unset_dont_touchinstances_netsReport Don’t Touch#
Thereport_dont_touch reports all the instances and nets that are marked as dont touch.
report_dont_touchBuffer Ports#
Thebuffer_ports-inputs command adds a buffer between the input and itsloads. Thebuffer_ports-outputs adds a buffer between the port driverand the output port. Inserting buffers on input and output ports makesthe block input capacitances and output drives independent of the blockinternals. It uses the buffer library cell defined by-buffer_cell if it is given.
buffer_ports[-inputs][-outputs][-max_utilizationutil][-buffer_cellbuf_cell][-verbose]
Options#
Switch Name | Description |
|---|---|
| Insert a buffer between the input and load, output and load respectively. The default behavior is |
| Defines the percentage of core area used. |
| Specifies the buffer cell type to be used. |
| Enable verbose logging. |
Instance Name Prefixes#
buffer_ports uses the following prefixes for the buffer instances that it inserts:
Instance Prefix | Purpose |
|---|---|
input | Buffering primary inputs |
output | Buffering primary outputs |
Remove Buffers#
Use theremove_buffers command to remove buffers inserted by synthesis. Thisstep is recommended before usingrepair_design so that there is more flexibilityin buffering nets. If buffer instances are specified, only specified buffer instanceswill be removed regardless of dont-touch or fixed cell. Direct input port to output portfeedthrough buffers will not be removed.If no buffer instances are specified, all buffers will be removed except those that are associated withdont-touch, fixed cell or direct input port to output port feedthrough buffering.
remove_buffers[instances]
Balance Row Usage#
Command description pending.
balance_row_usageRepair Design#
Therepair_design command inserts buffers on nets to repair max slew, maxcapacitance and max fanout violations, and on long wires to reduce RC delay inthe wire. It also resizes gates to normalize slews. Useestimate_parasitics-placement beforerepair_design to estimate parasitics consideredduring repair. Placement-based parasitics cannot accurately predictrouted parasitics, so a margin can be used to “over-repair” the designto compensate.
repair_design[-max_wire_lengthmax_length][-slew_marginslew_margin][-cap_margincap_margin][-max_utilizationutil][-pre_placement][-buffer_gainfloat_value](deprecated)[-match_cell_footprint][-verbose]
Options#
Switch Name | Description |
|---|---|
| Maximum length of wires (in microns), defaults to a value that minimizes the wire delay for the wire RC values specified by |
| Add a slew margin. The default value is |
| Add a capactitance margin. The default value is |
| Defines the percentage of core area used. |
| Enables performing an initial pre-placement sizing and buffering round. |
| Deprecated alias for |
| Obey the Liberty cell footprint when swapping gates. |
| Enable verbose logging on progress of the repair. |
Instance Name Prefixes#
repair_design uses the following prefixes for the buffer instances that it inserts:
Instance Prefix | Purpose |
|---|---|
fanout | Fixing max fanout |
gain | Gain based buffering |
load_slew | Fixing max transition violations |
max_cap | Fixing max capacitance |
max_length | Fixing max length |
wire | Repairs load slew, length, and max capacitance violations in net wire segment |
Repair Tie Fanout#
Therepair_tie_fanout command connects each tie high/low load to a copyof the tie high/low cell.
repair_tie_fanout[-separationdist][-max_fanoutfanout][-verbose]lib_port
Options#
Switch Name | Description |
|---|---|
| Tie high/low insts are separated from the load by this value (Liberty units, usually microns). |
| Enable verbose logging of repair progress. |
| Tie high/low port, which can be a library/cell/port name or object returned by |
Repair Timing#
Therepair_timing command repairs setup and hold violations. Itshould be run after clock tree synthesis with propagated clocks.Setup repair is done before hold repair so that hold repair does notcause setup checks to fail.
The worst setup path is always repaired. Next, violating paths toendpoints are repaired to reduced the total negative slack.
repair_timing[-setup][-hold][-recover_powerpercent_of_paths_with_slack][-setup_marginsetup_margin][-hold_marginhold_margin][-slack_marginslack_margin][-librarieslibs][-allow_setup_violations][-sequence][-skip_pin_swap][-skip_gate_cloning][-skip_size_down][-skip_buffering][-skip_buffer_removal][-skip_last_gasp][-skip_vt_swap][-skip_crit_vt_swap][-repair_tnstns_end_percent][-max_passespasses][-max_repairs_per_passmax_repairs_per_pass][-max_utilizationutil][-max_buffer_percentbuffer_percent][-match_cell_footprint][-verbose]
Options#
Switch Name | Description |
|---|---|
| Repair setup timing. |
| Repair hold timing. |
| Set the percentage of paths to recover power for. The default value is |
| Add additional setup slack margin. |
| Add additional hold slack margin. |
| While repairing hold violations, buffers are not inserted that will cause setup violations unless |
| Specify a particular order of setup timing optimizations. The default is “unbuffer,vt_swap,sizeup,swap,buffer,clone,split”. Obeys skip flags also. |
| Flag to skip pin swap. The default is to perform pin swap transform during setup fixing. |
| Flag to skip gate cloning. The default is to perform gate cloning transform during setup fixing. |
| Flag to skip gate down sizing. The default is to perform non-critical fanout gate down sizing transform during setup fixing. |
| Flag to skip rebuffering and load splitting. The default is to perform rebuffering and load splitting transforms during setup fixing. |
| Flag to skip buffer removal. The default is to perform buffer removal transform during setup fixing. |
| Flag to skip final (“last gasp”) optimizations. The default is to perform greedy sizing at the end of optimization. |
| Flag to skip threshold voltage (VT) swap optimizations. The default is to perform VT swap optimization to improve timing QoR. |
| Flag to skip critical threshold voltage (VT) swap optimizations at the end of optimization. The default is to perform critical VT swap optimization to improve timing QoR beyond repairing just the worst path per each violating endpoint. |
| Percentage of violating endpoints to repair (0-100). When |
| Maximum repairs per pass, default is 1. On the worst paths, the maximum number of repairs is attempted. It gradually decreases until the final violations which only get 1 repair per pass. |
| Defines the percentage of core area used. |
| Specify a maximum number of buffers to insert to repair hold violations as a percentage of the number of instances in the design. The default value is |
| Obey the Liberty cell footprint when swapping gates. |
| Enable verbose logging of the repair progress. |
Use-recover_power to specify the percent of paths with positive slack whichwill be considered for gate resizing to save power. It is recommended thatthis option be used with global routing based parasitics.
Instance Name Prefixes#
repair_timing uses the following prefixes for the buffer and gate instances that it inserts:
Instance Prefix | Purpose |
|---|---|
clone | Gate cloning |
hold | Hold fixing |
rebuffer | Buffering for setup fixing |
split | Split off non-critical loads behind a buffer to reduce load |
Repair Clock Nets#
Theclock_tree_synthesis command inserts a clock tree in the designbut may leave a long wire from the clock input pin to the clock treeroot buffer.
Therepair_clock_nets command inserts buffers in thewire from the clock input pin to the clock root buffer.
repair_clock_nets[-max_wire_lengthmax_wire_length]
Options#
Switch Name | Description |
|---|---|
| Maximum length of wires (in microns), defaults to a value that minimizes the wire delay for the wire RC values specified by |
Repair Clock Inverters#
The repair_clock_inverters command replaces an inverter in the clocktree with multiple fanouts with one inverter per fanout. Thisprevents the inverter from splitting up the clock tree seen by CTS.It should be run before clock_tree_synthesis.
repair_clock_invertersReport Design Area#
Thereport_design_area command reports the area of the design’s componentsand the utilization.
report_design_areaReport Floating Nets#
Thereport_floating_nets command reports nets with connected loads but no connected drivers.
report_floating_nets[-verbose]
Report Overdriven Nets#
Thereport_overdriven_nets command reports nets with connected by multiple drivers.
report_overdriven_nets[-include_parallel_driven][-verbose]
Options#
Switch Name | Description |
|---|---|
| Include nets that are driven by multiple parallel drivers. |
| Print the net names. |
Eliminate Dead Logic#
Theeliminate_dead_logic command eliminates dead logic, i.e. it removes standard cell instances which can be removed without affecting the function of the design.
eliminate_dead_logicOptions#
Switch Name | Description |
|---|---|
| Print the net names. |
Useful Developer Commands#
If you are a developer, you might find these useful. More details can be found in thesource file or theswig file.
Command Name | Description |
|---|---|
| Repair setup pin violation. |
| Get the raw value for timing margin (e.g. |
| Get the above margin in perentage format. |
| Same as |
| Check maximum utilization. |
| Get maximum wirelength. |
| Check if wirelength is allowed by rsz for minimum delay. |
Setting Optimization Configuration#
Theset_opt_config command configures optimization settings that apply todata cell selection, affecting all optimization commands like repair_design and repair_timing.However, this does not apply to clock cell selection in clock_tree_synthesis or repair_clock_nets.
set_opt_config[-limit_sizing_areafloat_value][-limit_sizing_leakagefloat_value][-keep_sizing_siteboolean_value][-keep_sizing_vtboolean_value][-set_early_sizing_cap_ratiofloat_value][-set_early_buffer_sizing_cap_ratiofloat_value][-disable_buffer_pruningboolean_value][-sizing_area_limitfloat_value](deprecated)[-sizing_leakage_limitfloat_value](deprecated)
Options#
Switch Name | Description |
|---|---|
| Exclude cells from sizing if their area exceeds <float_value> times the current cell’s area. For example, with 2.0, only cells with an area <= 2X the current cell’s area are considered. The area is determined from LEF, not Liberty. |
| Exclude cells from sizing if their leakage power exceeds <float_value> times the current cell’s leakage. For example, with 2.0, only cells with leakage <= 2X the current cell’s leakage are considered. Leakage power is based on the current timing corner. |
| Ensure cells retain their original site type during sizing. This prevents short cells from being replaced by tall cells (or vice versa) in mixed-row designs. |
| Preserve the cell’s VT type during sizing, preventing swaps between HVT and LVT cells. This works only if VT layers are defined in the LEF obstruction section. |
| Maintain the specified ratio between input pin capacitance and output pin load when performing initial sizing of gates. |
| Maintain the specified ratio between input pin capacitance and output pin load when performing initial sizing of buffers. |
| Disable buffer pruning to improve hold fixing by not filtering out delay cells or slow buffers. |
| Deprecated. Use -limit_sizing_area instead. |
| Deprecated. Use -limit_sizing_leakage instead. |
Reporting Optimization Configuration#
Thereport_opt_config command reports current optimization configuration
report_opt_configResetting Optimization Configuration#
Thereset_opt_config command resets optimization settings applied fromset_opt_config command.If no options are specified, all optimization configurations are reset.
reset_opt_config[-limit_sizing_area][-limit_sizing_leakage][-keep_sizing_site][-keep_sizing_vt][-set_early_sizing_cap_ratio][-set_early_buffer_sizing_cap_ratio][-disable_buffer_pruning][-sizing_area_limit](deprecated)[-sizing_leakage_limit](deprecated)
Options#
Switch Name | Description |
|---|---|
| Remove area restriction during sizing. |
| Remove leakage power restriction during sizing. |
| Remove site restriction during sizing. |
| Remove VT type restriction during sizing. |
| Remove capacitance ratio setting for early sizing. |
| Remove capacitance ratio setting for early buffer sizing. |
| Restore buffer pruning for optimization. |
| Deprecated. Use -limit_sizing_area instead. |
| Deprecated. Use -limit_sizing_leakage instead. |
Finding Equivalent Cells#
Thereport_equiv_cells command finds all functionally equivalent library cells for a given library cell with relative area and leakage power details.
report_equiv_cells[-match_cell_footprint][-all][-vt]lib_cell
Options#
Switch Name | Description |
|---|---|
| Limit equivalent cell list to include only cells that match library cell_footprint attribute. |
| List all equivalent cells, ignoring sizing restrictions and cell_footprint. Cells excluded due to these restrictions are marked with an asterisk. |
| List all threshold voltage (VT) equivalent cells such as HVT, RVT, LVT, SLVT. |
Reporting Buffers#
Thereport_buffers command reports all usable buffers to include for optimization.Usable buffers are standard cell buffers that are not clock buffers, always on buffers,level shifters, or buffers marked as dont-use. VT type, cell site,cell footprint and leakage are also reported.
report_buffers[-filtered]
Options#
Switch Name | Description |
|---|---|
| Report buffers after filtering based on threshold voltage, cell footprint, drive strength and cell site. Subset of filtered buffers are used for rebuffering. |
Optimizing Arithmetic Modules#
Thereplace_arith_modules command optimizes design performance by intelligently swapping hierarchical arithmetic modules based on realistic timing models.This command analyzes critical timing paths and replaces arithmetic modules with equivalent but architecturally different implementations toimprove Quality of Results (QoR) for the specified target.
Arithmetic Module Types#
Yosys and OpenROAD support the following arithmetic module variants with different timing/area trade-offs.
ALU (Arithmetic Logic Unit) Variants
- Han-Carlson (default)
Balanced delay and area. Best for general purpose applications.
- Kogge-Stone
Fastest, largest area. Best for timing-constrained designs.
- Brent-Kung
Slower, smaller area. Best for area-constrained designs.
- Sklansky
Moderate delay/area. Best for balanced optimization.
MACC (Multiply-Accumulate) Variants
- Booth (default)
Balanced delay and area. Best for general purpose applications.
- Base (Han-Carlson)
Fastest, potentially larger area. Best for timing-constrained designs.
Requirements for Arithmetic Module Swap#
Hierarchical netlist with arithmetic operators. Yosys can produce such designs by enabling “wrapped operator synthesis”.In OpenROAD-flow-scripts, this can be done as follows:
cd OpenROAD-flow-scripts/flow
make SYNTH_WRAPPED_OPERATORS=1
This requires a Verilog netlist. DEF netlist alone is not sufficient for hierarchical optimization.
Hierarchically linked design. The design needs to be linked to preserve hierarchical boundaries. For example,
link_design top -hier
read_db -hier
replace_arith_modules[-path_countnum_critical_paths][-slack_thresholdfloat][-targetsetup|hold|power|area]
Options#
Switch Name | Description |
|---|---|
| Number of critical paths to analyze to identify candidate arithmetic modules to swap. The default value is |
| Slack threshold in library time units. Use positive values to include paths with small positive slack. The default value is |
| Optimization target. Valid types are |
Arguments#
SetupALU: replace all candidate modules with Kogge-Stone (fastest)MACC: replace all candidate modules with Base (fastest)
HoldNot available yet
PowerNot available yet
AreaNot available yet
SEE ALSO#
replace_hier_modules
EXAMPLES#
Arithmetic modules follow this naming convention per Yosys:
ALU_<io_config><width><config>_<architecture>
MACC_<io_config><width><architecture>
Examples:
ALU_20_0_25_0_25_unused_CO_X_HAN_CARLSON
ALU_20_0_25_0_25_unused_CO_X_KOGGE_STONE
ALU_20_0_25_0_25_unused_CO_X_BRENT_KUNG
ALU_25_0_20_0_25_unused_CO_X_SKLANSKY
\MACC_14’10001011010100_19_BOOTH
\MACC_14’10001011010100_19_BASE
Example scripts#
A typicalresizer command file (after a design and Liberty libraries havebeen read) is shown below.
read_sdcgcd.sdcset_wire_rc-layermetal2set_dont_use{CLKBUF_*AOI211_X1OAI211_X1}buffer_portsrepair_design-max_wire_length100repair_tie_fanoutLOGIC0_X1/Zrepair_tie_fanoutLOGIC1_X1/Z#clock tree synthesis...repair_timing
Note that OpenSTA commands can be used to report timing metrics beforeor after resizing the design.
set_wire_rc-layermetal2report_checksreport_tnsreport_wnsreport_checksrepair_designreport_checksreport_tnsreport_wns
Regression tests#
There are a set of regression tests in./test. For more information, refer to thissection.
Simply run the following script:
./test/regression
Limitations#
FAQs#
Check outGitHub discussionabout this tool.
License#
BSD 3-Clause License. SeeLICENSE file.