Source code :
https://github.com/TerosTechnology/vscode-terosHDL
Documentation :
https://terostechnology.github.io/terosHDLdoc/
Theme fund: NGI0 Entrust
Start: 2023-10
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TerosHDL: OSS, GHDL, NVC
IDE with support for Open SYthesis Suite and GHDL/NVC simulators
TerosHDL is an open-source graphical IDE tailored to FPGA/ASIC development. The goal is to empower engineers, hobbyists, and students to easily engage in RTL design, fostering innovation and growth in the field. TerosHDL serves as a comprehensive platform, supporting RTL design, synthesis, simulation and common code edition (linting, formatting, etc).
In this project, TerosHDL will incorporate support for a number of additional powerful RTL design tools: Yosys, GHDL, and NVC. This will give users an interface which is friendly to first time users, equipped with real-time feedback and debugging capabilities. This further streamlines the chip design process, enhancing efficiency and making RTL design more accessible and productive.
- The project's own website:https://terostechnology.github.io/terosHDLdoc/docs/intro
Run by TerosHDL
This project was funded through theNGI0 Entrust Fund, a fund established byNLnet with financial support from the European Commission'sNext Generation Internet programme, under the aegis ofDG Communications Networks, Content and Technology under grant agreement No 101069594.
