Movatterモバイル変換

Referenced bygetHalfSizedIntegerVT(), andgetRoundIntegerType().

Definition at line42 of fileValueTypes.h.

Definition at line43 of fileValueTypes.h.

Return true if this has the same number of bits as VT.

Definition at line251 of fileValueTypes.h.

ReferencesgetSizeInBits().

Referenced byllvm::SelectionDAG::getStrictFPExtendOrRound(),lowerFCMPIntrinsic(),lowerICMPIntrinsic(),llvm::AMDGPUDAGToDAGISel::Select(), andllvm::AMDGPUDAGToDAGISel::SelectVectorShuffle().

Return true if this has no less bits than VT.

Definition at line287 of fileValueTypes.h.

Referencesassert(),isScalableVector(), andknownBitsGE().

Referenced byfindFPToIntLibcall(),getCopyToPartsVector(),getMemcpyLoadsAndStores(),llvm::isConstOrConstSplat(),llvm::AMDGPUTargetLowering::performAssertSZExtCombine(),performSIGN_EXTEND_INREGCombine(), andunrollVectorShift().

Return true if this has more bits than VT.

Definition at line279 of fileValueTypes.h.

Referencesassert(),isScalableVector(), andknownBitsGT().

Referenced byAddCombineBUILD_VECTORToVPADDL(),llvm::R600TargetLowering::allowsMisalignedMemoryAccesses(),llvm::TargetLowering::findOptimalMemOpLowering(),foldCONCAT_VECTORS(),llvm::SelectionDAG::FoldConstantArithmetic(),llvm::SelectionDAG::getAnyExtOrTrunc(),llvm::AArch64TTIImpl::getCastInstrCost(),getCopyToPartsVector(),llvm::SelectionDAG::getFPExtendOrRound(),llvm::SelectionDAG::getNode(),llvm::FastISel::getRegForGEPIndex(),llvm::SelectionDAG::getSExtOrTrunc(),llvm::SelectionDAG::getStrictFPExtendOrRound(),getSVEPredicateBitCast(),llvm::SelectionDAG::getVPZExtOrTrunc(),llvm::SelectionDAG::getZExtOrTrunc(),LowerSELECTWithCmpZero(),llvm::R600TargetLowering::PerformDAGCombine(),llvm::HexagonTargetLowering::PerformDAGCombine(),llvm::PPCTargetLowering::PerformDAGCombine(),llvm::FastISel::selectOperator(),llvm::TargetLowering::SimplifySetCC(), andtryToReplaceScalarFPConversionWithSVE().

Return true if this has no more bits than VT.

Definition at line303 of fileValueTypes.h.

Referencesassert(),isScalableVector(), andknownBitsLE().

Referenced byllvm::SelectionDAG::getBoolExtOrTrunc(),llvm::SelectionDAG::getNode(),llvm::SelectionDAG::getSplatBuildVector(),llvm::SelectionDAG::getSplatVector(),llvm::SelectionDAG::getVPZeroExtendInReg(),llvm::SelectionDAG::getZeroExtendInReg(),llvm::RISCVTargetLowering::PerformDAGCombine(),llvm::AMDGPUTargetLowering::performMulCombine(),PerformVECREDUCE_ADDCombine(),llvm::TargetLowering::SimplifySetCC(), andVerifySDNode().

Return true if this has less bits than VT.

Definition at line295 of fileValueTypes.h.

Referencesassert(),isScalableVector(), andknownBitsLT().

Referenced byllvm::R600TargetLowering::allowsMisalignedMemoryAccesses(),combineShuffleOfScalars(),llvm::TargetLowering::expandMULO(),foldCONCAT_VECTORS(),llvm::SelectionDAG::FoldConstantArithmetic(),getCopyFromParts(),getCopyFromPartsVector(),llvm::SelectionDAG::getLoad(),getLoadExtOrTrunc(),getMemsetStores(),llvm::SelectionDAG::getNode(),llvm::FastISel::getRegForGEPIndex(),llvm::SelectionDAG::getSplatValue(),llvm::SelectionDAG::getTruncStore(),llvm::SelectionDAG::getTruncStoreVP(),llvm::SelectionDAG::getTruncStridedStoreVP(),llvm::TargetLowering::getTypeForExtReturn(),llvm::MipsTargetLowering::getTypeForExtReturn(),llvm::SelectionDAG::getVPZExtOrTrunc(),handleCMSEValue(),legalizeScatterGatherIndexType(),llvm::TargetLowering::lowerCmpEqZeroToCtlzSrl(),llvm::SITargetLowering::LowerFormalArguments(),LowerSELECTWithCmpZero(),matchPMADDWD_2(),narrowIndex(),OptimizeNoopCopyExpression(),llvm::AArch64TargetLowering::ReconstructShuffle(),llvm::SITargetLowering::ReplaceNodeResults(),llvm::RISCVTargetLowering::ReplaceNodeResults(),llvm::FastISel::selectOperator(), andllvm::TargetLowering::SimplifySetCC().

Return a VT for a type whose attributes match ourselves with the exception of the element type that is chosen by the caller.

Definition at line113 of fileValueTypes.h.

ReferenceschangeVectorElementType(),getScalarType(), andisVector().

Return the type converted to an equivalently sized integer or vector with integer element type.

Similar to changeVectorElementTypeToInteger, but also handles scalars.

Definition at line121 of fileValueTypes.h.

Referencesllvm::MVT::changeTypeToInteger(),changeVectorElementTypeToInteger(),getSimpleVT(),isSimple(), andisVector().

Referenced byadjustLoadValueTypeImpl(),combineFP_EXTEND(),constructRetValue(),llvm::TargetLowering::expandFP_TO_SINT(),llvm::TargetLowering::expandRoundInexactToOdd(),llvm::TargetLowering::expandVECTOR_COMPRESS(),GenerateFixedLengthSVETBL(),LowerFMINIMUM_FMAXIMUM(),llvm::SITargetLowering::LowerFormalArguments(),llvm::SITargetLowering::lowerFP_EXTEND(),PerformEXTRACTCombine(),performLD1ReplicateCombine(),performLDNT1Combine(),performSTNT1Combine(), andllvm::AMDGPUTargetLowering::performTruncateCombine().

Return a VT for a vector type whose attributes match ourselves with the exception of the element type that is chosen by the caller.

Definition at line102 of fileValueTypes.h.

Referencesassert(),llvm::MVT::changeVectorElementType(),getSimpleVT(), andisSimple().

Referenced bychangeElementType(),combineArithReduction(),combineConcatVectorOps(),combineEXTEND_VECTOR_INREG(),combineFP_EXTEND(),combineMulToPMADDWD(),combineSelect(),combineSIntToFP(),combineTruncateWithSat(),combineUIntToFP(),llvm::TargetLowering::expandFP_ROUND(),llvm::TargetLowering::expandVECTOR_COMPRESS(),llvm::TargetLowering::expandVectorFindLastActive(),findMoreOptimalIndexType(),llvm::X86TargetLowering::getNumRegistersForCallingConv(),getPredicateForScalableVector(),llvm::X86TargetLowering::getRegisterTypeForCallingConv(),getVectorBitwiseReduce(),llvm::X86TargetLowering::getVectorTypeBreakdownForCallingConv(),legalizeScatterGatherIndexType(),LowerFLDEXP(),LowerVectorAllEqual(),narrowIndex(),performBuildShuffleExtendCombine(),performBuildVectorCombine(),performMSTORECombine(),performUnpackCombine(),PerformVECREDUCE_ADDCombine(),reduceMaskedLoadToScalarLoad(),reduceMaskedStoreToScalarStore(),llvm::X86TargetLowering::ReplaceNodeResults(),tryToReplaceScalarFPConversionWithSVE(),tryToWidenSetCCOperands(), andwidenVectorToPartType().

Return a vector with the same number of elements as this vector, but with the element type converted to an integer type with the same bitwidth.

Definition at line94 of fileValueTypes.h.

Referencesllvm::MVT::changeVectorElementTypeToInteger(),getSimpleVT(), andisSimple().

Referenced bychangeTypeToInteger(),combineBitcast(),combineExtSetcc(),combineFP_EXTEND(),combineFP_ROUND(),combineSelect(),createVariablePermute(),llvm::XtensaTargetLowering::getSetCCResultType(),llvm::R600TargetLowering::getSetCCResultType(),llvm::SystemZTargetLowering::getSetCCResultType(),llvm::AArch64TargetLowering::getSetCCResultType(),llvm::ARMTargetLowering::getSetCCResultType(),llvm::CSKYTargetLowering::getSetCCResultType(),llvm::LoongArchTargetLowering::getSetCCResultType(),llvm::MipsTargetLowering::getSetCCResultType(),llvm::PPCTargetLowering::getSetCCResultType(),llvm::RISCVTargetLowering::getSetCCResultType(),llvm::SparcTargetLowering::getSetCCResultType(),llvm::X86TargetLowering::getSetCCResultType(),lowerVECTOR_SHUFFLE_VSHF(),LowerVSETCC(),performSelectCombine(),performVSelectCombine(),llvm::X86TargetLowering::ReplaceNodeResults(), andvectorToScalarBitmask().

Support for debugging, callable in GDB: VT.dump()

Definition at line201 of fileValueTypes.cpp.

Referencesllvm::dbgs(), andprint().

Definition at line458 of fileValueTypes.h.

ReferencesgetVectorElementCount(),getVectorElementType(), andgetVectorVT().

Referenced bycombineConcatVectorOps(),LowerCONCAT_VECTORS_i1(),performDUPCombine(),performExtBinopLoadFold(),performSignExtendInRegCombine(),performUADDVZextCombine(),performUzpCombine(), andtryCombineMULLWithUZP1().

Return the value type corresponding to the specified type.

getEVT - Return the value type corresponding to the specified type.

If HandleUnknown is true, unknown types are returned as Other, otherwise they are invalid. NB: This includes pointer types, which require aDataLayout to convert to a concrete value type.

Definition at line289 of fileValueTypes.cpp.

Referencesllvm::Type::FixedVectorTyID,llvm::Type::getContext(),llvm::VectorType::getElementCount(),llvm::VectorType::getElementType(),getEVT(),getIntegerVT(),llvm::Type::getTypeID(),getVectorVT(),llvm::MVT::getVT(),llvm::Type::IntegerTyID,llvm::Type::ScalableVectorTyID, andllvm::Type::TokenTyID.

Referenced byllvm::ARMTargetLowering::allowTruncateForTailCall(),llvm::X86TargetLowering::allowTruncateForTailCall(),llvm::CallLowering::determineAssignments(),llvm::BasicTTIImplBase< T >::getCastInstrCost(),getEVT(),llvm::TargetLoweringBase::getMemValueType(),llvm::AArch64TTIImpl::getPartialReductionCost(),llvm::FastISel::getRegForGEPIndex(),llvm::TargetLoweringBase::getValueType(),llvm::CallLowering::handleAssignments(),llvm::TargetLoweringBase::isExtFree(),isNoopBitcast(),llvm::HexagonTargetLowering::isTruncateFree(),llvm::HexagonSubtarget::isTypeForHVX(),llvm::ARMTargetLowering::lowerInterleavedLoad(),llvm::ARMTargetLowering::lowerInterleavedStore(),llvm::FastISel::selectBinaryOp(),llvm::AArch64TargetLowering::shouldExpandPartialReductionIntrinsic(), andsplitMergedValStore().

This function returns value type as a string, e.g. "i32".

getEVTString - This function returns value type as a string, e.g. "i32".

Definition at line162 of fileValueTypes.cpp.

ReferencesgetEVTString(),llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(),getRISCVVectorTupleNumFields(),getSizeInBits(),getVectorElementCount(),getVectorElementType(),isFloatingPoint(),isInteger(),isRISCVVectorTuple(),isScalableVector(),isVector(),llvm_unreachable, andllvm::MVT::SimpleTy.

Referenced bygetEVTString(),print(),llvm::MVT::print(), andllvm::SDNode::print_types().

Return the size of the specified fixed width value type in bits.

The function will assert if the type is scalable.

Definition at line376 of fileValueTypes.h.

Referencesllvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getFixedValue(), andgetSizeInBits().

Referenced byclampDynamicVectorIndex(),combineBROADCAST_LOAD(),combineConstantPoolLoads(),combineLoad(),combineSCALAR_TO_VECTOR(),llvm::TargetLowering::expandUnalignedStore(),llvm::TargetLowering::expandVectorSplice(),findMemType(),llvm::TargetLowering::forceExpandWideMUL(),getCopyFromPartsVector(),getCopyToPartsVector(),getFauxShuffleMask(),getReducedGprRegisterClass(),llvm::SDValue::getScalarValueSizeInBits(),llvm::TargetLowering::getVectorSubVecPointer(),llvm::TargetLowering::IncrementMemoryAddress(),IsMulWideOperandDemotable(),llvm::AArch64TargetLowering::isTruncateFree(),llvm::MSP430TargetLowering::isTruncateFree(),llvm::SystemZTargetLowering::isTruncateFree(),llvm::RISCVTargetLowering::joinRegisterPartsIntoValue(),lookThroughSignExtension(),llvm::NVPTXTargetLowering::LowerFormalArguments(),LowerVAARG(),lowerVECTOR_COMPRESS(),LowerVectorMatch(),performFPExtendCombine(),performSETCCCombine(),performSTORECombine(),llvm::AMDGPUTargetLowering::performTruncateCombine(),PromoteScalarIntegerPTX(),llvm::AArch64TargetLowering::ReconstructShuffle(),llvm::RISCVTargetLowering::splitValueIntoRegisterParts(),truncateScalarIntegerArg(),tryWidenMaskForShuffle(),llvm::AArch64Subtarget::useSVEForFixedLengthVectors(),llvm::AArch64TargetLowering::useSVEForFixedLengthVectorVT(), andwidenSubVector().

Returns theEVT that represents a floating-point type with the given number of bits.

There are two floating-point types with 128 bits - this returns f128 rather than ppcf128.

Definition at line59 of fileValueTypes.h.

Referencesllvm::BitWidth, andllvm::MVT::getFloatingPointVT().

Referenced byEltsFromConsecutiveLoads(),lowerFP_TO_SINT_STORE(),LowerVECTOR_SHUFFLE(), andllvm::LoongArchTargetLowering::ReplaceNodeResults().

Returns anAPFloat semantics tag appropriate for the value type.

If this is a vector type, the element semantics are returned.

Definition at line320 of fileValueTypes.cpp.

Referencesllvm::MVT::getFltSemantics(),getScalarType(), andgetSimpleVT().

Referenced byllvm::TargetLowering::expandFMINIMUM_FMAXIMUM(),llvm::TargetLowering::expandFP_TO_INT_SAT(),llvm::TargetLowering::expandFP_TO_UINT(),llvm::SelectionDAG::FoldConstantArithmetic(),llvm::SelectionDAG::foldConstantFPMath(),FoldIntToFPToInt(),llvm::SelectionDAG::getConstantFP(),llvm::SelectionDAG::getDenormalMode(),getEstimate(),llvm::AMDGPUTargetLowering::getIsFinite(),llvm::AMDGPUTargetLowering::getIsLtSmallestNormal(),getMemsetValue(),llvm::SelectionDAG::getNeutralElement(),llvm::TargetLowering::getSqrtInputTest(),llvm::isNeutralConstant(),llvm::ConstantFPSDNode::isValueValidForType(), andllvm::TargetLowering::SimplifyDemandedBits().

Definition at line448 of fileValueTypes.h.

Referencesassert(),getVectorElementCount(),getVectorElementType(), andgetVectorVT().

Referenced bycombineAndShuffleNot(),llvm::TargetLowering::expandVecReduce(),llvm::SelectionDAG::GetSplitDestVTs(),llvm::TargetLoweringBase::getTypeConversion(),LowerVectorExtend(),llvm::ARMTargetLowering::PerformMVEExtCombine(),llvm::ARMTargetLowering::PerformMVETruncCombine(),splitStores(),truncateVectorWithPACK(), andtryFormConcatFromShuffle().

Finds the smallest simple value type that is greater than or equal to half the width of thisEVT.

If no simple value type can be found, an extended integer value type of half the size (rounded up) is returned.

Definition at line425 of fileValueTypes.h.

Referencesassert(),EVT(),getIntegerVT(),getSizeInBits(),isInteger(), andisVector().

Referenced bycombineBinOpOfZExt(),llvm::TargetLowering::expandUnalignedStore(),llvm::AMDGPUTargetLowering::LowerSDIVREM(),llvm::AMDGPUTargetLowering::LowerUDIVREM64(),performVectorExtCombine(), andskipExtensionForVectorMULL().

Returns theEVT that represents an integer with the given number of bits.

Definition at line65 of fileValueTypes.h.

Referencesllvm::BitWidth,llvm::MVT::getIntegerVT(), andllvm::MVT::INVALID_SIMPLE_VALUE_TYPE.

Referenced byllvm::BasicTTIImplBase< T >::allowsMisalignedMemoryAccesses(),llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(),llvm::TargetLowering::BuildSDIV(),llvm::TargetLowering::BuildUDIV(),canCombineShuffleToExtendVectorInreg(),combineAnd(),combineBitcastvxi1(),combineBoolVectorAndTruncateStore(),combineCMP(),combineCONCAT_VECTORS(),combineConcatVectorOfScalars(),combineExtractVectorElt(),combineExtractWithShuffle(),combineLoad(),combineOr(),combinePredicateReduction(),combineScalarAndWithMaskSetcc(),combineSelect(),combineShiftToAVG(),combineShuffleToZeroExtendVectorInReg(),combineStore(),combineVectorMulToSraBitcast(),combinevXi1ConstantToInteger(),earlyExpandDIVFIX(),EltsFromConsecutiveLoads(),llvm::TargetLowering::expandAVG(),expandDivFix(),llvm::TargetLowering::expandFixedPointMul(),llvm::TargetLowering::expandIS_FPCLASS(),llvm::TargetLowering::expandMULO(),llvm::TargetLowering::expandUnalignedLoad(),llvm::TargetLowering::expandUnalignedStore(),llvm::TargetLowering::forceExpandWideMUL(),llvm::getApproximateEVTForLLT(),llvm::SelectionDAG::getBitcastedAnyExtOrTrunc(),getCopyFromParts(),getCopyFromPartsVector(),llvm::RegsForValue::getCopyFromRegs(),getCopyToParts(),getCopyToPartsVector(),llvm::AMDGPUTargetLowering::getEquivalentMemType(),getEVT(),getHalfSizedIntegerVT(),getMemsetValue(),getPackedVectorTypeFromPredicateType(),getRoundIntegerType(),llvm::SITargetLowering::getTgtMemIntrinsic(),llvm::X86TargetLowering::getTgtMemIntrinsic(),llvm::TargetLoweringBase::getTypeConversion(),llvm::AMDGPUTargetLowering::getTypeForExtReturn(),llvm::X86TargetLowering::getTypeToTransformTo(),getVectorBitwiseReduce(),llvm::TargetLowering::IncrementMemoryAddress(),lowerBitreverseShuffle(),llvm::SystemZTargetLowering::LowerCall(),llvm::AMDGPUTargetLowering::LowerDIVREM24(),lowerFCMPIntrinsic(),llvm::SITargetLowering::LowerFormalArguments(),lowerICMPIntrinsic(),LowerPredicateLoad(),LowerPredicateStore(),llvm::SelectionDAGBuilder::lowerRangeToAssertZExt(),LowerStore(),LowerVectorAllEqual(),narrowIndex(),llvm::AMDGPUTargetLowering::PerformDAGCombine(),PerformExtractFpToIntStores(),PerformMinMaxFpToSatCombine(),performMulVectorCmpZeroCombine(),PerformSplittingMVEEXTToWideningLoad(),PerformSplittingToNarrowingStores(),PerformSplittingToWideningLoad(),PerformUMinFpToSatCombine(),performVECTOR_SHUFFLECombine(),llvm::TargetLowering::scalarizeVectorLoad(),llvm::TargetLowering::scalarizeVectorStore(),llvm::FastISel::selectFNeg(),llvm::TargetLowering::ShrinkDemandedOp(),llvm::TargetLowering::SimplifyDemandedBits(),llvm::TargetLowering::SimplifySetCC(),llvm::X86TargetLowering::targetShrinkDemandedConstant(),truncateVectorWithNARROW(),truncateVectorWithPACK(), andwidenIntegerVectorElementType().

Widens the length of the given vectorEVT up to the nearest power of 2 and returns that type.

Definition at line472 of fileValueTypes.h.

Referencesllvm::ElementCount::get(),llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(),getVectorElementCount(),getVectorElementType(),getVectorVT(),isPow2VectorType(),llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isScalable(), andllvm::Log2_32_Ceil().

Referenced byllvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), andllvm::TargetLoweringBase::getTypeConversion().

Definition at line507 of fileValueTypes.h.

ReferencesisSimple().

Referenced byAddNodeIDCustom(),llvm::SelectionDAG::getAtomic(),llvm::SelectionDAG::getGatherVP(),llvm::SelectionDAG::getGetFPEnv(),llvm::SelectionDAG::getLoad(),llvm::SelectionDAG::getLoadVP(),llvm::SelectionDAG::getMaskedGather(),llvm::SelectionDAG::getMaskedHistogram(),llvm::SelectionDAG::getMaskedLoad(),llvm::SelectionDAG::getMaskedScatter(),llvm::SelectionDAG::getMaskedStore(),llvm::SelectionDAG::getMemIntrinsicNode(),llvm::SelectionDAG::getScatterVP(),llvm::SelectionDAG::getSetFPEnv(),llvm::SelectionDAG::getStore(),llvm::SelectionDAG::getStoreVP(),llvm::SelectionDAG::getStridedLoadVP(),llvm::SelectionDAG::getStridedStoreVP(),llvm::SelectionDAG::getTruncStore(),llvm::SelectionDAG::getTruncStoreVP(),llvm::SelectionDAG::getTruncStridedStoreVP(), andllvm::SelectionDAG::getVTList().

Given aRISCV vector tuple type, return the num_fields.

Definition at line359 of fileValueTypes.h.

Referenced bygetEVTString(),llvm::RISCVTargetLowering::LowerOperation(),llvm::RISCVTargetLowering::PerformDAGCombine(), andllvm::RISCVTargetLowering::splitValueIntoRegisterParts().

Rounds the bit-width of the given integerEVT up to the nearest power of two (and at least to eight), and returns the integerEVT with that number of bits.

Definition at line414 of fileValueTypes.h.

Referencesassert(),llvm::bit_ceil(),llvm::BitWidth,EVT(),getIntegerVT(),getSizeInBits(),isInteger(), andisVector().

Referenced byllvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(),llvm::TargetLoweringBase::getTypeConversion(), andnarrowIndex().

Definition at line380 of fileValueTypes.h.

Referencesllvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getFixedValue(),getScalarType(), andgetSizeInBits().

Referenced byllvm::ARMTargetLowering::allowsMisalignedMemoryAccesses(),llvm::AArch64TargetLowering::allowsMisalignedMemoryAccesses(),areLoadedOffsetButOtherwiseSame(),llvm::TargetLowering::BuildSDIV(),llvm::TargetLowering::BuildUDIV(),canCombineShuffleToExtendVectorInreg(),canExpandVectorCTPOP(),canLowerSRLToRoundingShiftForVT(),canonicalizeShuffleWithOp(),canReduceVMulWidth(),combineAnd(),combineAndMaskToShift(),combineArithReduction(),combineAVG(),combineBinOpOfExtractToReduceTree(),combineBinOpOfZExt(),combineBitcast(),combineBitOpWithMOVMSK(),combineBVOfVecSExt(),combineCMP(),combineConcatVectorOps(),combineConstantPoolLoads(),combineEXTEND_VECTOR_INREG(),combineEXTRACT_SUBVECTOR(),combineExtractVectorElt(),combineExtractWithShuffle(),combineHorizOpWithShuffle(),combineI8TruncStore(),combineLogicBlendIntoConditionalNegate(),combineLogicBlendIntoPBLENDV(),combineMaskedLoad(),combineMaskedStore(),combineOr(),combineOrXorWithSETCC(),combinePTESTCC(),combineScalarAndWithMaskSetcc(),combineSelect(),combineSetCC(),combineShiftAnd1ToBitTest(),combineShiftLeft(),combineShiftRightArithmetic(),combineShiftRightLogical(),combineShiftToAVG(),combineShiftToMULH(),combineShuffleToZeroExtendVectorInReg(),combineSIntToFP(),combineStore(),combineTargetShuffle(),combineTruncatedArithmetic(),combineTruncationShuffle(),combineTruncOfSraSext(),combineTruncSelectToSMaxUSat(),combineUIntToFP(),combineVectorCompareAndMaskUnaryOp(),combineVectorInsert(),combineVectorMulToSraBitcast(),combineVectorPack(),combineVectorShiftImm(),combineVSelectWithAllOnesOrZeros(),combineVTRUNC(),combineZext(),llvm::SelectionDAG::computeKnownBits(),llvm::ARMTargetLowering::computeKnownBitsForTargetNode(),llvm::AArch64TargetLowering::computeKnownBitsForTargetNode(),llvm::SystemZTargetLowering::computeKnownBitsForTargetNode(),llvm::X86TargetLowering::computeKnownBitsForTargetNode(),llvm::SelectionDAG::ComputeNumSignBits(),computeNumSignBitsBinOp(),llvm::AArch64TargetLowering::ComputeNumSignBitsForTargetNode(),llvm::SystemZTargetLowering::ComputeNumSignBitsForTargetNode(),llvm::X86TargetLowering::ComputeNumSignBitsForTargetNode(),createBSWAPShuffleMask(),createShuffleMaskFromVSELECT(),llvm::createUnpackShuffleMask(),createVariablePermute(),llvm::X86TargetLowering::decomposeMulByConstant(),llvm::XtensaTargetLowering::decomposeMulByConstant(),detectSSatPattern(),detectSSatSPattern(),detectSSatUPattern(),detectUSatPattern(),detectUSatUPattern(),earlyExpandDIVFIX(),EltsFromConsecutiveLoads(),EmitVectorComparison(),llvm::TargetLowering::expandABS(),llvm::TargetLowering::expandAVG(),llvm::TargetLowering::expandBITREVERSE(),llvm::TargetLowering::expandCMP(),llvm::TargetLowering::expandCTLZ(),llvm::TargetLowering::expandCTPOP(),llvm::TargetLowering::expandCTTZ(),llvm::TargetLowering::expandDIVREMByConstant(),llvm::TargetLowering::expandFixedPointMul(),llvm::TargetLowering::expandFP_TO_INT_SAT(),llvm::TargetLowering::expandFP_TO_SINT(),llvm::TargetLowering::expandFP_TO_UINT(),llvm::TargetLowering::expandFunnelShift(),llvm::TargetLowering::expandIS_FPCLASS(),llvm::TargetLowering::expandMUL_LOHI(),llvm::TargetLowering::expandMULO(),llvm::TargetLowering::expandROT(),llvm::TargetLowering::expandRoundInexactToOdd(),llvm::TargetLowering::expandShiftParts(),llvm::TargetLowering::expandShlSat(),llvm::TargetLowering::expandVPBITREVERSE(),llvm::TargetLowering::expandVPCTLZ(),llvm::TargetLowering::expandVPCTPOP(),expandVPFunnelShift(),extractShiftForRotate(),findMoreOptimalIndexType(),foldAddSubMasked1(),foldAddSubOfSignBit(),foldAndToUsubsat(),foldBoolSelectToLogic(),llvm::SelectionDAG::FoldConstantArithmetic(),FoldIntToFPToInt(),foldSubCtlzNot(),foldVSelectToSignBitSplatMask(),GeneratePerfectShuffle(),generateSToVPermutedForVecShuffle(),llvm::SelectionDAG::getAllOnesConstant(),llvm::GCNTTIImpl::getArithmeticReductionCost(),llvm::ARMTTIImpl::getArithmeticReductionCost(),llvm::SelectionDAG::getConstant(),llvm::BuildVectorSDNode::getConstantRawBits(),getEXTEND_VECTOR_INREG(),getFauxShuffleMask(),llvm::AArch64TTIImpl::getIntrinsicInstrCost(),llvm::ARMTTIImpl::getIntrinsicInstrCost(),llvm::AArch64TTIImpl::getMemoryOpCost(),getMemsetValue(),llvm::GCNTTIImpl::getMinMaxReductionCost(),llvm::ARMTTIImpl::getMinMaxReductionCost(),llvm::SelectionDAG::getNode(),llvm::SelectionDAG::getShiftAmountConstant(),llvm::SelectionDAG::getSignedConstant(),llvm::SelectionDAG::getStepVector(),getTargetConstantBitsFromNode(),getTruncatedUSUBSAT(),getVectorShuffleOpcode(),llvm::SelectionDAG::getVPZeroExtendInReg(),llvm::SelectionDAG::getZeroExtendInReg(),llvm::TargetLowering::IncrementMemoryAddress(),llvm::AArch64TargetLowering::isComplexDeinterleavingOperationSupported(),llvm::ARMTargetLowering::isComplexDeinterleavingOperationSupported(),llvm::BuildVectorSDNode::isConstantSequence(),llvm::BuildVectorSDNode::isConstantSplat(),isExtendedBUILD_VECTOR(),isFNEG(),llvm::RISCVTargetLowering::isFPImmLegal(),llvm::SelectionDAG::isKnownToBeAPowerOfTwo(),isLegalBitRotate(),llvm::AMDGPUTargetLowering::isLoadBitCastBeneficial(),llvm::AArch64TargetLowering::isMulAddWithConstProfitable(),llvm::ARMTargetLowering::isMulAddWithConstProfitable(),llvm::RISCVTargetLowering::isMulAddWithConstProfitable(),llvm::AMDGPUTargetLowering::isNarrowingProfitable(),llvm::AArch64TargetLowering::isShuffleMaskLegal(),llvm::ARMTargetLowering::isShuffleMaskLegal(),llvm::SelectionDAG::isSplatValue(),isValidEGW(),isVectorElementSwap(),llvm::isVREVMask(),isVShiftLImm(),isVShiftRImm(),isVTRN_v_undef_Mask(),isVTRNMask(),isVUZP_v_undef_Mask(),isVUZPMask(),isVZIP_v_undef_Mask(),isVZIPMask(),isWideDUPMask(),lower1BitShuffle(),lowerBALLOTIntrinsic(),lowerBitreverseShuffle(),LowerCONCAT_VECTORS(),LowerCTPOP(),llvm::AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(),LowerEXTRACT_SUBVECTOR(),LowerEXTRACT_VECTOR_ELT(),LowerEXTRACT_VECTOR_ELT_i1(),LowerFMINIMUM_FMAXIMUM(),llvm::R600TargetLowering::LowerFormalArguments(),LowerFP_TO_INT_SAT(),LowerINSERT_VECTOR_ELT_i1(),lowerMSABitClearImm(),LowerVECTOR_SHUFFLE(),LowerVECTOR_SHUFFLEUsingMovs(),LowerVectorAllEqual(),lowerVectorBitClearImm(),lowerVectorBitRevImm(),lowerVectorBitSetImm(),MatchVectorAllEqualTest(),narrowIndex(),PerformBITCASTCombine(),performBuildShuffleExtendCombine(),performCONCAT_VECTORSCombine(),performConcatVectorsCombine(),performDSPShiftCombine(),performExtBinopLoadFold(),PerformEXTRACTCombine(),performFP_TO_INTCombine(),performFpToIntCombine(),performGatherLoadCombine(),performLOADCombine(),performMulVectorCmpZeroCombine(),PerformMVEVMULLCombine(),performPostLD1Combine(),performScatterStoreCombine(),performSETCCCombine(),PerformSplittingMVEEXTToWideningLoad(),PerformSplittingMVETruncToNarrowingStores(),PerformSplittingToWideningLoad(),llvm::AMDGPUTargetLowering::performTruncateCombine(),performTruncateCombine(),PerformTruncatingStoreCombine(),performUADDVZextCombine(),PerformVDUPLANECombine(),PerformVECREDUCE_ADDCombine(),performVecReduceAddCombine(),performVECTOR_SHUFFLECombine(),performVP_STORECombine(),PerformVQDMULHCombine(),performVSelectCombine(),PerformVSetCCToVCTPCombine(),performZExtDeinterleaveShuffleCombine(),performZExtUZPCombine(),llvm::X86TargetLowering::preferedOpcodeForCmpEqPiecesOfOperand(),llvm::ARMTargetLowering::preferIncOfAddToSubOfNot(),llvm::AArch64TargetLowering::ReconstructShuffle(),reduceBuildVecToShuffleWithZero(),llvm::X86TargetLowering::ReplaceNodeResults(),SaturateWidenedDIVFIX(),llvm::AMDGPUDAGToDAGISel::Select(),selectUmullSmull(),llvm::TargetLowering::SimplifyDemandedBits(),llvm::TargetLowering::SimplifyDemandedVectorElts(),llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(),llvm::TargetLowering::SimplifyMultipleUseDemandedBits(),llvm::TargetLowering::SimplifySetCC(),SkipExtensionForVMULL(),llvm::SelectionDAG::SplitEVL(),stripModuloOnShift(),supportedVectorShiftWithImm(),supportedVectorVarShift(),llvm::X86TargetLowering::targetShrinkDemandedConstant(),truncateVectorWithNARROW(),truncateVectorWithPACK(),TryCombineBaseUpdate(),tryCombineToBSL(),tryLowerToSLI(),tryToFoldExtendOfConstant(),tryToWidenSetCCOperands(), andvisitORCommutative().

Definition at line397 of fileValueTypes.h.

Referencesllvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getFixedValue(),getScalarType(), andgetStoreSize().

Referenced bymatchIndexAsShuffle(),matchIndexAsWiderOp(), andllvm::RISCVTargetLowering::PerformDAGCombine().

If this is a vector type, return the element type, otherwise return this.

Definition at line318 of fileValueTypes.h.

ReferencesgetVectorElementType(), andisVector().

Referenced byllvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(),BuildExactSDIV(),BuildExactUDIV(),llvm::TargetLowering::BuildSDIV(),llvm::TargetLowering::BuildUDIV(),changeElementType(),combineAnd(),combineAndnp(),combineArithReduction(),combineAVG(),combineBitcast(),combineBitcastvxi1(),combineBITREVERSE(),combineConcatVectorOps(),combineExtractVectorElt(),combineExtractWithShuffle(),combineFMA(),combineFneg(),combineFP_EXTEND(),combineLoad(),combineMinMaxReduction(),combineSCALAR_TO_VECTOR(),combineSelect(),combineShuffleOfScalars(),combineSIntToFP(),combineTargetShuffle(),combineToExtendBoolVectorInReg(),combineTruncate(),combineTruncatedArithmetic(),combineUIntToFP(),CombineVMOVDRRCandidateWithVecOp(),combineVSelectWithAllOnesOrZeros(),llvm::X86TargetLowering::computeKnownBitsForTargetNode(),concatSubVectors(),llvm::createUnpackShuffleMask(),llvm::SITargetLowering::denormalsEnabledForType(),detectPMADDUBSW(),EltsFromConsecutiveLoads(),llvm::TargetLowering::expandFP_ROUND(),llvm::TargetLowering::expandIS_FPCLASS(),llvm::TargetLowering::expandRoundInexactToOdd(),llvm::TargetLowering::expandUINT_TO_FP(),llvm::TargetLowering::expandVECTOR_COMPRESS(),llvm::TargetLowering::expandVectorFindLastActive(),llvm::TargetLowering::expandVPCTTZElements(),foldCONCAT_VECTORS(),llvm::SelectionDAG::FoldConstantArithmetic(),llvm::SelectionDAG::FoldSetCC(),foldShuffleOfConcatUndefs(),llvm::ARMTTIImpl::getCastInstrCost(),llvm::SelectionDAG::getConstant(),llvm::SelectionDAG::getConstantFP(),getCopyFromPartsVector(),getCopyToPartsVector(),getEstimateRefinementSteps(),getFauxShuffleMask(),getFltSemantics(),llvm::SelectionDAG::getLoad(),getMemsetStores(),getMemsetValue(),llvm::X86TargetLowering::getNegatedExpression(),llvm::SelectionDAG::getNode(),llvm::SITargetLowering::getNumRegistersForCallingConv(),getReciprocalOpName(),llvm::SITargetLowering::getRegisterTypeForCallingConv(),getScalarSizeInBits(),getScalarStoreSize(),llvm::SDValue::getScalarValueSizeInBits(),llvm::SelectionDAG::getSplatValue(),llvm::SelectionDAG::getTruncStore(),llvm::SelectionDAG::getTruncStoreVP(),llvm::SelectionDAG::getTruncStridedStoreVP(),llvm::X86TTIImpl::getVectorInstrCost(),getVectorShuffle(),llvm::SITargetLowering::getVectorTypeBreakdownForCallingConv(),llvm::AArch64TargetLowering::isComplexDeinterleavingOperationSupported(),llvm::ARMTargetLowering::isComplexDeinterleavingOperationSupported(),llvm::X86TargetLowering::isExtractVecEltCheap(),llvm::AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(),llvm::SITargetLowering::isFMAFasterThanFMulAndFAdd(),llvm::LoongArchTargetLowering::isFMAFasterThanFMulAndFAdd(),llvm::RISCVTargetLowering::isFMAFasterThanFMulAndFAdd(),llvm::SystemZTargetLowering::isFMAFasterThanFMulAndFAdd(),llvm::X86TargetLowering::isFMAFasterThanFMulAndFAdd(),llvm::AMDGPUTargetLowering::isFNegFree(),llvm::SITargetLowering::isFPExtFoldable(),llvm::AMDGPUTargetLowering::isFPImmLegal(),llvm::RISCVTargetLowering::isLegalInterleavedAccessType(),llvm::RISCVTTIImpl::isLegalMaskedGatherScatter(),llvm::RISCVTTIImpl::isLegalMaskedLoadStore(),llvm::RISCVTargetLowering::isLegalStridedLoadStore(),llvm::AMDGPUTargetLowering::isLoadBitCastBeneficial(),isSaturatingMinMax(),llvm::X86TargetLowering::isVectorLoadExtDesirable(),LowerCONCAT_VECTORS_i1(),LowerEXTRACT_SUBVECTOR(),llvm::AMDGPUTargetLowering::lowerFEXP(),llvm::SITargetLowering::lowerFP_EXTEND(),LowerFP_TO_INT_SAT(),llvm::AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(),LowerTruncate(),LowerVECTOR_SHUFFLEUsingOneOff(),LowerVectorExtend(),lowerVectorSplatImm(),llvm::SelectionDAG::matchBinOpReduction(),matchPMADDWD_2(),narrowExtractedVectorBinOp(),padEltsToUndef(),performBitcastCombine(),performBuildShuffleExtendCombine(),performExtBinopLoadFold(),performLOADCombine(),PerformMinMaxFpToSatCombine(),llvm::AMDGPUTargetLowering::performMulCombine(),performTruncateCombine(),PerformTruncatingStoreCombine(),PerformUMinFpToSatCombine(),performVectorExtCombine(),PerformVQDMULHCombine(),performVSelectCombine(),llvm::X86TargetLowering::preferedOpcodeForCmpEqPiecesOfOperand(),ReplaceAddWithADDP(),scalarizeExtEltFP(),llvm::TargetLowering::scalarizeVectorLoad(),llvm::TargetLowering::scalarizeVectorStore(),setInfoSVEStN(),llvm::AMDGPUTargetLowering::shouldCombineMemoryType(),llvm::X86TargetLowering::shouldFoldSelectWithIdentityConstant(),llvm::AArch64TargetLowering::shouldRemoveRedundantExtend(),llvm::RISCVTargetLowering::shouldScalarizeBinop(),llvm::X86TargetLowering::shouldScalarizeBinop(),llvm::AMDGPUTargetLowering::ShouldShrinkFPConstant(),llvm::TargetLowering::SimplifyDemandedVectorElts(),llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(),simplifyDivRem(),llvm::TargetLowering::SimplifySetCC(),skipExtensionForVectorMULL(),takeInexpensiveLog2(),tryToFoldExtendOfConstant(), andwidenSubVector().

Return the SimpleValueType held in the specified simpleEVT.

Definition at line311 of fileValueTypes.h.

Referencesassert(), andisSimple().

Referenced byAddCombineBUILD_VECTORToVPADDL(),llvm::HexagonTargetLowering::allowsMemoryAccess(),llvm::ARMTargetLowering::allowsMisalignedMemoryAccesses(),llvm::HexagonTargetLowering::allowsMisalignedMemoryAccesses(),llvm::PPCTargetLowering::allowsMisalignedMemoryAccesses(),llvm::MipsSETargetLowering::allowsMisalignedMemoryAccesses(),analyzeCallOperands(),llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(),llvm::TargetLowering::BuildSDIV(),llvm::TargetLowering::BuildUDIV(),canonicalizeShuffleMaskWithHorizOp(),changeTypeToInteger(),changeVectorElementType(),changeVectorElementTypeToInteger(),combineAndMaskToShift(),combineArithReduction(),combineBitcastvxi1(),combineCONCAT_VECTORS(),combineConcatVectorOps(),combineExtractWithShuffle(),combineSCALAR_TO_VECTOR(),combineScalarCTPOPToVCPOP(),combineSelect(),llvm::VETargetLowering::combineSelectCC(),combineStore(),combineTargetShuffle(),combineVectorPack(),combineVectorShiftImm(),combineVectorShiftVar(),ComputePTXValueVTs(),llvm::TargetLowering::createSelectForFMINNUM_FMAXNUM(),createVariablePermute(),llvm::SITargetLowering::denormalsEnabledForType(),EltsFromConsecutiveLoads(),llvm::TargetLowering::expandBSWAP(),llvm::TargetLowering::expandIS_FPCLASS(),llvm::TargetLowering::expandVectorFindLastActive(),llvm::TargetLowering::expandVPBSWAP(),llvm::TargetLowering::findOptimalMemOpLowering(),foldFCmpToFPClassTest(),llvm::SelectionDAG::FoldSetCC(),foldVectorXorShiftIntoCmp(),llvm::AArch64TTIImpl::getArithmeticInstrCost(),llvm::X86TTIImpl::getArithmeticReductionCost(),llvm::TargetLoweringBase::getAtomicLoadExtAction(),llvm::AArch64TTIImpl::getCastInstrCost(),llvm::ARMTTIImpl::getCastInstrCost(),llvm::X86TTIImpl::getCastInstrCost(),llvm::AArch64TTIImpl::getCmpSelInstrCost(),llvm::ARMTTIImpl::getCmpSelInstrCost(),getContainerForFixedLengthVector(),getExtensionTo64Bits(),getFltSemantics(),llvm::RISCVTTIImpl::getInterleavedMemoryOpCost(),llvm::X86TTIImpl::getInterleavedMemoryOpCost(),llvm::AArch64TTIImpl::getIntrinsicInstrCost(),getLdStRegType(),llvm::TargetLoweringBase::getLoadExtAction(),llvm::X86TTIImpl::getMinMaxReductionCost(),llvm::TargetLoweringBase::getNumRegisters(),llvm::TargetLoweringBase::getOperationAction(),getPackedSVEVectorVT(),llvm::HexagonTargetLowering::getPostIndexedAddressParts(),getPredicateForFixedLengthVector(),llvm::SPIRVTargetLowering::getPreferredSwitchConditionType(),llvm::FastISel::getRegForGEPIndex(),llvm::FastISel::getRegForValue(),llvm::TargetLoweringBase::getRegisterType(),llvm::SITargetLowering::getRegisterTypeForCallingConv(),llvm::M68kTargetLowering::getScalarShiftAmountTy(),llvm::X86TargetLowering::getSetCCResultType(),llvm::X86TTIImpl::getShuffleCost(),getShuffleScalarElt(),llvm::SDValue::getSimpleValueType(),llvm::TargetLoweringBase::getSimpleValueType(),llvm::SDNode::getSimpleValueType(),llvm::AArch64TTIImpl::getSpliceCost(),getSVEContainerType(),llvm::TargetLoweringBase::getTruncStoreAction(),llvm::TargetLoweringBase::getTypeConversion(),llvm::BasicTTIImplBase< T >::getTypeLegalizationCost(),llvm::SelectionDAG::getValueType(),getVectorLoweringShape(),getVectorTyFromPredicateVector(),llvm::TargetLoweringBase::getVectorTypeBreakdown(),llvm::SITargetLowering::getVectorTypeBreakdownForCallingConv(),llvm::MipsTargetLowering::getVectorTypeBreakdownForCallingConv(),llvm::SelectionDAG::getVTList(),llvm::ISD::InputArg::InputArg(),is32Bit(),isAddSubOrSubAdd(),isConstantSplatVectorMaskForType(),llvm::HexagonTargetLowering::isExtractSubvectorCheap(),llvm::AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(),llvm::SITargetLowering::isFMAFasterThanFMulAndFAdd(),llvm::LoongArchTargetLowering::isFMAFasterThanFMulAndFAdd(),llvm::RISCVTargetLowering::isFMAFasterThanFMulAndFAdd(),llvm::SystemZTargetLowering::isFMAFasterThanFMulAndFAdd(),llvm::X86TargetLowering::isFMAFasterThanFMulAndFAdd(),llvm::ARMTargetLowering::isFNegFree(),llvm::PPCTargetLowering::isFPImmLegal(),llvm::HexagonSubtarget::isHVXVectorType(),llvm::TargetLoweringBase::isIndexedLoadLegal(),llvm::TargetLoweringBase::isIndexedMaskedLoadLegal(),llvm::TargetLoweringBase::isIndexedMaskedStoreLegal(),llvm::TargetLoweringBase::isIndexedStoreLegal(),isLegalAddressImmediate(),llvm::ARMTargetLowering::isLegalAddressingMode(),llvm::RISCVTargetLowering::isLegalElementTypeForRVV(),llvm::RISCVTargetLowering::isLegalInterleavedAccessType(),isLegalT1AddressImmediate(),isLegalT2AddressImmediate(),llvm::ARMTargetLowering::isLegalT2ScaledAddressingMode(),llvm::TargetLoweringBase::isLoadBitCastBeneficial(),llvm::RISCVTargetLowering::isShuffleMaskLegal(),llvm::X86TargetLowering::isShuffleMaskLegal(),isSupportedType(),llvm::HexagonTargetLowering::isTruncateFree(),llvm::HexagonSubtarget::isTypeForHVX(),llvm::TargetLoweringBase::isTypeLegal(),llvm::HexagonInstrInfo::isValidAutoIncImm(),isValidIndexedLoad(),llvm::ARMTargetLowering::isZExtFree(),llvm::X86TargetLowering::isZExtFree(),llvm::XCoreTargetLowering::isZExtFree(),LowerADDSUBSAT(),llvm::AVRTargetLowering::LowerAsmOperandForConstraint(),llvm::NVPTXTargetLowering::LowerCall(),LowerCONCAT_VECTORS_i1(),LowerEXTRACT_SUBVECTOR(),LowerFMINIMUM_FMAXIMUM(),llvm::SystemZTargetLowering::LowerFormalArguments(),llvm::InlineAsmLowering::lowerInlineAsm(),lowerLaneOp(),llvm::HexagonTargetLowering::LowerLoad(),lowerRegToMasks(),llvm::HexagonTargetLowering::LowerStore(),llvm::VETargetLowering::lowerToVVP(),lowerVECTOR_COMPRESS(),llvm::VETargetLowering::lowerVVP_GATHER_SCATTER(),NarrowVector(),llvm::TargetLowering::ParseConstraints(),performCONCAT_VECTORSCombine(),llvm::PPCTargetLowering::PerformDAGCombine(),llvm::RISCVTargetLowering::PerformDAGCombine(),PerformEXTRACTCombine(),performFP_TO_INTCombine(),performLOADCombine(),performScatterStoreCombine(),performUADDVZextCombine(),performUzpCombine(),performVSelectCombine(),llvm::SITargetLowering::PostISelFolding(),ReplaceINTRINSIC_W_CHAIN(),llvm::X86TargetLowering::ReplaceNodeResults(),llvm::FastISel::selectBinaryOp(),llvm::FastISel::selectBitCast(),llvm::FastISel::selectCast(),llvm::HexagonDAGToDAGISel::SelectExtractSubvector(),llvm::HvxSelector::selectExtractSubvector(),llvm::FastISel::selectExtractValue(),llvm::FastISel::selectFNeg(),llvm::FastISel::selectFreeze(),llvm::FastISel::selectGetElementPtr(),llvm::HexagonDAGToDAGISel::SelectIndexedLoad(),llvm::HexagonDAGToDAGISel::SelectIndexedStore(),llvm::ARMTargetLowering::shouldConvertFpToSat(),llvm::RISCVTargetLowering::shouldConvertFpToSat(),llvm::X86InstrInfo::shouldScheduleLoadsNear(),llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(),llvm::X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode(),llvm::TargetLowering::SimplifySetCC(),unpackFromRegLoc(),usePartialVectorLoads(),llvm::AArch64TargetLowering::useSVEForFixedLengthVectorVT(),llvm::SelectionDAGBuilder::visitBitTestHeader(),WidenVector(),X86ChooseCmpImmediateOpcode(), andX86ChooseCmpOpcode().

Return the size of the specified value type in bits.

If the value type is a scalable vector type, the scalable property will be set and the runtime size will be a positive integer multiple of the base size.

Definition at line368 of fileValueTypes.h.

ReferencesisSimple().

Referenced byAddRequiredExtensionForVMULL(),llvm::X86TargetLowering::allowsMemoryAccess(),llvm::SITargetLowering::allowsMisalignedMemoryAccesses(),allUsesTruncate(),llvm::SelectionDAG::areNonVolatileConsecutiveLoads(),bitsEq(),llvm::TargetLowering::BuildSDIV(),llvm::TargetLowering::buildSDIVPow2WithCMov(),llvm::TargetLowering::BuildUDIV(),BuildVectorFromScalar(),llvm::AArch64TargetLowering::canMergeStoresTo(),llvm::ARMTargetLowering::canMergeStoresTo(),llvm::X86TargetLowering::canMergeStoresTo(),llvm::R600TargetLowering::canMergeStoresTo(),llvm::SITargetLowering::canMergeStoresTo(),canonicalizeShuffleMaskWithHorizOp(),checkZExtBool(),clampDynamicVectorIndex(),collectConcatOps(),combineAddOfBooleanXor(),combineAddOfPMADDWD(),combineAnd(),combineArithReduction(),combineBasicSADPattern(),combineBEXTR(),combineBitcastvxi1(),combineBitOpWithMOVMSK(),combineBROADCAST_LOAD(),combineCMov(),combineCMP(),combineCONCAT_VECTORS(),combineConcatVectorOfExtracts(),combineConcatVectorOfScalars(),combineConcatVectorOps(),combineConstantPoolLoads(),combineDeMorganOfBoolean(),combineEXTEND_VECTOR_INREG(),combineEXTRACT_SUBVECTOR(),combineExtractFromVectorLoad(),combineExtractWithShuffle(),combineExtSetcc(),combineI8TruncStore(),combineLoad(),combineMinMaxReduction(),combineMulToPMADDWD(),combinePMULH(),combinePredicateReduction(),combineScalarAndWithMaskSetcc(),combineSelect(),combineSelectAndUse(),combineSetCC(),combineShiftRightArithmetic(),combineShiftToPMULH(),combineSignExtendInReg(),combineStore(),combineSubShiftToOrcB(),combineTargetShuffle(),combineToExtendBoolVectorInReg(),combineToFPTruncExtElt(),combineTruncateWithSat(),combineVectorCompareAndMaskUnaryOp(),combineVectorPack(),combineVectorSizedSetCCEquality(),combineVEXTRACT_STORE(),combineVPDPBUSDPattern(),combineX86ShuffleChainWithExtract(),combineX86ShufflesRecursively(),llvm::SelectionDAG::computeKnownBits(),llvm::ARMTargetLowering::computeKnownBitsForTargetNode(),llvm::FunctionLoweringInfo::ComputePHILiveOutRegInfo(),concatSubVectors(),ConstantBuildVector(),constructDup(),constructRetValue(),convertIntLogicToFPLogic(),createPSADBW(),llvm::createUnpackShuffleMask(),llvm::LoongArchTargetLowering::decomposeMulByConstant(),llvm::RISCVTargetLowering::decomposeMulByConstant(),llvm::XtensaTargetLowering::decomposeMulByConstant(),EltsFromConsecutiveLoads(),EmitVectorComparison(),Expand64BitShift(),expandDivFix(),llvm::TargetLowering::expandMULO(),llvm::TargetLowering::expandUnalignedLoad(),llvm::TargetLowering::expandUnalignedStore(),extractSubVector(),llvm::SwitchCG::SwitchLowering::findBitTestClusters(),findMemType(),llvm::TargetLowering::findOptimalMemOpLowering(),llvm::SelectionDAG::FoldConstantArithmetic(),foldExtendedSignBitTest(),foldVectorXorShiftIntoCmp(),foldXorTruncShiftIntoCmp(),llvm::TargetLowering::forceExpandMultiply(),llvm::TargetLowering::forceExpandWideMUL(),GenerateFixedLengthSVETBL(),GeneratePerfectShuffle(),GenerateTBL(),llvm::ARMTTIImpl::getCastInstrCost(),llvm::SelectionDAG::getConstant(),getCopyFromParts(),getCopyFromPartsVector(),getCopyToParts(),getCopyToPartsVector(),llvm::SelectionDAG::getElementCount(),getEVTString(),getEXTEND_VECTOR_INREG(),llvm::ARMTTIImpl::getExtendedReductionCost(),getExtensionTo64Bits(),getExtFactor(),getFauxShuffleMask(),getFixedSizeInBits(),getHalfSizedIntegerVT(),getHorizDemandedElts(),getLeftShift(),getLoadStackGuard(),getMemcpyLoadsAndStores(),getMemmoveLoadsAndStores(),getMemsetStores(),getMemsetStringVal(),getMemsetValue(),llvm::ARMTTIImpl::getMulAccReductionCost(),llvm::SelectionDAG::getNeutralElement(),llvm::SelectionDAG::getNode(),llvm::TargetLoweringBase::getNumRegisters(),llvm::SITargetLowering::getNumRegistersForCallingConv(),llvm::MipsTargetLowering::getNumRegistersForCallingConv(),llvm::SPIRVTargetLowering::getNumRegistersForCallingConv(),getOnesVector(),getPackDemandedElts(),getPredicateForFixedLengthVector(),llvm::X86TargetLowering::getPreferredSwitchConditionType(),llvm::SITargetLowering::getRegisterTypeForCallingConv(),llvm::MipsTargetLowering::getRegisterTypeForCallingConv(),llvm::SystemZTargetLowering::getRegisterTypeForCallingConv(),getRoundIntegerType(),llvm::XtensaTargetLowering::getScalarShiftAmountTy(),getScalarSizeInBits(),llvm::TargetLoweringBase::getShiftAmountTy(),llvm::X86TTIImpl::getShuffleCost(),getStoreSize(),getTargetConstantBitsFromNode(),llvm::TargetLoweringBase::getTypeConversion(),llvm::AMDGPUTargetLowering::getTypeForExtReturn(),llvm::MipsTargetLowering::getTypeForExtReturn(),llvm::SelectionDAGBuilder::getValueImpl(),llvm::SDValue::getValueSizeInBits(),llvm::SDNode::getValueSizeInBits(),getVectorBitwiseReduce(),llvm::X86TTIImpl::getVectorInstrCost(),getVectorLoweringShape(),llvm::TargetLowering::getVectorSubVecPointer(),llvm::TargetLoweringBase::getVectorTypeBreakdown(),llvm::AArch64TargetLowering::getVectorTypeBreakdownForCallingConv(),llvm::SITargetLowering::getVectorTypeBreakdownForCallingConv(),llvm::SelectionDAG::getVScale(),llvm::AArch64TargetLowering::hasAndNot(),llvm::X86TargetLowering::hasAndNot(),llvm::AArch64TargetLowering::hasPairedLoad(),llvm::TargetLowering::IncrementMemoryAddress(),insertSubVector(),isBitfieldDstMask(),isBitfieldExtractOpFromAnd(),isBitfieldExtractOpFromSExtInReg(),isBitfieldExtractOpFromShr(),isBitfieldPositioningOp(),isBitfieldPositioningOpFromAnd(),isByteSized(),isConcatMask(),isConsecutiveLSLoc(),llvm::BuildVectorSDNode::isConstantSplat(),llvm::RISCVTargetLowering::isDesirableToCommuteWithShift(),isExtendedFrom16Bits(),llvm::RISCVTargetLowering::isExtractSubvectorCheap(),llvm::X86TargetLowering::isExtractSubvectorCheap(),llvm::SITargetLowering::isExtractVecEltCheap(),llvm::AArch64TargetLowering::isFPImmLegal(),llvm::HexagonSubtarget::isHVXVectorType(),isI24(),isLegalT2AddressImmediate(),llvm::AMDGPUTargetLowering::isLoadBitCastBeneficial(),llvm::X86TargetLowering::isMemoryAccessFast(),llvm::AArch64TargetLowering::isMulAddWithConstProfitable(),llvm::AMDGPUTargetLowering::isNarrowingProfitable(),isPackedVectorType(),isPerfectIncrement(),isRound(),isSaturatingMinMax(),llvm::AArch64TargetLowering::isShuffleMaskLegal(),llvm::AMDGPUTargetLowering::isTruncateFree(),llvm::ARMTargetLowering::isTruncateFree(),llvm::RISCVTargetLowering::isTruncateFree(),llvm::PPCTargetLowering::isTruncateFree(),llvm::X86TargetLowering::isTruncateFree(),llvm::AArch64CallLowering::isTypeIsValidForThisReturn(),isUnpackedVectorVT(),llvm::HexagonInstrInfo::isValidAutoIncImm(),isValidEGW(),isVectorElementSwap(),isWideDUPMask(),isWorthFoldingIntoOrrWithShift(),isZeroSized(),llvm::AArch64TargetLowering::isZExtFree(),llvm::RISCVTargetLowering::joinRegisterPartsIntoValue(),llvm::SystemZTargetLowering::joinRegisterPartsIntoValue(),knownBitsGE(),knownBitsGT(),knownBitsLE(),knownBitsLT(),lowerAddSubToHorizontalOp(),llvm::NVPTXTargetLowering::LowerCall(),llvm::TargetLowering::LowerCallTo(),llvm::TargetLowering::lowerCmpEqZeroToCtlzSrl(),llvm::AMDGPUTargetLowering::LowerCONCAT_VECTORS(),LowerCTTZ(),llvm::AMDGPUTargetLowering::LowerDIVREM24(),llvm::SITargetLowering::LowerFormalArguments(),llvm::SystemZTargetLowering::LowerFormalArguments(),lowerLaneOp(),llvm::MipsTargetLowering::lowerLOAD(),llvm::RISCVTargetLowering::LowerOperation(),LowerPredicateLoad(),LowerPredicateStore(),llvm::HexagonTargetLowering::LowerSETCC(),llvm::LanaiTargetLowering::LowerSHL_PARTS(),llvm::MipsTargetLowering::lowerSTORE(),LowerSVEIntrinsicEXT(),llvm::AMDGPUTargetLowering::LowerUDIVREM64(),LowerVAARG(),llvm::VETargetLowering::lowerVAARG(),LowerVectorAllEqual(),lowerVectorSplatImm(),lowerX86CmpEqZeroToCtlzSrl(),llvm::ARMTargetLowering::LowerXConstraint(),MatchingStackOffset(),matchPMADDWD_2(),matchTruncateWithPACK(),MatchVectorAllEqualTest(),llvm::ARMTTIImpl::maybeLoweredToCall(),narrowExtractedVectorBinOp(),NormalizeBuildVector(),performANDCombine(),PerformARMBUILD_VECTORCombine(),performBITREVERSECombine(),llvm::ARMTargetLowering::PerformCMOVToBFICombine(),llvm::AMDGPUTargetLowering::PerformDAGCombine(),llvm::PPCTargetLowering::PerformDAGCombine(),llvm::RISCVTargetLowering::PerformDAGCombine(),performExtBinopLoadFold(),PerformEXTRACTCombine(),PerformExtractFpToIntStores(),llvm::AMDGPUTargetLowering::performFNegCombine(),performGatherLoadCombine(),PerformInsertSubvectorCombine(),performInsertSubvectorCombine(),performIntToFpCombine(),performLD1Combine(),performLOADCombine(),performMSTORECombine(),llvm::AMDGPUTargetLowering::performMulCombine(),llvm::AMDGPUTargetLowering::performMulhuCombine(),PerformMVEVLDCombine(),performNEONPostLDSTCombine(),performORCombine(),performScatterStoreCombine(),performSelectCombine(),performSHLCombine(),PerformSplittingMVEEXTToWideningLoad(),PerformSplittingToNarrowingStores(),PerformSplittingToWideningLoad(),performSRACombine(),performSVEAndCombine(),PerformTruncatingStoreCombine(),performUnpackCombine(),performVectorCompareAndMaskUnaryOpCombine(),performVectorExtCombine(),PerformVQDMULHCombine(),performVSelectCombine(),llvm::AArch64TargetLowering::ReconstructShuffle(),reduceBuildVecToShuffleWithZero(),ReplaceINTRINSIC_W_CHAIN(),ReplaceLoadVector(),llvm::LoongArchTargetLowering::ReplaceNodeResults(),llvm::X86TargetLowering::ReplaceNodeResults(),replaceZeroVectorStore(),resolveBuildVector(),llvm::TargetLowering::scalarizeVectorLoad(),llvm::TargetLowering::scalarizeVectorStore(),llvm::SelectionDAGISel::SelectCodeCommon(),llvm::FastISel::selectFNeg(),llvm::HexagonDAGToDAGISel::SelectIndexedLoad(),llvm::HexagonDAGToDAGISel::SelectIndexedStore(),llvm::LoongArchDAGToDAGISel::selectVSplatImm(),llvm::LoongArchDAGToDAGISel::selectVSplatUimmInvPow2(),llvm::LoongArchDAGToDAGISel::selectVSplatUimmPow2(),llvm::SITargetLowering::shouldExpandVectorDynExt(),llvm::AArch64TargetLowering::shouldReduceLoadWidth(),shouldTransformMulToShiftsAddsSubs(),llvm::TargetLowering::SimplifyDemandedBits(),llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(),llvm::TargetLowering::SimplifyMultipleUseDemandedBits(),llvm::TargetLowering::SimplifySetCC(),SplitOpsAndApply(),splitStores(),splitStoreSplat(),llvm::RISCVTargetLowering::splitValueIntoRegisterParts(),llvm::SystemZTargetLowering::splitValueIntoRegisterParts(),splitVector(),takeInexpensiveLog2(),llvm::AArch64TargetLowering::targetShrinkDemandedConstant(),transformAddImmMulImm(),transformAddShlImm(),truncateVectorWithNARROW(),truncateVectorWithPACK(),tryAdvSIMDModImm16(),tryAdvSIMDModImm32(),tryAdvSIMDModImm321s(),tryAdvSIMDModImm64(),tryAdvSIMDModImm8(),tryAdvSIMDModImmFP(),tryBitfieldInsertOpFromOr(),tryBitfieldInsertOpFromOrAndImm(),TryCombineBaseUpdate(),tryDemorganOfBooleanCondition(),TryMULWIDECombine(),tryToFoldExtendOfConstant(),tryToFoldExtOfAtomicLoad(),UnpackFromArgumentSlot(),unpackFromMemLoc(),unrollVectorShift(),vectorToScalarBitmask(),VerifySDNode(),llvm::AArch64TargetLowering::verifyTargetSDNode(),llvm::SelectionDAGBuilder::visitBitTestHeader(),widenIntegerVectorElementType(), andwidenVec().

Return the number of bytes overwritten by a store of the specified value type.

If the value type is a scalable vector type, the scalable property will be set and the runtime size will be a positive integer multiple of the base size.

Definition at line390 of fileValueTypes.h.

Referencesllvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(),getSizeInBits(), andllvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isScalable().

Referenced byllvm::AArch64TargetLowering::allowsMisalignedMemoryAccesses(),llvm::RISCVTargetLowering::allowsMisalignedMemoryAccesses(),llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(),llvm::X86TargetLowering::BuildFILD(),calculateSrcByte(),CalculateStackSlotAlignment(),CalculateStackSlotSize(),CanMergeParamLoadStoresStartingAt(),combineStore(),ComputePTXValueVTs(),llvm::SelectionDAG::CreateStackTemporary(),llvm::TargetLowering::expandUnalignedLoad(),llvm::TargetLowering::expandUnalignedStore(),llvm::TargetLowering::expandVECTOR_COMPRESS(),llvm::TargetLowering::expandVectorSplice(),findConsecutiveLoad(),getBROADCAST_LOAD(),llvm::SelectionDAG::getLoad(),llvm::SelectionDAG::getLoadVP(),llvm::SelectionDAG::getMemIntrinsicNode(),getParamsForOneTrueMaskedElt(),getScalarStoreSize(),llvm::SelectionDAG::getStore(),getStoreSizeInBits(),llvm::PPCTargetLowering::getTgtMemIntrinsic(),llvm::SelectionDAG::getTruncStore(),llvm::SelectionDAG::getTruncStoreVP(),getVPermMask(),llvm::TargetLowering::IncrementMemoryAddress(),llvm::RISCVTTIImpl::isLegalMaskedGatherScatter(),llvm::RISCVTTIImpl::isLegalMaskedLoadStore(),llvm::RISCVTargetLowering::isLegalStridedLoadStore(),isOnlyUsedByStores(),llvm::AMDGPUTargetLowering::loadStackInputValue(),llvm::SystemZTargetLowering::LowerCall(),llvm::LoongArchTargetLowering::LowerCall(),llvm::RISCVTargetLowering::LowerCall(),llvm::R600TargetLowering::LowerFormalArguments(),llvm::SITargetLowering::LowerFormalArguments(),llvm::XtensaTargetLowering::LowerFormalArguments(),llvm::MSP430TargetLowering::LowerRETURNADDR(),llvm::MemSDNode::MemSDNode(),narrowExtractedVectorLoad(),llvm::SITargetLowering::passSpecialInputs(),llvm::PPCTargetLowering::PerformDAGCombine(),llvm::AMDGPUTargetLowering::performLoadCombine(),llvm::AMDGPUTargetLowering::performStoreCombine(),llvm::SITargetLowering::ReplaceNodeResults(),llvm::RISCVDAGToDAGISel::Select(),llvm::AMDGPUTargetLowering::shouldCombineMemoryType(),ShrinkLoadReplaceStoreWithStore(),llvm::AMDGPUTargetLowering::SplitVectorLoad(),llvm::AMDGPUTargetLowering::SplitVectorStore(),splitVectorStore(), andunpackFromMemLoc().

Return the number of bits overwritten by a store of the specified value type.

If the value type is a scalable vector type, the scalable property will be set and the runtime size will be a positive integer multiple of the base size.

Definition at line407 of fileValueTypes.h.

ReferencesgetStoreSize().

Referenced byllvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(),combineBoolVectorAndTruncateStore(),EltsFromConsecutiveLoads(),llvm::AMDGPUTargetLowering::getEquivalentMemType(),llvm::TargetLowering::scalarizeVectorLoad(),llvm::AMDGPUTargetLowering::shouldReduceLoadWidth(), andllvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode().

This method returns an LLVM type corresponding to the specifiedEVT.

getTypeForEVT - This method returns an LLVM type corresponding to the specifiedEVT.

For integer types, this returns an unsigned type. Note that this will abort for types that cannot be represented.

Definition at line210 of fileValueTypes.cpp.

Referencesassert(),llvm::IntegerType::get(),llvm::TargetExtType::get(),llvm::FixedVectorType::get(),llvm::Type::getMetadataTy(),llvm::Type::getVoidTy(),llvm::Type::getWasm_ExternrefTy(),llvm::Type::getWasm_FuncrefTy(),llvm::Type::getX86_AMXTy(),isExtended(), andllvm::MVT::SimpleTy.

Referenced byllvm::TargetLoweringBase::allowsMemoryAccessForAlignment(),llvm::analyzeArguments(),canFoldInAddressingMode(),combineTargetShuffle(),llvm::SelectionDAG::CreateStackTemporary(),llvm::TargetLowering::expandIS_FPCLASS(),llvm::SelectionDAG::expandMultipleResultFPLibCall(),llvm::SelectionDAG::expandVAArg(),llvm::TargetLowering::expandVectorFindLastActive(),llvm::RISCVTTIImpl::getArithmeticInstrCost(),llvm::AArch64TTIImpl::getArithmeticReductionCostSVE(),llvm::AArch64TTIImpl::getCastInstrCost(),llvm::RISCVTTIImpl::getCastInstrCost(),getConstantVector(),getDivRemArgList(),llvm::SelectionDAG::getEVTAlign(),llvm::AArch64TTIImpl::getIntrinsicInstrCost(),getMemsetStores(),getMemsetStringVal(),llvm::AArch64TTIImpl::getMinMaxReductionCost(),llvm::BasicTTIImplBase< T >::getNumberOfParts(),getPrefTypeAlign(),llvm::SelectionDAG::getReducedAlign(),llvm::CallLowering::getReturnInfo(),llvm::AArch64TTIImpl::getSpliceCost(),llvm::PPCTargetLowering::isFMAFasterThanFMulAndFAdd(),isSaturatingMinMax(),llvm::NVPTXTargetLowering::LowerCall(),llvm::TargetLowering::LowerCallTo(),llvm::SparcTargetLowering::LowerF128_LibCallArg(),llvm::NVPTXTargetLowering::LowerFormalArguments(),LowerFSINCOS(),llvm::AArch64CallLowering::lowerReturn(),llvm::SystemZTargetLowering::makeExternalCall(),llvm::TargetLowering::makeLibCall(),llvm::PPCTargetLowering::PerformDAGCombine(), andllvm::SITargetLowering::ReplaceNodeResults().

Definition at line345 of fileValueTypes.h.

Referencesassert(),isSimple(), andisVector().

Referenced byllvm::TargetLowering::BuildSDIV(),llvm::TargetLowering::BuildUDIV(),combineBinOpOfZExt(),combineConcatVectorOfCasts(),combineConcatVectorOps(),combineShiftToAVG(),combineVectorMulToSraBitcast(),earlyExpandDIVFIX(),expandDivFix(),llvm::TargetLowering::expandFixedPointMul(),llvm::TargetLowering::expandIS_FPCLASS(),llvm::TargetLowering::expandMULO(),llvm::SelectionDAG::expandMultipleResultFPLibCall(),llvm::TargetLowering::expandVectorFindLastActive(),llvm::TargetLowering::expandVectorNaryOpBySplitting(),llvm::TargetLowering::expandVectorSplice(),llvm::TargetLowering::expandVPCTTZElements(),foldCONCAT_VECTORS(),llvm::SelectionDAG::FoldConstantArithmetic(),foldExtendVectorInregToExtendOfSubvector(),getCopyFromPartsVector(),getCopyToPartsVector(),llvm::SelectionDAG::GetDependentSplitDestVTs(),getDoubleNumVectorElementsVT(),getEVTString(),getHalfNumVectorElementsVT(),llvm::BasicTTIImplBase< T >::getIntrinsicInstrCost(),llvm::SelectionDAG::getLoad(),llvm::SelectionDAG::getNode(),llvm::AArch64TargetLowering::getNumRegistersForCallingConv(),getPackedVectorTypeFromPredicateType(),getPow2VectorType(),llvm::AArch64TargetLowering::getRegisterTypeForCallingConv(),llvm::AArch64TargetLowering::getSetCCResultType(),llvm::ARMTargetLowering::getSetCCResultType(),llvm::RISCVTargetLowering::getSetCCResultType(),llvm::X86TargetLowering::getSetCCResultType(),llvm::SelectionDAG::getTruncStore(),llvm::SelectionDAG::getTruncStoreVP(),llvm::SelectionDAG::getTruncStridedStoreVP(),llvm::TargetLoweringBase::getTypeConversion(),getVectorMinNumElements(),llvm::TargetLowering::getVectorSubVecPointer(),llvm::TargetLoweringBase::getVectorTypeBreakdown(),llvm::SelectionDAG::getVPZeroExtendInReg(),llvm::SelectionDAG::getZeroExtendInReg(),llvm::TargetLowering::IncrementMemoryAddress(),llvm::RISCVTargetLowering::PerformDAGCombine(),performLastTrueTestVectorCombine(),PerformMinMaxFpToSatCombine(),performMulVectorCmpZeroCombine(),PerformUMinFpToSatCombine(),performVectorExtCombine(),performVSelectCombine(),PromoteBinOpToF32(),setInfoSVEStN(),llvm::AArch64TargetLowering::shouldExpandPartialReductionIntrinsic(),llvm::TargetLowering::SimplifyDemandedBits(),llvm::TargetLowering::SimplifyDemandedVectorElts(),skipExtensionForVectorMULL(),llvm::SelectionDAG::SplitEVL(),tryCombineWhileLo(),llvm::AArch64TargetLowering::verifyTargetSDNode(),widenIntegerVectorElementType(), andwidenVectorToPartType().

Given a vector type, return the type of each element.

Definition at line323 of fileValueTypes.h.

Referencesassert(),isSimple(), andisVector().

Referenced byAddCombineBUILD_VECTORToVPADDL(),AddCombineVUZPToVPADDL(),addShuffleForVecExtend(),adjustLoadValueTypeImpl(),llvm::RISCVTargetLowering::allowsMisalignedMemoryAccesses(),CollectOpsToWiden(),combineAdd(),combineBinOpOfExtractToReduceTree(),combineBinOpOfZExt(),combineBitcast(),combineBitcastvxi1(),combineBoolVectorAndTruncateStore(),combineCastedMaskArithmetic(),combineCONCAT_VECTORS(),combineConcatVectorOfCasts(),combineConcatVectorOps(),combineExtractFromVectorLoad(),combineExtractWithShuffle(),combineExtSetcc(),combineFP_EXTEND(),combineFP_ROUND(),combineMulToPMADDWD(),combineMulToPMULDQ(),combinePMULH(),combineScalarAndWithMaskSetcc(),combineSelect(),combineSetCC(),combineShiftToMULH(),combineShiftToPMULH(),combineShuffleOfConcatUndef(),combineSIntToFP(),combineStore(),combineTruncateWithSat(),combineUIntToFP(),combineVSelectToBLENDV(),combinevXi1ConstantToInteger(),combineX86ShufflesRecursively(),combineXor(),CompactSwizzlableVector(),llvm::ARMTargetLowering::computeKnownBitsForTargetNode(),llvm::X86TargetLowering::computeKnownBitsForTargetNode(),ComputePTXValueVTs(),constructRetValue(),detectPMADDUBSW(),detectZextAbsDiff(),EmitVectorComparison(),expandDivFix(),llvm::TargetLowering::expandVecReduce(),llvm::TargetLowering::expandVecReduceSeq(),llvm::TargetLowering::expandVectorFindLastActive(),llvm::TargetLowering::expandVectorSplice(),extractSubVector(),llvm::SelectionDAG::ExtractVectorElements(),findMemType(),findMoreOptimalIndexType(),foldIndexIntoBase(),foldVectorXorShiftIntoCmp(),GenerateFixedLengthSVETBL(),GeneratePerfectShuffle(),llvm::ARMTTIImpl::getArithmeticReductionCost(),getContainerForFixedLengthVector(),getCopyFromPartsVector(),getCopyToPartsVector(),llvm::SelectionDAG::GetDependentSplitDestVTs(),getDoubleNumVectorElementsVT(),getEVTString(),getHalfNumVectorElementsVT(),getInvertedVectorForFMA(),getKnownUndefForVectorBinop(),llvm::AArch64TTIImpl::getMemoryOpCost(),getMemsetStringVal(),llvm::ARMTTIImpl::getMinMaxReductionCost(),llvm::SelectionDAG::getNode(),llvm::MipsTargetLowering::getNumRegistersForCallingConv(),llvm::SPIRVTargetLowering::getNumRegistersForCallingConv(),llvm::X86TargetLowering::getNumRegistersForCallingConv(),getOneTrueElt(),getPackedVectorTypeFromPredicateType(),getParamsForOneTrueMaskedElt(),getPow2VectorType(),getPredicateForFixedLengthVector(),getPredicateRegisterClass(),getPromotedVTForPredicate(),llvm::MipsTargetLowering::getRegisterTypeForCallingConv(),llvm::SPIRVTargetLowering::getRegisterTypeForCallingConv(),llvm::X86TargetLowering::getRegisterTypeForCallingConv(),getScalarType(),getShuffleScalarElt(),llvm::SelectionDAG::getSplatBuildVector(),llvm::SelectionDAG::getSplatVector(),llvm::AMDGPUTargetLowering::getSplitDestVTs(),llvm::SelectionDAG::getStepVector(),getSVEPredicateBitCast(),llvm::TargetLoweringBase::getTypeConversion(),getVectorBitwiseReduce(),llvm::TargetLowering::getVectorElementPointer(),getVectorLoweringShape(),llvm::TargetLowering::getVectorSubVecPointer(),llvm::TargetLoweringBase::getVectorTypeBreakdown(),llvm::AArch64TargetLowering::getVectorTypeBreakdownForCallingConv(),llvm::MipsTargetLowering::getVectorTypeBreakdownForCallingConv(),llvm::X86TargetLowering::getVectorTypeBreakdownForCallingConv(),getVPermMask(),INITIALIZE_PASS(),insertSubVector(),isConstantSplatVectorMaskForType(),llvm::HexagonTargetLowering::isExtractSubvectorCheap(),llvm::RISCVTargetLowering::isExtractSubvectorCheap(),llvm::X86TargetLowering::isExtractSubvectorCheap(),llvm::SITargetLowering::isExtractVecEltCheap(),isFNEG(),llvm::X86TargetLowering::isLoadBitCastBeneficial(),llvm::isMaskType(),llvm::RISCVTargetLowering::isTruncateFree(),llvm::X86TargetLowering::isTypeDesirableForOp(),llvm::HexagonSubtarget::isTypeForHVX(),isValidSplatLoad(),llvm::RISCVTargetLowering::joinRegisterPartsIntoValue(),legalizeScatterGatherIndexType(),llvm::AMDGPUTargetLowering::LowerCONCAT_VECTORS(),LowerCTTZ(),llvm::R600TargetLowering::LowerFormalArguments(),lowerLaneOp(),lowerMSACopyIntr(),LowerMULO(),llvm::AArch64TargetLowering::LowerOperation(),lowerScalarInsert(),LowerStore(),LowerSVEIntrinsicEXT(),LowerVecReduce(),LowerVecReduceMinMax(),lowerVECTOR_COMPRESS(),lowerVECTOR_SHUFFLE_VSHF(),LowerVectorINT_TO_FP(),LowerVectorMatch(),LowerVSETCC(),llvm::VETargetLowering::lowerVVP_GATHER_SCATTER(),matchPMADDWD(),matchPMADDWD_2(),matchTruncateWithPACK(),narrowIndex(),NarrowVector(),NormalizeBuildVector(),llvm::MipsCCState::originalEVTTypeIsVectorFloat(),performAddUADDVCombine(),PerformARMBUILD_VECTORCombine(),performBUILD_VECTORCombine(),PerformBUILD_VECTORCombine(),llvm::AMDGPUTargetLowering::PerformDAGCombine(),llvm::RISCVTargetLowering::PerformDAGCombine(),performDUPCombine(),performDupLane128Combine(),PerformEXTRACTCombine(),performExtractSubvectorCombine(),performFirstTrueTestVectorCombine(),performFPExtendCombine(),performGLD1Combine(),performINSERT_VECTOR_ELTCombine(),PerformInsertEltCombine(),performLastTrueTestVectorCombine(),performLOADCombine(),performMSTORECombine(),performPostLD1Combine(),performScatterStoreCombine(),performSETCCCombine(),performSignExtendInRegCombine(),PerformSplittingMVEEXTToWideningLoad(),PerformSplittingMVETruncToNarrowingStores(),PerformSplittingToNarrowingStores(),PerformSplittingToWideningLoad(),performSTORECombine(),performSVEAndCombine(),performTruncateCombine(),performUnpackCombine(),PerformVDUPLANECombine(),performVecReduceAddCombine(),performVecReduceBitwiseCombine(),performVP_REVERSECombine(),performVP_STORECombine(),performVSelectCombine(),llvm::AArch64TargetLowering::ReconstructShuffle(),reduceMaskedLoadToScalarLoad(),reduceMaskedStoreToScalarStore(),ReorganizeVector(),replaceBoolVectorBitcast(),ReplaceINTRINSIC_W_CHAIN(),ReplaceLoadVector(),llvm::X86TargetLowering::ReplaceNodeResults(),replaceVPICKVE2GRResults(),replaceZeroVectorStore(),scalarizeBinOpOfSplats(),scalarizeExtractedBinOp(),llvm::AMDGPUDAGToDAGISel::Select(),llvm::AMDGPUDAGToDAGISel::SelectBuildVector(),SelectOpcodeFromVT(),llvm::AMDGPUDAGToDAGISel::SelectVectorShuffle(),llvm::RISCVTargetLowering::shouldExpandCttzElements(),llvm::AArch64TargetLowering::shouldExpandPartialReductionIntrinsic(),llvm::SITargetLowering::shouldExpandVectorDynExt(),llvm::RISCVTargetLowering::shouldRemoveExtendFromGSIndex(),llvm::RISCVTargetLowering::splitValueIntoRegisterParts(),truncateAVX512SetCCNoBWI(),TryCombineBaseUpdate(),tryFormConcatFromShuffle(),tryGetOriginalBoolVectorType(),tryLowerPartialReductionToWideAdd(),tryWidenMaskForShuffle(),llvm::SelectionDAG::UnrollVectorOp(),llvm::SelectionDAG::UnrollVectorOverflowOp(),llvm::AArch64TargetLowering::useSVEForFixedLengthVectorVT(),vectorToScalarBitmask(),llvm::X86TargetLowering::visitMaskedLoad(),llvm::X86TargetLowering::visitMaskedStore(),widenIntegerVectorElementType(),llvm::AMDGPUTargetLowering::WidenOrSplitVectorLoad(),widenVec(),llvm::SelectionDAG::WidenVector(),WidenVector(), andwidenVectorToPartType().

Given a vector type, return the minimum number of elements it contains.

Definition at line354 of fileValueTypes.h.

Referencesllvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(), andgetVectorElementCount().

Referenced byllvm::SelectionDAG::canCreateUndefOrPoison(),clampDynamicVectorIndex(),combineBitcastvxi1(),llvm::TargetLowering::expandVectorSplice(),findMoreOptimalIndexType(),getCopyToPartsVector(),llvm::SelectionDAG::getNode(),llvm::SelectionDAG::getPartialReduceAdd(),getPromotedVTForPredicate(),getSubVectorSrc(),llvm::isConstOrConstSplat(),llvm::isConstOrConstSplatFP(),llvm::AArch64TargetLowering::isExtractSubvectorCheap(),isPow2VectorType(),lowerShuffleViaVRegSplitting(),narrowExtractedVectorLoad(),performBuildVectorCombine(),performUzpCombine(),PerformVECREDUCE_ADDCombine(),SelectOpcodeFromVT(),llvm::SelectionDAG::SplitEVL(), andllvm::SelectionDAG::SplitVector().

Given a vector type, return the number of elements it contains.

Definition at line331 of fileValueTypes.h.

Referencesassert(),isScalableVector(),isSimple(),isVector(), andllvm::reportInvalidSizeRequest().

Referenced byAddCombineBUILD_VECTORToVPADDL(),AddCombineVUZPToVPADDL(),addShuffleForVecExtend(),adjustLoadValueTypeImpl(),llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(),buildScalarToVector(),canCombineShuffleToExtendVectorInreg(),llvm::SelectionDAG::canCreateUndefOrPoison(),canonicalizeShuffleMaskWithHorizOp(),collectConcatOps(),CollectOpsToWiden(),combineAddOfPMADDWD(),combineAnd(),combineArithReduction(),combineBasicSADPattern(),combineBinOpOfExtractToReduceTree(),combineBitcast(),combineBitcastvxi1(),combineBITREVERSE(),combineCMP(),combineConcatVectorOfExtracts(),combineConcatVectorOfShuffleAndItsOperands(),combineConcatVectorOps(),combineCVTP2I_CVTTP2I(),combineEXTEND_VECTOR_INREG(),combineExtractVectorElt(),combineExtractWithShuffle(),combineFaddCFmul(),combineFP_EXTEND(),combineFP_ROUND(),combineKSHIFT(),combineLoad(),combineMaskedLoadConstantMask(),combineMulToPMADDWD(),combineMulToPMULDQ(),combineOr(),combinePredicateReduction(),combineScalarAndWithMaskSetcc(),combineSelect(),combineSetCCMOVMSK(),combineShuffle(),combineShuffleOfBitcast(),combineShuffleOfConcatUndef(),combineShuffleOfScalars(),combineShuffleOfSplatVal(),combineShuffleToAnyExtendVectorInreg(),combineShuffleToZeroExtendVectorInReg(),combineSIntToFP(),combineStore(),combineTargetShuffle(),combineToConsecutiveLoads(),combineToExtendBoolVectorInReg(),combineTruncateWithSat(),combineTruncationShuffle(),combineUIntToFP(),combineVectorPack(),combineVectorShiftImm(),combineVectorShiftVar(),CombineVMOVDRRCandidateWithVecOp(),combineVPDPBUSDPattern(),combinevXi1ConstantToInteger(),combineX86INT_TO_FP(),combineX86ShufflesRecursively(),llvm::SelectionDAG::computeKnownBits(),llvm::ARMTargetLowering::computeKnownBitsForTargetNode(),llvm::SystemZTargetLowering::computeKnownBitsForTargetNode(),llvm::X86TargetLowering::computeKnownBitsForTargetNode(),llvm::SelectionDAG::ComputeNumSignBits(),llvm::X86TargetLowering::ComputeNumSignBitsForTargetNode(),ComputePTXValueVTs(),llvm::SelectionDAG::computeVectorKnownZeroElements(),concatSubVectors(),constructDup(),constructRetValue(),ConvertSelectToConcatVector(),createBSWAPShuffleMask(),createShuffleMaskFromVSELECT(),llvm::createUnpackShuffleMask(),createVariablePermute(),detectPMADDUBSW(),EltsFromConsecutiveLoads(),llvm::TargetLowering::expandVecReduce(),llvm::TargetLowering::expandVecReduceSeq(),llvm::TargetLowering::expandVECTOR_COMPRESS(),ExtractBitFromMaskVector(),extractSubVector(),llvm::SelectionDAG::ExtractVectorElements(),FoldBUILD_VECTOR(),foldCONCAT_VECTORS(),llvm::SelectionDAG::FoldConstantArithmetic(),foldExtractSubvectorFromShuffleVector(),foldShuffleOfConcatUndefs(),GenerateFixedLengthSVETBL(),getBuildVectorSplat(),llvm::AArch64TTIImpl::getCastInstrCost(),llvm::ARMTTIImpl::getCastInstrCost(),llvm::SelectionDAG::getConstant(),getConstantLaneNumOfExtractHalfOperand(),getCopyFromPartsVector(),getDemandedSrcElements(),getEXTEND_VECTOR_INREG(),getFauxShuffleMask(),llvm::AArch64TTIImpl::getIntrinsicInstrCost(),getKnownUndefForVectorBinop(),llvm::ShuffleVectorSDNode::getMask(),llvm::VECustomDAG::getMaskBroadcast(),llvm::AArch64TTIImpl::getMemoryOpCost(),getMemsetStringVal(),llvm::SelectionDAG::getNode(),llvm::SITargetLowering::getNumRegistersForCallingConv(),llvm::MipsTargetLowering::getNumRegistersForCallingConv(),llvm::SPIRVTargetLowering::getNumRegistersForCallingConv(),llvm::X86TargetLowering::getNumRegistersForCallingConv(),getOneTrueElt(),getPredicateForFixedLengthVector(),llvm::SPIRVTargetLowering::getRegisterTypeForCallingConv(),llvm::SystemZTargetLowering::getRegisterTypeForCallingConv(),llvm::X86TargetLowering::getRegisterTypeForCallingConv(),llvm::HexagonTargetLowering::getSetCCResultType(),llvm::SITargetLowering::getSetCCResultType(),llvm::NVPTXTargetLowering::getSetCCResultType(),getShuffleScalarElt(),llvm::SelectionDAG::getSplatBuildVector(),llvm::ShuffleVectorSDNode::getSplatIndex(),llvm::SelectionDAG::getSplatSourceVector(),llvm::AMDGPUTargetLowering::getSplitDestVTs(),llvm::SelectionDAG::getStepVector(),getSToVPermuted(),getTargetConstantBitsFromNode(),getTargetShuffleAndZeroables(),llvm::SelectionDAG::getValidMaximumShiftAmount(),llvm::SelectionDAG::getValidMinimumShiftAmount(),llvm::SelectionDAG::getValidShiftAmount(),getVectorBitwiseReduce(),getVectorLoweringShape(),llvm::SelectionDAG::getVectorShuffle(),llvm::AArch64TargetLowering::getVectorTypeBreakdownForCallingConv(),llvm::SITargetLowering::getVectorTypeBreakdownForCallingConv(),llvm::MipsTargetLowering::getVectorTypeBreakdownForCallingConv(),llvm::X86TargetLowering::getVectorTypeBreakdownForCallingConv(),getVPermMask(),isAllConstantBuildVector(),isConcatMask(),isEXTMask(),llvm::ARMTargetLowering::isExtractSubvectorCheap(),llvm::RISCVTargetLowering::isExtractSubvectorCheap(),llvm::X86TargetLowering::isExtractSubvectorCheap(),llvm::SelectionDAG::isGuaranteedNotToBeUndefOrPoison(),isHorizontalBinOpPart(),llvm::HexagonSubtarget::isHVXVectorType(),isLegalBitRotate(),llvm::TargetLoweringBase::isLoadBitCastBeneficial(),llvm::isPackedVectorType(),isReverseMask(),llvm::AArch64TargetLowering::isShuffleMaskLegal(),llvm::ARMTargetLowering::isShuffleMaskLegal(),isSingletonEXTMask(),isSingletonVEXTMask(),llvm::ShuffleVectorSDNode::isSplatMask(),llvm::SelectionDAG::isSplatValue(),isTargetShuffleEquivalent(),isTRN_v_undef_Mask(),isTruncMask(),llvm::HexagonSubtarget::isTypeForHVX(),isUZP_v_undef_Mask(),isVectorElementSwap(),isVEXTMask(),isVMOVNMask(),isVMOVNTruncMask(),isVTRN_v_undef_Mask(),isVTRNMask(),isVUZP_v_undef_Mask(),isVUZPMask(),isVZIP_v_undef_Mask(),isVZIPMask(),isWideDUPMask(),isZIP_v_undef_Mask(),lowerAddSubToHorizontalOp(),LowerBUILD_VECTOR_i1(),LowerBUILD_VECTORToVIDUP(),LowerCONCAT_VECTORS_i1(),llvm::AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(),LowerEXTRACT_SUBVECTOR(),LowerINTRINSIC_W_CHAIN(),lowerLaneOp(),lowerMSASplatZExt(),LowerPredicateStore(),LowerReverse_VECTOR_SHUFFLE(),LowerStore(),llvm::VETargetLowering::lowerToVVP(),LowerVecReduce(),LowerVecReduceMinMax(),lowerVECTOR_COMPRESS(),LowerVECTOR_SHUFFLE(),lowerVECTOR_SHUFFLE_VSHF(),LowerVECTOR_SHUFFLEUsingMovs(),LowerVECTOR_SHUFFLEUsingOneOff(),LowerVSETCC(),llvm::VETargetLowering::lowerVVP_GATHER_SCATTER(),matchBinaryShuffle(),matchIndexAsShuffle(),matchIndexAsWiderOp(),matchPMADDWD(),matchPMADDWD_2(),matchScalarReduction(),mergeEltWithShuffle(),narrowExtractedVectorBinOp(),NarrowVector(),partitionShuffleOfConcats(),PerformARMBUILD_VECTORCombine(),performBitcastCombine(),performBUILD_VECTORCombine(),PerformBUILD_VECTORCombine(),performCONCAT_VECTORSCombine(),performConcatVectorsCombine(),llvm::AMDGPUTargetLowering::PerformDAGCombine(),llvm::R600TargetLowering::PerformDAGCombine(),llvm::RISCVTargetLowering::PerformDAGCombine(),performExtBinopLoadFold(),PerformEXTRACTCombine(),PerformExtractEltCombine(),PerformExtractEltToVMOVRRD(),performINSERT_VECTOR_ELTCombine(),PerformInsertEltCombine(),PerformInsertSubvectorCombine(),performInsertSubvectorCombine(),llvm::ARMTargetLowering::PerformMVEExtCombine(),performNEONPostLDSTCombine(),performPostLD1Combine(),performSelectCombine(),performSETCCCombine(),PerformSplittingMVEEXTToWideningLoad(),PerformSplittingMVETruncToNarrowingStores(),PerformSplittingToNarrowingStores(),PerformSplittingToWideningLoad(),PerformSTORECombine(),llvm::AMDGPUTargetLowering::performTruncateCombine(),PerformTruncatingStoreCombine(),performUADDVAddCombine(),PerformVECREDUCE_ADDCombine(),performVecReduceAddCombine(),PerformVECTOR_SHUFFLECombine(),performVECTOR_SHUFFLECombine(),PerformVQDMULHCombine(),performVSelectCombine(),PerformVSetCCToVCTPCombine(),performZExtDeinterleaveShuffleCombine(),performZExtUZPCombine(),llvm::AArch64TargetLowering::ReconstructShuffle(),ReconstructShuffleWithRuntimeMask(),reduceVMULWidth(),ReplaceAddWithADDP(),ReplaceINTRINSIC_W_CHAIN(),ReplaceLoadVector(),llvm::X86TargetLowering::ReplaceNodeResults(),replaceSplatVectorStore(),replaceZeroVectorStore(),llvm::TargetLowering::scalarizeVectorLoad(),llvm::TargetLowering::scalarizeVectorStore(),llvm::AMDGPUDAGToDAGISel::Select(),llvm::AMDGPUDAGToDAGISel::SelectBuildVector(),llvm::AMDGPUDAGToDAGISel::SelectVectorShuffle(),llvm::SITargetLowering::shouldExpandVectorDynExt(),llvm::TargetLowering::ShrinkDemandedConstant(),llvm::TargetLowering::SimplifyDemandedBits(),llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(),llvm::TargetLowering::SimplifyDemandedVectorElts(),llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(),llvm::TargetLowering::SimplifyMultipleUseDemandedBits(),SkipExtensionForVMULL(),SplitOpsAndApply(),splitStores(),llvm::AMDGPUTargetLowering::splitVector(),splitVector(),splitVectorIntUnary(),llvm::AMDGPUTargetLowering::SplitVectorLoad(),llvm::AMDGPUTargetLowering::SplitVectorStore(),llvm::X86TargetLowering::targetShrinkDemandedConstant(),truncateVectorWithNARROW(),truncateVectorWithPACK(),tryBuildVectorShuffle(),TryCombineBaseUpdate(),tryCombineMULLWithUZP1(),tryCombineToBSL(),tryToFoldExtendOfConstant(),tryWidenMaskForShuffle(),llvm::SelectionDAG::UnrollVectorOp(),llvm::SelectionDAG::UnrollVectorOverflowOp(),vectorToScalarBitmask(),llvm::AMDGPUTargetLowering::WidenOrSplitVectorLoad(),widenSubVector(),widenVec(),llvm::SelectionDAG::WidenVector(), andWidenVector().

Returns theEVT that represents a vector EC.Min elements in length, where each element is of type VT.

Definition at line84 of fileValueTypes.h.

Referencesllvm::MVT::getVectorVT(), andllvm::MVT::INVALID_SIMPLE_VALUE_TYPE.

Returns theEVT that represents a vector NumElements in length, where each element is of type VT.

Definition at line74 of fileValueTypes.h.

Referencesllvm::MVT::getVectorVT(), andllvm::MVT::INVALID_SIMPLE_VALUE_TYPE.

Referenced byAddCombineVUZPToVPADDL(),addShuffleForVecExtend(),adjustLoadValueTypeImpl(),llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(),llvm::TargetLowering::BuildSDIV(),llvm::TargetLowering::BuildUDIV(),BuildVectorFromScalar(),canCombineShuffleToExtendVectorInreg(),CollectOpsToWiden(),combineArithReduction(),combineBasicSADPattern(),combineBinOpOfExtractToReduceTree(),combineBinOpOfZExt(),combineBitcastToBoolVector(),combineConcatVectorOfCasts(),combineConcatVectorOfScalars(),combineConcatVectorOps(),combineExtractWithShuffle(),combineFP_EXTEND(),combineFP_ROUND(),combineI8TruncStore(),combineLoad(),combinePMULH(),combineShiftToAVG(),combineShuffleToZeroExtendVectorInReg(),combineSIntToFP(),combineStore(),combineTargetShuffle(),combineToExtendBoolVectorInReg(),combineToFPTruncExtElt(),combineTruncateWithSat(),combineUIntToFP(),combineV3I8LoadExt(),combineVectorMulToSraBitcast(),CombineVMOVDRRCandidateWithVecOp(),combineVPDPBUSDPattern(),concatSubVectors(),constructRetValue(),convertIntLogicToFPLogic(),detectPMADDUBSW(),earlyExpandDIVFIX(),EltsFromConsecutiveLoads(),expandDivFix(),llvm::TargetLowering::expandFixedPointMul(),llvm::TargetLowering::expandIS_FPCLASS(),llvm::TargetLowering::expandMULO(),llvm::TargetLowering::expandVectorSplice(),llvm::TargetLowering::expandVPCTTZElements(),extractSubVector(),foldExtendVectorInregToExtendOfSubvector(),foldShuffleOfConcatUndefs(),GenerateFixedLengthSVETBL(),llvm::getApproximateEVTForLLT(),llvm::SelectionDAG::getConstant(),getCopyFromPartsVector(),getCopyToPartsVector(),llvm::SelectionDAG::GetDependentSplitDestVTs(),getDoubleNumVectorElementsVT(),llvm::AMDGPUTargetLowering::getEquivalentMemType(),getEVT(),getHalfNumVectorElementsVT(),llvm::AArch64TTIImpl::getMemoryOpCost(),getMemsetStores(),getMemsetStringVal(),llvm::TargetLoweringBase::getMemValueType(),getPackedVectorTypeFromPredicateType(),getPow2VectorType(),llvm::HexagonTargetLowering::getSetCCResultType(),llvm::AArch64TargetLowering::getSetCCResultType(),llvm::SITargetLowering::getSetCCResultType(),llvm::RISCVTargetLowering::getSetCCResultType(),llvm::X86TargetLowering::getSetCCResultType(),llvm::NVPTXTargetLowering::getSetCCResultType(),llvm::AMDGPUTargetLowering::getSplitDestVTs(),llvm::AArch64TargetLowering::getTgtMemIntrinsic(),llvm::ARMTargetLowering::getTgtMemIntrinsic(),llvm::TargetLoweringBase::getTypeConversion(),getUniformBase(),llvm::SelectionDAGBuilder::getValueImpl(),llvm::TargetLoweringBase::getValueType(),llvm::TargetLowering::getVectorElementPointer(),llvm::TargetLoweringBase::getVectorTypeBreakdown(),llvm::AArch64TargetLowering::getVectorTypeBreakdownForCallingConv(),llvm::VECustomDAG::getVectorVT(),llvm::RISCVTargetLowering::joinRegisterPartsIntoValue(),LowerAsSplatVectorLoad(),lowerBitreverseShuffle(),llvm::AMDGPUTargetLowering::LowerCONCAT_VECTORS(),llvm::AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(),llvm::SITargetLowering::LowerFormalArguments(),llvm::NVPTXTargetLowering::LowerFormalArguments(),lowerLaneOp(),llvm::RISCVTargetLowering::LowerOperation(),LowerSVEIntrinsicEXT(),LowerVECTOR_SHUFFLE(),LowerVectorAllEqual(),LowerVSETCC(),llvm::SelectionDAG::matchBinOpReduction(),matchPMADDWD(),matchPMADDWD_2(),memVTFromLoadIntrData(),narrowExtractedVectorBinOp(),PerformARMBUILD_VECTORCombine(),PerformBUILD_VECTORCombine(),performConcatVectorsCombine(),llvm::RISCVTargetLowering::PerformDAGCombine(),performExtBinopLoadFold(),PerformInsertEltCombine(),performLOADCombine(),PerformMinMaxFpToSatCombine(),performMulVectorCmpZeroCombine(),performSelectCombine(),PerformSplittingMVEEXTToWideningLoad(),PerformSplittingMVETruncToNarrowingStores(),PerformSplittingToNarrowingStores(),PerformSplittingToWideningLoad(),PerformSTORECombine(),llvm::AMDGPUTargetLowering::performTruncateCombine(),PerformTruncatingStoreCombine(),PerformUMinFpToSatCombine(),performVecReduceAddCombine(),performVECTOR_SHUFFLECombine(),performVectorExtCombine(),PromoteBinOpToF32(),llvm::AArch64TargetLowering::ReconstructShuffle(),reduceVMULWidth(),llvm::RISCVTargetLowering::ReplaceNodeResults(),llvm::X86TargetLowering::ReplaceNodeResults(),setInfoSVEStN(),llvm::TargetLowering::SimplifyDemandedBits(),llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(),skipExtensionForVectorMULL(),llvm::RISCVTargetLowering::splitValueIntoRegisterParts(),llvm::X86TargetLowering::targetShrinkDemandedConstant(),truncateVectorWithNARROW(),truncateVectorWithPACK(),llvm::SelectionDAG::UnrollVectorOp(),llvm::SelectionDAG::UnrollVectorOverflowOp(),widenIntegerVectorElementType(),llvm::AMDGPUTargetLowering::WidenOrSplitVectorLoad(),widenVec(), andllvm::SelectionDAG::WidenVector().

Return true if this is a 1024-bit vector type.

Definition at line222 of fileValueTypes.h.

ReferencesisSimple().

Return true if this is a 128-bit vector type.

Definition at line207 of fileValueTypes.h.

ReferencesisSimple().

Referenced byAddCombineVUZPToVPADDL(),AddRequiredExtensionForVMULL(),combineAndShuffleNot(),combineBitcast(),combineConcatVectorOps(),combineConstantPoolLoads(),combineHorizOpWithShuffle(),combineLoad(),combineLogicBlendIntoPBLENDV(),combinePTESTCC(),combineShuffleOfConcatUndef(),combineStore(),combineToExtendBoolVectorInReg(),combineVectorPack(),combineVSelectToBLENDV(),constructDup(),EltsFromConsecutiveLoads(),getOnesVector(),getTargetVShiftNode(),getVectorShuffleOpcode(),getVShift(),getZeroVector(),INITIALIZE_PASS(),insert128BitVector(),isLegalMaskCompare(),llvm::AArch64TargetLowering::isShuffleMaskLegal(),llvm::ARMTargetLowering::isShuffleMaskLegal(),isVMOVModifiedImm(),LowerMUL(),LowerVecReduceMinMax(),LowerVectorMatch(),performANDCombine(),performConcatVectorsCombine(),performDupLane128Combine(),PerformMULCombine(),performORCombine(),PerformORCombine(),performPostLD1Combine(),performTruncateCombine(),PerformVECREDUCE_ADDCombine(),performVECTOR_SHUFFLECombine(),performXORCombine(),llvm::AArch64TargetLowering::ReconstructShuffle(),llvm::X86TargetLowering::ReplaceNodeResults(),scalarizeVectorStore(),skipExtensionForVectorMULL(),supportedVectorShiftWithImm(),supportedVectorVarShift(),truncateVectorWithNARROW(),truncateVectorWithPACK(), andllvm::AArch64TargetLowering::useSVEForFixedLengthVectorVT().

Return true if this is a 16-bit vector type.

Definition at line192 of fileValueTypes.h.

ReferencesisSimple().

Return true if this is a 2048-bit vector type.

Definition at line227 of fileValueTypes.h.

ReferencesisSimple().

Return true if this is a 256-bit vector type.

Definition at line212 of fileValueTypes.h.

ReferencesisSimple().

Referenced bycombineAndShuffleNot(),combineConcatVectorOps(),combineConstantPoolLoads(),combineEXTRACT_SUBVECTOR(),combineHorizOpWithShuffle(),combineLoad(),combineLogicBlendIntoPBLENDV(),combinePMULH(),combineShuffleOfConcatUndef(),combineStore(),EltsFromConsecutiveLoads(),extract128BitVector(),getOnesVector(),INITIALIZE_PASS(),isHorizontalBinOpPart(),isLegalMaskCompare(),narrowShuffle(),narrowVectorSelect(),ReplaceAddWithADDP(),llvm::X86TargetLowering::shouldReduceLoadWidth(),llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(),splitVectorIntBinary(),splitVectorIntUnary(),splitVectorStore(),supportedVectorShiftWithImm(),supportedVectorVarShift(),truncateVectorWithNARROW(),truncateVectorWithPACK(), andwidenSubVector().

Return true if this is a 32-bit vector type.

Definition at line197 of fileValueTypes.h.

ReferencesisSimple().

Return true if this is a 512-bit vector type.

Definition at line217 of fileValueTypes.h.

ReferencesisSimple().

Referenced bycombineAndShuffleNot(),combineConcatVectorOps(),combineScalarAndWithMaskSetcc(),combineStore(),combineTruncateWithSat(),combineVSelectToBLENDV(),EltsFromConsecutiveLoads(),extract128BitVector(),extract256BitVector(),getOnesVector(),LowerVectorAllEqual(),narrowShuffle(),llvm::X86TargetLowering::shouldFoldSelectWithIdentityConstant(),llvm::X86TargetLowering::shouldReduceLoadWidth(),llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(),splitVectorIntBinary(),splitVectorIntUnary(),splitVectorStore(),supportedVectorShiftWithImm(),supportedVectorVarShift(), andtruncateVectorWithPACK().

Return true if this is a 64-bit vector type.

Definition at line202 of fileValueTypes.h.

ReferencesisSimple().

Referenced byAddCombineVUZPToVPADDL(),combineVectorPack(),CombineVLDDUP(),getVectorShuffleOpcode(),llvm::AArch64TargetLowering::isShuffleMaskLegal(),llvm::ARMTargetLowering::isShuffleMaskLegal(),isVUZP_v_undef_Mask(),isVUZPMask(),isVZIP_v_undef_Mask(),isVZIPMask(),LowerCTPOP(),LowerMUL(),performANDCombine(),performDUPCombine(),PerformMULCombine(),performPostLD1Combine(),performTruncateCombine(),llvm::AArch64TargetLowering::ReconstructShuffle(), andllvm::AArch64TargetLowering::useSVEForFixedLengthVectorVT().

Return true if the bit size is a multiple of 8.

Definition at line238 of fileValueTypes.h.

ReferencesgetSizeInBits(),llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isKnownMultipleOf(), andisZeroSized().

Referenced bycalculateSrcByte(),getFauxShuffleMask(),llvm::TargetLoweringBase::isPaddedAtMostSignificantBitsWhenStored(),matchPERM(),narrowExtractedVectorLoad(),performVP_REVERSECombine(),performVP_STORECombine(),llvm::TargetLowering::scalarizeVectorLoad(),llvm::TargetLowering::scalarizeVectorStore(), andllvm::AMDGPUTargetLowering::shouldCombineMemoryType().

Test if the givenEVT is extended (as opposed to being simple).

Definition at line142 of fileValueTypes.h.

ReferencesisSimple().

Referenced byllvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(),llvm::TargetLoweringBase::getAtomicLoadExtAction(),llvm::TargetLoweringBase::getLoadExtAction(),llvm::TargetLoweringBase::getOperationAction(),llvm::TargetLoweringBase::getTruncStoreAction(),getTypeForEVT(),llvm::SelectionDAG::getValueType(),llvm::SelectionDAG::getVTList(), andllvm::PPCTargetLowering::PerformDAGCombine().

Definition at line181 of fileValueTypes.h.

ReferencesisSimple().

Referenced byllvm::SelectionDAG::canCreateUndefOrPoison(),llvm::AArch64TargetLowering::canMergeStoresTo(),clampDynamicVectorIndex(),llvm::SelectionDAG::computeKnownBits(),llvm::SelectionDAG::ComputeNumSignBits(),convertFromScalableVector(),findMoreOptimalIndexType(),llvm::SelectionDAG::FoldConstantArithmetic(),foldExtractSubvectorFromShuffleVector(),llvm::AArch64TTIImpl::getCastInstrCost(),llvm::ARMTTIImpl::getCastInstrCost(),getConstantLaneNumOfExtractHalfOperand(),getContainerForFixedLengthVector(),llvm::AArch64TTIImpl::getIntrinsicInstrCost(),getKnownUndefForVectorBinop(),llvm::SelectionDAG::getNode(),llvm::AArch64TargetLowering::getNumRegistersForCallingConv(),getPredicateForFixedLengthVector(),getPredicateForVector(),llvm::AArch64TargetLowering::getRegisterTypeForCallingConv(),llvm::SelectionDAG::getValidMaximumShiftAmount(),llvm::SelectionDAG::getValidMinimumShiftAmount(),llvm::SelectionDAG::getValidShiftAmount(),getVectorBitwiseReduce(),llvm::isConstOrConstSplat(),llvm::isConstOrConstSplatFP(),llvm::RISCVTargetLowering::isCtpopFast(),llvm::SelectionDAG::isGuaranteedNotToBeUndefOrPoison(),llvm::RISCVTTIImpl::isLegalMaskedGatherScatter(),llvm::RISCVTTIImpl::isLegalMaskedLoadStore(),llvm::RISCVTargetLowering::isLegalStridedLoadStore(),llvm::TargetLoweringBase::isLoadBitCastBeneficial(),isPackedVectorType(),isPassedInFPR(),llvm::RISCVTargetLowering::LowerOperation(),narrowExtractedVectorBinOp(),performBitcastCombine(),llvm::RISCVTargetLowering::PerformDAGCombine(),performExtBinopLoadFold(),performFP_TO_INTCombine(),performFPExtendCombine(),PerformInsertSubvectorCombine(),performInsertSubvectorCombine(),performSETCCCombine(),performSTORECombine(),performTruncateCombine(),performVecReduceBitwiseCombine(),performVectorExtCombine(),llvm::RISCVTargetLowering::ReplaceNodeResults(),llvm::AArch64TargetLowering::shouldExpandCmpUsingSelects(),llvm::RISCVTargetLowering::shouldFoldSelectWithIdentityConstant(),llvm::TargetLowering::SimplifyDemandedBits(),llvm::TargetLowering::SimplifyMultipleUseDemandedBits(),llvm::SelectionDAG::SplitEVL(),splitStores(),tryAdvSIMDModImm16(),tryAdvSIMDModImm32(),tryCombineToBSL(),tryToFoldExtOfLoad(),llvm::AArch64Subtarget::useSVEForFixedLengthVectors(), andllvm::AArch64TargetLowering::useSVEForFixedLengthVectorVT().

Return true if this is a FP or a vector FP type.

Definition at line147 of fileValueTypes.h.

ReferencesisSimple().

Referenced byllvm::PPCTargetLowering::allowsMisalignedMemoryAccesses(),combineBitcast(),combineBitcastToBoolVector(),combineBitOpWithMOVMSK(),combineConcatVectorOfScalars(),combineConcatVectorOps(),combineExtractWithShuffle(),combineHorizOpWithShuffle(),llvm::VETargetLowering::combineSelect(),combineSelect(),llvm::VETargetLowering::combineSelectCC(),combineVSelectWithAllOnesOrZeros(),llvm::SelectionDAG::computeKnownBits(),llvm::SelectionDAG::ComputeNumSignBits(),decideComp(),EltsFromConsecutiveLoads(),emitComparison(),EmitVectorComparison(),llvm::AArch64TargetLowering::enableAggressiveFMAFusion(),llvm::PPCTargetLowering::enableAggressiveFMAFusion(),llvm::TargetLowering::expandIS_FPCLASS(),llvm::TargetLowering::expandUnalignedLoad(),llvm::TargetLowering::expandUnalignedStore(),llvm::TargetLowering::findOptimalMemOpLowering(),foldAndOrOfSETCC(),llvm::SelectionDAG::FoldSetCC(),llvm::ARMTTIImpl::getCastInstrCost(),llvm::SelectionDAG::getConstantFP(),getCopyFromParts(),getCopyFromPartsVector(),getCopyToParts(),getCopyToPartsVector(),getEVTString(),getLdStRegType(),llvm::SelectionDAG::getNode(),getPredicateForSetCC(),llvm::ARMTargetLowering::getSchedulingPreference(),llvm::SelectionDAGBuilder::getValueImpl(),llvm::AArch64TargetLowering::hasPairedLoad(),llvm::TargetLoweringBase::isFAbsFree(),llvm::AMDGPUTargetLowering::isFAbsFree(),llvm::TargetLoweringBase::isFNegFree(),llvm::AMDGPUTargetLowering::isFNegFree(),llvm::TargetLoweringBase::isFPExtFoldable(),llvm::TargetLoweringBase::isFPExtFree(),llvm::PPCTargetLowering::isFPExtFree(),isLegalT2AddressImmediate(),isLegalToCombineMinNumMaxNum(),isMImm(),llvm::RISCVTargetLowering::isMultiStoresCheaperThanBitsMerge(),llvm::X86TargetLowering::isMultiStoresCheaperThanBitsMerge(),isPassedInFPR(),isSimm7(),isSupportedType(),llvm::ConstantFPSDNode::isValueValidForType(),llvm::NVPTXTargetLowering::LowerCall(),lowerLaneOp(),LowerVectorAllEqual(),LowerVSETCC(),llvm::TargetLowering::LowerXConstraint(),llvm::ARMTargetLowering::LowerXConstraint(),llvm::X86TargetLowering::LowerXConstraint(),llvm::ARMTTIImpl::maybeLoweredToCall(),NormalizeBuildVector(),llvm::MipsCCState::originalEVTTypeIsVectorFloat(),performGatherLoadCombine(),performLD1ReplicateCombine(),performLDNT1Combine(),performScatterStoreCombine(),performSelectCombine(),performST1Combine(),performSTNT1Combine(),llvm::AMDGPUTargetLowering::performTruncateCombine(),PerformVCMPCombine(),performVECTOR_SHUFFLECombine(),performVSelectCombine(),llvm::X86TargetLowering::reduceSelectOfFPConstantLoads(),ReplaceAddWithADDP(),replaceSplatVectorStore(),safeWithoutCompWithNull(),llvm::TargetLowering::SimplifyDemandedBits(),tryWidenMaskForShuffle(), andVerifySDNode().

Return true if this is an integer or a vector integer type.

Definition at line152 of fileValueTypes.h.

ReferencesisSimple().

Referenced byAddCombineBUILD_VECTORToVPADDL(),canCombineShuffleToExtendVectorInreg(),combineAddOrSubToADCOrSBB(),combineAndMaskToShift(),combineBinOpOfExtractToReduceTree(),combineBitcast(),combineBITREVERSE(),combineCarryThroughADD(),combineConcatVectorOfScalars(),combineExtractFromVectorLoad(),combineExtractVectorElt(),combineExtractWithShuffle(),combineLogicBlendIntoConditionalNegate(),combineLogicBlendIntoPBLENDV(),combineMul(),combineSelect(),combineSetCC(),combineShiftLeft(),combineShuffleOfScalars(),combineShuffleToAnyExtendVectorInreg(),combineShuffleToZeroExtendVectorInReg(),combineSubOfBoolean(),combineTruncationShuffle(),llvm::SelectionDAG::computeKnownBits(),llvm::SelectionDAG::ComputeNumSignBits(),convertValVTToLocVT(),EltsFromConsecutiveLoads(),llvm::TargetLowering::expandAddSubSat(),llvm::TargetLowering::expandCTPOP(),llvm::TargetLowering::expandShlSat(),llvm::TargetLowering::expandUnalignedLoad(),llvm::TargetLowering::expandUnalignedStore(),llvm::TargetLowering::expandVPCTPOP(),llvm::TargetLowering::findOptimalMemOpLowering(),foldAndOrOfSETCC(),llvm::SelectionDAG::FoldConstantArithmetic(),llvm::SelectionDAG::FoldSetCC(),llvm::SelectionDAG::getAssertAlign(),llvm::ARMTTIImpl::getCastInstrCost(),llvm::SelectionDAG::getConstant(),getCopyFromParts(),getCopyFromPartsVector(),getCopyToParts(),getEVTString(),getHalfSizedIntegerVT(),llvm::SelectionDAG::getLoad(),getMemcpyLoadsAndStores(),getMemsetStringVal(),getMemsetValue(),llvm::SelectionDAG::getNode(),llvm::TargetLoweringBase::getNumRegisters(),llvm::SPIRVTargetLowering::getNumRegistersForCallingConv(),llvm::TargetLoweringBase::getRegisterType(),llvm::SITargetLowering::getRegisterTypeForCallingConv(),llvm::GetReturnInfo(),getRoundIntegerType(),llvm::SelectionDAG::getShiftAmountConstant(),llvm::TargetLoweringBase::getShiftAmountTy(),llvm::SelectionDAG::getSplatBuildVector(),llvm::SelectionDAG::getSplatValue(),llvm::SelectionDAG::getSplatVector(),llvm::SelectionDAG::getTruncStore(),llvm::SelectionDAG::getTruncStoreVP(),llvm::SelectionDAG::getTruncStridedStoreVP(),llvm::TargetLoweringBase::getTypeConversion(),llvm::SITargetLowering::getVectorTypeBreakdownForCallingConv(),llvm::SelectionDAG::getVPZeroExtendInReg(),llvm::SelectionDAG::getZeroExtendInReg(),llvm::AArch64TargetLowering::hasPairedLoad(),llvm::X86TargetLowering::isDesirableToCombineLogicOpOfSETCC(),isLegalT2AddressImmediate(),isMImm(),llvm::RISCVTargetLowering::isMultiStoresCheaperThanBitsMerge(),llvm::X86TargetLowering::isMultiStoresCheaperThanBitsMerge(),llvm::AMDGPUTargetLowering::isNarrowingProfitable(),isSimm7(),llvm::SelectionDAG::isSplatValue(),isSupportedType(),llvm::ARMTargetLowering::isTruncateFree(),llvm::RISCVTargetLowering::isTruncateFree(),llvm::AArch64TargetLowering::isTruncateFree(),llvm::MSP430TargetLowering::isTruncateFree(),llvm::PPCTargetLowering::isTruncateFree(),llvm::SystemZTargetLowering::isTruncateFree(),llvm::AArch64TargetLowering::isZExtFree(),llvm::ARMTargetLowering::isZExtFree(),llvm::X86TargetLowering::isZExtFree(),llvm::XCoreTargetLowering::isZExtFree(),lowerBuildVectorAsBroadcast(),llvm::NVPTXTargetLowering::LowerCall(),llvm::NVPTXTargetLowering::LowerFormalArguments(),LowerMUL(),llvm::TargetLowering::LowerXConstraint(),llvm::ARMTTIImpl::maybeLoweredToCall(),OptimizeNoopCopyExpression(),llvm::ARMTargetLowering::PerformCMOVCombine(),performExtractVectorEltCombine(),performGatherLoadCombine(),performLD1Combine(),performSELECTCombine(),performSignExtendSetCCCombine(),performXORCombine(),llvm::X86TargetLowering::preferedOpcodeForCmpEqPiecesOfOperand(),llvm::RISCVTargetLowering::ReplaceNodeResults(),llvm::TargetLowering::SimplifyDemandedBits(),llvm::TargetLowering::SimplifyMultipleUseDemandedBits(),llvm::TargetLowering::SimplifySetCC(),simplifySetCCWithCTPOP(),llvm::TargetLowering::softenSetCCOperands(),splitVSETCC(),takeInexpensiveLog2(),VerifySDNode(), andllvm::AArch64TargetLowering::verifyTargetSDNode().

Return true if this is an overloaded type forTableGen.

Definition at line232 of fileValueTypes.h.

Returns true if the given vector is a power of 2.

Definition at line465 of fileValueTypes.h.

ReferencesgetVectorMinNumElements().

Referenced byllvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(),llvm::TargetLowering::expandVecReduce(),llvm::MipsTargetLowering::getNumRegistersForCallingConv(),getPow2VectorType(),llvm::MipsTargetLowering::getRegisterTypeForCallingConv(),llvm::TargetLoweringBase::getTypeConversion(),getVectorBitwiseReduce(),llvm::MipsTargetLowering::getVectorTypeBreakdownForCallingConv(),performVecReduceBitwiseCombine(),PerformVQDMULHCombine(), andllvm::AArch64TargetLowering::useSVEForFixedLengthVectorVT().

Return true if this is a vector value type.

Definition at line179 of fileValueTypes.h.

Referenced bygetEVTString(),llvm::SelectionDAGBuilder::getValueImpl(),llvm::RISCVTargetLowering::LowerOperation(),llvm::RISCVTargetLowering::PerformDAGCombine(), andllvm::RISCVTargetLowering::splitValueIntoRegisterParts().

Return true if the size is a power-of-two number of bytes.

Definition at line243 of fileValueTypes.h.

ReferencesgetSizeInBits(), andisScalableVector().

Referenced byllvm::MipsTargetLowering::getNumRegistersForCallingConv(),llvm::MipsTargetLowering::getRegisterTypeForCallingConv(),llvm::MipsTargetLowering::getVectorTypeBreakdownForCallingConv(), andisOnlyUsedByStores().

Return true if this is a vector type where the runtime length is machine dependent.

Definition at line163 of fileValueTypes.h.

ReferencesisSimple().

Referenced byisScalableVT().

Return true if this is a vector type where the runtime length is machine dependent.

Definition at line174 of fileValueTypes.h.

ReferencesisSimple().

Referenced byllvm::AArch64TargetLowering::allowsMisalignedMemoryAccesses(),bitsGE(),bitsGT(),bitsLE(),bitsLT(),clampDynamicVectorIndex(),combineBinOpOfExtractToReduceTree(),combineConcatVectorOfExtracts(),combineConcatVectorOfScalars(),combineConcatVectorOfShuffleAndItsOperands(),combineShuffleToZeroExtendVectorInReg(),llvm::SelectionDAG::computeKnownBits(),llvm::SelectionDAG::ComputeNumSignBits(),llvm::SelectionDAG::computeVectorKnownZeroElements(),convertToScalableVector(),convertValVTToLocVT(),llvm::TargetLowering::expandFMINNUM_FMAXNUM(),llvm::TargetLowering::expandVecReduce(),llvm::TargetLowering::expandVecReduceSeq(),llvm::TargetLowering::expandVECTOR_COMPRESS(),llvm::TargetLowering::expandVectorFindLastActive(),findMemType(),FoldBUILD_VECTOR(),foldCONCAT_VECTORS(),llvm::AArch64TargetLowering::generateFMAsInMachineCombiner(),llvm::SelectionDAG::getConstant(),getCopyToPartsVector(),getEVTString(),llvm::SelectionDAG::getNode(),getPackedVectorTypeFromPredicateType(),getPredicateForScalableVector(),getPredicateRegisterClass(),getPromotedVTForPredicate(),llvm::AArch64TargetLowering::getSetCCResultType(),llvm::RISCVTargetLowering::getSetCCResultType(),llvm::SelectionDAG::getSplat(),llvm::SelectionDAG::getSplatSourceVector(),llvm::SelectionDAG::getStepVector(),getSVEPredicateBitCast(),getVectorNumElements(),llvm::TargetLowering::getVectorSubVecPointer(),llvm::TargetLowering::IncrementMemoryAddress(),llvm::RISCVTargetLowering::isCtpopFast(),llvm::RISCVTargetLowering::isExtractSubvectorCheap(),llvm::HexagonSubtarget::isHVXVectorType(),llvm::RISCVTTIImpl::isLegalMaskedGatherScatter(),isPassedInFPR(),isRound(),isScalableVT(),llvm::SelectionDAG::isSplatValue(),isUnpackedVectorVT(),llvm::RISCVTargetLowering::joinRegisterPartsIntoValue(),llvm::RISCVTargetLowering::LowerCall(),llvm::RISCVTargetLowering::LowerOperation(),LowerSVEIntrinsicEXT(),LowerVectorMatch(),performANDCombine(),performBSPExpandForSVE(),performBUILD_VECTORCombine(),performCONCAT_VECTORSCombine(),performConcatVectorsCombine(),performExtractSubvectorCombine(),performFirstTrueTestVectorCombine(),performGatherLoadCombine(),performINSERT_VECTOR_ELTCombine(),performLastTrueTestVectorCombine(),performLOADCombine(),performScatterStoreCombine(),performSVEMulAddSubCombine(),performTruncateCombine(),llvm::AArch64TargetLowering::ReconstructShuffle(),ReconstructShuffleWithRuntimeMask(),replaceZeroVectorStore(),llvm::TargetLowering::scalarizeVectorLoad(),llvm::TargetLowering::scalarizeVectorStore(),SelectOpcodeFromVT(),llvm::AArch64TargetLowering::shouldFoldSelectWithIdentityConstant(),llvm::AArch64TargetLowering::shouldReduceLoadWidth(),llvm::TargetLowering::SimplifyDemandedBits(),llvm::TargetLowering::SimplifyDemandedVectorElts(),llvm::TargetLowering::SimplifyMultipleUseDemandedBits(),llvm::RISCVTargetLowering::splitValueIntoRegisterParts(),llvm::SelectionDAG::SplitVector(),takeInexpensiveLog2(),tryCombineToBSL(),tryLowerPartialReductionToDot(), andtrySimplifySrlAddToRshrnb().

Return true if the type is a scalable type.

Definition at line187 of fileValueTypes.h.

ReferencesisScalableTargetExtVT(), andisScalableVector().

Referenced bycanLowerSRLToRoundingShiftForVT(),performSelectCombine(), andperformVecReduceAddCombine().

Return true if this is an integer, but not a vector.

Definition at line157 of fileValueTypes.h.

ReferencesisSimple().

Referenced bycombineBitcast(),combineBMILogicOp(),combineCastedMaskArithmetic(),combineExtractWithShuffle(),combineOr(),combineScalarCTPOPToVCPOP(),combineSetCC(),combineToExtendBoolVectorInReg(),combineVectorSizedSetCCEquality(),llvm::ARMTargetLowering::convertSetCCLogicToBitwiseLogic(),llvm::PPCTargetLowering::convertSetCCLogicToBitwiseLogic(),llvm::RISCVTargetLowering::convertSetCCLogicToBitwiseLogic(),llvm::SystemZTargetLowering::convertSetCCLogicToBitwiseLogic(),llvm::X86TargetLowering::convertSetCCLogicToBitwiseLogic(),llvm::LoongArchTargetLowering::decomposeMulByConstant(),llvm::PPCTargetLowering::decomposeMulByConstant(),llvm::RISCVTargetLowering::decomposeMulByConstant(),llvm::XtensaTargetLowering::decomposeMulByConstant(),llvm::TargetLowering::expandABD(),llvm::TargetLowering::expandAVG(),expandDivFix(),getReducedGprRegisterClass(),handleCMSEValue(),llvm::SystemZTTIImpl::hasDivRemOp(),llvm::RISCVTargetLowering::isDesirableToCommuteWithShift(),llvm::TargetLoweringBase::isPaddedAtMostSignificantBitsWhenStored(),llvm::X86TargetLowering::isTruncateFree(),isWorthFoldingAdd(),LowerSELECTWithCmpZero(),performAddCSelIntoCSinc(),performAddUADDVCombine(),performBitcastCombine(),performBITREVERSECombine(),llvm::RISCVTargetLowering::PerformDAGCombine(),performSETCCCombine(),llvm::AArch64TargetLowering::preferIncOfAddToSubOfNot(),llvm::ARMTargetLowering::preferIncOfAddToSubOfNot(),llvm::PPCTargetLowering::preferIncOfAddToSubOfNot(),PromoteScalarIntegerPTX(),truncateScalarIntegerArg(),tryDemorganOfBooleanCondition(), anduseInversedSetcc().

Test if the givenEVT is simple (as opposed to being extended).

Definition at line137 of fileValueTypes.h.

Referencesllvm::MVT::INVALID_SIMPLE_VALUE_TYPE.

Referenced byllvm::HexagonTargetLowering::allowsMemoryAccess(),llvm::ARMTargetLowering::allowsMisalignedMemoryAccesses(),llvm::HexagonTargetLowering::allowsMisalignedMemoryAccesses(),llvm::PPCTargetLowering::allowsMisalignedMemoryAccesses(),llvm::R600TargetLowering::allowsMisalignedMemoryAccesses(),analyzeCallOperands(),llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(),llvm::TargetLowering::BuildSDIV(),llvm::TargetLowering::BuildUDIV(),changeTypeToInteger(),changeVectorElementType(),changeVectorElementTypeToInteger(),combineAndMaskToShift(),combineBitcastvxi1(),combineConcatVectorOps(),combineMul(),combineScalarCTPOPToVCPOP(),combineStore(),combineVectorInsert(),combineX86ShufflesRecursively(),llvm::createUnpackShuffleMask(),llvm::TargetLowering::expandBSWAP(),llvm::TargetLowering::expandVPBSWAP(),llvm::SelectionDAG::FoldSetCC(),foldVectorXorShiftIntoCmp(),llvm::X86TTIImpl::getArithmeticReductionCost(),llvm::ARMTTIImpl::getArithmeticReductionCost(),llvm::AArch64TTIImpl::getCastInstrCost(),llvm::ARMTTIImpl::getCastInstrCost(),llvm::X86TTIImpl::getCastInstrCost(),llvm::AArch64TTIImpl::getCmpSelInstrCost(),llvm::ARMTTIImpl::getCmpSelInstrCost(),llvm::ARMTTIImpl::getExtendedReductionCost(),getExtensionTo64Bits(),getFauxShuffleMask(),llvm::X86TTIImpl::getInterleavedMemoryOpCost(),llvm::AArch64TTIImpl::getIntrinsicInstrCost(),llvm::X86TTIImpl::getMinMaxReductionCost(),llvm::ARMTTIImpl::getMulAccReductionCost(),llvm::TargetLoweringBase::getNumRegisters(),llvm::HexagonTargetLowering::getPostIndexedAddressParts(),getRawBits(),llvm::FastISel::getRegForValue(),llvm::TargetLoweringBase::getRegisterType(),llvm::M68kTargetLowering::getScalarShiftAmountTy(),llvm::X86TTIImpl::getShuffleCost(),getShuffleHalfVectors(),getSimpleVT(),getSizeInBits(),getSVEContainerType(),getTargetShuffleInputs(),getTargetVShiftNode(),llvm::TargetLoweringBase::getTypeConversion(),llvm::BasicTTIImplBase< T >::getTypeLegalizationCost(),llvm::SelectionDAG::getValueType(),getVectorElementCount(),getVectorElementType(),getVectorLoweringShape(),getVectorNumElements(),llvm::AArch64TargetLowering::hasPairedLoad(),is1024BitVector(),is128BitVector(),is16BitVector(),is2048BitVector(),is256BitVector(),is32BitVector(),is512BitVector(),is64BitVector(),isConstantSplatVectorMaskForType(),isExtended(),llvm::HexagonTargetLowering::isExtractSubvectorCheap(),isFixedLengthVector(),isFloatingPoint(),llvm::AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(),llvm::LoongArchTargetLowering::isFMAFasterThanFMulAndFAdd(),llvm::RISCVTargetLowering::isFMAFasterThanFMulAndFAdd(),llvm::SystemZTargetLowering::isFMAFasterThanFMulAndFAdd(),llvm::X86TargetLowering::isFMAFasterThanFMulAndFAdd(),llvm::ARMTargetLowering::isFNegFree(),llvm::PPCTargetLowering::isFPImmLegal(),llvm::HexagonSubtarget::isHVXVectorType(),llvm::TargetLoweringBase::isIndexedLoadLegal(),llvm::TargetLoweringBase::isIndexedMaskedLoadLegal(),llvm::TargetLoweringBase::isIndexedMaskedStoreLegal(),llvm::TargetLoweringBase::isIndexedStoreLegal(),isInteger(),isLegalAddressImmediate(),llvm::ARMTargetLowering::isLegalAddressingMode(),llvm::RISCVTargetLowering::isLegalElementTypeForRVV(),llvm::TargetLoweringBase::isLoadBitCastBeneficial(),isSaturatingMinMax(),isScalableTargetExtVT(),isScalableVector(),isScalarInteger(),llvm::X86TargetLowering::isShuffleMaskLegal(),isSupportedType(),llvm::HexagonTargetLowering::isTruncateFree(),llvm::HexagonSubtarget::isTypeForHVX(),llvm::TargetLoweringBase::isTypeLegal(),isVector(),isVectorElementSwap(),llvm::AArch64TargetLowering::isZExtFree(),llvm::ARMTargetLowering::isZExtFree(),llvm::X86TargetLowering::isZExtFree(),llvm::XCoreTargetLowering::isZExtFree(),LowerADDSUBSAT(),llvm::VETargetLowering::lowerToVVP(),llvm::TargetLowering::ParseConstraints(),llvm::PPCTargetLowering::PerformDAGCombine(),PerformEXTRACTCombine(),performTruncateCombine(),performUzpCombine(),performVSelectCombine(),ReplaceINTRINSIC_W_CHAIN(),llvm::FastISel::selectBinaryOp(),llvm::FastISel::selectCast(),llvm::FastISel::selectExtractValue(),llvm::HexagonDAGToDAGISel::SelectIndexedLoad(),llvm::HexagonDAGToDAGISel::SelectIndexedStore(),llvm::ARMTargetLowering::shouldConvertFpToSat(),llvm::RISCVTargetLowering::shouldConvertFpToSat(),llvm::TargetLoweringBase::shouldFormOverflowOp(),llvm::X86TargetLowering::shouldFormOverflowOp(),llvm::TargetLowering::SimplifyDemandedBits(),supportedVectorShiftWithImm(),supportedVectorVarShift(),tryGetOriginalBoolVectorType(),usePartialVectorLoads(),llvm::AArch64TargetLowering::useSVEForFixedLengthVectorVT(), andvectorToScalarBitmask().

Return true if this is a vector value type.

Definition at line168 of fileValueTypes.h.

ReferencesisSimple().

Referenced byadjustLoadValueTypeImpl(),llvm::X86TargetLowering::allowsMemoryAccess(),llvm::PPCTargetLowering::allowsMisalignedMemoryAccesses(),llvm::RISCVTargetLowering::allowsMisalignedMemoryAccesses(),llvm::X86TargetLowering::allowsMisalignedMemoryAccesses(),llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(),llvm::TargetLowering::BuildSDIV(),llvm::TargetLowering::BuildUDIV(),CanCombineFCOPYSIGN_EXTEND_ROUND(),canExpandVectorCTPOP(),changeElementType(),changeTypeToInteger(),CollectOpsToWiden(),combineAdd(),combineAnd(),combineAVG(),combineBinOpOfZExt(),combineBitcast(),combineBitcastToBoolVector(),combineBITREVERSE(),combineBoolVectorAndTruncateStore(),combineCastedMaskArithmetic(),combineConcatVectorOfCasts(),combineConcatVectorOps(),combineExtSetcc(),combineFMinNumFMaxNum(),combineFP_EXTEND(),combineFP_ROUND(),combineLoad(),combineMul(),combineMulToPMADDWD(),combineMulToPMULDQ(),combineOr(),combinePMULH(),combinePTESTCC(),combineScalarAndWithMaskSetcc(),llvm::VETargetLowering::combineSelect(),combineSelect(),combineSelectAndUse(),llvm::VETargetLowering::combineSelectCC(),combineSetCC(),combineSext(),combineShiftLeft(),combineShiftRightArithmetic(),combineShiftToAVG(),combineShiftToMULH(),combineShiftToPMULH(),combineShuffleOfBitcast(),combineSIntToFP(),combineStore(),combineTargetShuffle(),combineToExtendBoolVectorInReg(),combineTruncatedArithmetic(),combineTruncateWithSat(),combineTruncOfSraSext(),combineTruncSelectToSMaxUSat(),combineUIntToFP(),combineVectorCompareAndMaskUnaryOp(),combineVectorMulToSraBitcast(),CombineVMOVDRRCandidateWithVecOp(),combineVSelectWithAllOnesOrZeros(),combineX86ShufflesRecursively(),combineXor(),combineZext(),llvm::SelectionDAG::computeKnownBits(),llvm::ARMTargetLowering::computeKnownBitsForTargetNode(),llvm::SystemZTargetLowering::computeKnownBitsForTargetNode(),llvm::X86TargetLowering::computeKnownBitsForTargetNode(),llvm::SelectionDAG::ComputeNumSignBits(),ComputePTXValueVTs(),llvm::SelectionDAG::computeVectorKnownZeroElements(),constructRetValue(),llvm::X86TargetLowering::convertSelectOfConstantsToMath(),llvm::TargetLowering::createSelectForFMINNUM_FMAXNUM(),detectPMADDUBSW(),earlyExpandDIVFIX(),EltsFromConsecutiveLoads(),llvm::TargetLowering::expandABD(),llvm::TargetLowering::expandABS(),llvm::TargetLowering::expandAddSubSat(),llvm::TargetLowering::expandCTLZ(),llvm::TargetLowering::expandCTPOP(),llvm::TargetLowering::expandCTTZ(),expandDivFix(),llvm::TargetLowering::expandFixedPointMul(),llvm::TargetLowering::expandFMINIMUM_FMAXIMUM(),llvm::TargetLowering::expandFMINIMUMNUM_FMAXIMUMNUM(),llvm::TargetLowering::expandFP_ROUND(),llvm::TargetLowering::expandFP_TO_UINT(),llvm::TargetLowering::expandFunnelShift(),llvm::TargetLowering::expandIntMINMAX(),llvm::TargetLowering::expandIS_FPCLASS(),llvm::TargetLowering::expandMUL_LOHI(),llvm::TargetLowering::expandMULO(),llvm::SelectionDAG::expandMultipleResultFPLibCall(),llvm::TargetLowering::expandROT(),llvm::TargetLowering::expandShlSat(),llvm::TargetLowering::expandUINT_TO_FP(),llvm::TargetLowering::expandUnalignedLoad(),llvm::TargetLowering::expandUnalignedStore(),llvm::TargetLowering::expandVectorNaryOpBySplitting(),llvm::TargetLowering::findOptimalMemOpLowering(),llvm::SelectionDAG::FoldConstantArithmetic(),foldIndexIntoBase(),foldVectorXorShiftIntoCmp(),llvm::SelectionDAG::getBitcastedAnyExtOrTrunc(),llvm::SelectionDAG::getBitcastedSExtOrTrunc(),llvm::SelectionDAG::getBitcastedZExtOrTrunc(),llvm::VECustomDAG::getBroadcast(),llvm::ARMTTIImpl::getCastInstrCost(),llvm::SelectionDAG::getConstant(),llvm::SelectionDAG::getConstantFP(),getCopyFromParts(),getCopyFromPartsVector(),getCopyToParts(),getCopyToPartsVector(),getDemandedSrcElements(),getEVTString(),getEXTEND_VECTOR_INREG(),getFauxShuffleMask(),getHalfSizedIntegerVT(),getKnownUndefForVectorBinop(),llvm::SelectionDAG::getLoad(),getMemcpyLoadsAndStores(),getMemsetStores(),getMemsetStringVal(),llvm::SelectionDAG::getNode(),llvm::TargetLoweringBase::getNumRegisters(),llvm::SITargetLowering::getNumRegistersForCallingConv(),llvm::MipsTargetLowering::getNumRegistersForCallingConv(),llvm::SPIRVTargetLowering::getNumRegistersForCallingConv(),llvm::X86TargetLowering::getNumRegistersForCallingConv(),llvm::ARMTargetLowering::getPostIndexedAddressParts(),llvm::ARMTargetLowering::getPreIndexedAddressParts(),llvm::PPCTargetLowering::getPreIndexedAddressParts(),getReciprocalOpName(),llvm::SelectionDAG::getReducedAlign(),llvm::TargetLoweringBase::getRegisterType(),llvm::SITargetLowering::getRegisterTypeForCallingConv(),llvm::MipsTargetLowering::getRegisterTypeForCallingConv(),llvm::SPIRVTargetLowering::getRegisterTypeForCallingConv(),llvm::SystemZTargetLowering::getRegisterTypeForCallingConv(),llvm::X86TargetLowering::getRegisterTypeForCallingConv(),getRoundIntegerType(),getScalarType(),llvm::ARMTargetLowering::getSchedulingPreference(),llvm::SelectionDAG::getSetCC(),llvm::XtensaTargetLowering::getSetCCResultType(),llvm::HexagonTargetLowering::getSetCCResultType(),llvm::R600TargetLowering::getSetCCResultType(),llvm::SystemZTargetLowering::getSetCCResultType(),llvm::TargetLoweringBase::getSetCCResultType(),llvm::AArch64TargetLowering::getSetCCResultType(),llvm::SITargetLowering::getSetCCResultType(),llvm::ARMTargetLowering::getSetCCResultType(),llvm::AVRTargetLowering::getSetCCResultType(),llvm::CSKYTargetLowering::getSetCCResultType(),llvm::LoongArchTargetLowering::getSetCCResultType(),llvm::MipsTargetLowering::getSetCCResultType(),llvm::PPCTargetLowering::getSetCCResultType(),llvm::RISCVTargetLowering::getSetCCResultType(),llvm::SparcTargetLowering::getSetCCResultType(),llvm::X86TargetLowering::getSetCCResultType(),llvm::NVPTXTargetLowering::getSetCCResultType(),llvm::SelectionDAG::getShiftAmountOperand(),llvm::TargetLoweringBase::getShiftAmountTy(),llvm::X86TTIImpl::getShuffleCost(),getShuffleScalarElt(),llvm::SelectionDAG::getSplat(),llvm::SelectionDAG::GetSplitDestVTs(),getTargetShuffleInputs(),llvm::SelectionDAG::getTruncStore(),llvm::SelectionDAG::getTruncStoreVP(),llvm::SelectionDAG::getTruncStridedStoreVP(),llvm::TargetLoweringBase::getTypeConversion(),llvm::AMDGPUTargetLowering::getTypeForExtReturn(),llvm::getTypePacking(),llvm::TargetLoweringBase::getTypeToExpandTo(),getVectorElementCount(),getVectorElementType(),getVectorLoweringShape(),getVectorNumElements(),llvm::TargetLoweringBase::getVectorTypeBreakdown(),llvm::SITargetLowering::getVectorTypeBreakdownForCallingConv(),llvm::X86TargetLowering::getVectorTypeBreakdownForCallingConv(),llvm::SelectionDAG::getVPZeroExtendInReg(),llvm::SelectionDAG::getZeroExtendInReg(),getZeroVector(),llvm::AArch64TargetLowering::hasAndNot(),llvm::VETargetLowering::hasAndNot(),llvm::X86TargetLowering::hasAndNot(),llvm::RISCVTargetLowering::hasAndNotCompare(),llvm::X86TargetLowering::hasAndNotCompare(),llvm::BuildVectorSDNode::isConstantSplat(),llvm::X86TargetLowering::isDesirableToCombineLogicOpOfSETCC(),isExtendedFrom16Bits(),llvm::RISCVTargetLowering::isFMAFasterThanFMulAndFAdd(),isHorizontalBinOpPart(),llvm::HexagonSubtarget::isHVXVectorType(),llvm::AArch64TargetLowering::isIntDivCheap(),llvm::RISCVTargetLowering::isIntDivCheap(),llvm::X86TargetLowering::isIntDivCheap(),isLegalT2AddressImmediate(),llvm::X86TargetLowering::isLoadBitCastBeneficial(),llvm::isMaskType(),isMImm(),llvm::AArch64TargetLowering::isMulAddWithConstProfitable(),llvm::ARMTargetLowering::isMulAddWithConstProfitable(),llvm::RISCVTargetLowering::isMulAddWithConstProfitable(),llvm::AMDGPUTargetLowering::isNarrowingProfitable(),llvm::isPackedVectorType(),isPackedVectorType(),isSimm7(),llvm::SelectionDAG::isSplatValue(),isSupportedType(),llvm::ARMTargetLowering::isTruncateFree(),llvm::RISCVTargetLowering::isTruncateFree(),llvm::AArch64TargetLowering::isTruncateFree(),llvm::X86TargetLowering::isTypeDesirableForOp(),isVectorElementSwap(),isVShiftLImm(),isVShiftRImm(),llvm::X86TargetLowering::isXAndYEqZeroPreferableToXAndYEqY(),llvm::AArch64TargetLowering::isZExtFree(),lowerBuildVectorAsBroadcast(),LowerCTTZ(),llvm::AMDGPUTargetLowering::lowerFEXP(),LowerFMINIMUM_FMAXIMUM(),llvm::R600TargetLowering::LowerFormalArguments(),lowerLaneOp(),llvm::VETargetLowering::lowerLOAD(),llvm::RISCVTargetLowering::LowerOperation(),LowerShift(),lowerStatepointMetaArgs(),LowerStore(),llvm::VETargetLowering::lowerSTORE(),LowerTruncateVectorStore(),llvm::ARMTargetLowering::LowerXConstraint(),matchPMADDWD(),matchPMADDWD_2(),llvm::X86TargetLowering::mergeStoresAfterLegalization(),llvm::MipsCCState::originalEVTTypeIsVectorFloat(),padEltsToUndef(),PerformADDCombine(),llvm::AMDGPUTargetLowering::PerformDAGCombine(),llvm::PPCTargetLowering::PerformDAGCombine(),llvm::RISCVTargetLowering::PerformDAGCombine(),PerformFADDCombine(),performFP_TO_INTCombine(),llvm::AMDGPUTargetLowering::performLoadCombine(),PerformLOADCombine(),performMADD_MSUBCombine(),PerformMinMaxFpToSatCombine(),llvm::AMDGPUTargetLowering::performMulCombine(),performMULCombine(),PerformMULCombineWithOperands(),llvm::AMDGPUTargetLowering::performMulhsCombine(),llvm::AMDGPUTargetLowering::performMulhuCombine(),PerformORCombine(),performSelectCombine(),PerformShiftCombine(),PerformSplittingMVEEXTToWideningLoad(),PerformSplittingToNarrowingStores(),PerformSplittingToWideningLoad(),llvm::AMDGPUTargetLowering::performStoreCombine(),PerformSTORECombine(),llvm::AMDGPUTargetLowering::performTruncateCombine(),performTruncateCombine(),PerformTruncatingStoreCombine(),PerformUMinFpToSatCombine(),performVectorCompareAndMaskUnaryOpCombine(),PerformVQDMULHCombine(),llvm::X86TargetLowering::preferedOpcodeForCmpEqPiecesOfOperand(),llvm::X86TargetLowering::preferSextInRegOfTruncate(),PromoteBinOpToF32(),PromoteMaskArithmetic(),replaceBoolVectorBitcast(),ReplaceINTRINSIC_W_CHAIN(),ReplaceLoadVector(),llvm::RISCVTargetLowering::ReplaceNodeResults(),llvm::X86TargetLowering::ReplaceNodeResults(),llvm::AMDGPUTargetLowering::shouldCombineMemoryType(),llvm::X86TargetLowering::shouldFoldConstantShiftPairToMask(),llvm::X86TargetLowering::shouldFoldMaskToVariableShiftPair(),llvm::RISCVTargetLowering::shouldFoldSelectWithIdentityConstant(),llvm::X86TargetLowering::shouldFoldSelectWithIdentityConstant(),llvm::TargetLoweringBase::shouldFormOverflowOp(),llvm::X86TargetLowering::shouldFormOverflowOp(),llvm::TargetLoweringBase::shouldReduceLoadWidth(),llvm::AArch64TargetLowering::shouldTransformSignedTruncationCheck(),llvm::RISCVTargetLowering::shouldTransformSignedTruncationCheck(),llvm::X86TargetLowering::shouldTransformSignedTruncationCheck(),llvm::TargetLowering::ShrinkDemandedConstant(),llvm::TargetLowering::ShrinkDemandedOp(),llvm::TargetLowering::SimplifyDemandedBits(),llvm::TargetLowering::SimplifyDemandedVectorElts(),llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(),llvm::TargetLowering::SimplifyMultipleUseDemandedBits(),llvm::TargetLowering::SimplifySetCC(),simplifySetCCWithCTPOP(),llvm::SelectionDAG::SplitScalar(),llvm::SITargetLowering::splitTernaryVectorOp(),llvm::AMDGPUTargetLowering::splitVector(),llvm::AMDGPUTargetLowering::SplitVectorLoad(),stripModuloOnShift(),takeInexpensiveLog2(),llvm::AArch64TargetLowering::targetShrinkDemandedConstant(),llvm::ARMTargetLowering::targetShrinkDemandedConstant(),llvm::RISCVTargetLowering::targetShrinkDemandedConstant(),llvm::X86TargetLowering::targetShrinkDemandedConstant(),transformAddImmMulImm(),transformAddShlImm(),truncateAVX512SetCCNoBWI(),truncateVectorWithPACK(),tryCombineToBSL(),tryFoldToZero(),tryGetOriginalBoolVectorType(),tryLowerToSLI(),tryToFoldExtendOfConstant(),tryToFoldExtOfExtload(),tryToFoldExtOfLoad(),tryToReplaceScalarFPConversionWithSVE(),tryToWidenSetCCOperands(),llvm::SelectionDAG::UnrollVectorOp(),vectorToScalarBitmask(),VerifySDNode(),llvm::AArch64TargetLowering::verifyTargetSDNode(),widenAbs(),widenVec(), andwidenVectorToPartType().

Test if the givenEVT has zero size, this will fail if called on a scalable type.

Definition at line132 of fileValueTypes.h.

ReferencesgetSizeInBits(), andllvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isZero().

Referenced byllvm::TargetLoweringBase::allowsMemoryAccessForAlignment(), andisByteSized().

Return true if we know at compile time this has more than or the same bits as VT.

Definition at line263 of fileValueTypes.h.

ReferencesgetSizeInBits(), andllvm::details::FixedOrScalableQuantity< TypeSize, uint64_t >::isKnownGE().

Referenced bybitsGE().

Return true if we know at compile time this has more bits than VT.

Definition at line257 of fileValueTypes.h.

ReferencesgetSizeInBits(), andllvm::details::FixedOrScalableQuantity< TypeSize, uint64_t >::isKnownGT().

Referenced bybitsGT().

Return true if we know at compile time this has fewer than or the same bits as VT.

Definition at line274 of fileValueTypes.h.

ReferencesgetSizeInBits(), andllvm::details::FixedOrScalableQuantity< TypeSize, uint64_t >::isKnownLE().

Referenced bybitsLE().

Return true if we know at compile time this has fewer bits than VT.

Definition at line268 of fileValueTypes.h.

ReferencesgetSizeInBits(), andllvm::details::FixedOrScalableQuantity< TypeSize, uint64_t >::isKnownLT().

Referenced bybitsLT().

Definition at line48 of fileValueTypes.h.

Referencesllvm::MVT::INVALID_SIMPLE_VALUE_TYPE, andllvm::MVT::SimpleTy.

Definition at line45 of fileValueTypes.h.

Implement operator<<.

Definition at line491 of fileValueTypes.h.

ReferencesgetEVTString(), andOS.

Referenced bydump().

Return a VT for an integer vector type with the size of the elements doubled.

The typed returned may be an extended type.

Definition at line439 of fileValueTypes.h.

ReferencesgetIntegerVT(),getSizeInBits(),getVectorElementCount(),getVectorElementType(), andgetVectorVT().

Referenced byperformMSTORECombine().