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LLVM 20.0.0git
Namespaces |Classes |Typedefs |Enumerations |Functions |Variables
llvm::AMDGPU Namespace Reference

Namespaces

namespace  Barrier
 
namespace  CPol
 
namespace  DepCtr
 
namespace  DPP
 
namespace  ElfNote
 
namespace  EncValues
 
namespace  Exp
 
namespace  GenericVersion
 Generic target versions emitted by this version of LLVM.
 
namespace  HSAMD
 
namespace  HWEncoding
 
namespace  Hwreg
 
namespace  ImplicitArg
 
namespace  IsaInfo
 
namespace  MFMAScaleFormats
 
namespace  MTBUFFormat
 
namespace  PALMD
 
namespace  SDWA
 
namespace  SendMsg
 
namespace  Swizzle
 
namespace  UCVersion
 
namespace  UfmtGFX10
 
namespace  UfmtGFX11
 
namespace  VGPRIndexMode
 
namespace  VirtRegFlag
 
namespace  VOP3PEncoding
 
namespace  VOPD
 

Classes

struct  AMDGPUMCKernelCodeT
 
struct  CanBeVOPD
 
struct  CustomOperand
 
struct  CustomOperandVal
 
struct  CvtScaleF32_F32F16ToF8F4_Info
 
struct  D16ImageDimIntrinsic
 
struct  DPMACCInstructionInfo
 
struct  EncodingField
 
struct  EncodingFields
 
struct  FP4FP8DstByteSelInfo
 
struct  GcnBufferFormatInfo
 
struct  ImageDimIntrinsicInfo
 
class  IntrinsicLaneMaskAnalyzer
 
struct  IsaVersion
 Instruction set architecture version.More...
 
struct  LDSUsesInfoTy
 
struct  MAIInstInfo
 
struct  MCKernelDescriptor
 
struct  MFMA_F8F6F4_Info
 
struct  MIMGBaseOpcodeInfo
 
struct  MIMGBiasMappingInfo
 
struct  MIMGDimInfo
 
struct  MIMGG16MappingInfo
 
struct  MIMGInfo
 
struct  MIMGLZMappingInfo
 
struct  MIMGMIPMappingInfo
 
struct  MIMGOffsetMappingInfo
 
struct  MTBUFInfo
 
struct  MUBUFInfo
 
struct  PredicateMapping
 
class  RegBankLegalizeHelper
 
struct  RegBankLegalizeRule
 
class  RegBankLegalizeRules
 
struct  RegBankLLTMapping
 
struct  RsrcIntrinsic
 
class  SetOfRulesForOpcode
 
struct  SMInfo
 
struct  VOP3CDPPAsmOnlyInfo
 
struct  VOPC64DPPInfo
 
struct  VOPCDPPAsmOnlyInfo
 
struct  VOPDComponentInfo
 
struct  VOPDInfo
 
struct  VOPInfo
 
struct  VOPTrue16Info
 
struct  Waitcnt
 Represents the counter values to wait for in an s_waitcnt instruction.More...
 
struct  WMMAOpcodeMappingInfo
 

Typedefs

using FunctionVariableMap =DenseMap<Function *,DenseSet<GlobalVariable * > >
 
using VariableFunctionMap =DenseMap<GlobalVariable *,DenseSet<Function * > >
 
template<unsigned Bit,unsigned D = 0>
using EncodingBit =EncodingField< Bit, Bit,D >
 

Enumerations

enum  GPUKind : uint32_t {
  GK_NONE = 0,GK_R600 = 1,GK_R630 = 2,GK_RS880 = 3,
  GK_RV670 = 4,GK_RV710 = 5,GK_RV730 = 6,GK_RV770 = 7,
  GK_CEDAR = 8,GK_CYPRESS = 9,GK_JUNIPER = 10,GK_REDWOOD = 11,
  GK_SUMO = 12,GK_BARTS = 13,GK_CAICOS = 14,GK_CAYMAN = 15,
  GK_TURKS = 16,GK_R600_FIRST = GK_R600,GK_R600_LAST = GK_TURKS,GK_GFX600 = 32,
  GK_GFX601 = 33,GK_GFX602 = 34,GK_GFX700 = 40,GK_GFX701 = 41,
  GK_GFX702 = 42,GK_GFX703 = 43,GK_GFX704 = 44,GK_GFX705 = 45,
  GK_GFX801 = 50,GK_GFX802 = 51,GK_GFX803 = 52,GK_GFX805 = 53,
  GK_GFX810 = 54,GK_GFX900 = 60,GK_GFX902 = 61,GK_GFX904 = 62,
  GK_GFX906 = 63,GK_GFX908 = 64,GK_GFX909 = 65,GK_GFX90A = 66,
  GK_GFX90C = 67,GK_GFX940 = 68,GK_GFX941 = 69,GK_GFX942 = 70,
  GK_GFX950 = 71,GK_GFX1010 = 72,GK_GFX1011 = 73,GK_GFX1012 = 74,
  GK_GFX1013 = 75,GK_GFX1030 = 76,GK_GFX1031 = 77,GK_GFX1032 = 78,
  GK_GFX1033 = 79,GK_GFX1034 = 80,GK_GFX1035 = 81,GK_GFX1036 = 82,
  GK_GFX1100 = 90,GK_GFX1101 = 91,GK_GFX1102 = 92,GK_GFX1103 = 93,
  GK_GFX1150 = 94,GK_GFX1151 = 95,GK_GFX1152 = 96,GK_GFX1153 = 97,
  GK_GFX1200 = 100,GK_GFX1201 = 101,GK_AMDGCN_FIRST = GK_GFX600,GK_AMDGCN_LAST = GK_GFX1201,
  GK_GFX9_GENERIC = 192,GK_GFX10_1_GENERIC = 193,GK_GFX10_3_GENERIC = 194,GK_GFX11_GENERIC = 195,
  GK_GFX12_GENERIC = 196,GK_GFX9_4_GENERIC = 197,GK_AMDGCN_GENERIC_FIRST = GK_GFX9_GENERIC,GK_AMDGCN_GENERIC_LAST = GK_GFX9_4_GENERIC
}
 GPU kinds supported by the AMDGPU target.More...
 
enum  ArchFeatureKind : uint32_t {
  FEATURE_NONE = 0,FEATURE_FMA = 1 << 1,FEATURE_LDEXP = 1 << 2,FEATURE_FP64 = 1 << 3,
  FEATURE_FAST_FMA_F32 = 1 << 4,FEATURE_FAST_DENORMAL_F32 = 1 << 5,FEATURE_WAVE32 = 1 << 6,FEATURE_XNACK = 1 << 7,
  FEATURE_SRAMECC = 1 << 8,FEATURE_WGP = 1 << 9
}
 
enum  FeatureError : uint32_t {NO_ERROR = 0,INVALID_FEATURE_COMBINATION,UNSUPPORTED_TARGET_FEATURE }
 
enum  TargetIndex {
  TI_CONSTDATA_START,TI_SCRATCH_RSRC_DWORD0,TI_SCRATCH_RSRC_DWORD1,TI_SCRATCH_RSRC_DWORD2,
  TI_SCRATCH_RSRC_DWORD3
}
 
enum class  SchedulingPhase {Initial,PreRAReentry,PostRA }
 
enum  UniformityLLTOpPredicateID {
  _,S1,S16,S32,
  S64,UniS1,UniS16,UniS32,
  UniS64,DivS1,DivS32,DivS64,
  P1,P3,P4,P5,
  UniP1,UniP3,UniP4,UniP5,
  DivP1,DivP3,DivP4,DivP5,
  V2S16,V2S32,V3S32,V4S32,
  B32,B64,B96,B128,
  B256,B512,UniB32,UniB64,
  UniB96,UniB128,UniB256,UniB512,
  DivB32,DivB64,DivB96,DivB128,
  DivB256,DivB512
}
 
enum  RegBankLLTMappingApplyID {
  InvalidMapping,None,IntrId,Imm,
  Vcc,Sgpr16,Sgpr32,Sgpr64,
  SgprP1,SgprP3,SgprP4,SgprP5,
  SgprV4S32,SgprB32,SgprB64,SgprB96,
  SgprB128,SgprB256,SgprB512,Vgpr32,
  Vgpr64,VgprP1,VgprP3,VgprP4,
  VgprP5,VgprB32,VgprB64,VgprB96,
  VgprB128,VgprB256,VgprB512,VgprV4S32,
  UniInVcc,UniInVgprS32,UniInVgprV4S32,UniInVgprB32,
  UniInVgprB64,UniInVgprB96,UniInVgprB128,UniInVgprB256,
  UniInVgprB512,Sgpr32Trunc,Sgpr32AExt,Sgpr32AExtBoolInReg,
  Sgpr32SExt
}
 
enum  LoweringMethodID {
  DoNotLower,UniExtToSel,VgprToVccCopy,SplitTo32,
  Ext32To64,UniCstExt,SplitLoad,WidenLoad
}
 
enum  FastRulesTypes {NoFastRules,Standard,StandardB,Vector }
 
enum  Fixups {fixup_si_sopp_br = FirstTargetFixupKind,LastTargetFixupKind,NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind }
 
enum  OperandType : unsigned {
  OPERAND_REG_IMM_INT32 = MCOI::OPERAND_FIRST_TARGET,OPERAND_REG_IMM_INT64,OPERAND_REG_IMM_INT16,OPERAND_REG_IMM_FP32,
  OPERAND_REG_IMM_FP64,OPERAND_REG_IMM_BF16,OPERAND_REG_IMM_FP16,OPERAND_REG_IMM_BF16_DEFERRED,
  OPERAND_REG_IMM_FP16_DEFERRED,OPERAND_REG_IMM_FP32_DEFERRED,OPERAND_REG_IMM_V2BF16,OPERAND_REG_IMM_V2FP16,
  OPERAND_REG_IMM_V2INT16,OPERAND_REG_IMM_V2INT32,OPERAND_REG_IMM_V2FP32,OPERAND_REG_INLINE_C_INT16,
  OPERAND_REG_INLINE_C_INT32,OPERAND_REG_INLINE_C_INT64,OPERAND_REG_INLINE_C_BF16,OPERAND_REG_INLINE_C_FP16,
  OPERAND_REG_INLINE_C_FP32,OPERAND_REG_INLINE_C_FP64,OPERAND_REG_INLINE_C_V2INT16,OPERAND_REG_INLINE_C_V2BF16,
  OPERAND_REG_INLINE_C_V2FP16,OPERAND_REG_INLINE_C_V2INT32,OPERAND_REG_INLINE_C_V2FP32,OPERAND_INLINE_SPLIT_BARRIER_INT32,
  OPERAND_KIMM32,OPERAND_KIMM16,OPERAND_REG_INLINE_AC_INT16,OPERAND_REG_INLINE_AC_INT32,
  OPERAND_REG_INLINE_AC_BF16,OPERAND_REG_INLINE_AC_FP16,OPERAND_REG_INLINE_AC_FP32,OPERAND_REG_INLINE_AC_FP64,
  OPERAND_REG_INLINE_AC_V2INT16,OPERAND_REG_INLINE_AC_V2BF16,OPERAND_REG_INLINE_AC_V2FP16,OPERAND_REG_INLINE_AC_V2INT32,
  OPERAND_REG_INLINE_AC_V2FP32,OPERAND_INPUT_MODS,OPERAND_SDWA_VOPC_DST,OPERAND_REG_IMM_FIRST = OPERAND_REG_IMM_INT32,
  OPERAND_REG_IMM_LAST = OPERAND_REG_IMM_V2FP32,OPERAND_REG_INLINE_C_FIRST = OPERAND_REG_INLINE_C_INT16,OPERAND_REG_INLINE_C_LAST = OPERAND_REG_INLINE_AC_V2FP32,OPERAND_REG_INLINE_AC_FIRST = OPERAND_REG_INLINE_AC_INT16,
  OPERAND_REG_INLINE_AC_LAST = OPERAND_REG_INLINE_AC_V2FP32,OPERAND_SRC_FIRST = OPERAND_REG_IMM_INT32,OPERAND_SRC_LAST = OPERAND_REG_INLINE_C_LAST,OPERAND_KIMM_FIRST = OPERAND_KIMM32,
  OPERAND_KIMM_LAST = OPERAND_KIMM16
}
 
enum  OperandSemantics : unsigned {
  INT = 0,FP16 = 1,BF16 = 2,FP32 = 3,
  FP64 = 4
}
 
enum  AsmComments {SGPR_SPILL = MachineInstr::TAsmComments }
 
enum  AMDGPUFltRounds : int8_t {
  TowardZero = static_cast<int8_t>(RoundingMode::TowardZero),NearestTiesToEven = static_cast<int8_t>(RoundingMode::NearestTiesToEven),TowardPositive = static_cast<int8_t>(RoundingMode::TowardPositive),TowardNegative = static_cast<int8_t>(RoundingMode::TowardNegative),
  NearestTiesToAwayUnsupported,Dynamic = static_cast<int8_t>(RoundingMode::Dynamic),NearestTiesToEvenF32_NearestTiesToEvenF64 = NearestTiesToEven,NearestTiesToEvenF32_TowardPositiveF64 = 8,
  NearestTiesToEvenF32_TowardNegativeF64 = 9,NearestTiesToEvenF32_TowardZeroF64 = 10,TowardPositiveF32_NearestTiesToEvenF64 = 11,TowardPositiveF32_TowardPositiveF64 = TowardPositive,
  TowardPositiveF32_TowardNegativeF64 = 12,TowardPositiveF32_TowardZeroF64 = 13,TowardNegativeF32_NearestTiesToEvenF64 = 14,TowardNegativeF32_TowardPositiveF64 = 15,
  TowardNegativeF32_TowardNegativeF64 = TowardNegative,TowardNegativeF32_TowardZeroF64 = 16,TowardZeroF32_NearestTiesToEvenF64 = 17,TowardZeroF32_TowardPositiveF64 = 18,
  TowardZeroF32_TowardNegativeF64 = 19,TowardZeroF32_TowardZeroF64 = TowardZero,Invalid = static_cast<int8_t>(RoundingMode::Invalid)
}
 Return values used for llvm.get.rounding.More...
 
enum  {AMDHSA_COV4 = 4,AMDHSA_COV5 = 5,AMDHSA_COV6 = 6 }
 
enum class  FPType {None,FP4,FP8 }
 

Functions

bool isFlatGlobalAddrSpace (unsigned AS)
 
bool isExtendedGlobalAddrSpace (unsigned AS)
 
bool isConstantAddressSpace (unsigned AS)
 
StringRef getArchFamilyNameAMDGCN (GPUKind AK)
 
StringRef getArchNameAMDGCN (GPUKind AK)
 
StringRef getArchNameR600 (GPUKind AK)
 
StringRef getCanonicalArchName (constTriple &T,StringRef Arch)
 
GPUKind parseArchAMDGCN (StringRef CPU)
 
GPUKind parseArchR600 (StringRef CPU)
 
unsigned getArchAttrAMDGCN (GPUKind AK)
 
unsigned getArchAttrR600 (GPUKind AK)
 
void fillValidArchListAMDGCN (SmallVectorImpl<StringRef > &Values)
 
void fillValidArchListR600 (SmallVectorImpl<StringRef > &Values)
 
IsaVersion getIsaVersion (StringRef GPU)
 
void fillAMDGPUFeatureMap (StringRef GPU,constTriple &T,StringMap<bool > &Features)
 Fills Features map with default values for given target GPU.
 
std::pair<FeatureError,StringRef > insertWaveSizeFeature (StringRef GPU,constTriple &T,StringMap<bool > &Features)
 Inserts wave size feature for given GPU into features map.
 
staticbool addrspacesMayAlias (unsigned AS1,unsigned AS2)
 
staticuint64_t getRedzoneSizeForScale (int AsanScale)
 
staticuint64_t getMinRedzoneSizeForGlobal (int AsanScale)
 
uint64_t getRedzoneSizeForGlobal (int Scale,uint64_t SizeInBytes)
 Given SizeInBytes of theValue to be instrunmented, Returns the redzone size corresponding to it.
 
static size_t TypeStoreSizeToSizeIndex (uint32_tTypeSize)
 
staticInstruction * genAMDGPUReportBlock (Module &M,IRBuilder<> &IRB,Value *Cond,bool Recover)
 
staticValue * createSlowPathCmp (Module &M,IRBuilder<> &IRB,Type *IntptrTy,Value *AddrLong,Value *ShadowValue,uint32_t TypeStoreSize, int AsanScale)
 
staticInstruction * generateCrashCode (Module &M,IRBuilder<> &IRB,Type *IntptrTy,Instruction *InsertBefore,Value *Addr,bool IsWrite, size_t AccessSizeIndex,Value *SizeArgument,bool Recover)
 
staticValue * memToShadow (Module &M,IRBuilder<> &IRB,Type *IntptrTy,Value *Shadow, int AsanScale,uint32_t AsanOffset)
 
static void instrumentAddressImpl (Module &M,IRBuilder<> &IRB,Instruction *OrigIns,Instruction *InsertBefore,Value *Addr,Align Alignment,uint32_t TypeStoreSize,bool IsWrite,Value *SizeArgument,bool UseCalls,bool Recover, int AsanScale, int AsanOffset)
 
void instrumentAddress (Module &M,IRBuilder<> &IRB,Instruction *OrigIns,Instruction *InsertBefore,Value *Addr,Align Alignment,TypeSize TypeStoreSize,bool IsWrite,Value *SizeArgument,bool UseCalls,bool Recover, int Scale, intOffset)
 Instrument the memory operand Addr.
 
void getInterestingMemoryOperands (Module &M,Instruction *I,SmallVectorImpl<InterestingMemoryOperand > &Interesting)
 Get all the memory operands from the instruction that needs to be instrumented.
 
std::pair<Register,unsigned > getBaseWithConstantOffset (MachineRegisterInfo &MRI,RegisterReg,GISelKnownBits *KnownBits=nullptr,bool CheckNUW=false)
 Returns base register and constant offset.
 
void buildReadAnyLane (MachineIRBuilder &B,Register SgprDst,Register VgprSrc,constRegisterBankInfo &RBI)
 
Intrinsic::ID getIntrinsicID (constMachineInstr &I)
 Return the intrinsic ID for opcodes with the G_AMDGPU_INTRIN_ prefix.
 
constRsrcIntrinsic * lookupRsrcIntrinsic (unsignedIntr)
 
constD16ImageDimIntrinsic * lookupD16ImageDimIntrinsic (unsignedIntr)
 
constImageDimIntrinsicInfo * getImageDimIntrinsicInfo (unsignedIntr)
 
constImageDimIntrinsicInfo * getImageDimIntrinsicByBaseOpcode (unsigned BaseOpcode,unsigned Dim)
 
Align getAlign (constDataLayout &DL,constGlobalVariable *GV)
 
TargetExtType * isNamedBarrier (constGlobalVariable &GV)
 
bool isDynamicLDS (constGlobalVariable &GV)
 
bool isLDSVariableToLower (constGlobalVariable &GV)
 
bool eliminateConstantExprUsesOfLDSFromAllInstructions (Module &M)
 
void getUsesOfLDSByFunction (constCallGraph &CG,Module &M,FunctionVariableMap &kernels,FunctionVariableMap &Functions)
 
bool isKernelLDS (constFunction *F)
 
LDSUsesInfoTy getTransitiveUsesOfLDS (constCallGraph &CG,Module &M)
 
void removeFnAttrFromReachable (CallGraph &CG,Function *KernelRoot,ArrayRef<StringRef > FnAttrs)
 Strip FnAttr attribute from any functions where we may have introduced its use.
 
bool isReallyAClobber (constValue *Ptr,MemoryDef *Def,AAResults *AA)
 Given aDef clobbering a load fromPtr according to the MSSA check if this is actually a memory update or an artificial clobber to facilitate ordering constraints.
 
bool isClobberedInFunction (constLoadInst *Load,MemorySSA *MSSA,AAResults *AA)
 Check is aLoad is clobbered in its function.
 
void printAMDGPUMCExpr (constMCExpr *Expr,raw_ostream &OS,constMCAsmInfo *MAI)
 
constMCExpr * foldAMDGPUMCExpr (constMCExpr *Expr,MCContext &Ctx)
 
LLVM_READONLY int getVOPe64 (uint16_t Opcode)
 
LLVM_READONLY int getVOPe32 (uint16_t Opcode)
 
LLVM_READONLY int getSDWAOp (uint16_t Opcode)
 
LLVM_READONLY int getDPPOp32 (uint16_t Opcode)
 
LLVM_READONLY int getDPPOp64 (uint16_t Opcode)
 
LLVM_READONLY int getBasicFromSDWAOp (uint16_t Opcode)
 
LLVM_READONLY int getCommuteRev (uint16_t Opcode)
 
LLVM_READONLY int getCommuteOrig (uint16_t Opcode)
 
LLVM_READONLY int getAddr64Inst (uint16_t Opcode)
 
LLVM_READONLY int getIfAddr64Inst (uint16_t Opcode)
 Check ifOpcode is an Addr64 opcode.
 
LLVM_READONLY int getSOPKOp (uint16_t Opcode)
 
LLVM_READONLY int getGlobalSaddrOp (uint16_t Opcode)
 
LLVM_READONLY int getGlobalVaddrOp (uint16_t Opcode)
 
LLVM_READONLY int getVCMPXNoSDstOp (uint16_t Opcode)
 
LLVM_READONLY int getFlatScratchInstSTfromSS (uint16_t Opcode)
 
LLVM_READONLY int getFlatScratchInstSVfromSVS (uint16_t Opcode)
 
LLVM_READONLY int getFlatScratchInstSSfromSV (uint16_t Opcode)
 
LLVM_READONLY int getFlatScratchInstSVfromSS (uint16_t Opcode)
 
LLVM_READONLY int getMFMAEarlyClobberOp (uint16_t Opcode)
 
LLVM_READONLY int getMFMASrcCVDstAGPROp (uint16_t Opcode)
 
LLVM_READONLY int getVCMPXOpFromVCMP (uint16_t Opcode)
 
uint32_t decodeFltRoundToHWConversionTable (uint32_t FltRounds)
 Read the hardware rounding mode equivalent of a AMDGPUFltRounds value.
 
unsigned getRegBitWidth (constTargetRegisterClass &RC)
 Get the size in bits of a register from the register classRC.
 
template<size_t N>
staticStringRef getNameFromOperandTable (constCustomOperand(&Table)[N],unsigned Encoding,constMCSubtargetInfo &STI)
 Map from the encoding of a sendmsg/hwreg asm operand to it's name.
 
template<size_t N>
static int64_t getEncodingFromOperandTable (constCustomOperand(&Table)[N],StringRefName,constMCSubtargetInfo &STI)
 Map from a symbolic name for a sendmsg/hwreg asm operand to it's encoding.
 
bool hasSMRDSignedImmOffset (constMCSubtargetInfo &ST)
 
bool isHsaAbi (constMCSubtargetInfo &STI)
 
unsigned getAMDHSACodeObjectVersion (constModule &M)
 
unsigned getDefaultAMDHSACodeObjectVersion ()
 
unsigned getAMDHSACodeObjectVersion (unsigned ABIVersion)
 
uint8_t getELFABIVersion (constTriple &T,unsigned CodeObjectVersion)
 
unsigned getMultigridSyncArgImplicitArgPosition (unsigned CodeObjectVersion)
 
unsigned getHostcallImplicitArgPosition (unsigned CodeObjectVersion)
 
unsigned getDefaultQueueImplicitArgPosition (unsigned CodeObjectVersion)
 
unsigned getCompletionActionImplicitArgPosition (unsigned CodeObjectVersion)
 
int getMIMGOpcode (unsigned BaseOpcode,unsigned MIMGEncoding,unsigned VDataDwords,unsigned VAddrDwords)
 
constMIMGBaseOpcodeInfo * getMIMGBaseOpcode (unsigned Opc)
 
int getMaskedMIMGOp (unsigned Opc,unsigned NewChannels)
 
unsigned getAddrSizeMIMGOp (constMIMGBaseOpcodeInfo *BaseOpcode,constMIMGDimInfo *Dim,bool IsA16,bool IsG16Supported)
 
int getMTBUFBaseOpcode (unsigned Opc)
 
int getMTBUFOpcode (unsigned BaseOpc,unsigned Elements)
 
int getMTBUFElements (unsigned Opc)
 
bool getMTBUFHasVAddr (unsigned Opc)
 
bool getMTBUFHasSrsrc (unsigned Opc)
 
bool getMTBUFHasSoffset (unsigned Opc)
 
int getMUBUFBaseOpcode (unsigned Opc)
 
int getMUBUFOpcode (unsigned BaseOpc,unsigned Elements)
 
int getMUBUFElements (unsigned Opc)
 
bool getMUBUFHasVAddr (unsigned Opc)
 
bool getMUBUFHasSrsrc (unsigned Opc)
 
bool getMUBUFHasSoffset (unsigned Opc)
 
bool getMUBUFIsBufferInv (unsigned Opc)
 
bool getMUBUFTfe (unsigned Opc)
 
bool getSMEMIsBuffer (unsigned Opc)
 
bool getVOP1IsSingle (unsigned Opc)
 
bool getVOP2IsSingle (unsigned Opc)
 
bool getVOP3IsSingle (unsigned Opc)
 
bool isVOPC64DPP (unsigned Opc)
 
bool isVOPCAsmOnly (unsigned Opc)
 
bool getMAIIsDGEMM (unsigned Opc)
 Returns true if MAI operation is a double precision GEMM.
 
bool getMAIIsGFX940XDL (unsigned Opc)
 
uint8_t mfmaScaleF8F6F4FormatToNumRegs (unsigned EncodingVal)
 
constMFMA_F8F6F4_Info * getMFMA_F8F6F4_WithFormatArgs (unsigned CBSZ,unsigned BLGP,unsigned F8F8Opcode)
 
unsigned getVOPDEncodingFamily (constMCSubtargetInfo &ST)
 
CanBeVOPD getCanBeVOPD (unsigned Opc)
 
unsigned getVOPDOpcode (unsigned Opc)
 
bool isVOPD (unsigned Opc)
 
bool isMAC (unsigned Opc)
 
bool isPermlane16 (unsigned Opc)
 
bool isCvt_F32_Fp8_Bf8_e64 (unsigned Opc)
 
bool isGenericAtomic (unsigned Opc)
 
bool isTrue16Inst (unsigned Opc)
 
FPType getFPDstSelType (unsigned Opc)
 
unsigned mapWMMA2AddrTo3AddrOpcode (unsigned Opc)
 
unsigned mapWMMA3AddrTo2AddrOpcode (unsigned Opc)
 
int getMCOpcode (uint16_t Opcode,unsigned Gen)
 
int getVOPDFull (unsigned OpX,unsigned OpY,unsigned EncodingFamily)
 
std::pair<unsigned,unsigned > getVOPDComponents (unsigned VOPDOpcode)
 
VOPD::InstInfo getVOPDInstInfo (constMCInstrDesc &OpX,constMCInstrDesc &OpY)
 
VOPD::InstInfo getVOPDInstInfo (unsigned VOPDOpcode,constMCInstrInfo *InstrInfo)
 
void initDefaultAMDKernelCodeT (AMDGPUMCKernelCodeT &KernelCode,constMCSubtargetInfo *STI)
 
bool isGroupSegment (constGlobalValue *GV)
 
bool isGlobalSegment (constGlobalValue *GV)
 
bool isReadOnlySegment (constGlobalValue *GV)
 
bool shouldEmitConstantsToTextSection (constTriple &TT)
 
std::pair<unsigned,unsigned > getIntegerPairAttribute (constFunction &F,StringRefName, std::pair<unsigned,unsigned >Default,bool OnlyFirstRequired)
 
std::optional< std::pair<unsigned, std::optional<unsigned > > > getIntegerPairAttribute (constFunction &F,StringRefName,bool OnlyFirstRequired)
 
SmallVector<unsigned > getIntegerVecAttribute (constFunction &F,StringRefName,unsignedSize,unsignedDefaultVal)
 
unsigned getVmcntBitMask (constIsaVersion &Version)
 
unsigned getLoadcntBitMask (constIsaVersion &Version)
 
unsigned getSamplecntBitMask (constIsaVersion &Version)
 
unsigned getBvhcntBitMask (constIsaVersion &Version)
 
unsigned getExpcntBitMask (constIsaVersion &Version)
 
unsigned getLgkmcntBitMask (constIsaVersion &Version)
 
unsigned getDscntBitMask (constIsaVersion &Version)
 
unsigned getKmcntBitMask (constIsaVersion &Version)
 
unsigned getStorecntBitMask (constIsaVersion &Version)
 
unsigned getWaitcntBitMask (constIsaVersion &Version)
 
unsigned decodeVmcnt (constIsaVersion &Version,unsignedWaitcnt)
 
unsigned decodeExpcnt (constIsaVersion &Version,unsignedWaitcnt)
 
unsigned decodeLgkmcnt (constIsaVersion &Version,unsignedWaitcnt)
 
void decodeWaitcnt (constIsaVersion &Version,unsignedWaitcnt,unsigned &Vmcnt,unsigned &Expcnt,unsigned &Lgkmcnt)
 Decodes Vmcnt, Expcnt and Lgkmcnt from givenWaitcnt for given isaVersion, and writes decoded values intoVmcnt,Expcnt andLgkmcnt respectively.
 
Waitcnt decodeWaitcnt (constIsaVersion &Version,unsigned Encoded)
 
unsigned encodeVmcnt (constIsaVersion &Version,unsignedWaitcnt,unsigned Vmcnt)
 
unsigned encodeExpcnt (constIsaVersion &Version,unsignedWaitcnt,unsigned Expcnt)
 
unsigned encodeLgkmcnt (constIsaVersion &Version,unsignedWaitcnt,unsigned Lgkmcnt)
 
unsigned encodeWaitcnt (constIsaVersion &Version,unsigned Vmcnt,unsigned Expcnt,unsigned Lgkmcnt)
 EncodesVmcnt,Expcnt andLgkmcnt intoWaitcnt for given isaVersion.
 
unsigned encodeWaitcnt (constIsaVersion &Version,constWaitcnt &Decoded)
 
staticunsigned getCombinedCountBitMask (constIsaVersion &Version,bool IsStore)
 
Waitcnt decodeLoadcntDscnt (constIsaVersion &Version,unsigned LoadcntDscnt)
 
Waitcnt decodeStorecntDscnt (constIsaVersion &Version,unsigned StorecntDscnt)
 
staticunsigned encodeLoadcnt (constIsaVersion &Version,unsignedWaitcnt,unsigned Loadcnt)
 
staticunsigned encodeStorecnt (constIsaVersion &Version,unsignedWaitcnt,unsigned Storecnt)
 
staticunsigned encodeDscnt (constIsaVersion &Version,unsignedWaitcnt,unsigned Dscnt)
 
staticunsigned encodeLoadcntDscnt (constIsaVersion &Version,unsigned Loadcnt,unsigned Dscnt)
 
unsigned encodeLoadcntDscnt (constIsaVersion &Version,constWaitcnt &Decoded)
 
staticunsigned encodeStorecntDscnt (constIsaVersion &Version,unsigned Storecnt,unsigned Dscnt)
 
unsigned encodeStorecntDscnt (constIsaVersion &Version,constWaitcnt &Decoded)
 
staticunsigned getDefaultCustomOperandEncoding (constCustomOperandVal *Opr, intSize,constMCSubtargetInfo &STI)
 
staticbool isSymbolicCustomOperandEncoding (constCustomOperandVal *Opr, intSize,unsigned Code,bool &HasNonDefaultVal,constMCSubtargetInfo &STI)
 
staticbool decodeCustomOperand (constCustomOperandVal *Opr, intSize,unsigned Code, int &Idx,StringRef &Name,unsigned &Val,bool &IsDefault,constMCSubtargetInfo &STI)
 
static int encodeCustomOperandVal (constCustomOperandVal &Op, int64_t InputVal)
 
static int encodeCustomOperand (constCustomOperandVal *Opr, intSize,constStringRefName, int64_t InputVal,unsigned &UsedOprMask,constMCSubtargetInfo &STI)
 
unsigned getInitialPSInputAddr (constFunction &F)
 
bool getHasColorExport (constFunction &F)
 
bool getHasDepthExport (constFunction &F)
 
bool isShader (CallingConv::ID cc)
 
bool isGraphics (CallingConv::ID cc)
 
bool isCompute (CallingConv::ID cc)
 
bool isEntryFunctionCC (CallingConv::IDCC)
 
bool isModuleEntryFunctionCC (CallingConv::IDCC)
 
bool isChainCC (CallingConv::IDCC)
 
bool isKernelCC (constFunction *Func)
 
bool hasXNACK (constMCSubtargetInfo &STI)
 
bool hasSRAMECC (constMCSubtargetInfo &STI)
 
bool hasMIMG_R128 (constMCSubtargetInfo &STI)
 
bool hasA16 (constMCSubtargetInfo &STI)
 
bool hasG16 (constMCSubtargetInfo &STI)
 
bool hasPackedD16 (constMCSubtargetInfo &STI)
 
bool hasGDS (constMCSubtargetInfo &STI)
 
unsigned getNSAMaxSize (constMCSubtargetInfo &STI,bool HasSampler)
 
unsigned getMaxNumUserSGPRs (constMCSubtargetInfo &STI)
 
bool isSI (constMCSubtargetInfo &STI)
 
bool isCI (constMCSubtargetInfo &STI)
 
bool isVI (constMCSubtargetInfo &STI)
 
bool isGFX9 (constMCSubtargetInfo &STI)
 
bool isGFX9_GFX10 (constMCSubtargetInfo &STI)
 
bool isGFX9_GFX10_GFX11 (constMCSubtargetInfo &STI)
 
bool isGFX8_GFX9_GFX10 (constMCSubtargetInfo &STI)
 
bool isGFX8Plus (constMCSubtargetInfo &STI)
 
bool isGFX9Plus (constMCSubtargetInfo &STI)
 
bool isNotGFX9Plus (constMCSubtargetInfo &STI)
 
bool isGFX10 (constMCSubtargetInfo &STI)
 
bool isGFX10_GFX11 (constMCSubtargetInfo &STI)
 
bool isGFX10Plus (constMCSubtargetInfo &STI)
 
bool isGFX11 (constMCSubtargetInfo &STI)
 
bool isGFX11Plus (constMCSubtargetInfo &STI)
 
bool isGFX12 (constMCSubtargetInfo &STI)
 
bool isGFX12Plus (constMCSubtargetInfo &STI)
 
bool isNotGFX12Plus (constMCSubtargetInfo &STI)
 
bool isNotGFX11Plus (constMCSubtargetInfo &STI)
 
bool isNotGFX10Plus (constMCSubtargetInfo &STI)
 
bool isGFX10Before1030 (constMCSubtargetInfo &STI)
 
bool isGCN3Encoding (constMCSubtargetInfo &STI)
 
bool isGFX10_AEncoding (constMCSubtargetInfo &STI)
 
bool isGFX10_BEncoding (constMCSubtargetInfo &STI)
 
bool hasGFX10_3Insts (constMCSubtargetInfo &STI)
 
bool isGFX10_3_GFX11 (constMCSubtargetInfo &STI)
 
bool isGFX90A (constMCSubtargetInfo &STI)
 
bool isGFX940 (constMCSubtargetInfo &STI)
 
bool hasArchitectedFlatScratch (constMCSubtargetInfo &STI)
 
bool hasMAIInsts (constMCSubtargetInfo &STI)
 
bool hasVOPD (constMCSubtargetInfo &STI)
 
bool hasDPPSrc1SGPR (constMCSubtargetInfo &STI)
 
unsigned hasKernargPreload (constMCSubtargetInfo &STI)
 
int32_t getTotalNumVGPRs (bool has90AInsts, int32_t ArgNumAGPR, int32_t ArgNumVGPR)
 
bool isSGPR (MCRegisterReg,constMCRegisterInfo *TRI)
 Is Reg - scalar register.
 
bool isHi16Reg (MCRegisterReg,constMCRegisterInfo &MRI)
 
MCRegister getMCReg (MCRegisterReg,constMCSubtargetInfo &STI)
 IfReg is a pseudo reg, return the correct hardware register givenSTI otherwise returnReg.
 
MCRegister mc2PseudoReg (MCRegisterReg)
 Convert hardware registerReg to a pseudo register.
 
bool isInlineValue (unsignedReg)
 
bool isSISrcOperand (constMCInstrDesc &Desc,unsigned OpNo)
 Is this anAMDGPU specific source operand? These include registers, inline constants, literals and mandatory literals (KImm).
 
bool isKImmOperand (constMCInstrDesc &Desc,unsigned OpNo)
 Is this a KImm operand?
 
bool isSISrcFPOperand (constMCInstrDesc &Desc,unsigned OpNo)
 Is this floating-point operand?
 
bool isSISrcInlinableOperand (constMCInstrDesc &Desc,unsigned OpNo)
 Does this operand support only inlinable literals?
 
unsigned getRegBitWidth (unsigned RCID)
 Get the size in bits of a register from the register classRC.
 
unsigned getRegBitWidth (constMCRegisterClass &RC)
 Get the size in bits of a register from the register classRC.
 
unsigned getRegOperandSize (constMCRegisterInfo *MRI,constMCInstrDesc &Desc,unsigned OpNo)
 Get size of register operand.
 
bool isInlinableLiteral64 (int64_tLiteral,bool HasInv2Pi)
 Is this literal inlinable.
 
bool isInlinableLiteral32 (int32_tLiteral,bool HasInv2Pi)
 
bool isInlinableLiteralBF16 (int16_tLiteral,bool HasInv2Pi)
 
bool isInlinableLiteralI16 (int32_tLiteral,bool HasInv2Pi)
 
bool isInlinableLiteralFP16 (int16_tLiteral,bool HasInv2Pi)
 
std::optional<unsigned > getInlineEncodingV216 (bool IsFloat,uint32_tLiteral)
 
std::optional<unsigned > getInlineEncodingV2I16 (uint32_tLiteral)
 
std::optional<unsigned > getInlineEncodingV2BF16 (uint32_tLiteral)
 
std::optional<unsigned > getInlineEncodingV2F16 (uint32_tLiteral)
 
bool isInlinableLiteralV216 (uint32_tLiteral,uint8_t OpType)
 
bool isInlinableLiteralV2I16 (uint32_tLiteral)
 
bool isInlinableLiteralV2BF16 (uint32_tLiteral)
 
bool isInlinableLiteralV2F16 (uint32_tLiteral)
 
bool isValid32BitLiteral (uint64_t Val,bool IsFP64)
 
bool isArgPassedInSGPR (constArgument *A)
 
bool isArgPassedInSGPR (constCallBase *CB,unsigned ArgNo)
 
staticbool hasSMEMByteOffset (constMCSubtargetInfo &ST)
 
bool isLegalSMRDEncodedUnsignedOffset (constMCSubtargetInfo &ST, int64_t EncodedOffset)
 
bool isLegalSMRDEncodedSignedOffset (constMCSubtargetInfo &ST, int64_t EncodedOffset,bool IsBuffer)
 
staticbool isDwordAligned (uint64_t ByteOffset)
 
uint64_t convertSMRDOffsetUnits (constMCSubtargetInfo &ST,uint64_t ByteOffset)
 ConvertByteOffset to dwords if the subtarget uses dword SMRD immediate offsets.
 
std::optional< int64_t > getSMRDEncodedOffset (constMCSubtargetInfo &ST, int64_t ByteOffset,bool IsBuffer,bool HasSOffset)
 
std::optional< int64_t > getSMRDEncodedLiteralOffset32 (constMCSubtargetInfo &ST, int64_t ByteOffset)
 
unsigned getNumFlatOffsetBits (constMCSubtargetInfo &ST)
 For pre-GFX12 FLAT instructions the offset must be positive; MSB is ignored and forced to zero.
 
bool isIntrinsicSourceOfDivergence (unsigned IntrID)
 
bool isIntrinsicAlwaysUniform (unsigned IntrID)
 
constGcnBufferFormatInfo * getGcnBufferFormatInfo (uint8_t BitsPerComp,uint8_t NumComponents,uint8_t NumFormat,constMCSubtargetInfo &STI)
 
constGcnBufferFormatInfo * getGcnBufferFormatInfo (uint8_tFormat,constMCSubtargetInfo &STI)
 
bool hasAny64BitVGPROperands (constMCInstrDesc &OpDesc)
 
bool isDPALU_DPP (constMCInstrDesc &OpDesc)
 
unsigned getLdsDwGranularity (constMCSubtargetInfo &ST)
 
LLVM_READONLY int16_t getNamedOperandIdx (uint16_t Opcode,uint16_t NamedIdx)
 
LLVM_READONLYbool hasNamedOperand (uint64_t Opcode,uint64_t NamedIdx)
 
LLVM_READONLY int getSOPPWithRelaxation (uint16_t Opcode)
 
LLVM_READONLYconstMIMGBaseOpcodeInfo * getMIMGBaseOpcodeInfo (unsigned BaseOpcode)
 
LLVM_READONLYconstMIMGDimInfo * getMIMGDimInfo (unsigned DimEnum)
 
LLVM_READONLYconstMIMGDimInfo * getMIMGDimInfoByEncoding (uint8_t DimEnc)
 
LLVM_READONLYconstMIMGDimInfo * getMIMGDimInfoByAsmSuffix (StringRef AsmSuffix)
 
LLVM_READONLYconstMIMGLZMappingInfo * getMIMGLZMappingInfo (unsigned L)
 
LLVM_READONLYconstMIMGMIPMappingInfo * getMIMGMIPMappingInfo (unsigned MIP)
 
LLVM_READONLYconstMIMGBiasMappingInfo * getMIMGBiasMappingInfo (unsigned Bias)
 
LLVM_READONLYconstMIMGOffsetMappingInfo * getMIMGOffsetMappingInfo (unsignedOffset)
 
LLVM_READONLYconstMIMGG16MappingInfo * getMIMGG16MappingInfo (unsignedG)
 
LLVM_READONLYconstMIMGInfo * getMIMGInfo (unsigned Opc)
 
LLVM_READONLYbool isInvalidSingleUseConsumerInst (unsigned Opc)
 
LLVM_READONLYbool isInvalidSingleUseProducerInst (unsigned Opc)
 
bool isDPMACCInstruction (unsigned Opc)
 
int getIntegerAttribute (constFunction &F,StringRefName, intDefault)
 
LLVM_READNONEbool isKernel (CallingConv::IDCC)
 
LLVM_READNONEunsigned getOperandSize (constMCOperandInfo &OpInfo)
 
LLVM_READNONEunsigned getOperandSize (constMCInstrDesc &Desc,unsigned OpNo)
 
LLVM_READNONEbool isInlinableIntLiteral (int64_tLiteral)
 Is this literal inlinable, and not one of the values intended for floating point values.
 
bool isLegalSMRDImmOffset (constMCSubtargetInfo &ST, int64_t ByteOffset)
 
LLVM_READNONEbool isLegalDPALU_DPPControl (unsigned DC)
 
constexpr std::pair<unsigned,unsigned > getShiftMask (unsignedValue)
 Deduce the least significant bit aligned shift and mask values for a binary ComplementValue (as they're defined inSIDefines.h as C_*) as a returned pair<shift, mask>.
 
constMCExpr * maskShiftSet (constMCExpr *Val,uint32_t Mask,uint32_t Shift,MCContext &Ctx)
 Provided with theMCExpr *Val, uint32Mask andShift, will return the masked and left shifted, in said order of operations,MCExpr * created within theMCContextCtx.
 
constMCExpr * maskShiftGet (constMCExpr *Val,uint32_t Mask,uint32_t Shift,MCContext &Ctx)
 Provided with theMCExpr *Val, uint32Mask andShift, will return the right shifted and masked, in said order of operations,MCExpr * created within theMCContextCtx.
 

Variables

constuint64_t RSRC_DATA_FORMAT = 0xf00000000000LL
 
constuint64_t RSRC_ELEMENT_SIZE_SHIFT = (32 + 19)
 
constuint64_t RSRC_INDEX_STRIDE_SHIFT = (32 + 21)
 
constuint64_t RSRC_TID_ENABLE = UINT64_C(1) << (32 + 23)
 
static constexpruint32_t ExtendedFltRoundOffset = 4
 Offset of nonstandard values for llvm.get.rounding results from the largest supported mode.
 
static constexpruint32_t F32FltRoundOffset = 0
 Offset in mode register of f32 rounding mode.
 
static constexpruint32_t F64FltRoundOffset = 2
 Offset in mode register of f64/f16 rounding mode.
 
constuint64_t FltRoundConversionTable
 
constuint64_t FltRoundToHWConversionTable
 
const int OPR_ID_UNKNOWN = -1
 
const int OPR_ID_UNSUPPORTED = -2
 
const int OPR_ID_DUPLICATE = -3
 
const int OPR_VAL_INVALID = -4
 

Typedef Documentation

◆ EncodingBit

template<unsigned Bit,unsigned D = 0>
usingllvm::AMDGPU::EncodingBit = typedefEncodingField<Bit, Bit,D>

Definition at line382 of fileAMDGPUBaseInfo.h.

◆ FunctionVariableMap

usingllvm::AMDGPU::FunctionVariableMap = typedefDenseMap<Function *,DenseSet<GlobalVariable *> >

Definition at line33 of fileAMDGPUMemoryUtils.h.

◆ VariableFunctionMap

usingllvm::AMDGPU::VariableFunctionMap = typedefDenseMap<GlobalVariable *,DenseSet<Function *> >

Definition at line34 of fileAMDGPUMemoryUtils.h.

Enumeration Type Documentation

◆ anonymous enum

anonymous enum
Enumerator
AMDHSA_COV4 
AMDHSA_COV5 
AMDHSA_COV6 

Definition at line56 of fileAMDGPUBaseInfo.h.

◆ AMDGPUFltRounds

enumllvm::AMDGPU::AMDGPUFltRounds : int8_t

Return values used for llvm.get.rounding.

When both the F32 and F64/F16 modes are the same, returns the standard values. If they differ, returns an extended mode starting at 8.

Enumerator
TowardZero 
NearestTiesToEven 
TowardPositive 
TowardNegative 
NearestTiesToAwayUnsupported 
Dynamic 
NearestTiesToEvenF32_NearestTiesToEvenF64 
NearestTiesToEvenF32_TowardPositiveF64 
NearestTiesToEvenF32_TowardNegativeF64 
NearestTiesToEvenF32_TowardZeroF64 
TowardPositiveF32_NearestTiesToEvenF64 
TowardPositiveF32_TowardPositiveF64 
TowardPositiveF32_TowardNegativeF64 
TowardPositiveF32_TowardZeroF64 
TowardNegativeF32_NearestTiesToEvenF64 
TowardNegativeF32_TowardPositiveF64 
TowardNegativeF32_TowardNegativeF64 
TowardNegativeF32_TowardZeroF64 
TowardZeroF32_NearestTiesToEvenF64 
TowardZeroF32_TowardPositiveF64 
TowardZeroF32_TowardNegativeF64 
TowardZeroF32_TowardZeroF64 
Invalid 

Definition at line96 of fileSIModeRegisterDefaults.h.

◆ ArchFeatureKind

enumllvm::AMDGPU::ArchFeatureKind :uint32_t
Enumerator
FEATURE_NONE 
FEATURE_FMA 
FEATURE_LDEXP 
FEATURE_FP64 
FEATURE_FAST_FMA_F32 
FEATURE_FAST_DENORMAL_F32 
FEATURE_WAVE32 
FEATURE_XNACK 
FEATURE_SRAMECC 
FEATURE_WGP 

Definition at line138 of fileTargetParser.h.

◆ AsmComments

enumllvm::AMDGPU::AsmComments
Enumerator
SGPR_SPILL 

Definition at line1602 of fileSIInstrInfo.h.

◆ FastRulesTypes

enumllvm::AMDGPU::FastRulesTypes
Enumerator
NoFastRules 
Standard 
StandardB 
Vector 

Definition at line174 of fileAMDGPURegBankLegalizeRules.h.

◆ FeatureError

enumllvm::AMDGPU::FeatureError :uint32_t
Enumerator
NO_ERROR 
INVALID_FEATURE_COMBINATION 
UNSUPPORTED_TARGET_FEATURE 

Definition at line163 of fileTargetParser.h.

◆ Fixups

enumllvm::AMDGPU::Fixups
Enumerator
fixup_si_sopp_br 

16-bit PC relative fixup for SOPP branch instructions.

LastTargetFixupKind 
NumTargetFixupKinds 

Definition at line16 of fileAMDGPUFixupKinds.h.

◆ FPType

enum classllvm::AMDGPU::FPType
strong
Enumerator
None 
FP4 
FP8 

Definition at line58 of fileAMDGPUBaseInfo.h.

◆ GPUKind

enumllvm::AMDGPU::GPUKind :uint32_t

GPU kinds supported by theAMDGPU target.

Enumerator
GK_NONE 
GK_R600 
GK_R630 
GK_RS880 
GK_RV670 
GK_RV710 
GK_RV730 
GK_RV770 
GK_CEDAR 
GK_CYPRESS 
GK_JUNIPER 
GK_REDWOOD 
GK_SUMO 
GK_BARTS 
GK_CAICOS 
GK_CAYMAN 
GK_TURKS 
GK_R600_FIRST 
GK_R600_LAST 
GK_GFX600 
GK_GFX601 
GK_GFX602 
GK_GFX700 
GK_GFX701 
GK_GFX702 
GK_GFX703 
GK_GFX704 
GK_GFX705 
GK_GFX801 
GK_GFX802 
GK_GFX803 
GK_GFX805 
GK_GFX810 
GK_GFX900 
GK_GFX902 
GK_GFX904 
GK_GFX906 
GK_GFX908 
GK_GFX909 
GK_GFX90A 
GK_GFX90C 
GK_GFX940 
GK_GFX941 
GK_GFX942 
GK_GFX950 
GK_GFX1010 
GK_GFX1011 
GK_GFX1012 
GK_GFX1013 
GK_GFX1030 
GK_GFX1031 
GK_GFX1032 
GK_GFX1033 
GK_GFX1034 
GK_GFX1035 
GK_GFX1036 
GK_GFX1100 
GK_GFX1101 
GK_GFX1102 
GK_GFX1103 
GK_GFX1150 
GK_GFX1151 
GK_GFX1152 
GK_GFX1153 
GK_GFX1200 
GK_GFX1201 
GK_AMDGCN_FIRST 
GK_AMDGCN_LAST 
GK_GFX9_GENERIC 
GK_GFX10_1_GENERIC 
GK_GFX10_3_GENERIC 
GK_GFX11_GENERIC 
GK_GFX12_GENERIC 
GK_GFX9_4_GENERIC 
GK_AMDGCN_GENERIC_FIRST 
GK_AMDGCN_GENERIC_LAST 

Definition at line35 of fileTargetParser.h.

◆ LoweringMethodID

enumllvm::AMDGPU::LoweringMethodID
Enumerator
DoNotLower 
UniExtToSel 
VgprToVccCopy 
SplitTo32 
Ext32To64 
UniCstExt 
SplitLoad 
WidenLoad 

Definition at line163 of fileAMDGPURegBankLegalizeRules.h.

◆ OperandSemantics

enumllvm::AMDGPU::OperandSemantics :unsigned
Enumerator
INT 
FP16 
BF16 
FP32 
FP64 

Definition at line274 of fileSIDefines.h.

◆ OperandType

enumllvm::AMDGPU::OperandType :unsigned
Enumerator
OPERAND_REG_IMM_INT32 

Operands with register or 32-bit immediate.

OPERAND_REG_IMM_INT64 
OPERAND_REG_IMM_INT16 
OPERAND_REG_IMM_FP32 
OPERAND_REG_IMM_FP64 
OPERAND_REG_IMM_BF16 
OPERAND_REG_IMM_FP16 
OPERAND_REG_IMM_BF16_DEFERRED 
OPERAND_REG_IMM_FP16_DEFERRED 
OPERAND_REG_IMM_FP32_DEFERRED 
OPERAND_REG_IMM_V2BF16 
OPERAND_REG_IMM_V2FP16 
OPERAND_REG_IMM_V2INT16 
OPERAND_REG_IMM_V2INT32 
OPERAND_REG_IMM_V2FP32 
OPERAND_REG_INLINE_C_INT16 

Operands with register or inline constant.

OPERAND_REG_INLINE_C_INT32 
OPERAND_REG_INLINE_C_INT64 
OPERAND_REG_INLINE_C_BF16 
OPERAND_REG_INLINE_C_FP16 
OPERAND_REG_INLINE_C_FP32 
OPERAND_REG_INLINE_C_FP64 
OPERAND_REG_INLINE_C_V2INT16 
OPERAND_REG_INLINE_C_V2BF16 
OPERAND_REG_INLINE_C_V2FP16 
OPERAND_REG_INLINE_C_V2INT32 
OPERAND_REG_INLINE_C_V2FP32 
OPERAND_INLINE_SPLIT_BARRIER_INT32 
OPERAND_KIMM32 

Operand with 32-bit immediate that uses the constant bus.

OPERAND_KIMM16 
OPERAND_REG_INLINE_AC_INT16 

Operands with an AccVGPR register or inline constant.

OPERAND_REG_INLINE_AC_INT32 
OPERAND_REG_INLINE_AC_BF16 
OPERAND_REG_INLINE_AC_FP16 
OPERAND_REG_INLINE_AC_FP32 
OPERAND_REG_INLINE_AC_FP64 
OPERAND_REG_INLINE_AC_V2INT16 
OPERAND_REG_INLINE_AC_V2BF16 
OPERAND_REG_INLINE_AC_V2FP16 
OPERAND_REG_INLINE_AC_V2INT32 
OPERAND_REG_INLINE_AC_V2FP32 
OPERAND_INPUT_MODS 
OPERAND_SDWA_VOPC_DST 
OPERAND_REG_IMM_FIRST 
OPERAND_REG_IMM_LAST 
OPERAND_REG_INLINE_C_FIRST 
OPERAND_REG_INLINE_C_LAST 
OPERAND_REG_INLINE_AC_FIRST 
OPERAND_REG_INLINE_AC_LAST 
OPERAND_SRC_FIRST 
OPERAND_SRC_LAST 
OPERAND_KIMM_FIRST 
OPERAND_KIMM_LAST 

Definition at line198 of fileSIDefines.h.

◆ RegBankLLTMappingApplyID

enumllvm::AMDGPU::RegBankLLTMappingApplyID
Enumerator
InvalidMapping 
None 
IntrId 
Imm 
Vcc 
Sgpr16 
Sgpr32 
Sgpr64 
SgprP1 
SgprP3 
SgprP4 
SgprP5 
SgprV4S32 
SgprB32 
SgprB64 
SgprB96 
SgprB128 
SgprB256 
SgprB512 
Vgpr32 
Vgpr64 
VgprP1 
VgprP3 
VgprP4 
VgprP5 
VgprB32 
VgprB64 
VgprB96 
VgprB128 
VgprB256 
VgprB512 
VgprV4S32 
UniInVcc 
UniInVgprS32 
UniInVgprV4S32 
UniInVgprB32 
UniInVgprB64 
UniInVgprB96 
UniInVgprB128 
UniInVgprB256 
UniInVgprB512 
Sgpr32Trunc 
Sgpr32AExt 
Sgpr32AExtBoolInReg 
Sgpr32SExt 

Definition at line101 of fileAMDGPURegBankLegalizeRules.h.

◆ SchedulingPhase

enum classllvm::AMDGPU::SchedulingPhase
strong
Enumerator
Initial 
PreRAReentry 
PostRA 

Definition at line20 of fileAMDGPUIGroupLP.h.

◆ TargetIndex

enumllvm::AMDGPU::TargetIndex
Enumerator
TI_CONSTDATA_START 
TI_SCRATCH_RSRC_DWORD0 
TI_SCRATCH_RSRC_DWORD1 
TI_SCRATCH_RSRC_DWORD2 
TI_SCRATCH_RSRC_DWORD3 

Definition at line467 of fileAMDGPU.h.

◆ UniformityLLTOpPredicateID

enumllvm::AMDGPU::UniformityLLTOpPredicateID
Enumerator
_ 
S1 
S16 
S32 
S64 
UniS1 
UniS16 
UniS32 
UniS64 
DivS1 
DivS32 
DivS64 
P1 
P3 
P4 
P5 
UniP1 
UniP3 
UniP4 
UniP5 
DivP1 
DivP3 
DivP4 
DivP5 
V2S16 
V2S32 
V3S32 
V4S32 
B32 
B64 
B96 
B128 
B256 
B512 
UniB32 
UniB64 
UniB96 
UniB128 
UniB256 
UniB512 
DivB32 
DivB64 
DivB96 
DivB128 
DivB256 
DivB512 

Definition at line35 of fileAMDGPURegBankLegalizeRules.h.

Function Documentation

◆ addrspacesMayAlias()

staticbool llvm::AMDGPU::addrspacesMayAlias(unsigned AS1,
unsigned AS2 
)
inlinestatic

Definition at line475 of fileAMDGPU.h.

Referencesllvm::AMDGPUAS::MAX_AMDGPU_ADDRESS.

Referenced byllvm::GCNTTIImpl::addrspacesMayAlias(), andllvm::AMDGPUAAResult::alias().

◆ buildReadAnyLane()

void llvm::AMDGPU::buildReadAnyLane(MachineIRBuilder & B,
Register SgprDst,
Register VgprSrc,
constRegisterBankInfo & RBI 
)

Definition at line155 of fileAMDGPUGlobalISelUtils.cpp.

ReferencesB,getReadAnyLaneSplitTy(),llvm::LLT::getSizeInBits(), andunmergeReadAnyLane().

Referenced byunmergeReadAnyLane().

◆ convertSMRDOffsetUnits()

uint64_t llvm::AMDGPU::convertSMRDOffsetUnits(constMCSubtargetInfo & ST,
uint64_t ByteOffset 
)

ConvertByteOffset to dwords if the subtarget uses dword SMRD immediate offsets.

Definition at line2898 of fileAMDGPUBaseInfo.cpp.

Referencesassert(),hasSMEMByteOffset(), andisDwordAligned().

Referenced bygetSMRDEncodedLiteralOffset32(), andgetSMRDEncodedOffset().

◆ createSlowPathCmp()

staticValue * llvm::AMDGPU::createSlowPathCmp(Module & M,
IRBuilder<> & IRB,
Type * IntptrTy,
Value * AddrLong,
Value * ShadowValue,
uint32_t TypeStoreSize,
int AsanScale 
)
static

Definition at line79 of fileAMDGPUAsanInstrumentation.cpp.

Referencesllvm::IRBuilderBase::CreateAdd(),llvm::IRBuilderBase::CreateAnd(),llvm::IRBuilderBase::CreateICmpSGE(),llvm::IRBuilderBase::CreateIntCast(), andllvm::Value::getType().

Referenced byinstrumentAddressImpl().

◆ decodeCustomOperand()

staticbool llvm::AMDGPU::decodeCustomOperand(constCustomOperandVal * Opr,
int Size,
unsigned Code,
int & Idx,
StringRef & Name,
unsigned & Val,
bool & IsDefault,
constMCSubtargetInfo & STI 
)
static

Definition at line1633 of fileAMDGPUBaseInfo.cpp.

ReferencesIdx,Name, andSize.

Referenced byllvm::AMDGPU::DepCtr::decodeDepCtr().

◆ decodeExpcnt()

unsigned llvm::AMDGPU::decodeExpcnt(constIsaVersion & Version,
unsigned Waitcnt 
)
Returns
Decoded Expcnt from givenWaitcnt for given isaVersion.

Definition at line1462 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::Version.

Referenced bydecodeWaitcnt().

◆ decodeFltRoundToHWConversionTable()

uint32_t llvm::AMDGPU::decodeFltRoundToHWConversionTable(uint32_t FltRounds)

Read the hardware rounding mode equivalent of a AMDGPUFltRounds value.

Definition at line247 of fileSIModeRegisterDefaults.cpp.

ReferencesFltRoundToHWConversionTable.

Referenced byllvm::SITargetLowering::lowerSET_ROUNDING().

◆ decodeLgkmcnt()

unsigned llvm::AMDGPU::decodeLgkmcnt(constIsaVersion & Version,
unsigned Waitcnt 
)
Returns
Decoded Lgkmcnt from givenWaitcnt for given isaVersion.

Definition at line1467 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::Version.

Referenced bydecodeWaitcnt().

◆ decodeLoadcntDscnt()

Waitcnt llvm::AMDGPU::decodeLoadcntDscnt(constIsaVersion & Version,
unsigned LoadcntDscnt 
)
Returns
DecodedWaitcnt structure from givenLoadcntDscnt for given isaVersion.

Definition at line1535 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::AMDGPU::Waitcnt::DsCnt,llvm::AMDGPU::Waitcnt::LoadCnt, andllvm::Version.

◆ decodeStorecntDscnt()

Waitcnt llvm::AMDGPU::decodeStorecntDscnt(constIsaVersion & Version,
unsigned StorecntDscnt 
)
Returns
DecodedWaitcnt structure from givenStorecntDscnt for given isaVersion.

Definition at line1545 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::AMDGPU::Waitcnt::DsCnt,llvm::AMDGPU::Waitcnt::StoreCnt, andllvm::Version.

◆ decodeVmcnt()

unsigned llvm::AMDGPU::decodeVmcnt(constIsaVersion & Version,
unsigned Waitcnt 
)
Returns
Decoded Vmcnt from givenWaitcnt for given isaVersion.

Definition at line1454 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::Version.

Referenced bydecodeWaitcnt().

◆ decodeWaitcnt()[1/2]

Waitcnt llvm::AMDGPU::decodeWaitcnt(constIsaVersion & Version,
unsigned Encoded 
)

Definition at line1479 of fileAMDGPUBaseInfo.cpp.

ReferencesdecodeExpcnt(),decodeLgkmcnt(),decodeVmcnt(),llvm::AMDGPU::Waitcnt::DsCnt,llvm::AMDGPU::Waitcnt::ExpCnt,llvm::AMDGPU::Waitcnt::LoadCnt, andllvm::Version.

◆ decodeWaitcnt()[2/2]

void llvm::AMDGPU::decodeWaitcnt(constIsaVersion & Version,
unsigned Waitcnt,
unsigned & Vmcnt,
unsigned & Expcnt,
unsigned & Lgkmcnt 
)

Decodes Vmcnt, Expcnt and Lgkmcnt from givenWaitcnt for given isaVersion, and writes decoded values intoVmcnt,Expcnt andLgkmcnt respectively.

Should not be used on gfx12+, the instruction which needs it is deprecated

Vmcnt,Expcnt andLgkmcnt are decoded as follows:Vmcnt =Waitcnt[3:0] (pre-gfx9)Vmcnt =Waitcnt[15:14,3:0] (gfx9,10)Vmcnt =Waitcnt[15:10] (gfx11)Expcnt =Waitcnt[6:4] (pre-gfx11)Expcnt =Waitcnt[2:0] (gfx11)Lgkmcnt =Waitcnt[11:8] (pre-gfx10)Lgkmcnt =Waitcnt[13:8] (gfx10)Lgkmcnt =Waitcnt[9:4] (gfx11)

Definition at line1472 of fileAMDGPUBaseInfo.cpp.

ReferencesdecodeExpcnt(),decodeLgkmcnt(),decodeVmcnt(), andllvm::Version.

Referenced byllvm::AMDGPUInstPrinter::printSWaitCnt().

◆ eliminateConstantExprUsesOfLDSFromAllInstructions()

bool llvm::AMDGPU::eliminateConstantExprUsesOfLDSFromAllInstructions(Module & M)

Definition at line86 of fileAMDGPUMemoryUtils.cpp.

Referencesllvm::convertUsersOfConstantsToInstructions(),isLDSVariableToLower(), andllvm::SmallVectorTemplateBase< T, bool >::push_back().

◆ encodeCustomOperand()

static int llvm::AMDGPU::encodeCustomOperand(constCustomOperandVal * Opr,
int Size,
constStringRef Name,
int64_t InputVal,
unsigned & UsedOprMask,
constMCSubtargetInfo & STI 
)
static

Definition at line1657 of fileAMDGPUBaseInfo.cpp.

ReferencesencodeCustomOperandVal(),Idx,Name,OPR_ID_DUPLICATE,OPR_ID_UNKNOWN,OPR_ID_UNSUPPORTED, andSize.

Referenced byllvm::AMDGPU::DepCtr::encodeDepCtr().

◆ encodeCustomOperandVal()

static int llvm::AMDGPU::encodeCustomOperandVal(constCustomOperandVal & Op,
int64_t InputVal 
)
static

Definition at line1650 of fileAMDGPUBaseInfo.cpp.

ReferencesOPR_VAL_INVALID.

Referenced byencodeCustomOperand().

◆ encodeDscnt()

staticunsigned llvm::AMDGPU::encodeDscnt(constIsaVersion & Version,
unsigned Waitcnt,
unsigned Dscnt 
)
static

Definition at line1567 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::Version.

Referenced byencodeLoadcntDscnt(), andencodeStorecntDscnt().

◆ encodeExpcnt()

unsigned llvm::AMDGPU::encodeExpcnt(constIsaVersion & Version,
unsigned Waitcnt,
unsigned Expcnt 
)
Returns
Waitcnt with encodedExpcnt for given isaVersion.

Definition at line1496 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::Version.

Referenced byencodeWaitcnt().

◆ encodeLgkmcnt()

unsigned llvm::AMDGPU::encodeLgkmcnt(constIsaVersion & Version,
unsigned Waitcnt,
unsigned Lgkmcnt 
)
Returns
Waitcnt with encodedLgkmcnt for given isaVersion.

Definition at line1502 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::Version.

Referenced byencodeWaitcnt().

◆ encodeLoadcnt()

staticunsigned llvm::AMDGPU::encodeLoadcnt(constIsaVersion & Version,
unsigned Waitcnt,
unsigned Loadcnt 
)
static

Definition at line1555 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::Version.

Referenced byencodeLoadcntDscnt().

◆ encodeLoadcntDscnt()[1/2]

unsigned llvm::AMDGPU::encodeLoadcntDscnt(constIsaVersion & Version,
constWaitcnt & Decoded 
)
Returns
Loadcnt andDscnt components ofDecoded encoded as an immediate that can be used with S_WAIT_LOADCNT_DSCNT for given isaVersion.

Definition at line1581 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::AMDGPU::Waitcnt::DsCnt,encodeLoadcntDscnt(),llvm::AMDGPU::Waitcnt::LoadCnt, andllvm::Version.

◆ encodeLoadcntDscnt()[2/2]

staticunsigned llvm::AMDGPU::encodeLoadcntDscnt(constIsaVersion & Version,
unsigned Loadcnt,
unsigned Dscnt 
)
static

Definition at line1573 of fileAMDGPUBaseInfo.cpp.

ReferencesencodeDscnt(),encodeLoadcnt(),getCombinedCountBitMask(), andllvm::Version.

Referenced byencodeLoadcntDscnt().

◆ encodeStorecnt()

staticunsigned llvm::AMDGPU::encodeStorecnt(constIsaVersion & Version,
unsigned Waitcnt,
unsigned Storecnt 
)
static

Definition at line1561 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::Version.

Referenced byencodeStorecntDscnt().

◆ encodeStorecntDscnt()[1/2]

unsigned llvm::AMDGPU::encodeStorecntDscnt(constIsaVersion & Version,
constWaitcnt & Decoded 
)
Returns
Storecnt andDscnt components ofDecoded encoded as an immediate that can be used with S_WAIT_STORECNT_DSCNT for given isaVersion.

Definition at line1593 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::AMDGPU::Waitcnt::DsCnt,encodeStorecntDscnt(),llvm::AMDGPU::Waitcnt::StoreCnt, andllvm::Version.

◆ encodeStorecntDscnt()[2/2]

staticunsigned llvm::AMDGPU::encodeStorecntDscnt(constIsaVersion & Version,
unsigned Storecnt,
unsigned Dscnt 
)
static

Definition at line1585 of fileAMDGPUBaseInfo.cpp.

ReferencesencodeDscnt(),encodeStorecnt(),getCombinedCountBitMask(), andllvm::Version.

Referenced byencodeStorecntDscnt().

◆ encodeVmcnt()

unsigned llvm::AMDGPU::encodeVmcnt(constIsaVersion & Version,
unsigned Waitcnt,
unsigned Vmcnt 
)
Returns
Waitcnt with encodedVmcnt for given isaVersion.

Definition at line1487 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::Version.

Referenced byencodeWaitcnt().

◆ encodeWaitcnt()[1/2]

unsigned llvm::AMDGPU::encodeWaitcnt(constIsaVersion & Version,
constWaitcnt & Decoded 
)

Definition at line1517 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::AMDGPU::Waitcnt::DsCnt,encodeWaitcnt(),llvm::AMDGPU::Waitcnt::ExpCnt,llvm::AMDGPU::Waitcnt::LoadCnt, andllvm::Version.

◆ encodeWaitcnt()[2/2]

unsigned llvm::AMDGPU::encodeWaitcnt(constIsaVersion & Version,
unsigned Vmcnt,
unsigned Expcnt,
unsigned Lgkmcnt 
)

EncodesVmcnt,Expcnt andLgkmcnt intoWaitcnt for given isaVersion.

Should not be used on gfx12+, the instruction which needs it is deprecated

Vmcnt,Expcnt andLgkmcnt are encoded as follows:Waitcnt[2:0] =Expcnt (gfx11+)Waitcnt[3:0] =Vmcnt (pre-gfx9)Waitcnt[3:0] =Vmcnt[3:0] (gfx9,10)Waitcnt[6:4] =Expcnt (pre-gfx11)Waitcnt[9:4] =Lgkmcnt (gfx11)Waitcnt[11:8] =Lgkmcnt (pre-gfx10)Waitcnt[13:8] =Lgkmcnt (gfx10)Waitcnt[15:10] =Vmcnt (gfx11)Waitcnt[15:14] =Vmcnt[5:4] (gfx9,10)

Returns
Waitcnt with encodedVmcnt,Expcnt andLgkmcnt for given isaVersion.

Definition at line1508 of fileAMDGPUBaseInfo.cpp.

ReferencesencodeExpcnt(),encodeLgkmcnt(),encodeVmcnt(),getWaitcntBitMask(), andllvm::Version.

Referenced byencodeWaitcnt().

◆ fillAMDGPUFeatureMap()

void llvm::AMDGPU::fillAMDGPUFeatureMap(StringRef GPU,
constTriple & T,
StringMap<bool > & Features 
)

Fills Features map with default values for given target GPU.

Definition at line322 of fileTargetParser.cpp.

Referencesllvm::StringRef::empty(),GK_BARTS,GK_CAICOS,GK_CAYMAN,GK_CEDAR,GK_CYPRESS,GK_GFX1010,GK_GFX1011,GK_GFX1012,GK_GFX1013,GK_GFX1030,GK_GFX1031,GK_GFX1032,GK_GFX1033,GK_GFX1034,GK_GFX1035,GK_GFX1036,GK_GFX10_1_GENERIC,GK_GFX10_3_GENERIC,GK_GFX1100,GK_GFX1101,GK_GFX1102,GK_GFX1103,GK_GFX1150,GK_GFX1151,GK_GFX1152,GK_GFX1153,GK_GFX11_GENERIC,GK_GFX1200,GK_GFX1201,GK_GFX12_GENERIC,GK_GFX600,GK_GFX601,GK_GFX602,GK_GFX700,GK_GFX701,GK_GFX702,GK_GFX703,GK_GFX704,GK_GFX705,GK_GFX801,GK_GFX802,GK_GFX803,GK_GFX805,GK_GFX810,GK_GFX900,GK_GFX902,GK_GFX904,GK_GFX906,GK_GFX908,GK_GFX909,GK_GFX90A,GK_GFX90C,GK_GFX940,GK_GFX941,GK_GFX942,GK_GFX950,GK_GFX9_4_GENERIC,GK_GFX9_GENERIC,GK_JUNIPER,GK_NONE,GK_R600,GK_R630,GK_REDWOOD,GK_RS880,GK_RV670,GK_RV710,GK_RV730,GK_RV770,GK_SUMO,GK_TURKS,llvm_unreachable,parseArchAMDGCN(), andparseArchR600().

◆ fillValidArchListAMDGCN()

void llvm::AMDGPU::fillValidArchListAMDGCN(SmallVectorImpl<StringRef > & Values)

Definition at line218 of fileTargetParser.cpp.

Referencesllvm::CallingConv::C, andllvm::SmallVectorTemplateBase< T, bool >::push_back().

◆ fillValidArchListR600()

void llvm::AMDGPU::fillValidArchListR600(SmallVectorImpl<StringRef > & Values)

Definition at line224 of fileTargetParser.cpp.

Referencesllvm::CallingConv::C, andllvm::SmallVectorTemplateBase< T, bool >::push_back().

◆ foldAMDGPUMCExpr()

constMCExpr * llvm::AMDGPU::foldAMDGPUMCExpr(constMCExpr * Expr,
MCContext & Ctx 
)

Definition at line672 of fileAMDGPUMCExpr.cpp.

ReferencesknownBitsMapHelper(), andtryFoldHelper().

Referenced byllvm::AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(), andllvm::AMDGPUTargetAsmStreamer::EmitAMDKernelCodeT().

◆ genAMDGPUReportBlock()

staticInstruction * llvm::AMDGPU::genAMDGPUReportBlock(Module & M,
IRBuilder<> & IRB,
Value * Cond,
bool Recover 
)
static

Definition at line57 of fileAMDGPUAsanInstrumentation.cpp.

ReferencesCond,llvm::IRBuilderBase::CreateIntrinsic(),llvm::IRBuilderBase::CreateIsNotNull(),llvm::MDBuilder::createUnlikelyBranchWeights(),llvm::IRBuilderBase::GetInsertPoint(),llvm::IRBuilderBase::getInt64Ty(),llvm::IRBuilderBase::SetInsertPoint(), andllvm::SplitBlockAndInsertIfThen().

Referenced byinstrumentAddressImpl().

◆ generateCrashCode()

staticInstruction * llvm::AMDGPU::generateCrashCode(Module & M,
IRBuilder<> & IRB,
Type * IntptrTy,
Instruction * InsertBefore,
Value * Addr,
bool IsWrite,
size_t AccessSizeIndex,
Value * SizeArgument,
bool Recover 
)
static

Definition at line97 of fileAMDGPUAsanInstrumentation.cpp.

ReferencesAddr,llvm::IRBuilderBase::CreateCall(),llvm::FunctionType::get(),llvm::IRBuilderBase::getVoidTy(),kAsanReportErrorTemplate,llvm::IRBuilderBase::SetInsertPoint(), andllvm::raw_svector_ostream::str().

Referenced byinstrumentAddressImpl().

◆ getAddr64Inst()

LLVM_READONLY int llvm::AMDGPU::getAddr64Inst(uint16_t Opcode)

Referenced byllvm::SIInstrInfo::legalizeOperands().

◆ getAddrSizeMIMGOp()

LLVM_READONLYunsigned llvm::AMDGPU::getAddrSizeMIMGOp(constMIMGBaseOpcodeInfo * BaseOpcode,
constMIMGDimInfo * Dim,
bool IsA16,
bool IsG16Supported 
)

Definition at line293 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::AMDGPU::MIMGBaseOpcodeInfo::Coordinates,llvm::divideCeil(),llvm::AMDGPU::MIMGBaseOpcodeInfo::G16,llvm::AMDGPU::MIMGBaseOpcodeInfo::Gradients,llvm::AMDGPU::MIMGBaseOpcodeInfo::LodOrClampOrMip,llvm::AMDGPU::MIMGDimInfo::NumCoords,llvm::AMDGPU::MIMGBaseOpcodeInfo::NumExtraArgs, andllvm::AMDGPU::MIMGDimInfo::NumGradients.

Referenced byllvm::AMDGPUDisassembler::convertMIMGInst(), andllvm::SIInstrInfo::verifyInstruction().

◆ getAlign()

Align llvm::AMDGPU::getAlign(constDataLayout & DL,
constGlobalVariable * GV 
)

Definition at line29 of fileAMDGPUMemoryUtils.cpp.

ReferencesDL,llvm::Value::getPointerAlignment(), andllvm::GlobalValue::getValueType().

◆ getAMDHSACodeObjectVersion()[1/2]

unsigned llvm::AMDGPU::getAMDHSACodeObjectVersion(constModule & M)
Returns
Code object version from the IR module flag.

Definition at line172 of fileAMDGPUBaseInfo.cpp.

ReferencesgetDefaultAMDHSACodeObjectVersion().

Referenced byllvm::AMDGPUAsmPrinter::doInitialization(),llvm::AMDGPU::HSAMD::MetadataStreamerMsgPackV4::emitKernel(),llvm::AMDGPUSubtarget::getImplicitArgNumBytes(),llvm::AMDGPULegalizerInfo::getSegmentAperture(),llvm::AMDGPULegalizerInfo::legalizeTrapHsaQueuePtr(),llvm::AMDGPULowerKernelAttributesPass::run(),llvm::AMDGPUResourceUsageAnalysis::runOnMachineFunction(), andllvm::AMDGPUDisassembler::setABIVersion().

◆ getAMDHSACodeObjectVersion()[2/2]

unsigned llvm::AMDGPU::getAMDHSACodeObjectVersion(unsigned ABIVersion)
Returns
Code object version fromELF's e_ident[EI_ABIVERSION].

Definition at line185 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::ELF::ELFABIVERSION_AMDGPU_HSA_V4,llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V5,llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V6, andgetDefaultAMDHSACodeObjectVersion().

◆ getArchAttrAMDGCN()

unsigned llvm::AMDGPU::getArchAttrAMDGCN(GPUKind AK)

Definition at line206 of fileTargetParser.cpp.

ReferencesFEATURE_NONE.

◆ getArchAttrR600()

unsigned llvm::AMDGPU::getArchAttrR600(GPUKind AK)

Definition at line212 of fileTargetParser.cpp.

ReferencesFEATURE_NONE.

◆ getArchFamilyNameAMDGCN()

StringRef llvm::AMDGPU::getArchFamilyNameAMDGCN(GPUKind AK)

Definition at line157 of fileTargetParser.cpp.

Referencesllvm::StringRef::drop_back(),llvm::StringRef::empty(),getArchNameAMDGCN(),GK_GFX10_1_GENERIC,GK_GFX10_3_GENERIC,GK_GFX11_GENERIC,GK_GFX12_GENERIC,GK_GFX9_4_GENERIC, andGK_GFX9_GENERIC.

◆ getArchNameAMDGCN()

StringRef llvm::AMDGPU::getArchNameAMDGCN(GPUKind AK)

Definition at line176 of fileTargetParser.cpp.

Referenced bygetArchFamilyNameAMDGCN(),llvm::AMDGPUTargetStreamer::getArchNameFromElfMach(), andgetCanonicalArchName().

◆ getArchNameR600()

StringRef llvm::AMDGPU::getArchNameR600(GPUKind AK)

Definition at line182 of fileTargetParser.cpp.

Referenced byllvm::AMDGPUTargetStreamer::getArchNameFromElfMach(), andgetCanonicalArchName().

◆ getBaseWithConstantOffset()

std::pair<Register,unsigned > llvm::AMDGPU::getBaseWithConstantOffset(MachineRegisterInfo & MRI,
Register Reg,
GISelKnownBits * KnownBits =nullptr,
bool CheckNUW =false 
)

Returns base register and constant offset.

Definition at line26 of fileAMDGPUGlobalISelUtils.cpp.

Referencesassert(),llvm::sampleprof::Base,llvm::getDefIgnoringCopies(),llvm::MIPatternMatch::m_Copy(),llvm::MIPatternMatch::m_GOr(),llvm::MIPatternMatch::m_GPtrAdd(),llvm::MIPatternMatch::m_ICst(),llvm::MIPatternMatch::m_MInstr(),llvm::MIPatternMatch::m_Reg(),llvm::MIPatternMatch::mi_match(),MRI,llvm::MachineInstr::NoUWrap, andllvm::Offset.

Referenced byllvm::AMDGPURegisterBankInfo::applyMappingImpl(),computeIndirectRegIndex(),llvm::AMDGPURegisterBankInfo::setBufferOffsets(), andllvm::AMDGPULegalizerInfo::splitBufferOffsets().

◆ getBasicFromSDWAOp()

LLVM_READONLY int llvm::AMDGPU::getBasicFromSDWAOp(uint16_t Opcode)

Referenced byllvm::SIInstrInfo::verifyInstruction().

◆ getBvhcntBitMask()

unsigned llvm::AMDGPU::getBvhcntBitMask(constIsaVersion & Version)
Returns
Bvhcnt bit mask for given isaVersion. Returns 0 for versions that do not support BVHcnt

Definition at line1418 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::Version.

◆ getCanBeVOPD()

LLVM_READONLYCanBeVOPD llvm::AMDGPU::getCanBeVOPD(unsigned Opc)

Definition at line570 of fileAMDGPUBaseInfo.cpp.

ReferencesInfo.

Referenced byshouldScheduleVOPDAdjacent().

◆ getCanonicalArchName()

StringRef llvm::AMDGPU::getCanonicalArchName(constTriple & T,
StringRef Arch 
)

Definition at line313 of fileTargetParser.cpp.

Referencesassert(),getArchNameAMDGCN(),getArchNameR600(),GK_NONE,parseArchAMDGCN(), andparseArchR600().

◆ getCombinedCountBitMask()

staticunsigned llvm::AMDGPU::getCombinedCountBitMask(constIsaVersion & Version,
bool IsStore 
)
static

Definition at line1521 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::Version.

Referenced byencodeLoadcntDscnt(), andencodeStorecntDscnt().

◆ getCommuteOrig()

LLVM_READONLY int llvm::AMDGPU::getCommuteOrig(uint16_t Opcode)

Referenced byllvm::SIInstrInfo::commuteOpcode().

◆ getCommuteRev()

LLVM_READONLY int llvm::AMDGPU::getCommuteRev(uint16_t Opcode)

Referenced byllvm::SIInstrInfo::commuteOpcode().

◆ getCompletionActionImplicitArgPosition()

unsigned llvm::AMDGPU::getCompletionActionImplicitArgPosition(unsigned CodeObjectVersion)

Definition at line251 of fileAMDGPUBaseInfo.cpp.

ReferencesAMDHSA_COV4,AMDHSA_COV5,AMDHSA_COV6, andllvm::AMDGPU::ImplicitArg::COMPLETION_ACTION_OFFSET.

◆ getDefaultAMDHSACodeObjectVersion()

unsigned llvm::AMDGPU::getDefaultAMDHSACodeObjectVersion()
Returns
The default HSA code object version. This should only be used when we lack a more accurate CodeObjectVersion value (e.g. from the IR module flag or a .amdhsa_code_object_version directive)

Definition at line181 of fileAMDGPUBaseInfo.cpp.

ReferencesDefaultAMDHSACodeObjectVersion.

Referenced bygetAMDHSACodeObjectVersion().

◆ getDefaultCustomOperandEncoding()

staticunsigned llvm::AMDGPU::getDefaultCustomOperandEncoding(constCustomOperandVal * Opr,
int Size,
constMCSubtargetInfo & STI 
)
static

Definition at line1602 of fileAMDGPUBaseInfo.cpp.

ReferencesIdx, andSize.

Referenced byllvm::AMDGPU::DepCtr::getDefaultDepCtrEncoding().

◆ getDefaultQueueImplicitArgPosition()

unsigned llvm::AMDGPU::getDefaultQueueImplicitArgPosition(unsigned CodeObjectVersion)

Definition at line240 of fileAMDGPUBaseInfo.cpp.

ReferencesAMDHSA_COV4,AMDHSA_COV5,AMDHSA_COV6, andllvm::AMDGPU::ImplicitArg::DEFAULT_QUEUE_OFFSET.

◆ getDPPOp32()

LLVM_READONLY int llvm::AMDGPU::getDPPOp32(uint16_t Opcode)

◆ getDPPOp64()

LLVM_READONLY int llvm::AMDGPU::getDPPOp64(uint16_t Opcode)

◆ getDscntBitMask()

unsigned llvm::AMDGPU::getDscntBitMask(constIsaVersion & Version)
Returns
Dscnt bit mask for given isaVersion. Returns 0 for versions that do not support DScnt

Definition at line1430 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::Version.

◆ getELFABIVersion()

uint8_t llvm::AMDGPU::getELFABIVersion(constTriple & OS,
unsigned CodeObjectVersion 
)
Returns
ABIVersion suitable for use inELF's e_ident[EI_ABIVERSION].
Parameters
CodeObjectVersionis a value returned bygetAMDHSACodeObjectVersion().

Definition at line198 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::Triple::AMDHSA,llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V4,llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V5,llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V6, andllvm::report_fatal_error().

Referenced byllvm::AMDGPUTargetELFStreamer::finish().

◆ getEncodingFromOperandTable()

template<size_t N>
static int64_t llvm::AMDGPU::getEncodingFromOperandTable(constCustomOperand(&) Table[N],
StringRef Name,
constMCSubtargetInfo & STI 
)
static

Map from a symbolic name for a sendmsg/hwreg asm operand to it's encoding.

Definition at line51 of fileAMDGPUAsmUtils.cpp.

ReferencesName,OPR_ID_UNKNOWN, andOPR_ID_UNSUPPORTED.

Referenced byllvm::AMDGPU::Hwreg::getHwregId(),llvm::AMDGPU::SendMsg::getMsgId(), andllvm::AMDGPU::SendMsg::getMsgOpId().

◆ getExpcntBitMask()

unsigned llvm::AMDGPU::getExpcntBitMask(constIsaVersion & Version)
Returns
Expcnt bit mask for given isaVersion.

Definition at line1422 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::Version.

Referenced byllvm::AMDGPUInstPrinter::printSWaitCnt().

◆ getFlatScratchInstSSfromSV()

LLVM_READONLY int llvm::AMDGPU::getFlatScratchInstSSfromSV(uint16_t Opcode)
Returns
SS (SADDR) form of a FLAT Scratch instruction given anOpcode of an SV (VADDR) form.

◆ getFlatScratchInstSTfromSS()

LLVM_READONLY int llvm::AMDGPU::getFlatScratchInstSTfromSS(uint16_t Opcode)
Returns
ST form with only immediate offset of a FLAT Scratch instruction given anOpcode of an SS (SADDR) form.

Referenced byllvm::SIRegisterInfo::buildSpillLoadStore(),llvm::SIRegisterInfo::eliminateFrameIndex(), andgetFlatScratchSpillOpcode().

◆ getFlatScratchInstSVfromSS()

LLVM_READONLY int llvm::AMDGPU::getFlatScratchInstSVfromSS(uint16_t Opcode)
Returns
SV (VADDR) form of a FLAT Scratch instruction given anOpcode of an SS (SADDR) form.

Referenced byllvm::SIRegisterInfo::buildSpillLoadStore(),getFlatScratchSpillOpcode(), andllvm::SIInstrInfo::moveFlatAddrToVGPR().

◆ getFlatScratchInstSVfromSVS()

LLVM_READONLY int llvm::AMDGPU::getFlatScratchInstSVfromSVS(uint16_t Opcode)
Returns
SV (VADDR) form of a FLAT Scratch instruction given anOpcode of an SVS (SADDR + VADDR) form.

Referenced byllvm::SIRegisterInfo::eliminateFrameIndex().

◆ getFPDstSelType()

LLVM_READONLYFPType llvm::AMDGPU::getFPDstSelType(unsigned Opc)

Definition at line659 of fileAMDGPUBaseInfo.cpp.

ReferencesFP4,FP8,Info, andNone.

Referenced bygetDstSelForwardingOperand().

◆ getGcnBufferFormatInfo()[1/2]

LLVM_READONLYconstGcnBufferFormatInfo * llvm::AMDGPU::getGcnBufferFormatInfo(uint8_t BitsPerComp,
uint8_t NumComponents,
uint8_t NumFormat,
constMCSubtargetInfo & STI 
)

Definition at line2985 of fileAMDGPUBaseInfo.cpp.

ReferencesisGFX10(), andisGFX11Plus().

Referenced bygetBufferFormatWithCompCount().

◆ getGcnBufferFormatInfo()[2/2]

LLVM_READONLYconstGcnBufferFormatInfo * llvm::AMDGPU::getGcnBufferFormatInfo(uint8_t Format,
constMCSubtargetInfo & STI 
)

Definition at line2998 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::Format,isGFX10(), andisGFX11Plus().

◆ getGlobalSaddrOp()

LLVM_READONLY int llvm::AMDGPU::getGlobalSaddrOp(uint16_t Opcode)
Returns
SADDR form of a FLAT Global instruction given anOpcode of a VADDR form.

◆ getGlobalVaddrOp()

LLVM_READONLY int llvm::AMDGPU::getGlobalVaddrOp(uint16_t Opcode)
Returns
VADDR form of a FLAT Global instruction given anOpcode of a SADDR form.

Referenced byllvm::SIInstrInfo::moveFlatAddrToVGPR().

◆ getHasColorExport()

bool llvm::AMDGPU::getHasColorExport(constFunction & F)

Definition at line2030 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::CallingConv::AMDGPU_PS, andF.

Referenced bygenerateEndPgm().

◆ getHasDepthExport()

bool llvm::AMDGPU::getHasDepthExport(constFunction & F)

Definition at line2037 of fileAMDGPUBaseInfo.cpp.

ReferencesF.

Referenced bygenerateEndPgm().

◆ getHostcallImplicitArgPosition()

unsigned llvm::AMDGPU::getHostcallImplicitArgPosition(unsigned COV)
Returns
The offset of the hostcall pointer argument from implicitarg_ptr

Definition at line229 of fileAMDGPUBaseInfo.cpp.

ReferencesAMDHSA_COV4,AMDHSA_COV5,AMDHSA_COV6, andllvm::AMDGPU::ImplicitArg::HOSTCALL_PTR_OFFSET.

◆ getIfAddr64Inst()

LLVM_READONLY int llvm::AMDGPU::getIfAddr64Inst(uint16_t Opcode)

Check ifOpcode is an Addr64 opcode.

Returns
Opcode if it is an Addr64 opcode, otherwise -1.

Referenced byllvm::SIInstrInfo::legalizeOperands().

◆ getImageDimIntrinsicByBaseOpcode()

constImageDimIntrinsicInfo * llvm::AMDGPU::getImageDimIntrinsicByBaseOpcode(unsigned BaseOpcode,
unsigned Dim 
)

Referenced bysimplifyAMDGCNImageIntrinsic().

◆ getImageDimIntrinsicInfo()

constImageDimIntrinsicInfo * llvm::AMDGPU::getImageDimIntrinsicInfo(unsigned Intr)

Referenced bycollectMergeableInsts(),llvm::SITargetLowering::getTgtMemIntrinsic(),llvm::GCNTTIImpl::instCombineIntrinsic(),llvm::AMDGPULegalizerInfo::legalizeIntrinsic(),optimizeSection(), andllvm::AMDGPUInstructionSelector::select().

◆ getInitialPSInputAddr()

unsigned llvm::AMDGPU::getInitialPSInputAddr(constFunction & F)

Definition at line2026 of fileAMDGPUBaseInfo.cpp.

ReferencesF.

Referenced byllvm::SIMachineFunctionInfo::SIMachineFunctionInfo().

◆ getInlineEncodingV216()

std::optional<unsigned > llvm::AMDGPU::getInlineEncodingV216(bool IsFloat,
uint32_t Literal 
)

Definition at line2680 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::Literal, andSigned.

Referenced bygetInlineEncodingV2F16(),getInlineEncodingV2I16(), andisInlinableLiteralV216().

◆ getInlineEncodingV2BF16()

LLVM_READNONE std::optional<unsigned > llvm::AMDGPU::getInlineEncodingV2BF16(uint32_t Literal)

Definition at line2741 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::Literal, andSigned.

Referenced byllvm::SITargetLowering::checkAsmConstraintValA(), andisInlinableLiteralV2BF16().

◆ getInlineEncodingV2F16()

LLVM_READNONE std::optional<unsigned > llvm::AMDGPU::getInlineEncodingV2F16(uint32_t Literal)

Definition at line2769 of fileAMDGPUBaseInfo.cpp.

ReferencesgetInlineEncodingV216(), andllvm::Literal.

Referenced byllvm::SITargetLowering::checkAsmConstraintValA(), andisInlinableLiteralV2F16().

◆ getInlineEncodingV2I16()

LLVM_READNONE std::optional<unsigned > llvm::AMDGPU::getInlineEncodingV2I16(uint32_t Literal)

Definition at line2735 of fileAMDGPUBaseInfo.cpp.

ReferencesgetInlineEncodingV216(), andllvm::Literal.

Referenced byllvm::SITargetLowering::checkAsmConstraintValA(), andisInlinableLiteralV2I16().

◆ getIntegerAttribute()

int llvm::AMDGPU::getIntegerAttribute(constFunction & F,
StringRef Name,
int Default 
)
Returns
Integer value requested usingF'sName attribute.
Default if attribute is not present.
Default and emits error if requested value cannot be converted to integer.

◆ getIntegerPairAttribute()[1/2]

std::optional< std::pair<unsigned, std::optional<unsigned > > > llvm::AMDGPU::getIntegerPairAttribute(constFunction & F,
StringRef Name,
bool OnlyFirstRequired =false 
)
Returns
A pair of integer values requested usingF'sName attribute in "first[,second]" format ("second" is optional unlessOnlyFirstRequired is false).
std::nullopt if attribute is not present.
std::nullopt and emits error if one of the requested values cannot be converted to integer, orOnlyFirstRequired is false and "second" value is not present.

Definition at line1341 of fileAMDGPUBaseInfo.cpp.

ReferencesA,llvm::LLVMContext::emitError(),F, andName.

◆ getIntegerPairAttribute()[2/2]

std::pair<unsigned,unsigned > llvm::AMDGPU::getIntegerPairAttribute(constFunction & F,
StringRef Name,
std::pair<unsigned,unsigned > Default,
bool OnlyFirstRequired =false 
)
Returns
A pair of integer values requested usingF'sName attribute in "first[,second]" format ("second" is optional unlessOnlyFirstRequired is false).
Default if attribute is not present.
Default and emits error if one of the requested values cannot be converted to integer, orOnlyFirstRequired is false and "second" value is not present.

Definition at line1332 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::Default,F,getIntegerPairAttribute(), andName.

Referenced byllvm::AMDGPUMachineFunction::AMDGPUMachineFunction(),llvm::AMDGPUSubtarget::getFlatWorkGroupSizes(),getIntegerPairAttribute(), andllvm::AMDGPUSubtarget::getWavesPerEU().

◆ getIntegerVecAttribute()

SmallVector<unsigned > llvm::AMDGPU::getIntegerVecAttribute(constFunction & F,
StringRef Name,
unsigned Size,
unsigned DefaultVal =0 
)
Returns
Generate a vector of integer values requested usingF'sName attribute.
true if exactly Size (>2) number of integers are found in the attribute.
false if any error occurs.

Definition at line1367 of fileAMDGPUBaseInfo.cpp.

ReferencesA,assert(),llvm::Default,DefaultVal,llvm::LLVMContext::emitError(),llvm::StringRef::empty(),F,Name,Size, andllvm::StringRef::split().

Referenced byllvm::AMDGPUSubtarget::getMaxNumWorkGroups(), andprocessUse().

◆ getInterestingMemoryOperands()

void llvm::AMDGPU::getInterestingMemoryOperands(Module & M,
Instruction * I,
SmallVectorImpl<InterestingMemoryOperand > & Interesting 
)

Get all the memory operands from the instruction that needs to be instrumented.

Definition at line220 of fileAMDGPUAsanInstrumentation.cpp.

ReferencesDL,llvm::SmallVectorImpl< T >::emplace_back(),llvm::VectorType::get(),I,Ptr,llvm::Align::value(), andllvm::MaybeAlign::valueOrOne().

◆ getIntrinsicID()

Intrinsic::ID llvm::AMDGPU::getIntrinsicID(constMachineInstr & I)

Return the intrinsic ID for opcodes with the G_AMDGPU_INTRIN_ prefix.

These opcodes have anIntrinsic::ID operand similar to aGIntrinsic. But they are not actual instances of GIntrinsics, so we cannot useGIntrinsic::getIntrinsicID() on them.

Definition at line30 of fileAMDGPUInstrInfo.cpp.

ReferencesI.

Referenced byllvm::AMDGPURegisterBankInfo::applyMappingImpl(),llvm::AMDGPURegisterBankInfo::getInstrMapping(), andllvm::AMDGPUInstructionSelector::select().

◆ getIsaVersion()

AMDGPU::IsaVersion llvm::AMDGPU::getIsaVersion(StringRef GPU)

Definition at line229 of fileTargetParser.cpp.

ReferencesGK_GFX1010,GK_GFX1011,GK_GFX1012,GK_GFX1013,GK_GFX1030,GK_GFX1031,GK_GFX1032,GK_GFX1033,GK_GFX1034,GK_GFX1035,GK_GFX1036,GK_GFX10_1_GENERIC,GK_GFX10_3_GENERIC,GK_GFX1100,GK_GFX1101,GK_GFX1102,GK_GFX1103,GK_GFX1150,GK_GFX1151,GK_GFX1152,GK_GFX1153,GK_GFX11_GENERIC,GK_GFX1200,GK_GFX1201,GK_GFX12_GENERIC,GK_GFX600,GK_GFX601,GK_GFX602,GK_GFX700,GK_GFX701,GK_GFX702,GK_GFX703,GK_GFX704,GK_GFX705,GK_GFX801,GK_GFX802,GK_GFX803,GK_GFX805,GK_GFX810,GK_GFX900,GK_GFX902,GK_GFX904,GK_GFX906,GK_GFX908,GK_GFX909,GK_GFX90A,GK_GFX90C,GK_GFX940,GK_GFX941,GK_GFX942,GK_GFX950,GK_GFX9_4_GENERIC,GK_GFX9_GENERIC, andparseArchAMDGCN().

Referenced byllvm::AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(),llvm::AMDGPU::IsaInfo::getAddressableNumSGPRs(),llvm::AMDGPU::MCKernelDescriptor::getDefaultAmdhsaKernelDescriptor(),llvm::AMDGPU::IsaInfo::getMaxNumSGPRs(),llvm::AMDGPU::IsaInfo::getMinNumSGPRs(),getNSAMaxSize(),llvm::AMDGPU::IsaInfo::getNumExtraSGPRs(),llvm::AMDGPU::IsaInfo::getSGPRAllocGranule(),llvm::AMDGPU::IsaInfo::getTotalNumSGPRs(),initDefaultAMDKernelCodeT(),llvm::AMDGPUInstPrinter::printSWaitCnt(), andllvm::AMDGPU::IsaInfo::AMDGPUTargetID::toString().

◆ getKmcntBitMask()

unsigned llvm::AMDGPU::getKmcntBitMask(constIsaVersion & Version)
Returns
Dscnt bit mask for given isaVersion. Returns 0 for versions that do not support KMcnt

Definition at line1434 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::Version.

◆ getLdsDwGranularity()

unsigned llvm::AMDGPU::getLdsDwGranularity(constMCSubtargetInfo & ST)
Returns
lds block size in terms of dwords.This is used to calculate the lds size encoded for PAL metadata 3.0+ which must be defined in terms of bytes.

Definition at line3024 of fileAMDGPUBaseInfo.cpp.

Referenced byEmitPALMetadataCommon().

◆ getLgkmcntBitMask()

unsigned llvm::AMDGPU::getLgkmcntBitMask(constIsaVersion & Version)
Returns
Lgkmcnt bit mask for given isaVersion.

Definition at line1426 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::Version.

Referenced byllvm::AMDGPUInstPrinter::printSWaitCnt().

◆ getLoadcntBitMask()

unsigned llvm::AMDGPU::getLoadcntBitMask(constIsaVersion & Version)
Returns
Loadcnt bit mask for given isaVersion. Returns 0 for versions that do not support LOADcnt

Definition at line1410 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::Version.

◆ getMAIIsDGEMM()

LLVM_READONLYbool llvm::AMDGPU::getMAIIsDGEMM(unsigned Opc)

Returns true if MAI operation is a double precision GEMM.

Definition at line528 of fileAMDGPUBaseInfo.cpp.

ReferencesInfo.

Referenced byisDGEMM().

◆ getMAIIsGFX940XDL()

LLVM_READONLYbool llvm::AMDGPU::getMAIIsGFX940XDL(unsigned Opc)

Definition at line533 of fileAMDGPUBaseInfo.cpp.

ReferencesInfo.

Referenced byisXDL().

◆ getMaskedMIMGOp()

LLVM_READONLY int llvm::AMDGPU::getMaskedMIMGOp(unsigned Opc,
unsigned NewChannels 
)

Definition at line285 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::AMDGPU::MIMGInfo::BaseOpcode,getMIMGInfo(),llvm::AMDGPU::MIMGInfo::MIMGEncoding,llvm::AMDGPU::MIMGInfo::Opcode, andllvm::AMDGPU::MIMGInfo::VAddrDwords.

◆ getMaxNumUserSGPRs()

unsigned llvm::AMDGPU::getMaxNumUserSGPRs(constMCSubtargetInfo & STI)

Definition at line2146 of fileAMDGPUBaseInfo.cpp.

Referenced byllvm::GCNUserSGPRUsageInfo::allocKernargPreloadSGPRs(),llvm::GCNSubtarget::getMaxNumUserSGPRs(), andllvm::GCNUserSGPRUsageInfo::getNumFreeUserSGPRs().

◆ getMCOpcode()

LLVM_READONLY int llvm::AMDGPU::getMCOpcode(uint16_t Opcode,
unsigned Gen 
)

Definition at line684 of fileAMDGPUBaseInfo.cpp.

Referenced byllvm::SIInstrInfo::pseudoToMCOpcode().

◆ getMCReg()

MCRegister llvm::AMDGPU::getMCReg(MCRegister Reg,
constMCSubtargetInfo & STI 
)

IfReg is a pseudo reg, return the correct hardware register givenSTI otherwise returnReg.

Definition at line2349 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::Triple::getArch(),llvm::MCSubtargetInfo::getTargetTriple(),MAP_REG2REG,llvm::Triple::r600, andReg.

Referenced byllvm::AMDGPUDisassembler::createRegOperand(), andAMDGPUMCInstLower::lowerOperand().

◆ getMFMA_F8F6F4_WithFormatArgs()

LLVM_READONLYconstMFMA_F8F6F4_Info * llvm::AMDGPU::getMFMA_F8F6F4_WithFormatArgs(unsigned CBSZ,
unsigned BLGP,
unsigned F8F8Opcode 
)

Definition at line554 of fileAMDGPUBaseInfo.cpp.

ReferencesmfmaScaleF8F6F4FormatToNumRegs().

Referenced byllvm::AMDGPUDisassembler::convertMAIInst().

◆ getMFMAEarlyClobberOp()

LLVM_READONLY int llvm::AMDGPU::getMFMAEarlyClobberOp(uint16_t Opcode)
Returns
earlyclobber version of a MAC MFMA is exists.

Referenced byllvm::SIInstrInfo::convertToThreeAddress(), andllvm::SIInstrInfo::pseudoToMCOpcode().

◆ getMFMASrcCVDstAGPROp()

LLVM_READONLY int llvm::AMDGPU::getMFMASrcCVDstAGPROp(uint16_t Opcode)
Returns
Version of an MFMA instruction which uses AGPRs for srcC and vdst, given anOpcode of an MFMA which uses VGPRs for srcC/vdst.

◆ getMIMGBaseOpcode()

LLVM_READONLYconstMIMGBaseOpcodeInfo * llvm::AMDGPU::getMIMGBaseOpcode(unsigned Opc)

Definition at line280 of fileAMDGPUBaseInfo.cpp.

ReferencesgetMIMGBaseOpcodeInfo(),getMIMGInfo(), andInfo.

◆ getMIMGBaseOpcodeInfo()

LLVM_READONLYconstMIMGBaseOpcodeInfo * llvm::AMDGPU::getMIMGBaseOpcodeInfo(unsigned BaseOpcode)

Referenced byllvm::AMDGPUDisassembler::convertMIMGInst(),getMIMGBaseOpcode(),llvm::SITargetLowering::getTgtMemIntrinsic(),llvm::AMDGPULegalizerInfo::legalizeImageIntrinsic(),simplifyAMDGCNImageIntrinsic(), andllvm::SIInstrInfo::verifyInstruction().

◆ getMIMGBiasMappingInfo()

LLVM_READONLYconstMIMGBiasMappingInfo * llvm::AMDGPU::getMIMGBiasMappingInfo(unsigned Bias)

Referenced bysimplifyAMDGCNImageIntrinsic().

◆ getMIMGDimInfo()

LLVM_READONLYconstMIMGDimInfo * llvm::AMDGPU::getMIMGDimInfo(unsigned DimEnum)

◆ getMIMGDimInfoByAsmSuffix()

LLVM_READONLYconstMIMGDimInfo * llvm::AMDGPU::getMIMGDimInfoByAsmSuffix(StringRef AsmSuffix)

◆ getMIMGDimInfoByEncoding()

LLVM_READONLYconstMIMGDimInfo * llvm::AMDGPU::getMIMGDimInfoByEncoding(uint8_t DimEnc)

Referenced byllvm::AMDGPUDisassembler::convertMIMGInst(), andllvm::SIInstrInfo::verifyInstruction().

◆ getMIMGG16MappingInfo()

LLVM_READONLYconstMIMGG16MappingInfo * llvm::AMDGPU::getMIMGG16MappingInfo(unsigned G)

◆ getMIMGInfo()

LLVM_READONLYconstMIMGInfo * llvm::AMDGPU::getMIMGInfo(unsigned Opc)

Referenced byllvm::AMDGPUDisassembler::convertMIMGInst(),getMaskedMIMGOp(),getMIMGBaseOpcode(), andllvm::SIInstrInfo::verifyInstruction().

◆ getMIMGLZMappingInfo()

LLVM_READONLYconstMIMGLZMappingInfo * llvm::AMDGPU::getMIMGLZMappingInfo(unsigned L)

Referenced bysimplifyAMDGCNImageIntrinsic().

◆ getMIMGMIPMappingInfo()

LLVM_READONLYconstMIMGMIPMappingInfo * llvm::AMDGPU::getMIMGMIPMappingInfo(unsigned MIP)

Referenced bysimplifyAMDGCNImageIntrinsic().

◆ getMIMGOffsetMappingInfo()

LLVM_READONLYconstMIMGOffsetMappingInfo * llvm::AMDGPU::getMIMGOffsetMappingInfo(unsigned Offset)

Referenced bysimplifyAMDGCNImageIntrinsic().

◆ getMIMGOpcode()

LLVM_READONLY int llvm::AMDGPU::getMIMGOpcode(unsigned BaseOpcode,
unsigned MIMGEncoding,
unsigned VDataDwords,
unsigned VAddrDwords 
)

Definition at line273 of fileAMDGPUBaseInfo.cpp.

ReferencesInfo.

Referenced byllvm::AMDGPUDisassembler::convertMIMGInst(), andllvm::AMDGPULegalizerInfo::legalizeBVHIntrinsic().

◆ getMinRedzoneSizeForGlobal()

staticuint64_t llvm::AMDGPU::getMinRedzoneSizeForGlobal(int AsanScale)
static

Definition at line24 of fileAMDGPUAsanInstrumentation.cpp.

ReferencesgetRedzoneSizeForScale().

Referenced bygetRedzoneSizeForGlobal().

◆ getMTBUFBaseOpcode()

LLVM_READONLY int llvm::AMDGPU::getMTBUFBaseOpcode(unsigned Opc)

Definition at line432 of fileAMDGPUBaseInfo.cpp.

ReferencesInfo.

◆ getMTBUFElements()

LLVM_READONLY int llvm::AMDGPU::getMTBUFElements(unsigned Opc)

Definition at line442 of fileAMDGPUBaseInfo.cpp.

ReferencesInfo.

◆ getMTBUFHasSoffset()

LLVM_READONLYbool llvm::AMDGPU::getMTBUFHasSoffset(unsigned Opc)

Definition at line457 of fileAMDGPUBaseInfo.cpp.

ReferencesInfo.

◆ getMTBUFHasSrsrc()

LLVM_READONLYbool llvm::AMDGPU::getMTBUFHasSrsrc(unsigned Opc)

Definition at line452 of fileAMDGPUBaseInfo.cpp.

ReferencesInfo.

◆ getMTBUFHasVAddr()

LLVM_READONLYbool llvm::AMDGPU::getMTBUFHasVAddr(unsigned Opc)

Definition at line447 of fileAMDGPUBaseInfo.cpp.

ReferencesInfo.

◆ getMTBUFOpcode()

LLVM_READONLY int llvm::AMDGPU::getMTBUFOpcode(unsigned BaseOpc,
unsigned Elements 
)

Definition at line437 of fileAMDGPUBaseInfo.cpp.

ReferencesInfo.

◆ getMUBUFBaseOpcode()

LLVM_READONLY int llvm::AMDGPU::getMUBUFBaseOpcode(unsigned Opc)

Definition at line462 of fileAMDGPUBaseInfo.cpp.

ReferencesInfo.

◆ getMUBUFElements()

LLVM_READONLY int llvm::AMDGPU::getMUBUFElements(unsigned Opc)

Definition at line472 of fileAMDGPUBaseInfo.cpp.

ReferencesInfo.

◆ getMUBUFHasSoffset()

LLVM_READONLYbool llvm::AMDGPU::getMUBUFHasSoffset(unsigned Opc)

Definition at line487 of fileAMDGPUBaseInfo.cpp.

ReferencesInfo.

◆ getMUBUFHasSrsrc()

LLVM_READONLYbool llvm::AMDGPU::getMUBUFHasSrsrc(unsigned Opc)

Definition at line482 of fileAMDGPUBaseInfo.cpp.

ReferencesInfo.

◆ getMUBUFHasVAddr()

LLVM_READONLYbool llvm::AMDGPU::getMUBUFHasVAddr(unsigned Opc)

Definition at line477 of fileAMDGPUBaseInfo.cpp.

ReferencesInfo.

◆ getMUBUFIsBufferInv()

LLVM_READONLYbool llvm::AMDGPU::getMUBUFIsBufferInv(unsigned Opc)

Definition at line492 of fileAMDGPUBaseInfo.cpp.

ReferencesInfo.

◆ getMUBUFOpcode()

LLVM_READONLY int llvm::AMDGPU::getMUBUFOpcode(unsigned BaseOpc,
unsigned Elements 
)

Definition at line467 of fileAMDGPUBaseInfo.cpp.

ReferencesInfo.

◆ getMUBUFTfe()

LLVM_READONLYbool llvm::AMDGPU::getMUBUFTfe(unsigned Opc)

Definition at line497 of fileAMDGPUBaseInfo.cpp.

ReferencesInfo.

Referenced byllvm::SITargetLowering::AddMemOpInit().

◆ getMultigridSyncArgImplicitArgPosition()

unsigned llvm::AMDGPU::getMultigridSyncArgImplicitArgPosition(unsigned COV)
Returns
The offset of the multigrid_sync_arg argument from implicitarg_ptr

Definition at line215 of fileAMDGPUBaseInfo.cpp.

ReferencesAMDHSA_COV4,AMDHSA_COV5,AMDHSA_COV6, andllvm::AMDGPU::ImplicitArg::MULTIGRID_SYNC_ARG_OFFSET.

◆ getNamedOperandIdx()

LLVM_READONLY int16_t llvm::AMDGPU::getNamedOperandIdx(uint16_t Opcode,
uint16_t NamedIdx 
)

Referenced byllvm::SITargetLowering::AddMemOpInit(),addSrcModifiersAndSrc(),llvm::SITargetLowering::AdjustInstrPostInstrSelection(),llvm::SIInstrInfo::areLoadsFromSameBasePtr(),llvm::SIInstrInfo::buildShrunkInst(),llvm::SIRegisterInfo::buildSpillLoadStore(),collectVOPModifiers(),llvm::SIInstrInfo::commuteInstructionImpl(),llvm::AMDGPUDisassembler::convertDPP8Inst(),llvm::AMDGPUDisassembler::convertMAIInst(),llvm::AMDGPUDisassembler::convertMIMGInst(),llvm::AMDGPUDisassembler::convertSDWAInst(),llvm::SIInstrInfo::convertToThreeAddress(),llvm::AMDGPUDisassembler::convertTrue16OpSel(),llvm::AMDGPUDisassembler::convertVOP3DPPInst(),cvtVOP3DstOpSelOnly(),decodeAVLdSt(),llvm::AMDGPUDisassembler::decodeVOPDDstYOp(),llvm::SIRegisterInfo::eliminateFrameIndex(),llvm::SIInstrInfo::enforceOperandRCAlignment(),llvm::SIInstrInfo::findCommutedOpIndices(),llvm::SIInstrInfo::foldImmediate(),llvm::SIRegisterInfo::getFrameIndexInstrOffset(),llvm::AMDGPUDisassembler::getInstruction(),llvm::SIInstrInfo::getInstSizeInBytes(),llvm::SIInstrInfo::getMemOperandsWithOffsetWidth(),llvm::SIInstrInfo::getNamedImmOperand(),llvm::SIInstrInfo::getNamedOperand(),llvm::SIInstrInfo::getRegClass(),llvm::SIRegisterInfo::getScratchInstrOffset(),getSrcOperandIndices(),hasAny64BitVGPROperands(),hasNamedOperand(),llvm::SIInstrWorklist::insert(),insertNamedMCOperand(),IsAGPROperand(),llvm::SIInstrInfo::isBufferSMRD(),llvm::SIInstrInfo::isImmOperandLegal(),llvm::SIInstrInfo::isLegalRegOperand(),llvm::SIInstrInfo::isLegalToSwap(),llvm::AMDGPUDisassembler::isMacDPP(),isSendMsgTraceDataOrGDS(),llvm::SIInstrInfo::legalizeOperands(),llvm::SIInstrInfo::legalizeOperandsVOP2(),llvm::SIInstrInfo::legalizeOperandsVOP3(),AMDGPUMCInstLower::lower(),llvm::SIInstrInfo::moveFlatAddrToVGPR(),llvm::SIInstrInfo::moveToVALUImpl(),nodesHaveSameOperandValue(),llvm::SIFrameLowering::processFunctionBeforeFrameFinalized(),llvm::SIInstrInfo::removeModOperands(),updateOperandIfDifferent(), andllvm::SIInstrInfo::verifyInstruction().

◆ getNameFromOperandTable()

template<size_t N>
staticStringRef llvm::AMDGPU::getNameFromOperandTable(constCustomOperand(&) Table[N],
unsigned Encoding,
constMCSubtargetInfo & STI 
)
static

Map from the encoding of a sendmsg/hwreg asm operand to it's name.

Definition at line27 of fileAMDGPUAsmUtils.cpp.

ReferencesIdx,N, andName.

Referenced byllvm::AMDGPU::Hwreg::getHwreg(),llvm::AMDGPU::SendMsg::getMsgName(), andllvm::AMDGPU::SendMsg::getMsgOpName().

◆ getNSAMaxSize()

unsigned llvm::AMDGPU::getNSAMaxSize(constMCSubtargetInfo & STI,
bool HasSampler 
)

Definition at line2135 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::MCSubtargetInfo::getCPU(),getIsaVersion(), andllvm::Version.

Referenced byllvm::GCNSubtarget::getNSAMaxSize().

◆ getNumFlatOffsetBits()

unsigned llvm::AMDGPU::getNumFlatOffsetBits(constMCSubtargetInfo & ST)

For pre-GFX12 FLAT instructions the offset must be positive; MSB is ignored and forced to zero.

Returns
The number of bits available for the signed offset field in flat instructions. Note that some forms of the instruction disallow negative offsets.

Definition at line2946 of fileAMDGPUBaseInfo.cpp.

ReferencesisGFX10(), andisGFX12().

Referenced byllvm::SIInstrInfo::isLegalFLATOffset(), andllvm::SIInstrInfo::splitFlatOffset().

◆ getOperandSize()[1/2]

LLVM_READNONEunsigned llvm::AMDGPU::getOperandSize(constMCInstrDesc & Desc,
unsigned OpNo 
)
inline

Definition at line1451 of fileAMDGPUBaseInfo.h.

ReferencesgetOperandSize().

◆ getOperandSize()[2/2]

LLVM_READNONEunsigned llvm::AMDGPU::getOperandSize(constMCOperandInfo & OpInfo)
inline

Definition at line1398 of fileAMDGPUBaseInfo.h.

Referencesllvm_unreachable,OPERAND_INLINE_SPLIT_BARRIER_INT32,OPERAND_KIMM16,OPERAND_KIMM32,OPERAND_REG_IMM_BF16,OPERAND_REG_IMM_BF16_DEFERRED,OPERAND_REG_IMM_FP16,OPERAND_REG_IMM_FP16_DEFERRED,OPERAND_REG_IMM_FP32,OPERAND_REG_IMM_FP32_DEFERRED,OPERAND_REG_IMM_FP64,OPERAND_REG_IMM_INT16,OPERAND_REG_IMM_INT32,OPERAND_REG_IMM_INT64,OPERAND_REG_IMM_V2BF16,OPERAND_REG_IMM_V2FP16,OPERAND_REG_IMM_V2FP32,OPERAND_REG_IMM_V2INT16,OPERAND_REG_IMM_V2INT32,OPERAND_REG_INLINE_AC_BF16,OPERAND_REG_INLINE_AC_FP16,OPERAND_REG_INLINE_AC_FP32,OPERAND_REG_INLINE_AC_FP64,OPERAND_REG_INLINE_AC_INT16,OPERAND_REG_INLINE_AC_INT32,OPERAND_REG_INLINE_AC_V2BF16,OPERAND_REG_INLINE_AC_V2FP16,OPERAND_REG_INLINE_AC_V2INT16,OPERAND_REG_INLINE_C_BF16,OPERAND_REG_INLINE_C_FP16,OPERAND_REG_INLINE_C_FP32,OPERAND_REG_INLINE_C_FP64,OPERAND_REG_INLINE_C_INT16,OPERAND_REG_INLINE_C_INT32,OPERAND_REG_INLINE_C_INT64,OPERAND_REG_INLINE_C_V2BF16,OPERAND_REG_INLINE_C_V2FP16,OPERAND_REG_INLINE_C_V2FP32,OPERAND_REG_INLINE_C_V2INT16,OPERAND_REG_INLINE_C_V2INT32, andllvm::MCOperandInfo::OperandType.

Referenced bygetOperandSize().

◆ getRedzoneSizeForGlobal()

uint64_t llvm::AMDGPU::getRedzoneSizeForGlobal(int AsanScale,
uint64_t SizeInBytes 
)

Given SizeInBytes of theValue to be instrunmented, Returns the redzone size corresponding to it.

Definition at line28 of fileAMDGPUAsanInstrumentation.cpp.

Referencesassert(), andgetMinRedzoneSizeForGlobal().

◆ getRedzoneSizeForScale()

staticuint64_t llvm::AMDGPU::getRedzoneSizeForScale(int AsanScale)
static

Definition at line18 of fileAMDGPUAsanInstrumentation.cpp.

Referenced bygetMinRedzoneSizeForGlobal().

◆ getRegBitWidth()[1/3]

unsigned llvm::AMDGPU::getRegBitWidth(constMCRegisterClass & RC)

Get the size in bits of a register from the register classRC.

Definition at line2588 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::MCRegisterClass::getID(), andgetRegBitWidth().

◆ getRegBitWidth()[2/3]

unsigned llvm::AMDGPU::getRegBitWidth(constTargetRegisterClass & RC)

Get the size in bits of a register from the register classRC.

Definition at line3201 of fileSIRegisterInfo.cpp.

Referencesllvm::TargetRegisterClass::getID(), andgetRegBitWidth().

Referenced byllvm::SIRegisterInfo::buildSpillLoadStore(),llvm::SIInstrInfo::canInsertSelect(),getRegBitWidth(),getRegOperandSize(), andllvm::SIRegisterInfo::getRegSplitParts().

◆ getRegBitWidth()[3/3]

unsigned llvm::AMDGPU::getRegBitWidth(unsigned RCID)

Get the size in bits of a register from the register classRC.

Definition at line2447 of fileAMDGPUBaseInfo.cpp.

Referencesllvm_unreachable.

◆ getRegOperandSize()

unsigned llvm::AMDGPU::getRegOperandSize(constMCRegisterInfo * MRI,
constMCInstrDesc & Desc,
unsigned OpNo 
)

Get size of register operand.

Definition at line2592 of fileAMDGPUBaseInfo.cpp.

Referencesassert(), andgetRegBitWidth().

◆ getSamplecntBitMask()

unsigned llvm::AMDGPU::getSamplecntBitMask(constIsaVersion & Version)
Returns
Samplecnt bit mask for given isaVersion. Returns 0 for versions that do not support SAMPLEcnt

Definition at line1414 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::Version.

◆ getSDWAOp()

LLVM_READONLY int llvm::AMDGPU::getSDWAOp(uint16_t Opcode)

◆ getShiftMask()

constexpr std::pair<unsigned,unsigned > llvm::AMDGPU::getShiftMask(unsigned Value)
constexpr

Deduce the least significant bit aligned shift and mask values for a binary ComplementValue (as they're defined inSIDefines.h as C_*) as a returned pair<shift, mask>.

That is to sayValue == ~(mask << shift)

For example, given C_00B848_FWD_PROGRESS (i.e., 0x7FFFFFFF) fromSIDefines.h, this will return the pair as (31,1).

Definition at line27 of fileSIDefinesUtils.h.

◆ getSMEMIsBuffer()

LLVM_READONLYbool llvm::AMDGPU::getSMEMIsBuffer(unsigned Opc)

Definition at line502 of fileAMDGPUBaseInfo.cpp.

ReferencesInfo.

◆ getSMRDEncodedLiteralOffset32()

std::optional< int64_t > llvm::AMDGPU::getSMRDEncodedLiteralOffset32(constMCSubtargetInfo & ST,
int64_t ByteOffset 
)
Returns
The encoding that can be used for a 32-bit literal offset in an SMRD instruction. This is only useful on CI.s

Definition at line2936 of fileAMDGPUBaseInfo.cpp.

ReferencesconvertSMRDOffsetUnits(),isCI(), andisDwordAligned().

◆ getSMRDEncodedOffset()

std::optional< int64_t > llvm::AMDGPU::getSMRDEncodedOffset(constMCSubtargetInfo & ST,
int64_t ByteOffset,
bool IsBuffer,
bool HasSOffset =false 
)
Returns
The encoding that will be used forByteOffset in the SMRD offset field, or std::nullopt if it won't fit. On GFX9 and GFX10 S_LOAD instructions have a signed offset, on other subtargets it is unsigned. S_BUFFER has an unsigned offset for all subtargets.

Definition at line2907 of fileAMDGPUBaseInfo.cpp.

Referencesassert(),convertSMRDOffsetUnits(),hasSMEMByteOffset(),hasSMRDSignedImmOffset(),isDwordAligned(),isGFX12Plus(), andisLegalSMRDEncodedUnsignedOffset().

◆ getSOPKOp()

LLVM_READONLY int llvm::AMDGPU::getSOPKOp(uint16_t Opcode)

◆ getSOPPWithRelaxation()

LLVM_READONLY int llvm::AMDGPU::getSOPPWithRelaxation(uint16_t Opcode)

◆ getStorecntBitMask()

unsigned llvm::AMDGPU::getStorecntBitMask(constIsaVersion & Version)
Returns
STOREcnt or VScnt bit mask for given isaVersion. returns 0 for versions that do not support STOREcnt or VScnt. STOREcnt and VScnt are the same counter, the name used depends on the ISA version.

Definition at line1438 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::Version.

◆ getTotalNumVGPRs()

int llvm::AMDGPU::getTotalNumVGPRs(bool has90AInsts,
int32_t ArgNumAGPR,
int32_t ArgNumVGPR 
)

Definition at line2274 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::alignTo().

◆ getTransitiveUsesOfLDS()

LDSUsesInfoTy llvm::AMDGPU::getTransitiveUsesOfLDS(constCallGraph & CG,
Module & M 
)

Definition at line138 of fileAMDGPUMemoryUtils.cpp.

Referencesassert(),llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::contains(),llvm::detail::DenseSetImpl< ValueT, MapTy, ValueInfoT >::contains(),llvm::SmallVectorBase< Size_T >::empty(),F,getUsesOfLDSByFunction(),llvm::detail::DenseSetImpl< ValueT, MapTy, ValueInfoT >::insert(),llvm::SmallPtrSetImpl< PtrType >::insert(),isDynamicLDS(),isKernelLDS(),isNamedBarrier(),llvm::SmallVectorImpl< T >::pop_back_val(),llvm::SmallVectorTemplateBase< T, bool >::push_back(),llvm::report_fatal_error(), andllvm::set_union().

◆ getUsesOfLDSByFunction()

void llvm::AMDGPU::getUsesOfLDSByFunction(constCallGraph & CG,
Module & M,
FunctionVariableMap & kernels,
FunctionVariableMap & Functions 
)

Definition at line107 of fileAMDGPUMemoryUtils.cpp.

ReferencesF,I,llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::insert(),isKernelLDS(), andisLDSVariableToLower().

Referenced bygetTransitiveUsesOfLDS().

◆ getVCMPXNoSDstOp()

LLVM_READONLY int llvm::AMDGPU::getVCMPXNoSDstOp(uint16_t Opcode)

◆ getVCMPXOpFromVCMP()

LLVM_READONLY int llvm::AMDGPU::getVCMPXOpFromVCMP(uint16_t Opcode)
Returns
v_cmpx version of a v_cmp instruction.

◆ getVmcntBitMask()

unsigned llvm::AMDGPU::getVmcntBitMask(constIsaVersion & Version)
Returns
Vmcnt bit mask for given isaVersion.

Definition at line1404 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::Version.

Referenced byllvm::AMDGPUInstPrinter::printSWaitCnt().

◆ getVOP1IsSingle()

LLVM_READONLYbool llvm::AMDGPU::getVOP1IsSingle(unsigned Opc)

Definition at line507 of fileAMDGPUBaseInfo.cpp.

ReferencesInfo.

◆ getVOP2IsSingle()

LLVM_READONLYbool llvm::AMDGPU::getVOP2IsSingle(unsigned Opc)

Definition at line512 of fileAMDGPUBaseInfo.cpp.

ReferencesInfo.

◆ getVOP3IsSingle()

LLVM_READONLYbool llvm::AMDGPU::getVOP3IsSingle(unsigned Opc)

Definition at line517 of fileAMDGPUBaseInfo.cpp.

ReferencesInfo.

◆ getVOPDComponents()

LLVM_READONLY std::pair<unsigned,unsigned > llvm::AMDGPU::getVOPDComponents(unsigned VOPDOpcode)

Definition at line694 of fileAMDGPUBaseInfo.cpp.

Referencesassert(), andInfo.

Referenced bygetVOPDInstInfo().

◆ getVOPDEncodingFamily()

LLVM_READONLYunsigned llvm::AMDGPU::getVOPDEncodingFamily(constMCSubtargetInfo & ST)
Returns
SIEncodingFamily used forVOPD encoding on aST.

Definition at line562 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::SIEncodingFamily::GFX11,llvm::SIEncodingFamily::GFX12, andllvm_unreachable.

◆ getVOPDFull()

LLVM_READONLY int llvm::AMDGPU::getVOPDFull(unsigned OpX,
unsigned OpY,
unsigned EncodingFamily 
)

Definition at line688 of fileAMDGPUBaseInfo.cpp.

ReferencesInfo.

◆ getVOPDInstInfo()[1/2]

LLVM_READONLYVOPD::InstInfo llvm::AMDGPU::getVOPDInstInfo(constMCInstrDesc & OpX,
constMCInstrDesc & OpY 
)

Definition at line790 of fileAMDGPUBaseInfo.cpp.

Referenced byllvm::checkVOPDRegConstraints().

◆ getVOPDInstInfo()[2/2]

LLVM_READONLYVOPD::InstInfo llvm::AMDGPU::getVOPDInstInfo(unsigned VOPDOpcode,
constMCInstrInfo * InstrInfo 
)

Definition at line794 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::AMDGPU::VOPD::COMPONENT_X,llvm::MCInstrInfo::get(), andgetVOPDComponents().

◆ getVOPDOpcode()

LLVM_READONLYunsigned llvm::AMDGPU::getVOPDOpcode(unsigned Opc)

Definition at line577 of fileAMDGPUBaseInfo.cpp.

ReferencesInfo.

◆ getVOPe32()

LLVM_READONLY int llvm::AMDGPU::getVOPe32(uint16_t Opcode)

Referenced byllvm::SIInstrInfo::hasVALU32BitEncoding().

◆ getVOPe64()

LLVM_READONLY int llvm::AMDGPU::getVOPe64(uint16_t Opcode)

Referenced byllvm::SITargetLowering::EmitInstrWithCustomInserter().

◆ getWaitcntBitMask()

unsigned llvm::AMDGPU::getWaitcntBitMask(constIsaVersion & Version)
Returns
Waitcnt bit mask for given isaVersion.

Definition at line1442 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::Version.

Referenced byencodeWaitcnt().

◆ hasA16()

bool llvm::AMDGPU::hasA16(constMCSubtargetInfo & STI)

Definition at line2118 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::MCSubtargetInfo::hasFeature().

◆ hasAny64BitVGPROperands()

bool llvm::AMDGPU::hasAny64BitVGPROperands(constMCInstrDesc & OpDesc)
Returns
true if an instruction may have a 64-bit VGPR operand.

Definition at line3005 of fileAMDGPUBaseInfo.cpp.

ReferencesgetNamedOperandIdx(),llvm::MCInstrDesc::getOpcode(),Idx, andllvm::MCInstrDesc::operands().

Referenced byisDPALU_DPP().

◆ hasArchitectedFlatScratch()

bool llvm::AMDGPU::hasArchitectedFlatScratch(constMCSubtargetInfo & STI)

Definition at line2254 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::MCSubtargetInfo::hasFeature().

Referenced byllvm::AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor().

◆ hasDPPSrc1SGPR()

bool llvm::AMDGPU::hasDPPSrc1SGPR(constMCSubtargetInfo & STI)

Definition at line2266 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::MCSubtargetInfo::hasFeature().

◆ hasG16()

bool llvm::AMDGPU::hasG16(constMCSubtargetInfo & STI)

Definition at line2122 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::MCSubtargetInfo::hasFeature().

Referenced byllvm::AMDGPUDisassembler::convertMIMGInst().

◆ hasGDS()

bool llvm::AMDGPU::hasGDS(constMCSubtargetInfo & STI)

Definition at line2131 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::MCSubtargetInfo::hasFeature().

Referenced byllvm::AMDGPUDisassembler::getInstruction().

◆ hasGFX10_3Insts()

bool llvm::AMDGPU::hasGFX10_3Insts(constMCSubtargetInfo & STI)

Definition at line2238 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::MCSubtargetInfo::hasFeature().

Referenced byllvm::AMDGPU::IsaInfo::getMaxWavesPerEU(), andllvm::AMDGPU::IsaInfo::getVGPRAllocGranule().

◆ hasKernargPreload()

unsigned llvm::AMDGPU::hasKernargPreload(constMCSubtargetInfo & STI)

Definition at line2270 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::MCSubtargetInfo::hasFeature().

Referenced byllvm::AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(), andllvm::AMDGPUDisassembler::hasKernargPreload().

◆ hasMAIInsts()

bool llvm::AMDGPU::hasMAIInsts(constMCSubtargetInfo & STI)

Definition at line2258 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::MCSubtargetInfo::hasFeature().

◆ hasMIMG_R128()

bool llvm::AMDGPU::hasMIMG_R128(constMCSubtargetInfo & STI)

Definition at line2114 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::MCSubtargetInfo::hasFeature().

◆ hasNamedOperand()

LLVM_READONLYbool llvm::AMDGPU::hasNamedOperand(uint64_t Opcode,
uint64_t NamedIdx 
)
inline

Definition at line400 of fileAMDGPUBaseInfo.h.

ReferencesgetNamedOperandIdx().

Referenced byllvm::SIInstrInfo::areLoadsFromSameBasePtr(),llvm::AMDGPUDisassembler::convertDPP8Inst(),llvm::AMDGPUDisassembler::convertSDWAInst(),llvm::SIInstrInfo::convertToThreeAddress(),llvm::AMDGPUDisassembler::convertVOP3DPPInst(),llvm::AMDGPUDisassembler::convertVOP3PDPPInst(),llvm::AMDGPUDisassembler::convertVOPC64DPPInst(),llvm::AMDGPUDisassembler::convertVOPCDPPInst(),cvtVOP3DstOpSelOnly(),llvm::SIRegisterInfo::eliminateFrameIndex(),getDstSelForwardingOperand(),getFlatScratchSpillOpcode(),llvm::SIInstrInfo::getRegClass(),llvm::SIInstrInfo::hasModifiers(),llvm::AMDGPUDisassembler::isMacDPP(),isVOPD(),llvm::SIInstrInfo::moveToVALUImpl(), andllvm::SITargetLowering::PostISelFolding().

◆ hasPackedD16()

bool llvm::AMDGPU::hasPackedD16(constMCSubtargetInfo & STI)

Definition at line2126 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::MCSubtargetInfo::hasFeature(),isCI(), andisSI().

Referenced byllvm::AMDGPUDisassembler::convertMIMGInst().

◆ hasSMEMByteOffset()

staticbool llvm::AMDGPU::hasSMEMByteOffset(constMCSubtargetInfo & ST)
static

Definition at line2870 of fileAMDGPUBaseInfo.cpp.

ReferencesisGCN3Encoding(), andisGFX10Plus().

Referenced byconvertSMRDOffsetUnits(),getSMRDEncodedOffset(), andisLegalSMRDEncodedUnsignedOffset().

◆ hasSMRDSignedImmOffset()

bool llvm::AMDGPU::hasSMRDSignedImmOffset(constMCSubtargetInfo & ST)
Returns
true if the target supports signed immediate offset for SMRD instructions.

Definition at line163 of fileAMDGPUBaseInfo.cpp.

ReferencesisGFX9Plus().

Referenced bygetSMRDEncodedOffset(), andisLegalSMRDEncodedSignedOffset().

◆ hasSRAMECC()

bool llvm::AMDGPU::hasSRAMECC(constMCSubtargetInfo & STI)

Definition at line2110 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::MCSubtargetInfo::hasFeature().

◆ hasVOPD()

bool llvm::AMDGPU::hasVOPD(constMCSubtargetInfo & STI)

Definition at line2262 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::MCSubtargetInfo::hasFeature().

Referenced byllvm::AMDGPUDisassembler::decodeMandatoryLiteralConstant().

◆ hasXNACK()

bool llvm::AMDGPU::hasXNACK(constMCSubtargetInfo & STI)

Definition at line2106 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::MCSubtargetInfo::hasFeature().

◆ initDefaultAMDKernelCodeT()

void llvm::AMDGPU::initDefaultAMDKernelCodeT(AMDGPUMCKernelCodeT & KernelCode,
constMCSubtargetInfo * STI 
)

Definition at line1279 of fileAMDGPUBaseInfo.cpp.

ReferencesAMD_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32,llvm::AMDGPU::AMDGPUMCKernelCodeT::amd_kernel_code_version_major,llvm::AMDGPU::AMDGPUMCKernelCodeT::amd_kernel_code_version_minor,llvm::AMDGPU::AMDGPUMCKernelCodeT::amd_machine_kind,llvm::AMDGPU::AMDGPUMCKernelCodeT::amd_machine_version_major,llvm::AMDGPU::AMDGPUMCKernelCodeT::amd_machine_version_minor,llvm::AMDGPU::AMDGPUMCKernelCodeT::amd_machine_version_stepping,llvm::AMDGPU::AMDGPUMCKernelCodeT::call_convention,llvm::AMDGPU::AMDGPUMCKernelCodeT::code_properties,llvm::AMDGPU::AMDGPUMCKernelCodeT::compute_pgm_resource_registers,llvm::MCSubtargetInfo::getCPU(),llvm::MCSubtargetInfo::getFeatureBits(),getIsaVersion(),llvm::AMDGPU::AMDGPUMCKernelCodeT::group_segment_alignment,llvm::AMDGPU::AMDGPUMCKernelCodeT::kernarg_segment_alignment,llvm::AMDGPU::AMDGPUMCKernelCodeT::kernel_code_entry_byte_offset,llvm::AMDGPU::AMDGPUMCKernelCodeT::private_segment_alignment,S_00B848_MEM_ORDERED,S_00B848_WGP_MODE,llvm::FeatureBitset::test(),llvm::Version, andllvm::AMDGPU::AMDGPUMCKernelCodeT::wavefront_size.

Referenced byllvm::AMDGPU::AMDGPUMCKernelCodeT::initDefault().

◆ insertWaveSizeFeature()

std::pair<FeatureError,StringRef > llvm::AMDGPU::insertWaveSizeFeature(StringRef GPU,
constTriple & T,
StringMap<bool > & Features 
)

Inserts wave size feature for given GPU into features map.

Definition at line670 of fileTargetParser.cpp.

Referencesllvm::StringMap< ValueTy, AllocatorTy >::count(),llvm::StringRef::empty(),llvm::StringMap< ValueTy, AllocatorTy >::insert(),INVALID_FEATURE_COMBINATION,isWave32Capable(),NO_ERROR, andUNSUPPORTED_TARGET_FEATURE.

◆ instrumentAddress()

void llvm::AMDGPU::instrumentAddress(Module & M,
IRBuilder<> & IRB,
Instruction * OrigIns,
Instruction * InsertBefore,
Value * Addr,
Align Alignment,
TypeSize TypeStoreSize,
bool IsWrite,
Value * SizeArgument,
bool UseCalls,
bool Recover,
int Scale,
int Offset 
)

Instrument the memory operand Addr.

Generates report blocks that catch the addressing errors.

Definition at line183 of fileAMDGPUAsanInstrumentation.cpp.

ReferencesAddr,llvm::IRBuilderBase::CreateAdd(),llvm::IRBuilderBase::CreateIntToPtr(),llvm::IRBuilderBase::CreateLShr(),llvm::IRBuilderBase::CreatePtrToInt(),llvm::IRBuilderBase::CreateTypeSize(),llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getFixedValue(),instrumentAddressImpl(),llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isScalable(),llvm::IRBuilderBase::SetInsertPoint(),Size, andllvm::Align::value().

◆ instrumentAddressImpl()

static void llvm::AMDGPU::instrumentAddressImpl(Module & M,
IRBuilder<> & IRB,
Instruction * OrigIns,
Instruction * InsertBefore,
Value * Addr,
Align Alignment,
uint32_t TypeStoreSize,
bool IsWrite,
Value * SizeArgument,
bool UseCalls,
bool Recover,
int AsanScale,
int AsanOffset 
)
static

Definition at line150 of fileAMDGPUAsanInstrumentation.cpp.

ReferencesAddr,llvm::IRBuilderBase::CreateAlignedLoad(),llvm::IRBuilderBase::CreateAnd(),llvm::IRBuilderBase::CreateIntToPtr(),llvm::IRBuilderBase::CreateIsNotNull(),llvm::IRBuilderBase::CreatePtrToInt(),createSlowPathCmp(),genAMDGPUReportBlock(),generateCrashCode(),llvm::IntegerType::get(),llvm::PointerType::get(),llvm::Instruction::getDebugLoc(),llvm::Type::getPointerAddressSpace(),memToShadow(),llvm::Instruction::setDebugLoc(),llvm::IRBuilderBase::SetInsertPoint(),TypeStoreSizeToSizeIndex(), andllvm::Align::value().

Referenced byinstrumentAddress().

◆ isArgPassedInSGPR()[1/2]

bool llvm::AMDGPU::isArgPassedInSGPR(constArgument * A)

Definition at line2815 of fileAMDGPUBaseInfo.cpp.

ReferencesA,llvm::CallingConv::AMDGPU_CS,llvm::CallingConv::AMDGPU_CS_Chain,llvm::CallingConv::AMDGPU_CS_ChainPreserve,llvm::CallingConv::AMDGPU_ES,llvm::CallingConv::AMDGPU_Gfx,llvm::CallingConv::AMDGPU_GS,llvm::CallingConv::AMDGPU_HS,llvm::CallingConv::AMDGPU_KERNEL,llvm::CallingConv::AMDGPU_LS,llvm::CallingConv::AMDGPU_PS,llvm::CallingConv::AMDGPU_VS,CC,F, andllvm::CallingConv::SPIR_KERNEL.

Referenced byadjustInliningThresholdUsingCallee(),llvm::GCNTTIImpl::isSourceOfDivergence(), andllvm::AMDGPUInstrInfo::isUniformMMO().

◆ isArgPassedInSGPR()[2/2]

bool llvm::AMDGPU::isArgPassedInSGPR(constCallBase * CB,
unsigned ArgNo 
)

Definition at line2844 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::CallingConv::AMDGPU_CS,llvm::CallingConv::AMDGPU_CS_Chain,llvm::CallingConv::AMDGPU_CS_ChainPreserve,llvm::CallingConv::AMDGPU_ES,llvm::CallingConv::AMDGPU_Gfx,llvm::CallingConv::AMDGPU_GS,llvm::CallingConv::AMDGPU_HS,llvm::CallingConv::AMDGPU_KERNEL,llvm::CallingConv::AMDGPU_LS,llvm::CallingConv::AMDGPU_PS,llvm::CallingConv::AMDGPU_VS,CC,llvm::CallBase::getCallingConv(),llvm::CallBase::paramHasAttr(), andllvm::CallingConv::SPIR_KERNEL.

◆ isChainCC()

LLVM_READNONEbool llvm::AMDGPU::isChainCC(CallingConv::ID CC)

Definition at line2092 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::CallingConv::AMDGPU_CS_Chain,llvm::CallingConv::AMDGPU_CS_ChainPreserve, andCC.

Referenced bygetCallOpcode(),llvm::AMDGPUCallLowering::handleImplicitCallArguments(),llvm::SITargetLowering::isEligibleForTailCallOptimization(),isModuleEntryFunctionCC(),llvm::SITargetLowering::LowerCall(),llvm::AMDGPUCallLowering::lowerTailCall(), andllvm::SIMachineFunctionInfo::SIMachineFunctionInfo().

◆ isCI()

bool llvm::AMDGPU::isCI(constMCSubtargetInfo & STI)

Definition at line2152 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::MCSubtargetInfo::hasFeature().

Referenced byllvm::AMDGPU::MTBUFFormat::getNfmtLookupTable(),getSMRDEncodedLiteralOffset32(),hasPackedD16(), andisNotGFX10Plus().

◆ isClobberedInFunction()

bool llvm::AMDGPU::isClobberedInFunction(constLoadInst * Load,
MemorySSA * MSSA,
AAResults * AA 
)

Check is aLoad is clobbered in its function.

Definition at line389 of fileAMDGPUMemoryUtils.cpp.

Referencesllvm::dbgs(),llvm::MemoryLocation::get(),llvm::MemorySSAWalker::getClobberingMemoryAccess(),llvm::MemorySSA::getWalker(),llvm::SmallSet< T, N, C >::insert(),llvm::MemorySSA::isLiveOnEntryDef(),isReallyAClobber(), andLLVM_DEBUG.

◆ isCompute()

LLVM_READNONEbool llvm::AMDGPU::isCompute(CallingConv::ID cc)

Definition at line2062 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::CallingConv::AMDGPU_CS, andisGraphics().

Referenced byEmitPALMetadataCommon(),llvm::SIProgramInfo::getPGMRSrc1(),llvm::SIProgramInfo::getPGMRSrc2(),llvm::AMDGPULegalizerInfo::loadInputValue(),llvm::R600InstrInfo::usesTextureCache(), andllvm::R600InstrInfo::usesVertexCache().

◆ isConstantAddressSpace()

bool llvm::AMDGPU::isConstantAddressSpace(unsigned AS)
inline

Definition at line97 of fileAMDGPUAddrSpace.h.

◆ isCvt_F32_Fp8_Bf8_e64()

LLVM_READNONEbool llvm::AMDGPU::isCvt_F32_Fp8_Bf8_e64(unsigned Opc)

Definition at line621 of fileAMDGPUBaseInfo.cpp.

◆ isDPALU_DPP()

bool llvm::AMDGPU::isDPALU_DPP(constMCInstrDesc & OpDesc)
Returns
true if an instruction is a DP ALUDPP.

Definition at line3020 of fileAMDGPUBaseInfo.cpp.

ReferenceshasAny64BitVGPROperands().

Referenced byllvm::SIInstrInfo::verifyInstruction().

◆ isDPMACCInstruction()

bool llvm::AMDGPU::isDPMACCInstruction(unsigned Opc)

◆ isDwordAligned()

staticbool llvm::AMDGPU::isDwordAligned(uint64_t ByteOffset)
static

Definition at line2894 of fileAMDGPUBaseInfo.cpp.

Referenced byconvertSMRDOffsetUnits(),getSMRDEncodedLiteralOffset32(), andgetSMRDEncodedOffset().

◆ isDynamicLDS()

bool llvm::AMDGPU::isDynamicLDS(constGlobalVariable & GV)

Definition at line56 of fileAMDGPUMemoryUtils.cpp.

ReferencesDL,llvm::GlobalValue::getParent(),llvm::Type::getPointerAddressSpace(),llvm::GlobalValue::getType(),llvm::GlobalValue::getValueType(), andllvm::AMDGPUAS::LOCAL_ADDRESS.

Referenced bygetTransitiveUsesOfLDS(), andisLDSVariableToLower().

◆ isEntryFunctionCC()

LLVM_READNONEbool llvm::AMDGPU::isEntryFunctionCC(CallingConv::ID CC)

Definition at line2066 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::CallingConv::AMDGPU_CS,llvm::CallingConv::AMDGPU_ES,llvm::CallingConv::AMDGPU_GS,llvm::CallingConv::AMDGPU_HS,llvm::CallingConv::AMDGPU_KERNEL,llvm::CallingConv::AMDGPU_LS,llvm::CallingConv::AMDGPU_PS,llvm::CallingConv::AMDGPU_VS,CC, andllvm::CallingConv::SPIR_KERNEL.

Referenced byllvm::SITargetLowering::CanLowerReturn(),llvm::MCResourceInfo::gatherResourceInfo(),llvm::GCNUserSGPRUsageInfo::GCNUserSGPRUsageInfo(),INITIALIZE_PASS(),isModuleEntryFunctionCC(),llvm::AMDGPULegalizerInfo::loadInputValue(),llvm::AMDGPUCallLowering::lowerFormalArguments(),llvm::SITargetLowering::LowerFormalArguments(),llvm::SITargetLowering::mayBeEmittedAsTailCall(),mustPreserveGV(),recursivelyVisitUsers(), andllvm::SIMachineFunctionInfo::usesAGPRs().

◆ isExtendedGlobalAddrSpace()

bool llvm::AMDGPU::isExtendedGlobalAddrSpace(unsigned AS)
inline

Definition at line91 of fileAMDGPUAddrSpace.h.

Referencesllvm::AMDGPUAS::CONSTANT_ADDRESS,llvm::AMDGPUAS::CONSTANT_ADDRESS_32BIT,llvm::AMDGPUAS::GLOBAL_ADDRESS, andllvm::AMDGPUAS::MAX_AMDGPU_ADDRESS.

Referenced byllvm::SITargetLowering::allowsMisalignedMemoryAccessesImpl(),llvm::AMDGPURegisterBankInfo::applyMappingLoad(),llvm::GCNTTIImpl::isValidAddrSpaceCast(),llvm::GCNTTIImpl::rewriteIntrinsicWithAddressSpace(), andllvm::SITargetLowering::shouldExpandAtomicRMWInIR().

◆ isFlatGlobalAddrSpace()

bool llvm::AMDGPU::isFlatGlobalAddrSpace(unsigned AS)
inline

Definition at line86 of fileAMDGPUAddrSpace.h.

Referencesllvm::AMDGPUAS::CONSTANT_ADDRESS,llvm::AMDGPUAS::FLAT_ADDRESS,llvm::AMDGPUAS::GLOBAL_ADDRESS, andllvm::AMDGPUAS::MAX_AMDGPU_ADDRESS.

Referenced byllvm::AMDGPURegisterBankInfo::applyMappingImpl(),llvm::AMDGPURegisterBankInfo::getInstrMappingForLoad(),llvm::AMDGPURegisterBankInfo::getValueMappingForPtr(),llvm::AMDGPUTargetMachine::isNoopAddrSpaceCast(),llvm::GCNTTIImpl::isValidAddrSpaceCast(),llvm::AMDGPULegalizerInfo::legalizeAtomicCmpXChg(),llvm::SITargetLowering::shouldExpandAtomicRMWInIR(), andllvm::GCNTTIImpl::shouldPrefetchAddressSpace().

◆ isGCN3Encoding()

bool llvm::AMDGPU::isGCN3Encoding(constMCSubtargetInfo & STI)

Definition at line2226 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::MCSubtargetInfo::hasFeature().

Referenced byhasSMEMByteOffset().

◆ isGenericAtomic()

LLVM_READNONEbool llvm::AMDGPU::isGenericAtomic(unsigned Opc)

Definition at line634 of fileAMDGPUBaseInfo.cpp.

Referenced byllvm::SIInstrInfo::getGenericInstructionUniformity().

◆ isGFX10()

bool llvm::AMDGPU::isGFX10(constMCSubtargetInfo & STI)

Definition at line2186 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::MCSubtargetInfo::hasFeature().

Referenced bygetGcnBufferFormatInfo(),getNumFlatOffsetBits(),llvm::AMDGPU::MTBUFFormat::getUnifiedFormatName(),llvm::AMDGPUDisassembler::isGFX10(),isGFX10_GFX11(),isGFX10Before1030(),isGFX10Plus(),isGFX8_GFX9_GFX10(),isGFX9_GFX10(),isGFX9_GFX10_GFX11(), andllvm::AMDGPU::MTBUFFormat::isValidUnifiedFormat().

◆ isGFX10_3_GFX11()

bool llvm::AMDGPU::isGFX10_3_GFX11(constMCSubtargetInfo & STI)

Definition at line2242 of fileAMDGPUBaseInfo.cpp.

ReferencesisGFX10_BEncoding(), andisGFX12Plus().

◆ isGFX10_AEncoding()

bool llvm::AMDGPU::isGFX10_AEncoding(constMCSubtargetInfo & STI)

Definition at line2230 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::MCSubtargetInfo::hasFeature().

◆ isGFX10_BEncoding()

bool llvm::AMDGPU::isGFX10_BEncoding(constMCSubtargetInfo & STI)

Definition at line2234 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::MCSubtargetInfo::hasFeature().

Referenced byisGFX10_3_GFX11(), andisGFX10Before1030().

◆ isGFX10_GFX11()

bool llvm::AMDGPU::isGFX10_GFX11(constMCSubtargetInfo & STI)

Definition at line2190 of fileAMDGPUBaseInfo.cpp.

ReferencesisGFX10(), andisGFX11().

◆ isGFX10Before1030()

bool llvm::AMDGPU::isGFX10Before1030(constMCSubtargetInfo & STI)

Definition at line2222 of fileAMDGPUBaseInfo.cpp.

ReferencesisGFX10(), andisGFX10_BEncoding().

◆ isGFX10Plus()

bool llvm::AMDGPU::isGFX10Plus(constMCSubtargetInfo & STI)

Definition at line2194 of fileAMDGPUBaseInfo.cpp.

ReferencesisGFX10(), andisGFX11Plus().

Referenced bycreateAMDGPUMCSubtargetInfo(),llvm::AMDGPUAsmPrinter::doFinalization(),generateEndPgm(),llvm::AMDGPU::MTBUFFormat::getDefaultFormatEncoding(),llvm::AMDGPU::IsaInfo::getEUsPerCU(),llvm::AMDGPU::IsaInfo::getLocalMemorySize(),llvm::AMDGPU::IsaInfo::getMaxWavesPerEU(),llvm::AMDGPU::IsaInfo::getMaxWorkGroupsPerCU(),llvm::AMDGPU::IsaInfo::getTotalNumVGPRs(),hasSMEMByteOffset(),llvm::GCNSubtarget::initializeSubtargetDependencies(),llvm::AMDGPUDisassembler::isGFX10Plus(),isGFX9Plus(),llvm::AMDGPU::Exp::isSupportedTgtId(),llvm::AMDGPU::MTBUFFormat::isValidFormatEncoding(), andllvm::AMDGPU::AMDGPUMCKernelCodeT::validate().

◆ isGFX11()

bool llvm::AMDGPU::isGFX11(constMCSubtargetInfo & STI)

Definition at line2198 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::MCSubtargetInfo::hasFeature().

Referenced byisGFX10_GFX11(),isGFX11Plus(),isGFX9_GFX10_GFX11(), andllvm::AMDGPULegalizerInfo::legalizeBVHIntrinsic().

◆ isGFX11Plus()

bool llvm::AMDGPU::isGFX11Plus(constMCSubtargetInfo & STI)

Definition at line2202 of fileAMDGPUBaseInfo.cpp.

ReferencesisGFX11(), andisGFX12Plus().

Referenced byllvm::AMDGPU::MTBUFFormat::convertDfmtNfmt2Ufmt(),llvm::AMDGPU::SendMsg::decodeMsg(),llvm::AMDGPUTargetAsmStreamer::EmitCodeEnd(),llvm::AMDGPUTargetELFStreamer::EmitCodeEnd(),getGcnBufferFormatInfo(),llvm::AMDGPU::SendMsg::getMsgIdMask(),llvm::AMDGPU::MTBUFFormat::getUnifiedFormat(),imageIntrinsicOptimizerImpl(),isGFX10Plus(),llvm::AMDGPUDisassembler::isGFX11Plus(),isNotGFX11Plus(),llvm::AMDGPU::Exp::isSupportedTgtId(),llvm::AMDGPU::SendMsg::isValidMsgStream(),llvm::AMDGPULegalizerInfo::legalizeBVHIntrinsic(),llvm::AMDGPU::SendMsg::msgRequiresOp(), andllvm::AMDGPU::SendMsg::msgSupportsStream().

◆ isGFX12()

bool llvm::AMDGPU::isGFX12(constMCSubtargetInfo & STI)

Definition at line2206 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::MCSubtargetInfo::getFeatureBits().

Referenced bygetNumFlatOffsetBits(), andisGFX12Plus().

◆ isGFX12Plus()

bool llvm::AMDGPU::isGFX12Plus(constMCSubtargetInfo & STI)

Definition at line2210 of fileAMDGPUBaseInfo.cpp.

ReferencesisGFX12().

Referenced byllvm::SIInstrInfo::allowNegativeFlatOffset(),getSMRDEncodedOffset(),isGFX10_3_GFX11(),isGFX11Plus(),llvm::AMDGPUDisassembler::isGFX12Plus(),isLegalSMRDEncodedSignedOffset(),isLegalSMRDEncodedUnsignedOffset(),isNotGFX12Plus(),llvm::AMDGPULegalizerInfo::legalizeBVHIntrinsic(), andllvm::AMDGPU::AMDGPUMCKernelCodeT::validate().

◆ isGFX8_GFX9_GFX10()

bool llvm::AMDGPU::isGFX8_GFX9_GFX10(constMCSubtargetInfo & STI)

Definition at line2172 of fileAMDGPUBaseInfo.cpp.

ReferencesisGFX10(),isGFX9(), andisVI().

◆ isGFX8Plus()

bool llvm::AMDGPU::isGFX8Plus(constMCSubtargetInfo & STI)

Definition at line2176 of fileAMDGPUBaseInfo.cpp.

ReferencesisGFX9Plus(), andisVI().

◆ isGFX9()

bool llvm::AMDGPU::isGFX9(constMCSubtargetInfo & STI)

Definition at line2160 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::MCSubtargetInfo::hasFeature().

Referenced byllvm::AMDGPU::MTBUFFormat::getNfmtLookupTable(),isGFX8_GFX9_GFX10(),llvm::AMDGPUDisassembler::isGFX9(),isGFX9_GFX10(),isGFX9_GFX10_GFX11(),isGFX9Plus(), andisNotGFX10Plus().

◆ isGFX90A()

bool llvm::AMDGPU::isGFX90A(constMCSubtargetInfo & STI)

Definition at line2246 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::MCSubtargetInfo::hasFeature().

Referenced byllvm::AMDGPUAsmPrinter::doFinalization(),llvm::AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(),llvm::AMDGPUTargetAsmStreamer::EmitCodeEnd(),llvm::AMDGPUTargetELFStreamer::EmitCodeEnd(),llvm::AMDGPU::MCKernelDescriptor::getDefaultAmdhsaKernelDescriptor(), andllvm::AMDGPU::IsaInfo::getMaxWavesPerEU().

◆ isGFX940()

bool llvm::AMDGPU::isGFX940(constMCSubtargetInfo & STI)

Definition at line2250 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::MCSubtargetInfo::hasFeature().

◆ isGFX9_GFX10()

bool llvm::AMDGPU::isGFX9_GFX10(constMCSubtargetInfo & STI)

Definition at line2164 of fileAMDGPUBaseInfo.cpp.

ReferencesisGFX10(), andisGFX9().

◆ isGFX9_GFX10_GFX11()

bool llvm::AMDGPU::isGFX9_GFX10_GFX11(constMCSubtargetInfo & STI)

Definition at line2168 of fileAMDGPUBaseInfo.cpp.

ReferencesisGFX10(),isGFX11(), andisGFX9().

◆ isGFX9Plus()

bool llvm::AMDGPU::isGFX9Plus(constMCSubtargetInfo & STI)

Definition at line2180 of fileAMDGPUBaseInfo.cpp.

ReferencesisGFX10Plus(), andisGFX9().

Referenced byhasSMRDSignedImmOffset(),isGFX8Plus(),llvm::AMDGPUDisassembler::isGFX9Plus(),isNotGFX9Plus(), andllvm::AMDGPUInstPrinter::printSwizzle().

◆ isGlobalSegment()

bool llvm::AMDGPU::isGlobalSegment(constGlobalValue * GV)

Definition at line1317 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::GlobalValue::getAddressSpace(), andllvm::AMDGPUAS::GLOBAL_ADDRESS.

◆ isGraphics()

LLVM_READNONEbool llvm::AMDGPU::isGraphics(CallingConv::ID cc)

Definition at line2058 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::CallingConv::AMDGPU_Gfx, andisShader().

Referenced byllvm::GCNUserSGPRUsageInfo::GCNUserSGPRUsageInfo(),isCompute(),llvm::SIInstrInfo::legalizeOperands(),llvm::AMDGPUCallLowering::lowerFormalArguments(),llvm::SITargetLowering::LowerFormalArguments(), andllvm::SIMachineFunctionInfo::SIMachineFunctionInfo().

◆ isGroupSegment()

bool llvm::AMDGPU::isGroupSegment(constGlobalValue * GV)

Definition at line1313 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::GlobalValue::getAddressSpace(), andllvm::AMDGPUAS::LOCAL_ADDRESS.

◆ isHi16Reg()

bool llvm::AMDGPU::isHi16Reg(MCRegister Reg,
constMCRegisterInfo & MRI 
)
Returns
ifReg occupies the high 16-bits of a 32-bit register.

Definition at line2288 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::AMDGPU::HWEncoding::IS_HI16,MRI, andReg.

Referenced byllvm::SIInstrInfo::copyPhysReg(),cvtVOP3DstOpSelOnly(), andllvm::SIRegisterInfo::SIRegisterInfo().

◆ isHsaAbi()

bool llvm::AMDGPU::isHsaAbi(constMCSubtargetInfo & STI)
Returns
True ifSTI is AMDHSA.

Definition at line168 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::Triple::AMDHSA,llvm::Triple::getOS(), andllvm::MCSubtargetInfo::getTargetTriple().

◆ isInlinableIntLiteral()

LLVM_READNONEbool llvm::AMDGPU::isInlinableIntLiteral(int64_t Literal)
inline

Is this literal inlinable, and not one of the values intended for floating point values.

Definition at line1458 of fileAMDGPUBaseInfo.h.

Referencesllvm::Literal.

Referenced byllvm::SITargetLowering::checkAsmConstraintVal(),clearUnusedBits(),llvm::SIRegisterInfo::eliminateFrameIndex(),llvm::SIRegisterInfo::isFrameOffsetLegal(),isInlinableLiteral32(),isInlinableLiteral64(),isInlinableLiteralBF16(),isInlinableLiteralFP16(),llvm::SIInstrInfo::isInlineConstant(), andllvm::AMDGPUAsmPrinter::PrintAsmOperand().

◆ isInlinableLiteral32()

LLVM_READNONEbool llvm::AMDGPU::isInlinableLiteral32(int32_t Literal,
bool HasInv2Pi 
)

Definition at line2616 of fileAMDGPUBaseInfo.cpp.

ReferencesisInlinableIntLiteral(), andllvm::Literal.

Referenced byllvm::SITargetLowering::checkAsmConstraintValA(),llvm::SIRegisterInfo::eliminateFrameIndex(),isInlinableLiteralI16(),isInlineableLiteralOp16(), andllvm::SIInstrInfo::isInlineConstant().

◆ isInlinableLiteral64()

LLVM_READNONEbool llvm::AMDGPU::isInlinableLiteral64(int64_t Literal,
bool HasInv2Pi 
)

Is this literal inlinable.

Definition at line2599 of fileAMDGPUBaseInfo.cpp.

ReferencesisInlinableIntLiteral(), andllvm::Literal.

Referenced byllvm::SITargetLowering::checkAsmConstraintValA(),llvm::SIInstrInfo::isInlineConstant(), andllvm::SIInstrInfo::isOperandLegal().

◆ isInlinableLiteralBF16()

LLVM_READNONEbool llvm::AMDGPU::isInlinableLiteralBF16(int16_t Literal,
bool HasInv2Pi 
)

Definition at line2642 of fileAMDGPUBaseInfo.cpp.

ReferencesisInlinableIntLiteral(), andllvm::Literal.

Referenced byllvm::SITargetLowering::checkAsmConstraintValA(),isInlineableLiteralOp16(), andllvm::SIInstrInfo::isInlineConstant().

◆ isInlinableLiteralFP16()

LLVM_READNONEbool llvm::AMDGPU::isInlinableLiteralFP16(int16_t Literal,
bool HasInv2Pi 
)

Definition at line2663 of fileAMDGPUBaseInfo.cpp.

ReferencesisInlinableIntLiteral(), andllvm::Literal.

Referenced byllvm::SITargetLowering::checkAsmConstraintValA(),isInlineableLiteralOp16(), andllvm::SIInstrInfo::isInlineConstant().

◆ isInlinableLiteralI16()

LLVM_READNONEbool llvm::AMDGPU::isInlinableLiteralI16(int32_t Literal,
bool HasInv2Pi 
)

Definition at line2659 of fileAMDGPUBaseInfo.cpp.

ReferencesisInlinableLiteral32(), andllvm::Literal.

Referenced byllvm::SITargetLowering::checkAsmConstraintValA(), andllvm::SIInstrInfo::isInlineConstant().

◆ isInlinableLiteralV216()

LLVM_READNONEbool llvm::AMDGPU::isInlinableLiteralV216(uint32_t Literal,
uint8_t OpType 
)

Definition at line2774 of fileAMDGPUBaseInfo.cpp.

ReferencesgetInlineEncodingV216(),isInlinableLiteralV2BF16(),llvm::Literal,llvm_unreachable,OPERAND_REG_IMM_V2BF16,OPERAND_REG_IMM_V2FP16,OPERAND_REG_IMM_V2INT16,OPERAND_REG_INLINE_AC_V2BF16,OPERAND_REG_INLINE_AC_V2FP16,OPERAND_REG_INLINE_AC_V2INT16,OPERAND_REG_INLINE_C_V2BF16,OPERAND_REG_INLINE_C_V2FP16, andOPERAND_REG_INLINE_C_V2INT16.

◆ isInlinableLiteralV2BF16()

LLVM_READNONEbool llvm::AMDGPU::isInlinableLiteralV2BF16(uint32_t Literal)

Definition at line2799 of fileAMDGPUBaseInfo.cpp.

ReferencesgetInlineEncodingV2BF16(), andllvm::Literal.

Referenced byisInlinableLiteralV216(), andllvm::SIInstrInfo::isInlineConstant().

◆ isInlinableLiteralV2F16()

LLVM_READNONEbool llvm::AMDGPU::isInlinableLiteralV2F16(uint32_t Literal)

Definition at line2804 of fileAMDGPUBaseInfo.cpp.

ReferencesgetInlineEncodingV2F16(), andllvm::Literal.

Referenced byllvm::SIInstrInfo::isInlineConstant().

◆ isInlinableLiteralV2I16()

LLVM_READNONEbool llvm::AMDGPU::isInlinableLiteralV2I16(uint32_t Literal)

Definition at line2794 of fileAMDGPUBaseInfo.cpp.

ReferencesgetInlineEncodingV2I16(), andllvm::Literal.

Referenced byllvm::SIInstrInfo::isInlineConstant().

◆ isInlineValue()

LLVM_READNONEbool llvm::AMDGPU::isInlineValue(unsigned Reg)

Definition at line2367 of fileAMDGPUBaseInfo.cpp.

ReferencesReg.

◆ isIntrinsicAlwaysUniform()

bool llvm::AMDGPU::isIntrinsicAlwaysUniform(unsigned IntrID)
Returns
true if the intrinsic is uniform

Definition at line2981 of fileAMDGPUBaseInfo.cpp.

Referenced byllvm::SIInstrInfo::getGenericInstructionUniformity(),llvm::GCNTTIImpl::isAlwaysUniform(),llvm::AMDGPUTargetLowering::isSDNodeAlwaysUniform(), andisTriviallyUniform().

◆ isIntrinsicSourceOfDivergence()

bool llvm::AMDGPU::isIntrinsicSourceOfDivergence(unsigned IntrID)
Returns
true if the intrinsic is divergent

Definition at line2977 of fileAMDGPUBaseInfo.cpp.

Referenced byllvm::SIInstrInfo::getGenericInstructionUniformity(),llvm::SITargetLowering::isSDNodeSourceOfDivergence(), andllvm::GCNTTIImpl::isSourceOfDivergence().

◆ isInvalidSingleUseConsumerInst()

LLVM_READONLYbool llvm::AMDGPU::isInvalidSingleUseConsumerInst(unsigned Opc)

◆ isInvalidSingleUseProducerInst()

LLVM_READONLYbool llvm::AMDGPU::isInvalidSingleUseProducerInst(unsigned Opc)

◆ isKernel()

LLVM_READNONEbool llvm::AMDGPU::isKernel(CallingConv::ID CC)
inline

Definition at line1301 of fileAMDGPUBaseInfo.h.

Referencesllvm::CallingConv::AMDGPU_KERNEL,CC, andllvm::CallingConv::SPIR_KERNEL.

Referenced byllvm::AMDGPUSubtarget::getImplicitArgNumBytes(),isKernelLDS(),llvm::AMDGPULegalizerInfo::legalizeIntrinsic(),llvm::SITargetLowering::LowerFormalArguments(),llvm::AMDGPUCallLowering::lowerReturn(), andllvm::SITargetLowering::LowerReturn().

◆ isKernelCC()

bool llvm::AMDGPU::isKernelCC(constFunction * Func)

Definition at line2102 of fileAMDGPUBaseInfo.cpp.

ReferencesisModuleEntryFunctionCC().

◆ isKernelLDS()

bool llvm::AMDGPU::isKernelLDS(constFunction * F)

Definition at line127 of fileAMDGPUMemoryUtils.cpp.

ReferencesF, andisKernel().

Referenced bygetTransitiveUsesOfLDS(),getUsesOfLDSByFunction(), andremoveFnAttrFromReachable().

◆ isKImmOperand()

bool llvm::AMDGPU::isKImmOperand(constMCInstrDesc & Desc,
unsigned OpNo 
)

Is this a KImm operand?

Definition at line2403 of fileAMDGPUBaseInfo.cpp.

Referencesassert(),OPERAND_KIMM_FIRST, andOPERAND_KIMM_LAST.

◆ isLDSVariableToLower()

bool llvm::AMDGPU::isLDSVariableToLower(constGlobalVariable & GV)

Definition at line65 of fileAMDGPUMemoryUtils.cpp.

Referencesllvm::GlobalVariable::getInitializer(),llvm::Type::getPointerAddressSpace(),llvm::GlobalValue::getType(),llvm::GlobalVariable::hasInitializer(),llvm::GlobalVariable::isConstant(),isDynamicLDS(), andllvm::AMDGPUAS::LOCAL_ADDRESS.

Referenced byeliminateConstantExprUsesOfLDSFromAllInstructions(), andgetUsesOfLDSByFunction().

◆ isLegalDPALU_DPPControl()

LLVM_READNONEbool llvm::AMDGPU::isLegalDPALU_DPPControl(unsigned DC)
inline

Definition at line1549 of fileAMDGPUBaseInfo.h.

Referencesllvm::AMDGPU::DPP::ROW_NEWBCAST_FIRST, andllvm::AMDGPU::DPP::ROW_NEWBCAST_LAST.

Referenced byllvm::SIInstrInfo::expandMovDPP64(),llvm::AMDGPULegalizerInfo::legalizeLaneOp(),lowerLaneOp(), andllvm::SIInstrInfo::verifyInstruction().

◆ isLegalSMRDEncodedSignedOffset()

LLVM_READONLYbool llvm::AMDGPU::isLegalSMRDEncodedSignedOffset(constMCSubtargetInfo & ST,
int64_t EncodedOffset,
bool IsBuffer 
)

Definition at line2883 of fileAMDGPUBaseInfo.cpp.

ReferenceshasSMRDSignedImmOffset(), andisGFX12Plus().

◆ isLegalSMRDEncodedUnsignedOffset()

LLVM_READONLYbool llvm::AMDGPU::isLegalSMRDEncodedUnsignedOffset(constMCSubtargetInfo & ST,
int64_t EncodedOffset 
)

Definition at line2874 of fileAMDGPUBaseInfo.cpp.

ReferenceshasSMEMByteOffset(), andisGFX12Plus().

Referenced bygetSMRDEncodedOffset().

◆ isLegalSMRDImmOffset()

bool llvm::AMDGPU::isLegalSMRDImmOffset(constMCSubtargetInfo & ST,
int64_t ByteOffset 
)
Returns
true if this offset is small enough to fit in the SMRD offset field.ByteOffset should be the offset in bytes and not the encoded offset.

◆ isMAC()

LLVM_READNONEbool llvm::AMDGPU::isMAC(unsigned Opc)

Definition at line586 of fileAMDGPUBaseInfo.cpp.

Referenced byllvm::AMDGPUDisassembler::getInstruction().

◆ isModuleEntryFunctionCC()

LLVM_READNONEbool llvm::AMDGPU::isModuleEntryFunctionCC(CallingConv::ID CC)

Definition at line2083 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::CallingConv::AMDGPU_Gfx,CC,isChainCC(), andisEntryFunctionCC().

Referenced byisKernelCC().

◆ isNamedBarrier()

TargetExtType * llvm::AMDGPU::isNamedBarrier(constGlobalVariable & GV)

Definition at line34 of fileAMDGPUMemoryUtils.cpp.

Referencesllvm::GlobalValue::getValueType().

Referenced byllvm::AMDGPUMachineFunction::allocateLDSGlobal(),getTransitiveUsesOfLDS(),llvm::AMDGPULegalizerInfo::legalizeGlobalValue(), andllvm::AMDGPUTargetLowering::LowerGlobalAddress().

◆ isNotGFX10Plus()

bool llvm::AMDGPU::isNotGFX10Plus(constMCSubtargetInfo & STI)

Definition at line2218 of fileAMDGPUBaseInfo.cpp.

ReferencesisCI(),isGFX9(),isSI(), andisVI().

◆ isNotGFX11Plus()

bool llvm::AMDGPU::isNotGFX11Plus(constMCSubtargetInfo & STI)

Definition at line2214 of fileAMDGPUBaseInfo.cpp.

ReferencesisGFX11Plus().

◆ isNotGFX12Plus()

bool llvm::AMDGPU::isNotGFX12Plus(constMCSubtargetInfo & STI)

Definition at line2212 of fileAMDGPUBaseInfo.cpp.

ReferencesisGFX12Plus().

◆ isNotGFX9Plus()

bool llvm::AMDGPU::isNotGFX9Plus(constMCSubtargetInfo & STI)

Definition at line2184 of fileAMDGPUBaseInfo.cpp.

ReferencesisGFX9Plus().

◆ isPermlane16()

LLVM_READNONEbool llvm::AMDGPU::isPermlane16(unsigned Opc)

Definition at line610 of fileAMDGPUBaseInfo.cpp.

◆ isReadOnlySegment()

bool llvm::AMDGPU::isReadOnlySegment(constGlobalValue * GV)

Definition at line1321 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::AMDGPUAS::CONSTANT_ADDRESS,llvm::AMDGPUAS::CONSTANT_ADDRESS_32BIT, andllvm::GlobalValue::getAddressSpace().

Referenced byllvm::AMDGPUTargetObjectFile::SelectSectionForGlobal().

◆ isReallyAClobber()

bool llvm::AMDGPU::isReallyAClobber(constValue * Ptr,
MemoryDef * Def,
AAResults * AA 
)

Given aDef clobbering a load fromPtr according to the MSSA check if this is actually a memory update or an artificial clobber to facilitate ordering constraints.

Definition at line350 of fileAMDGPUMemoryUtils.cpp.

ReferencesI,II,llvm::AAResults::isNoAlias(), andPtr.

Referenced byisClobberedInFunction().

◆ isSGPR()

bool llvm::AMDGPU::isSGPR(MCRegister Reg,
constMCRegisterInfo * TRI 
)

Is Reg - scalar register.

Definition at line2281 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::MCRegisterClass::contains(),Reg, andTRI.

◆ isShader()

LLVM_READNONEbool llvm::AMDGPU::isShader(CallingConv::ID cc)

Definition at line2041 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::CallingConv::AMDGPU_CS,llvm::CallingConv::AMDGPU_CS_Chain,llvm::CallingConv::AMDGPU_CS_ChainPreserve,llvm::CallingConv::AMDGPU_ES,llvm::CallingConv::AMDGPU_GS,llvm::CallingConv::AMDGPU_HS,llvm::CallingConv::AMDGPU_LS,llvm::CallingConv::AMDGPU_PS, andllvm::CallingConv::AMDGPU_VS.

Referenced byllvm::SIModeRegisterDefaults::getDefaultForCallingConv(),isGraphics(),llvm::GCNSubtarget::isMesaGfxShader(),llvm::AMDGPUSubtarget::isMesaKernel(),llvm::R600TargetLowering::LowerFormalArguments(),llvm::AMDGPUCallLowering::lowerReturn(),llvm::SITargetLowering::LowerReturn(), andreservePrivateMemoryRegs().

◆ isSI()

bool llvm::AMDGPU::isSI(constMCSubtargetInfo & STI)

Definition at line2148 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::MCSubtargetInfo::hasFeature().

Referenced byllvm::AMDGPU::MTBUFFormat::getNfmtLookupTable(),hasPackedD16(), andisNotGFX10Plus().

◆ isSISrcFPOperand()

bool llvm::AMDGPU::isSISrcFPOperand(constMCInstrDesc & Desc,
unsigned OpNo 
)

Is this floating-point operand?

Definition at line2410 of fileAMDGPUBaseInfo.cpp.

Referencesassert(),OPERAND_REG_IMM_FP16,OPERAND_REG_IMM_FP16_DEFERRED,OPERAND_REG_IMM_FP32,OPERAND_REG_IMM_FP32_DEFERRED,OPERAND_REG_IMM_FP64,OPERAND_REG_IMM_V2FP16,OPERAND_REG_IMM_V2FP32,OPERAND_REG_INLINE_AC_FP16,OPERAND_REG_INLINE_AC_FP32,OPERAND_REG_INLINE_AC_FP64,OPERAND_REG_INLINE_AC_V2FP16,OPERAND_REG_INLINE_C_FP16,OPERAND_REG_INLINE_C_FP32,OPERAND_REG_INLINE_C_FP64,OPERAND_REG_INLINE_C_V2FP16, andOPERAND_REG_INLINE_C_V2FP32.

◆ isSISrcInlinableOperand()

bool llvm::AMDGPU::isSISrcInlinableOperand(constMCInstrDesc & Desc,
unsigned OpNo 
)

Does this operand support only inlinable literals?

Definition at line2436 of fileAMDGPUBaseInfo.cpp.

Referencesassert(),OPERAND_REG_INLINE_AC_FIRST,OPERAND_REG_INLINE_AC_LAST,OPERAND_REG_INLINE_C_FIRST, andOPERAND_REG_INLINE_C_LAST.

◆ isSISrcOperand()

bool llvm::AMDGPU::isSISrcOperand(constMCInstrDesc & Desc,
unsigned OpNo 
)

Is this anAMDGPU specific source operand? These include registers, inline constants, literals and mandatory literals (KImm).

Definition at line2396 of fileAMDGPUBaseInfo.cpp.

Referencesassert(),OPERAND_SRC_FIRST, andOPERAND_SRC_LAST.

Referenced byllvm::SIInstrInfo::isImmOperandLegal(), andllvm::SIInstrInfo::isOperandLegal().

◆ isSymbolicCustomOperandEncoding()

staticbool llvm::AMDGPU::isSymbolicCustomOperandEncoding(constCustomOperandVal * Opr,
int Size,
unsigned Code,
bool & HasNonDefaultVal,
constMCSubtargetInfo & STI 
)
static

Definition at line1614 of fileAMDGPUBaseInfo.cpp.

ReferencesIdx, andSize.

Referenced byllvm::AMDGPU::DepCtr::isSymbolicDepCtrEncoding().

◆ isTrue16Inst()

LLVM_READONLYbool llvm::AMDGPU::isTrue16Inst(unsigned Opc)

Definition at line654 of fileAMDGPUBaseInfo.cpp.

ReferencesInfo.

Referenced byllvm::SIInstrInfo::moveToVALUImpl().

◆ isValid32BitLiteral()

LLVM_READNONEbool llvm::AMDGPU::isValid32BitLiteral(uint64_t Val,
bool IsFP64 
)

Definition at line2808 of fileAMDGPUBaseInfo.cpp.

Referenced byllvm::SIInstrInfo::isOperandLegal(), andllvm::AMDGPUDAGToDAGISel::Select().

◆ isVI()

bool llvm::AMDGPU::isVI(constMCSubtargetInfo & STI)

Definition at line2156 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::MCSubtargetInfo::hasFeature().

Referenced byllvm::AMDGPU::MTBUFFormat::getNfmtLookupTable(),isGFX8_GFX9_GFX10(),isGFX8Plus(), andisNotGFX10Plus().

◆ isVOPC64DPP()

LLVM_READONLYbool llvm::AMDGPU::isVOPC64DPP(unsigned Opc)

Definition at line522 of fileAMDGPUBaseInfo.cpp.

Referenced byllvm::AMDGPUDisassembler::getInstruction().

◆ isVOPCAsmOnly()

LLVM_READONLYbool llvm::AMDGPU::isVOPCAsmOnly(unsigned Opc)

Definition at line526 of fileAMDGPUBaseInfo.cpp.

◆ isVOPD()

LLVM_READONLYbool llvm::AMDGPU::isVOPD(unsigned Opc)

Definition at line582 of fileAMDGPUBaseInfo.cpp.

ReferenceshasNamedOperand().

Referenced bygetSrcOperandIndices().

◆ lookupD16ImageDimIntrinsic()

constD16ImageDimIntrinsic * llvm::AMDGPU::lookupD16ImageDimIntrinsic(unsigned Intr)

◆ lookupRsrcIntrinsic()

constRsrcIntrinsic * llvm::AMDGPU::lookupRsrcIntrinsic(unsigned Intr)

Referenced byllvm::AMDGPURegisterBankInfo::applyMappingImpl(),llvm::AMDGPURegisterBankInfo::getInstrMapping(), andllvm::SITargetLowering::getTgtMemIntrinsic().

◆ mapWMMA2AddrTo3AddrOpcode()

LLVM_READONLYunsigned llvm::AMDGPU::mapWMMA2AddrTo3AddrOpcode(unsigned Opc)

Definition at line671 of fileAMDGPUBaseInfo.cpp.

ReferencesInfo.

Referenced byllvm::SIInstrInfo::convertToThreeAddress().

◆ mapWMMA3AddrTo2AddrOpcode()

LLVM_READONLYunsigned llvm::AMDGPU::mapWMMA3AddrTo2AddrOpcode(unsigned Opc)

Definition at line676 of fileAMDGPUBaseInfo.cpp.

ReferencesInfo.

◆ maskShiftGet()

constMCExpr * llvm::AMDGPU::maskShiftGet(constMCExpr * Val,
uint32_t Mask,
uint32_t Shift,
MCContext & Ctx 
)
inline

Provided with theMCExpr *Val, uint32Mask andShift, will return the right shifted and masked, in said order of operations,MCExpr * created within theMCContextCtx.

For example, givenMCExpr *Val, Mask == 0xf, Shift == 6 the returnedMCExpr

  • will be the equivalent of (Val >> 6) & 0xf

Definition at line63 of fileSIDefinesUtils.h.

Referencesllvm::MCConstantExpr::create(),llvm::MCBinaryExpr::createAnd(), andllvm::MCBinaryExpr::createLShr().

◆ maskShiftSet()

constMCExpr * llvm::AMDGPU::maskShiftSet(constMCExpr * Val,
uint32_t Mask,
uint32_t Shift,
MCContext & Ctx 
)
inline

Provided with theMCExpr *Val, uint32Mask andShift, will return the masked and left shifted, in said order of operations,MCExpr * created within theMCContextCtx.

For example, givenMCExpr *Val, Mask == 0xf, Shift == 6 the returnedMCExpr

  • will be the equivalent of (Val & 0xf) << 6

Definition at line44 of fileSIDefinesUtils.h.

Referencesllvm::MCConstantExpr::create(),llvm::MCBinaryExpr::createAnd(), andllvm::MCBinaryExpr::createShl().

Referenced byllvm::AMDGPU::AMDGPUMCKernelCodeT::EmitKernelCodeT().

◆ mc2PseudoReg()

LLVM_READNONEMCRegister llvm::AMDGPU::mc2PseudoReg(MCRegister Reg)

Convert hardware registerReg to a pseudo register.

Definition at line2365 of fileAMDGPUBaseInfo.cpp.

ReferencesMAP_REG2REG.

Referenced bycheckWriteLane().

◆ memToShadow()

staticValue * llvm::AMDGPU::memToShadow(Module & M,
IRBuilder<> & IRB,
Type * IntptrTy,
Value * Shadow,
int AsanScale,
uint32_t AsanOffset 
)
static

Definition at line139 of fileAMDGPUAsanInstrumentation.cpp.

Referencesllvm::IRBuilderBase::CreateAdd(), andllvm::IRBuilderBase::CreateLShr().

Referenced byinstrumentAddressImpl().

◆ mfmaScaleF8F6F4FormatToNumRegs()

LLVM_READNONEuint8_t llvm::AMDGPU::mfmaScaleF8F6F4FormatToNumRegs(unsigned EncodingVal)

Definition at line538 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::AMDGPU::MFMAScaleFormats::FP4_E2M1,llvm::AMDGPU::MFMAScaleFormats::FP6_E2M3,llvm::AMDGPU::MFMAScaleFormats::FP6_E3M2,llvm::AMDGPU::MFMAScaleFormats::FP8_E4M3,llvm::AMDGPU::MFMAScaleFormats::FP8_E5M2, andllvm_unreachable.

Referenced bygetMFMA_F8F6F4_WithFormatArgs().

◆ parseArchAMDGCN()

AMDGPU::GPUKind llvm::AMDGPU::parseArchAMDGCN(StringRef CPU)

Definition at line188 of fileTargetParser.cpp.

Referencesllvm::CallingConv::C.

Referenced byfillAMDGPUFeatureMap(),getCanonicalArchName(),llvm::AMDGPUTargetStreamer::getElfMach(),getIsaVersion(), andisWave32Capable().

◆ parseArchR600()

AMDGPU::GPUKind llvm::AMDGPU::parseArchR600(StringRef CPU)

Definition at line197 of fileTargetParser.cpp.

Referencesllvm::CallingConv::C.

Referenced byfillAMDGPUFeatureMap(),getCanonicalArchName(), andllvm::AMDGPUTargetStreamer::getElfMach().

◆ printAMDGPUMCExpr()

void llvm::AMDGPU::printAMDGPUMCExpr(constMCExpr * Expr,
raw_ostream & OS,
constMCAsmInfo * MAI 
)

Definition at line681 of fileAMDGPUMCExpr.cpp.

ReferencesOS, andllvm::MCExpr::print().

Referenced byllvm::AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(), andllvm::AMDGPUTargetAsmStreamer::EmitAMDKernelCodeT().

◆ removeFnAttrFromReachable()

void llvm::AMDGPU::removeFnAttrFromReachable(CallGraph & CG,
Function * KernelRoot,
ArrayRef<StringRef > FnAttrs 
)

Strip FnAttr attribute from any functions where we may have introduced its use.

Definition at line306 of fileAMDGPUMemoryUtils.cpp.

Referencesassert(),llvm::SmallVectorBase< Size_T >::empty(),F,llvm::CallGraph::getExternalCallingNode(),llvm::Function::getFunction(),llvm::SmallPtrSetImpl< PtrType >::insert(),isKernelLDS(),llvm::SmallVectorImpl< T >::pop_back_val(),llvm::SmallVectorTemplateBase< T, bool >::push_back(), andllvm::Function::removeFnAttr().

◆ shouldEmitConstantsToTextSection()

bool llvm::AMDGPU::shouldEmitConstantsToTextSection(constTriple & TT)
Returns
True if constants should be emitted to .text section for given target tripleTT, false otherwise.

Definition at line1327 of fileAMDGPUBaseInfo.cpp.

Referencesllvm::Triple::r600.

Referenced byllvm::AMDGPUTargetObjectFile::SelectSectionForGlobal(), andllvm::SITargetLowering::shouldEmitFixup().

◆ TypeStoreSizeToSizeIndex()

static size_t llvm::AMDGPU::TypeStoreSizeToSizeIndex(uint32_t TypeSize)
static

Definition at line52 of fileAMDGPUAsanInstrumentation.cpp.

Referencesllvm::countr_zero().

Referenced byinstrumentAddressImpl().

Variable Documentation

◆ ExtendedFltRoundOffset

constexpruint32_t llvm::AMDGPU::ExtendedFltRoundOffset = 4
staticconstexpr

Offset of nonstandard values for llvm.get.rounding results from the largest supported mode.

Definition at line135 of fileSIModeRegisterDefaults.h.

Referenced bydecodeFltRoundToHWConversionTable(),decodeIndexFltRoundConversionTable(),encodeFltRoundsTable(),encodeFltRoundsToHWTable(), andencodeFltRoundsToHWTableSame().

◆ F32FltRoundOffset

constexpruint32_t llvm::AMDGPU::F32FltRoundOffset = 0
staticconstexpr

Offset in mode register of f32 rounding mode.

Definition at line138 of fileSIModeRegisterDefaults.h.

Referenced bygetModeRegisterRoundMode().

◆ F64FltRoundOffset

constexpruint32_t llvm::AMDGPU::F64FltRoundOffset = 2
staticconstexpr

Offset in mode register of f64/f16 rounding mode.

Definition at line141 of fileSIModeRegisterDefaults.h.

Referenced bygetModeRegisterRoundMode().

◆ FltRoundConversionTable

constuint64_t llvm::AMDGPU::FltRoundConversionTable
extern

Definition at line86 of fileSIModeRegisterDefaults.cpp.

Referenced bydecodeIndexFltRoundConversionTable(), andllvm::SITargetLowering::lowerGET_ROUNDING().

◆ FltRoundToHWConversionTable

constuint64_t llvm::AMDGPU::FltRoundToHWConversionTable
extern

Definition at line200 of fileSIModeRegisterDefaults.cpp.

Referenced bydecodeFltRoundToHW(),decodeFltRoundToHWConversionTable(),decodeFltRoundToHWConversionTable(), andllvm::SITargetLowering::lowerSET_ROUNDING().

◆ OPR_ID_DUPLICATE

const int llvm::AMDGPU::OPR_ID_DUPLICATE = -3

Definition at line25 of fileAMDGPUAsmUtils.h.

Referenced byencodeCustomOperand().

◆ OPR_ID_UNKNOWN

const int llvm::AMDGPU::OPR_ID_UNKNOWN = -1

Definition at line23 of fileAMDGPUAsmUtils.h.

Referenced byencodeCustomOperand(), andgetEncodingFromOperandTable().

◆ OPR_ID_UNSUPPORTED

const int llvm::AMDGPU::OPR_ID_UNSUPPORTED = -2

Definition at line24 of fileAMDGPUAsmUtils.h.

Referenced byencodeCustomOperand(), andgetEncodingFromOperandTable().

◆ OPR_VAL_INVALID

const int llvm::AMDGPU::OPR_VAL_INVALID = -4

Definition at line26 of fileAMDGPUAsmUtils.h.

Referenced byencodeCustomOperandVal().

◆ RSRC_DATA_FORMAT

constuint64_t llvm::AMDGPU::RSRC_DATA_FORMAT = 0xf00000000000LL

Definition at line1594 of fileSIInstrInfo.h.

Referenced byllvm::SIInstrInfo::getDefaultRsrcDataFormat().

◆ RSRC_ELEMENT_SIZE_SHIFT

constuint64_t llvm::AMDGPU::RSRC_ELEMENT_SIZE_SHIFT = (32 + 19)

Definition at line1595 of fileSIInstrInfo.h.

Referenced byllvm::SIInstrInfo::getScratchRsrcWords23().

◆ RSRC_INDEX_STRIDE_SHIFT

constuint64_t llvm::AMDGPU::RSRC_INDEX_STRIDE_SHIFT = (32 + 21)

Definition at line1596 of fileSIInstrInfo.h.

Referenced byllvm::SIInstrInfo::getScratchRsrcWords23().

◆ RSRC_TID_ENABLE

constuint64_t llvm::AMDGPU::RSRC_TID_ENABLE = UINT64_C(1) << (32 + 23)

Definition at line1597 of fileSIInstrInfo.h.

Referenced byllvm::SIInstrInfo::getScratchRsrcWords23().

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