This base class forTargetLowering contains the SelectionDAG-independent parts that can be used from the rest of CodeGen.More...
#include "llvm/CodeGen/TargetLowering.h"
Classes | |
| struct | AddrMode |
| This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg + ScalableOffset*vscale If BaseGV is null, there is no BaseGV.More... | |
| class | ArgListEntry |
| struct | CondMergingParams |
| struct | IntrinsicInfo |
| class | ValueTypeActionImpl |
Public Types | |
| enum | LegalizeAction : uint8_t { Legal,Promote,Expand,LibCall, Custom } |
| This enum indicates whether operations are valid for a target, and if not, what action should be used to make them valid.More... | |
| enum | LegalizeTypeAction : uint8_t { TypeLegal,TypePromoteInteger,TypeExpandInteger,TypeSoftenFloat, TypeExpandFloat,TypeScalarizeVector,TypeSplitVector,TypeWidenVector, TypePromoteFloat,TypeSoftPromoteHalf,TypeScalarizeScalableVector } |
| This enum indicates whether a types are legal for a target, and if not, what action should be used to make them valid.More... | |
| enum | BooleanContent {UndefinedBooleanContent,ZeroOrOneBooleanContent,ZeroOrNegativeOneBooleanContent } |
| Enum that describes how the target represents true/false values.More... | |
| enum | SelectSupportKind {ScalarValSelect,ScalarCondVectorVal,VectorMaskSelect } |
| Enum that describes what type of support for selects the target has.More... | |
| enum class | AtomicExpansionKind { None,CastToInteger,LLSC,LLOnly, CmpXChg,MaskedIntrinsic,BitTestIntrinsic,CmpArithIntrinsic, Expand,NotAtomic } |
| Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.More... | |
| enum class | MulExpansionKind {Always,OnlyLegalOrCustom } |
| Enum that specifies when a multiplication should be expanded.More... | |
| enum class | NegatibleCost {Cheaper = 0,Neutral = 1,Expensive = 2 } |
| Enum that specifies when a float negation is beneficial.More... | |
| enum | AndOrSETCCFoldKind : uint8_t {None = 0,AddAnd = 1,NotAnd = 2,ABS = 4 } |
| Enum of different potentially desirable ways to fold (and/or (setcc ...), (setcc ...)).More... | |
| enum | ReciprocalEstimate : int {Unspecified = -1,Disabled = 0,Enabled = 1 } |
| Reciprocal estimate status values used by the functions below.More... | |
| enum class | ShiftLegalizationStrategy {ExpandToParts,ExpandThroughStack,LowerToLibcall } |
Return the preferred strategy to legalize tihs SHIFT instruction, withExpansionFactor being the recursion depth - how many expansion needed.More... | |
| using | LegalizeKind = std::pair<LegalizeTypeAction,EVT > |
| LegalizeKind holds the legalization kind that needs to happen toEVT in order to type-legalize it. | |
| using | ArgListTy = std::vector<ArgListEntry > |
Public Member Functions | |
| virtual void | markLibCallAttributes (MachineFunction *MF,unsignedCC,ArgListTy &Args)const |
| TargetLoweringBase (constTargetMachine &TM) | |
| NOTE: TheTargetMachine owns TLOF. | |
| TargetLoweringBase (constTargetLoweringBase &)=delete | |
| TargetLoweringBase & | operator= (constTargetLoweringBase &)=delete |
| virtual | ~TargetLoweringBase ()=default |
| bool | isStrictFPEnabled ()const |
| Return true if the target support strict float operation. | |
| constTargetMachine & | getTargetMachine ()const |
| virtualbool | useSoftFloat ()const |
| virtualMVT | getPointerTy (constDataLayout &DL,uint32_t AS=0)const |
| Return the pointer type for the given address space, defaults to the pointer type from the data layout. | |
| virtualMVT | getPointerMemTy (constDataLayout &DL,uint32_t AS=0)const |
| Return the in-memory pointer type for the given address space, defaults to the pointer type from the data layout. | |
| MVT | getFrameIndexTy (constDataLayout &DL)const |
| Return the type for frame index, which is determined by the alloca address space specified through the data layout. | |
| MVT | getProgramPointerTy (constDataLayout &DL)const |
| Return the type for code pointers, which is determined by the program address space specified through the data layout. | |
| virtualMVT | getFenceOperandTy (constDataLayout &DL)const |
| Return the type for operands of fence. | |
| virtualMVT | getScalarShiftAmountTy (constDataLayout &,EVT)const |
| Return the type to use for a scalar shift opcode, given the shifted amount type. | |
| EVT | getShiftAmountTy (EVT LHSTy,constDataLayout &DL)const |
| Returns the type for the shift amount of a shift opcode. | |
| virtualLLVM_READONLYLLT | getPreferredShiftAmountTy (LLT ShiftValueTy)const |
Return the preferred type to use for a shift opcode, given the shifted amount type isShiftValueTy. | |
| virtualMVT | getVectorIdxTy (constDataLayout &DL)const |
| Returns the type to be used for the index operand of:ISD::INSERT_VECTOR_ELT,ISD::EXTRACT_VECTOR_ELT,ISD::INSERT_SUBVECTOR, andISD::EXTRACT_SUBVECTOR. | |
| virtualMVT | getVPExplicitVectorLengthTy ()const |
| Returns the type to be used for the EVL/AVL operand of VP nodes: ISD::VP_ADD, ISD::VP_SUB, etc. | |
| virtualMachineMemOperand::Flags | getTargetMMOFlags (constInstruction &I)const |
| This callback is used to inspect load/store instructions and add target-specificMachineMemOperand flags to them. | |
| virtualMachineMemOperand::Flags | getTargetMMOFlags (constMemSDNode &Node)const |
| This callback is used to inspect load/storeSDNode. | |
| MachineMemOperand::Flags | getLoadMemOperandFlags (constLoadInst &LI,constDataLayout &DL,AssumptionCache *AC=nullptr,constTargetLibraryInfo *LibInfo=nullptr)const |
| MachineMemOperand::Flags | getStoreMemOperandFlags (constStoreInst &SI,constDataLayout &DL)const |
| MachineMemOperand::Flags | getAtomicMemOperandFlags (constInstruction &AI,constDataLayout &DL)const |
| virtualbool | isSelectSupported (SelectSupportKind)const |
| virtualbool | shouldExpandPartialReductionIntrinsic (constIntrinsicInst *I)const |
| Return true if the @llvm.experimental.vector.partial.reduce. | |
| virtualbool | shouldExpandGetActiveLaneMask (EVT VT,EVT OpVT)const |
| Return true if the @llvm.get.active.lane.mask intrinsic should be expanded using generic code inSelectionDAGBuilder. | |
| virtualbool | shouldExpandGetVectorLength (EVT CountVT,unsigned VF,bool IsScalable)const |
| virtualbool | shouldExpandCttzElements (EVT VT)const |
| Return true if the @llvm.experimental.cttz.elts intrinsic should be expanded using generic code inSelectionDAGBuilder. | |
| unsigned | getBitWidthForCttzElements (Type *RetTy,ElementCount EC,bool ZeroIsPoison,constConstantRange *VScaleRange)const |
| Return the minimum number of bits required to hold the maximum possible number of trailing zero vector elements. | |
| virtualbool | shouldExpandVectorMatch (EVT VT,unsigned SearchSize)const |
| Return true if the @llvm.experimental.vector.match intrinsic should be expanded for vector type ‘VT’ and search size ‘SearchSize’ using generic code inSelectionDAGBuilder. | |
| virtualbool | shouldReassociateReduction (unsigned RedOpc,EVT VT)const |
| virtualbool | reduceSelectOfFPConstantLoads (EVT CmpOpVT)const |
| Return true if it is profitable to convert a select of FP constants into a constant pool load whose address depends on the select condition. | |
| bool | hasMultipleConditionRegisters ()const |
| Return true if multiple condition registers are available. | |
| bool | hasExtractBitsInsn ()const |
| Return true if the target has BitExtract instructions. | |
| virtualTargetLoweringBase::LegalizeTypeAction | getPreferredVectorAction (MVT VT)const |
| Return the preferred vector type legalization action. | |
| virtualbool | softPromoteHalfType ()const |
| virtualbool | useFPRegsForHalfType ()const |
| virtualbool | shouldExpandBuildVectorWithShuffles (EVT,unsigned DefinedValues)const |
| virtualbool | isIntDivCheap (EVT VT,AttributeList Attr)const |
| Return true if integer divide is usually cheaper than a sequence of several shifts, adds, and multiplies for this target. | |
| virtualbool | hasStandaloneRem (EVT VT)const |
| Return true if the target can handle a standalone remainder operation. | |
| virtualbool | isFsqrtCheap (SDValueX,SelectionDAG &DAG)const |
| Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X). | |
| int | getRecipEstimateSqrtEnabled (EVT VT,MachineFunction &MF)const |
| Return a ReciprocalEstimate enum value for a square root of the given type based on the function's attributes. | |
| int | getRecipEstimateDivEnabled (EVT VT,MachineFunction &MF)const |
| Return a ReciprocalEstimate enum value for a division of the given type based on the function's attributes. | |
| int | getSqrtRefinementSteps (EVT VT,MachineFunction &MF)const |
| Return the refinement step count for a square root of the given type based on the function's attributes. | |
| int | getDivRefinementSteps (EVT VT,MachineFunction &MF)const |
| Return the refinement step count for a division of the given type based on the function's attributes. | |
| bool | isSlowDivBypassed ()const |
| Returns true if target has indicated at least one type should be bypassed. | |
| constDenseMap<unsigned int,unsigned int > & | getBypassSlowDivWidths ()const |
| Returns map of slow types for division or remainder with corresponding fast types. | |
| virtualbool | isVScaleKnownToBeAPowerOfTwo ()const |
| Return true only if vscale must be a power of two. | |
| bool | isJumpExpensive ()const |
| Return true if Flow Control is an expensive operation that should be avoided. | |
| virtualCondMergingParams | getJumpConditionMergingParams (Instruction::BinaryOps,constValue *,constValue *)const |
| bool | isPredictableSelectExpensive ()const |
| Return true if selects are only cheaper than branches if the branch is unlikely to be predicted right. | |
| virtualbool | fallBackToDAGISel (constInstruction &Inst)const |
| virtualbool | isLoadBitCastBeneficial (EVT LoadVT,EVT BitcastVT,constSelectionDAG &DAG,constMachineMemOperand &MMO)const |
| Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On architectures that don't natively support some vector loads efficiently, casting the load to a smaller vector of larger types and loading is more efficient, however, this can be undone by optimizations in dag combiner. | |
| virtualbool | isStoreBitCastBeneficial (EVT StoreVT,EVT BitcastVT,constSelectionDAG &DAG,constMachineMemOperand &MMO)const |
| Return true if the following transform is beneficial: (store (y (conv x)), y*)) -> (store x, (x*)) | |
| virtualbool | storeOfVectorConstantIsCheap (bool IsZero,EVT MemVT,unsigned NumElem,unsigned AddrSpace)const |
| Return true if it is expected to be cheaper to do a store of vector constant with the given size and type for the address space than to store the individual scalar element constants. | |
| virtualbool | mergeStoresAfterLegalization (EVT MemVT)const |
| Allow store merging for the specified type after legalization in addition to before legalization. | |
| virtualbool | canMergeStoresTo (unsigned AS,EVT MemVT,constMachineFunction &MF)const |
| Returns if it's reasonable to merge stores to MemVT size. | |
| virtualbool | isCheapToSpeculateCttz (Type *Ty)const |
| Return true if it is cheap to speculate a call to intrinsic cttz. | |
| virtualbool | isCheapToSpeculateCtlz (Type *Ty)const |
| Return true if it is cheap to speculate a call to intrinsic ctlz. | |
| virtualbool | isCtlzFast ()const |
| Return true if ctlz instruction is fast. | |
| virtualbool | isCtpopFast (EVT VT)const |
| Return true if ctpop instruction is fast. | |
| virtualunsigned | getCustomCtpopCost (EVT VT,ISD::CondCodeCond)const |
| Return the maximum number of "x & (x - 1)" operations that can be done instead of deferring to a custom CTPOP. | |
| virtualbool | isEqualityCmpFoldedWithSignedCmp ()const |
| Return true if instruction generated for equality comparison is folded with instruction generated for signed comparison. | |
| virtualbool | preferZeroCompareBranch ()const |
| Return true if the heuristic to prefer icmp eq zero should be used in code gen prepare. | |
| virtualbool | isMultiStoresCheaperThanBitsMerge (EVT LTy,EVT HTy)const |
| Return true if it is cheaper to split the store of a merged int val from a pair of smaller values into multiple stores. | |
| virtualbool | isMaskAndCmp0FoldingBeneficial (constInstruction &AndI)const |
| Return if the target supports combining a chain like: | |
| virtualbool | areTwoSDNodeTargetMMOFlagsMergeable (constMemSDNode &NodeX,constMemSDNode &NodeY)const |
| Return true if it is valid to merge the TargetMMOFlags in two SDNodes. | |
| virtualbool | convertSetCCLogicToBitwiseLogic (EVT VT)const |
| Use bitwise logic to make pairs of compares more efficient. | |
| virtualMVT | hasFastEqualityCompare (unsigned NumBits)const |
| Return the preferred operand type if the target has a quick way to compare integer values of the given size. | |
| virtualbool | hasAndNotCompare (SDValueY)const |
| Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) != Y —> (~X & Y) != 0. | |
| virtualbool | hasAndNot (SDValueX)const |
| Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify select or other instructions. | |
| virtualbool | hasBitTest (SDValueX,SDValueY)const |
| Return true if the target has a bit-test instruction: (X & (1 << Y)) ==/!= 0 This knowledge can be used to prevent breaking the pattern, or creating it if it could be recognized. | |
| virtualbool | shouldFoldMaskToVariableShiftPair (SDValueX)const |
| There are two ways to clear extreme bits (either low or high): Mask: x & (-1 << y) (the instcombine canonical form) Shifts: x >> y << y Return true if the variant with 2 variable shifts is preferred. | |
| virtualbool | shouldFoldConstantShiftPairToMask (constSDNode *N,CombineLevel Level)const |
| Return true if it is profitable to fold a pair of shifts into a mask. | |
| virtualbool | shouldTransformSignedTruncationCheck (EVT XVT,unsigned KeptBits)const |
| Should we tranform the IR-optimal check for whether given truncation down into KeptBits would be truncating or not: (add x, (1 << (KeptBits-1))) srccond (1 << KeptBits) Into it's more traditional form: ((x << C) a>> C) dstcond x Return true if we should transform. | |
| virtualbool | shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd (SDValueX,ConstantSDNode *XC,ConstantSDNode *CC,SDValueY,unsigned OldShiftOpcode,unsigned NewShiftOpcode,SelectionDAG &DAG)const |
| Given the pattern (X & (C l>>/<< Y)) ==/!= 0 return true if it should be transformed into: ((X <</l>> Y) & C) ==/!= 0 WARNING: if 'X' is a constant, the fold may deadlock! FIXME: we could avoid passing XC, but we can't useisConstOrConstSplat() here because it can end up being not linked in. | |
| virtualbool | optimizeFMulOrFDivAsShiftAddBitcast (SDNode *N,SDValue FPConst,SDValue IntPow2)const |
| virtualunsigned | preferedOpcodeForCmpEqPiecesOfOperand (EVT VT,unsigned ShiftOpc,bool MayTransformRotate,constAPInt &ShiftOrRotateAmt,const std::optional<APInt > &AndMask)const |
| virtualbool | preferIncOfAddToSubOfNot (EVT VT)const |
| These two forms are equivalent: sub y, (xor x, -1) add (add x, 1), y The variant with two add's is IR-canonical. | |
| virtualbool | preferABDSToABSWithNSW (EVT VT)const |
| virtualbool | preferScalarizeSplat (SDNode *N)const |
| virtualbool | preferSextInRegOfTruncate (EVT TruncVT,EVT VT,EVT ExtVT)const |
| bool | enableExtLdPromotion ()const |
| Return true if the target wants to use the optimization that turns ext(promotableInst1(...(promotableInstN(load)))) into promotedInst1(...(promotedInstN(ext(load)))). | |
| virtualbool | canCombineStoreAndExtract (Type *VectorTy,Value *Idx,unsigned &Cost)const |
| Return true if the target can combine store(extractelement VectorTy,Idx). | |
| virtualbool | shallExtractConstSplatVectorElementToStore (Type *VectorTy,unsigned ElemSizeInBits,unsigned &Index)const |
| Return true if the target shall perform extract vector element and store given that the vector is known to be splat of constant. | |
| virtualbool | shouldSplatInsEltVarIndex (EVT)const |
| Return true if inserting a scalar into a variable element of an undef vector is more efficiently handled by splatting the scalar instead. | |
| virtualbool | enableAggressiveFMAFusion (EVT VT)const |
| Return true if target always benefits from combining into FMA for a given value type. | |
| virtualbool | enableAggressiveFMAFusion (LLT Ty)const |
| Return true if target always benefits from combining into FMA for a given value type. | |
| virtualEVT | getSetCCResultType (constDataLayout &DL,LLVMContext &Context,EVT VT)const |
| Return the ValueType of the result of SETCC operations. | |
| virtualMVT::SimpleValueType | getCmpLibcallReturnType ()const |
| Return the ValueType for comparison libcalls. | |
| BooleanContent | getBooleanContents (bool isVec,bool isFloat)const |
| For targets without i1 registers, this gives the nature of the high-bits of boolean values held in types wider than i1. | |
| BooleanContent | getBooleanContents (EVTType)const |
| SDValue | promoteTargetBoolean (SelectionDAG &DAG,SDValueBool,EVT ValVT)const |
| Promote the given target boolean to a target boolean of the given type. | |
| Sched::Preference | getSchedulingPreference ()const |
| Return target scheduling preference. | |
| virtualSched::Preference | getSchedulingPreference (SDNode *)const |
| Some scheduler, e.g. | |
| virtualconstTargetRegisterClass * | getRegClassFor (MVT VT,bool isDivergent=false)const |
| Return the register class that should be used for the specified value type. | |
| virtualbool | requiresUniformRegister (MachineFunction &MF,constValue *)const |
| Allows target to decide about the register class of the specific value that is live outside the defining block. | |
| virtualconstTargetRegisterClass * | getRepRegClassFor (MVT VT)const |
| Return the 'representative' register class for the specified value type. | |
| virtualuint8_t | getRepRegClassCostFor (MVT VT)const |
| Return the cost of the 'representative' register class for the specified value type. | |
| virtualShiftLegalizationStrategy | preferredShiftLegalizationStrategy (SelectionDAG &DAG,SDNode *N,unsigned ExpansionFactor)const |
| bool | isTypeLegal (EVT VT)const |
| Return true if the target has native support for the specified value type. | |
| constValueTypeActionImpl & | getValueTypeActions ()const |
| LegalizeKind | getTypeConversion (LLVMContext &Context,EVT VT)const |
| Return pair that represents the legalization kind (first) that needs to happen toEVT (second) in order to type-legalize it. | |
| LegalizeTypeAction | getTypeAction (LLVMContext &Context,EVT VT)const |
| Return how we should legalize values of this type, either it is already legal (return 'Legal') or we need to promote it to a larger type (return 'Promote'), or we need to expand it into multiple registers of smaller integer type (return 'Expand'). | |
| LegalizeTypeAction | getTypeAction (MVT VT)const |
| virtualEVT | getTypeToTransformTo (LLVMContext &Context,EVT VT)const |
| For types supported by the target, this is an identity function. | |
| EVT | getTypeToExpandTo (LLVMContext &Context,EVT VT)const |
| For types supported by the target, this is an identity function. | |
| unsigned | getVectorTypeBreakdown (LLVMContext &Context,EVT VT,EVT &IntermediateVT,unsigned &NumIntermediates,MVT &RegisterVT)const |
| Vector types are broken down into some number of legal first class types. | |
| virtualunsigned | getVectorTypeBreakdownForCallingConv (LLVMContext &Context,CallingConv::IDCC,EVT VT,EVT &IntermediateVT,unsigned &NumIntermediates,MVT &RegisterVT)const |
| Certain targets such as MIPS require that some types such as vectors are always broken down into scalars in some contexts. | |
| virtualbool | getTgtMemIntrinsic (IntrinsicInfo &,constCallInst &,MachineFunction &,unsigned)const |
| Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (touches memory). | |
| virtualbool | isFPImmLegal (constAPFloat &,EVT,bool ForCodeSize=false)const |
| Returns true if the target can instruction select the specified FP immediate natively. | |
| virtualbool | isShuffleMaskLegal (ArrayRef< int >,EVT)const |
| Targets can use this to indicate that they only supportsome VECTOR_SHUFFLE operations, those with specific masks. | |
| virtualbool | canOpTrap (unsignedOp,EVT VT)const |
| Returns true if the operation can trap for the value type. | |
| virtualbool | isVectorClearMaskLegal (ArrayRef< int >,EVT)const |
| Similar to isShuffleMaskLegal. | |
| virtualLegalizeAction | getCustomOperationAction (SDNode &Op)const |
| How to legalize this custom operation? | |
| LegalizeAction | getOperationAction (unsignedOp,EVT VT)const |
| Return how this operation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. | |
| virtualbool | isSupportedFixedPointOperation (unsignedOp,EVT VT,unsigned Scale)const |
| Custom method defined by each target to indicate if an operation which may require a scale is supported natively by the target. | |
| LegalizeAction | getFixedPointOperationAction (unsignedOp,EVT VT,unsigned Scale)const |
| Some fixed point operations may be natively supported by the target but only for specific scales. | |
| LegalizeAction | getStrictFPOperationAction (unsignedOp,EVT VT)const |
| bool | isOperationLegalOrCustom (unsignedOp,EVT VT,bool LegalOnly=false)const |
| Return true if the specified operation is legal on this target or can be made legal with custom lowering. | |
| bool | isOperationLegalOrPromote (unsignedOp,EVT VT,bool LegalOnly=false)const |
| Return true if the specified operation is legal on this target or can be made legal using promotion. | |
| bool | isOperationLegalOrCustomOrPromote (unsignedOp,EVT VT,bool LegalOnly=false)const |
| Return true if the specified operation is legal on this target or can be made legal with custom lowering or using promotion. | |
| bool | isOperationCustom (unsignedOp,EVT VT)const |
| Return true if the operation uses custom lowering, regardless of whether the type is legal or not. | |
| virtualbool | areJTsAllowed (constFunction *Fn)const |
| Return true if lowering to a jump table is allowed. | |
| bool | rangeFitsInWord (constAPInt &Low,constAPInt &High,constDataLayout &DL)const |
| Check whether the range [Low,High] fits in a machine word. | |
| virtualbool | isSuitableForJumpTable (constSwitchInst *SI,uint64_t NumCases,uint64_tRange,ProfileSummaryInfo *PSI,BlockFrequencyInfo *BFI)const |
Return true if lowering to a jump table is suitable for a set of case clusters which may containNumCases cases,Range range of values. | |
| virtualMVT | getPreferredSwitchConditionType (LLVMContext &Context,EVT ConditionVT)const |
| Returns preferred type for switch condition. | |
| bool | isSuitableForBitTests (unsigned NumDests,unsigned NumCmps,constAPInt &Low,constAPInt &High,constDataLayout &DL)const |
Return true if lowering to a bit test is suitable for a set of case clusters which containsNumDests unique destinations,Low andHigh as its lowest and highest case values, and expectsNumCmps case value comparisons. | |
| bool | isOperationExpand (unsignedOp,EVT VT)const |
| Return true if the specified operation is illegal on this target or unlikely to be made legal with custom lowering. | |
| bool | isOperationLegal (unsignedOp,EVT VT)const |
| Return true if the specified operation is legal on this target. | |
| LegalizeAction | getLoadExtAction (unsigned ExtType,EVT ValVT,EVT MemVT)const |
| Return how this load with extension should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. | |
| bool | isLoadExtLegal (unsigned ExtType,EVT ValVT,EVT MemVT)const |
| Return true if the specified load with extension is legal on this target. | |
| bool | isLoadExtLegalOrCustom (unsigned ExtType,EVT ValVT,EVT MemVT)const |
| Return true if the specified load with extension is legal or custom on this target. | |
| LegalizeAction | getAtomicLoadExtAction (unsigned ExtType,EVT ValVT,EVT MemVT)const |
| Same as getLoadExtAction, but for atomic loads. | |
| bool | isAtomicLoadExtLegal (unsigned ExtType,EVT ValVT,EVT MemVT)const |
| Return true if the specified atomic load with extension is legal on this target. | |
| LegalizeAction | getTruncStoreAction (EVT ValVT,EVT MemVT)const |
| Return how this store with truncation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. | |
| bool | isTruncStoreLegal (EVT ValVT,EVT MemVT)const |
| Return true if the specified store with truncation is legal on this target. | |
| bool | isTruncStoreLegalOrCustom (EVT ValVT,EVT MemVT)const |
| Return true if the specified store with truncation has solution on this target. | |
| virtualbool | canCombineTruncStore (EVT ValVT,EVT MemVT,bool LegalOnly)const |
| LegalizeAction | getIndexedLoadAction (unsigned IdxMode,MVT VT)const |
| Return how the indexed load should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. | |
| bool | isIndexedLoadLegal (unsigned IdxMode,EVT VT)const |
| Return true if the specified indexed load is legal on this target. | |
| LegalizeAction | getIndexedStoreAction (unsigned IdxMode,MVT VT)const |
| Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. | |
| bool | isIndexedStoreLegal (unsigned IdxMode,EVT VT)const |
| Return true if the specified indexed load is legal on this target. | |
| LegalizeAction | getIndexedMaskedLoadAction (unsigned IdxMode,MVT VT)const |
| Return how the indexed load should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. | |
| bool | isIndexedMaskedLoadLegal (unsigned IdxMode,EVT VT)const |
| Return true if the specified indexed load is legal on this target. | |
| LegalizeAction | getIndexedMaskedStoreAction (unsigned IdxMode,MVT VT)const |
| Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it. | |
| bool | isIndexedMaskedStoreLegal (unsigned IdxMode,EVT VT)const |
| Return true if the specified indexed load is legal on this target. | |
| virtualbool | shouldExtendGSIndex (EVT VT,EVT &EltTy)const |
| Returns true if the index type for a masked gather/scatter requires extending. | |
| virtualbool | shouldRemoveExtendFromGSIndex (SDValue Extend,EVT DataVT)const |
| virtualbool | isLegalScaleForGatherScatter (uint64_t Scale,uint64_t ElemSize)const |
| LegalizeAction | getCondCodeAction (ISD::CondCodeCC,MVT VT)const |
| Return how the condition code should be treated: either it is legal, needs to be expanded to some other code sequence, or the target has a custom expander for it. | |
| bool | isCondCodeLegal (ISD::CondCodeCC,MVT VT)const |
| Return true if the specified condition code is legal for a comparison of the specified types on this target. | |
| bool | isCondCodeLegalOrCustom (ISD::CondCodeCC,MVT VT)const |
| Return true if the specified condition code is legal or custom for a comparison of the specified types on this target. | |
| MVT | getTypeToPromoteTo (unsignedOp,MVT VT)const |
| If the action for this operation is to promote, this method returns the ValueType to promote to. | |
| virtualEVT | getAsmOperandValueType (constDataLayout &DL,Type *Ty,bool AllowUnknown=false)const |
| EVT | getValueType (constDataLayout &DL,Type *Ty,bool AllowUnknown=false)const |
| Return theEVT corresponding to this LLVM type. | |
| EVT | getMemValueType (constDataLayout &DL,Type *Ty,bool AllowUnknown=false)const |
| MVT | getSimpleValueType (constDataLayout &DL,Type *Ty,bool AllowUnknown=false)const |
| Return theMVT corresponding to this LLVM type. See getValueType. | |
| virtualAlign | getByValTypeAlignment (Type *Ty,constDataLayout &DL)const |
| Returns the desired alignment for ByVal or InAlloca aggregate function arguments in the caller parameter area. | |
| MVT | getRegisterType (MVT VT)const |
| Return the type of registers that this ValueType will eventually require. | |
| MVT | getRegisterType (LLVMContext &Context,EVT VT)const |
| Return the type of registers that this ValueType will eventually require. | |
| virtualunsigned | getNumRegisters (LLVMContext &Context,EVT VT, std::optional<MVT > RegisterVT=std::nullopt)const |
| Return the number of registers that this ValueType will eventually require. | |
| virtualMVT | getRegisterTypeForCallingConv (LLVMContext &Context,CallingConv::IDCC,EVT VT)const |
| Certain combinations of ABIs, Targets and features require that types are legal for some operations and not for other operations. | |
| virtualunsigned | getNumRegistersForCallingConv (LLVMContext &Context,CallingConv::IDCC,EVT VT)const |
| Certain targets require unusual breakdowns of certain types. | |
| virtualAlign | getABIAlignmentForCallingConv (Type *ArgTy,constDataLayout &DL)const |
| Certain targets have context sensitive alignment requirements, where one type has the alignment requirement of another type. | |
| virtualbool | ShouldShrinkFPConstant (EVT)const |
| If true, then instruction selection should seek to shrink the FP constant of the specified type to a smaller type in order to save space and / or reduce runtime. | |
| virtualbool | shouldReduceLoadWidth (SDNode *Load,ISD::LoadExtType ExtTy,EVT NewVT)const |
| Return true if it is profitable to reduce a load to a smaller type. | |
| virtualbool | shouldRemoveRedundantExtend (SDValueOp)const |
| Return true (the default) if it is profitable to remove a sext_inreg(x) where the sext is redundant, and use x directly. | |
| bool | isPaddedAtMostSignificantBitsWhenStored (EVT VT)const |
| Indicates if any padding is guaranteed to go at the most significant bits when storing the type to memory and the type size isn't equal to the store size. | |
| bool | hasBigEndianPartOrdering (EVT VT,constDataLayout &DL)const |
| When splitting a value of the specified type into parts, does the Lo or Hi part come first? This usually follows the endianness, except for ppcf128, where the Hi part always comes first. | |
| bool | hasTargetDAGCombine (ISD::NodeType NT)const |
| If true, the target has custom DAG combine transformations that it can perform for the specified node. | |
| unsigned | getGatherAllAliasesMaxDepth ()const |
| virtualunsigned | getVaListSizeInBits (constDataLayout &DL)const |
| Returns the size of the platform's va_list object. | |
| unsigned | getMaxStoresPerMemset (bool OptSize)const |
| Get maximum # of store operations permitted for llvm.memset. | |
| unsigned | getMaxStoresPerMemcpy (bool OptSize)const |
| Get maximum # of store operations permitted for llvm.memcpy. | |
| virtualunsigned | getMaxGluedStoresPerMemcpy ()const |
| Get maximum # of store operations to be glued together. | |
| unsigned | getMaxExpandSizeMemcmp (bool OptSize)const |
| Get maximum # of load operations permitted for memcmp. | |
| unsigned | getMaxStoresPerMemmove (bool OptSize)const |
| Get maximum # of store operations permitted for llvm.memmove. | |
| virtualbool | allowsMisalignedMemoryAccesses (EVT,unsigned AddrSpace=0,Align Alignment=Align(1),MachineMemOperand::Flags Flags=MachineMemOperand::MONone,unsigned *=nullptr)const |
| Determine if the target supports unaligned memory accesses. | |
| virtualbool | allowsMisalignedMemoryAccesses (LLT,unsigned AddrSpace=0,Align Alignment=Align(1),MachineMemOperand::Flags Flags=MachineMemOperand::MONone,unsigned *=nullptr)const |
| LLT handling variant. | |
| bool | allowsMemoryAccessForAlignment (LLVMContext &Context,constDataLayout &DL,EVT VT,unsigned AddrSpace=0,Align Alignment=Align(1),MachineMemOperand::Flags Flags=MachineMemOperand::MONone,unsigned *Fast=nullptr)const |
| This function returns true if the memory access is aligned or if the target allows this specific unaligned memory access. | |
| bool | allowsMemoryAccessForAlignment (LLVMContext &Context,constDataLayout &DL,EVT VT,constMachineMemOperand &MMO,unsigned *Fast=nullptr)const |
| Return true if the memory access of this type is aligned or if the target allows this specific unaligned access for the givenMachineMemOperand. | |
| virtualbool | allowsMemoryAccess (LLVMContext &Context,constDataLayout &DL,EVT VT,unsigned AddrSpace=0,Align Alignment=Align(1),MachineMemOperand::Flags Flags=MachineMemOperand::MONone,unsigned *Fast=nullptr)const |
| Return true if the target supports a memory access of this type for the given address space and alignment. | |
| bool | allowsMemoryAccess (LLVMContext &Context,constDataLayout &DL,EVT VT,constMachineMemOperand &MMO,unsigned *Fast=nullptr)const |
| Return true if the target supports a memory access of this type for the givenMachineMemOperand. | |
| bool | allowsMemoryAccess (LLVMContext &Context,constDataLayout &DL,LLT Ty,constMachineMemOperand &MMO,unsigned *Fast=nullptr)const |
| LLT handling variant. | |
| virtualEVT | getOptimalMemOpType (constMemOp &Op,constAttributeList &)const |
| Returns the target specific optimal type for load and store operations as a result of memset, memcpy, and memmove lowering. | |
| virtualLLT | getOptimalMemOpLLT (constMemOp &Op,constAttributeList &)const |
| LLT returning variant. | |
| virtualbool | isSafeMemOpType (MVT)const |
| Returns true if it's safe to use load / store of the specified type to expand memcpy / memset inline. | |
| virtualunsigned | getMinimumJumpTableEntries ()const |
| Return lower limit for number of blocks in a jump table. | |
| unsigned | getMinimumJumpTableDensity (bool OptForSize)const |
| Return lower limit of the density in a jump table. | |
| unsigned | getMaximumJumpTableSize ()const |
| Return upper limit for number of entries in a jump table. | |
| virtualbool | isJumpTableRelative ()const |
| Register | getStackPointerRegisterToSaveRestore ()const |
| If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore. | |
| virtualRegister | getExceptionPointerRegister (constConstant *PersonalityFn)const |
| If a physical register, this returns the register that receives the exception address on entry to an EH pad. | |
| virtualRegister | getExceptionSelectorRegister (constConstant *PersonalityFn)const |
| If a physical register, this returns the register that receives the exception typeid on entry to a landing pad. | |
| virtualbool | needsFixedCatchObjects ()const |
| Align | getMinStackArgumentAlignment ()const |
| Return the minimum stack alignment of an argument. | |
| Align | getMinFunctionAlignment ()const |
| Return the minimum function alignment. | |
| Align | getPrefFunctionAlignment ()const |
| Return the preferred function alignment. | |
| virtualAlign | getPrefLoopAlignment (MachineLoop *ML=nullptr)const |
| Return the preferred loop alignment. | |
| virtualunsigned | getMaxPermittedBytesForAlignment (MachineBasicBlock *MBB)const |
| Return the maximum amount of bytes allowed to be emitted when padding for alignment. | |
| virtualbool | alignLoopsWithOptSize ()const |
| Should loops be aligned even when the function is marked OptSize (but not MinSize). | |
| virtualValue * | getIRStackGuard (IRBuilderBase &IRB)const |
| If the target has a standard location for the stack protector guard, returns the address of that location. | |
| virtual void | insertSSPDeclarations (Module &M)const |
| Inserts necessary declarations for SSP (stack protection) purpose. | |
| virtualValue * | getSDagStackGuard (constModule &M)const |
| Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nullptr. | |
| virtualbool | useStackGuardXorFP ()const |
| If this function returns true, stack protection checks should XOR the frame pointer (or whichever pointer is used to address locals) into the stack guard value before checking it. | |
| virtualFunction * | getSSPStackGuardCheck (constModule &M)const |
| If the target has a standard stack protection check function that performs validation and error handling, returns the function. | |
| virtualValue * | getSafeStackPointerLocation (IRBuilderBase &IRB)const |
| Returns the target-specific address of the unsafe stack pointer. | |
| virtualbool | hasStackProbeSymbol (constMachineFunction &MF)const |
| Returns the name of the symbol used to emit stack probes or the empty string if not applicable. | |
| virtualbool | hasInlineStackProbe (constMachineFunction &MF)const |
| virtualStringRef | getStackProbeSymbolName (constMachineFunction &MF)const |
| virtualbool | isFreeAddrSpaceCast (unsigned SrcAS,unsigned DestAS)const |
| Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g. | |
| virtualbool | shouldAlignPointerArgs (CallInst *,unsigned &,Align &)const |
| Return true if the pointer arguments to CI should be aligned by aligning the object whose address is being passed. | |
| virtual void | emitAtomicCmpXchgNoStoreLLBalance (IRBuilderBase &Builder)const |
| virtualbool | shouldSignExtendTypeInLibCall (Type *Ty,bool IsSigned)const |
| Returns true if arguments should be sign-extended in lib calls. | |
| virtualbool | shouldExtendTypeInLibCall (EVTType)const |
| Returns true if arguments should be extended in lib calls. | |
| virtualAtomicExpansionKind | shouldExpandAtomicLoadInIR (LoadInst *LI)const |
| Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass. | |
| virtualAtomicExpansionKind | shouldCastAtomicLoadInIR (LoadInst *LI)const |
| Returns how the given (atomic) load should be cast by the IR-level AtomicExpand pass. | |
| virtualAtomicExpansionKind | shouldExpandAtomicStoreInIR (StoreInst *SI)const |
| Returns how the given (atomic) store should be expanded by the IR-level AtomicExpand pass into. | |
| virtualAtomicExpansionKind | shouldCastAtomicStoreInIR (StoreInst *SI)const |
| Returns how the given (atomic) store should be cast by the IR-level AtomicExpand pass into. | |
| virtualAtomicExpansionKind | shouldExpandAtomicCmpXchgInIR (AtomicCmpXchgInst *AI)const |
| Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass. | |
| virtualAtomicExpansionKind | shouldExpandAtomicRMWInIR (AtomicRMWInst *RMW)const |
| Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all. | |
| virtualAtomicExpansionKind | shouldCastAtomicRMWIInIR (AtomicRMWInst *RMWI)const |
| Returns how the given atomic atomicrmw should be cast by the IR-level AtomicExpand pass. | |
| virtualLoadInst * | lowerIdempotentRMWIntoFencedLoad (AtomicRMWInst *RMWI)const |
| On some platforms, an AtomicRMW that never actually modifies the value (such as fetch_add of 0) can be turned into a fence followed by an atomic load. | |
| virtualISD::NodeType | getExtendForAtomicOps ()const |
| Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND). | |
| virtualISD::NodeType | getExtendForAtomicCmpSwapArg ()const |
| Returns how the platform's atomic compare and swap expects its comparison value to be extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND). | |
| virtualbool | shouldNormalizeToSelectSequence (LLVMContext &Context,EVT VT)const |
| Returns true if we should normalize select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely that it saves us from materializing N0 and N1 in an integer register. | |
| virtualbool | isProfitableToCombineMinNumMaxNum (EVT VT)const |
| virtualbool | convertSelectOfConstantsToMath (EVT VT)const |
| Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops with the condition value. | |
| virtualbool | decomposeMulByConstant (LLVMContext &Context,EVT VT,SDValueC)const |
| Return true if it is profitable to transform an integer multiplication-by-constant into simpler operations like shifts and adds. | |
| virtualbool | isMulAddWithConstProfitable (SDValue AddNode,SDValue ConstNode)const |
| Return true if it may be profitable to transform (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2). | |
| virtualbool | shouldUseStrictFP_TO_INT (EVT FpVT,EVT IntVT,bool IsSigned)const |
| Return true if it is more correct/profitable to use strict FP_TO_INT conversion operations - canonicalizing the FP source value instead of converting all cases and then selecting based on value. | |
| bool | isBeneficialToExpandPowI (int64_tExponent,bool OptForSize)const |
| Return true if it is beneficial to expand an @llvm.powi. | |
| virtualbool | getAddrModeArguments (constIntrinsicInst *,SmallVectorImpl<Value * > &,Type *&)const |
| CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the address. | |
| virtualbool | isLegalAddressingMode (constDataLayout &DL,constAddrMode &AM,Type *Ty,unsigned AddrSpace,Instruction *I=nullptr)const |
| Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type. | |
| virtualbool | addressingModeSupportsTLS (constGlobalValue &)const |
| Returns true if the targets addressing mode can target thread local storage (TLS). | |
| virtual int64_t | getPreferredLargeGEPBaseOffset (int64_t MinOffset, int64_t MaxOffset)const |
| Return the prefered common base offset. | |
| virtualbool | isLegalICmpImmediate (int64_t)const |
| Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register. | |
| virtualbool | isLegalAddImmediate (int64_t)const |
| Return true if the specified immediate is legal add immediate, that is the target has add instructions which can add a register with the immediate without having to materialize the immediate into a register. | |
| virtualbool | isLegalAddScalableImmediate (int64_t)const |
| Return true if adding the specified scalable immediate is legal, that is the target has add instructions which can add a register with the immediate (multiplied by vscale) without having to materialize the immediate into a register. | |
| virtualbool | isLegalStoreImmediate (int64_tValue)const |
| Return true if the specified immediate is legal for the value input of a store instruction. | |
| virtualType * | shouldConvertSplatType (ShuffleVectorInst *SVI)const |
| Given a shuffle vector SVI representing a vector splat, return a new scalar type of size equal to SVI's scalar type if the new type is more profitable. | |
| virtualbool | shouldConvertPhiType (Type *From,Type *To)const |
| Given a set in interconnected phis of type 'From' that are loaded/stored or bitcast to type 'To', return true if the set should be converted to 'To'. | |
| virtualbool | isCommutativeBinOp (unsigned Opcode)const |
| Returns true if the opcode is a commutative binary operation. | |
| virtualbool | isBinOp (unsigned Opcode)const |
| Return true if the node is a math/logic binary operator. | |
| virtualbool | isTruncateFree (Type *FromTy,Type *ToTy)const |
| Return true if it's free to truncate a value of type FromTy to type ToTy. | |
| virtualbool | allowTruncateForTailCall (Type *FromTy,Type *ToTy)const |
| Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail position. | |
| virtualbool | isTruncateFree (EVT FromVT,EVT ToVT)const |
| virtualbool | isTruncateFree (LLT FromTy,LLT ToTy,LLVMContext &Ctx)const |
| virtualbool | isTruncateFree (SDValue Val,EVT VT2)const |
| Return true if truncating the specific node Val to type VT2 is free. | |
| virtualbool | isProfitableToHoist (Instruction *I)const |
| bool | isExtFree (constInstruction *I)const |
Return true if the extension represented byI is free. | |
| bool | isExtLoad (constLoadInst *Load,constInstruction *Ext,constDataLayout &DL)const |
Return true ifLoad andExt can form an ExtLoad. | |
| virtualbool | isZExtFree (Type *FromTy,Type *ToTy)const |
| Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the value to ToTy in the result register. | |
| virtualbool | isZExtFree (EVT FromTy,EVT ToTy)const |
| virtualbool | isZExtFree (LLT FromTy,LLT ToTy,LLVMContext &Ctx)const |
| virtualbool | isZExtFree (SDValue Val,EVT VT2)const |
| Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicitly zero-extended such asARM ldrb / ldrh or because it's folded such asX86 zero-extending loads). | |
| virtualbool | isSExtCheaperThanZExt (EVT FromTy,EVT ToTy)const |
| Return true if sign-extension from FromTy to ToTy is cheaper than zero-extension. | |
| virtualbool | signExtendConstant (constConstantInt *C)const |
| Return true if this constant should be sign extended when promoting to a larger type. | |
| virtualbool | optimizeExtendOrTruncateConversion (Instruction *I,Loop *L,constTargetTransformInfo &TTI)const |
| Try to optimize extending or truncating conversion instructions (like zext, trunc, fptoui, uitofp) for the target. | |
| virtualbool | hasPairedLoad (EVT,Align &)const |
| Return true if the target supplies and combines to a paired load two loaded values of type LoadedType next to each other in memory. | |
| virtualbool | hasVectorBlend ()const |
| Return true if the target has a vector blend instruction. | |
| virtualunsigned | getMaxSupportedInterleaveFactor ()const |
| Get the maximum supported factor for interleaved memory accesses. | |
| virtualbool | lowerInterleavedLoad (LoadInst *LI,ArrayRef<ShuffleVectorInst * > Shuffles,ArrayRef<unsigned > Indices,unsigned Factor)const |
| Lower an interleaved load to target specific intrinsics. | |
| virtualbool | lowerInterleavedStore (StoreInst *SI,ShuffleVectorInst *SVI,unsigned Factor)const |
| Lower an interleaved store to target specific intrinsics. | |
| virtualbool | lowerDeinterleaveIntrinsicToLoad (LoadInst *LI,ArrayRef<Value * > DeinterleaveValues)const |
| Lower a deinterleave intrinsic to a target specific load intrinsic. | |
| virtualbool | lowerInterleaveIntrinsicToStore (StoreInst *SI,ArrayRef<Value * > InterleaveValues)const |
| Lower an interleave intrinsic to a target specific store intrinsic. | |
| virtualbool | isFPExtFree (EVT DestVT,EVT SrcVT)const |
| Return true if an fpext operation is free (for instance, because single-precision floating-point numbers are implicitly extended to double-precision). | |
| virtualbool | isFPExtFoldable (constMachineInstr &MI,unsigned Opcode,LLT DestTy,LLT SrcTy)const |
Return true if an fpext operation input to anOpcode operation is free (for instance, because half-precision floating-point numbers are implicitly extended to float-precision) for an FMA instruction. | |
| virtualbool | isFPExtFoldable (constSelectionDAG &DAG,unsigned Opcode,EVT DestVT,EVT SrcVT)const |
Return true if an fpext operation input to anOpcode operation is free (for instance, because half-precision floating-point numbers are implicitly extended to float-precision) for an FMA instruction. | |
| virtualbool | isVectorLoadExtDesirable (SDValue ExtVal)const |
| Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable. | |
| virtualbool | isFNegFree (EVT VT)const |
| Return true if an fneg operation is free to the point where it is never worthwhile to replace it with a bitwise operation. | |
| virtualbool | isFAbsFree (EVT VT)const |
| Return true if an fabs operation is free to the point where it is never worthwhile to replace it with a bitwise operation. | |
| virtualbool | isFMAFasterThanFMulAndFAdd (constMachineFunction &MF,EVT)const |
| Return true if an FMA operation is faster than a pair of fmul and fadd instructions. | |
| virtualbool | isFMAFasterThanFMulAndFAdd (constMachineFunction &MF,LLT)const |
| Return true if an FMA operation is faster than a pair of fmul and fadd instructions. | |
| virtualbool | isFMAFasterThanFMulAndFAdd (constFunction &F,Type *)const |
| IR version. | |
| virtualbool | isFMADLegal (constMachineInstr &MI,LLT Ty)const |
Returns true ifMI can be combined with another instruction to form TargetOpcode::G_FMAD. | |
| virtualbool | isFMADLegal (constSelectionDAG &DAG,constSDNode *N)const |
| Returns true if be combined with to form anISD::FMAD. | |
| virtualbool | generateFMAsInMachineCombiner (EVT VT,CodeGenOptLevel OptLevel)const |
| virtualbool | isNarrowingProfitable (SDNode *N,EVT SrcVT,EVT DestVT)const |
| Return true if it's profitable to narrow operations of type SrcVT to DestVT. | |
| virtualbool | shouldFoldSelectWithIdentityConstant (unsigned BinOpcode,EVT VT)const |
| Return true if pulling a binary operation into a select with an identity constant is profitable. | |
| virtualbool | shouldConvertConstantLoadToIntImm (constAPInt &Imm,Type *Ty)const |
| Return true if it is beneficial to convert a load of a constant to just the constant itself. | |
| virtualbool | isExtractSubvectorCheap (EVT ResVT,EVT SrcVT,unsignedIndex)const |
| Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type from this source type with this index. | |
| virtualbool | shouldScalarizeBinop (SDValue VecOp)const |
| Try to convert an extract element of a vector binary operation into an extract element followed by a scalar operation. | |
| virtualbool | isExtractVecEltCheap (EVT VT,unsignedIndex)const |
| Return true if extraction of a scalar element from the given vector type at the given index is cheap. | |
| virtualbool | shouldFormOverflowOp (unsigned Opcode,EVT VT,bool MathUsed)const |
| Try to convert math with an overflow comparison into the corresponding DAG node operation. | |
| virtualbool | aggressivelyPreferBuildVectorSources (EVT VecVT)const |
| virtualbool | shouldConsiderGEPOffsetSplit ()const |
| virtualbool | shouldAvoidTransformToShift (EVT VT,unsigned Amount)const |
| Return true if creating a shift of the type by the given amount is not profitable. | |
| virtualbool | shouldFoldSelectWithSingleBitTest (EVT VT,constAPInt &AndMask)const |
| virtualbool | shouldKeepZExtForFP16Conv ()const |
| Does this target require the clearing of high-order bits in a register passed to the fp16 to fp conversion library function. | |
| virtualbool | shouldConvertFpToSat (unsignedOp,EVT FPVT,EVT VT)const |
| Should we generate fp_to_si_sat and fp_to_ui_sat from type FPVT to type VT from min(max(fptoi)) saturation patterns. | |
| virtualbool | shouldExpandCmpUsingSelects (EVT VT)const |
| Should we expand [US]CMP nodes using two selects and two compares, or by doing arithmetic on boolean types. | |
| virtualbool | isComplexDeinterleavingSupported ()const |
| Does this target support complex deinterleaving. | |
| virtualbool | isComplexDeinterleavingOperationSupported (ComplexDeinterleavingOperationOperation,Type *Ty)const |
| Does this target support complex deinterleaving with the given operation and type. | |
| virtualValue * | createComplexDeinterleavingIR (IRBuilderBase &B,ComplexDeinterleavingOperation OperationType,ComplexDeinterleavingRotation Rotation,Value *InputA,Value *InputB,Value *Accumulator=nullptr)const |
| Create the IR node for the given complex deinterleaving operation. | |
| void | setLibcallName (RTLIB::Libcall Call,constchar *Name) |
| Rename the default libcall routine name for the specified libcall. | |
| void | setLibcallName (ArrayRef<RTLIB::Libcall > Calls,constchar *Name) |
| constchar * | getLibcallName (RTLIB::Libcall Call)const |
| Get the libcall routine name for the specified libcall. | |
| void | setCmpLibcallCC (RTLIB::Libcall Call,ISD::CondCodeCC) |
| Override the default CondCode to be used to test the result of the comparison libcall against zero. | |
| ISD::CondCode | getCmpLibcallCC (RTLIB::Libcall Call)const |
| Get the CondCode that's to be used to test the result of the comparison libcall against zero. | |
| void | setLibcallCallingConv (RTLIB::Libcall Call,CallingConv::IDCC) |
| Set theCallingConv that should be used for the specified libcall. | |
| CallingConv::ID | getLibcallCallingConv (RTLIB::Libcall Call)const |
| Get theCallingConv that should be used for the specified libcall. | |
| virtual void | finalizeLowering (MachineFunction &MF)const |
| Execute target specific actions to finalize target lowering. | |
| virtualbool | shouldLocalize (constMachineInstr &MI,constTargetTransformInfo *TTI)const |
Check whether or notMI needs to be moved close to its uses. | |
Helpers for TargetTransformInfo implementations | |
| int | InstructionOpcodeToISD (unsigned Opcode)const |
| Get theISD node that corresponds to theInstruction class opcode. | |
| int | IntrinsicIDToISD (Intrinsic::IDID)const |
| Get theISD node that corresponds to theIntrinsic ID. | |
Helpers for atomic expansion. | |
| unsigned | getMaxAtomicSizeInBitsSupported ()const |
| Returns the maximum atomic operation size (in bits) supported by the backend. | |
| unsigned | getMaxDivRemBitWidthSupported ()const |
| Returns the size in bits of the maximum div/rem the backend supports. | |
| unsigned | getMaxLargeFPConvertBitWidthSupported ()const |
| Returns the size in bits of the maximum larget fp convert the backend supports. | |
| unsigned | getMinCmpXchgSizeInBits ()const |
| Returns the size of the smallest cmpxchg or ll/sc instruction the backend supports. | |
| bool | supportsUnalignedAtomics ()const |
| Whether the target supports unaligned atomic operations. | |
| virtualbool | shouldInsertFencesForAtomic (constInstruction *I)const |
| WhetherAtomicExpandPass should automatically insert fences and reduce ordering for this atomic. | |
| virtualbool | shouldInsertTrailingFenceForAtomicStore (constInstruction *I)const |
| WhetherAtomicExpandPass should automatically insert a trailing fence without reducing the ordering for this atomic. | |
| virtualValue * | emitLoadLinked (IRBuilderBase &Builder,Type *ValueTy,Value *Addr,AtomicOrdering Ord)const |
| Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type. | |
| virtualValue * | emitStoreConditional (IRBuilderBase &Builder,Value *Val,Value *Addr,AtomicOrdering Ord)const |
| Perform a store-conditional operation to Addr. | |
| virtualValue * | emitMaskedAtomicRMWIntrinsic (IRBuilderBase &Builder,AtomicRMWInst *AI,Value *AlignedAddr,Value *Incr,Value *Mask,Value *ShiftAmt,AtomicOrdering Ord)const |
| Perform a masked atomicrmw using a target-specific intrinsic. | |
| virtual void | emitExpandAtomicRMW (AtomicRMWInst *AI)const |
| Perform a atomicrmw expansion using a target-specific way. | |
| virtual void | emitExpandAtomicCmpXchg (AtomicCmpXchgInst *CI)const |
| Perform a cmpxchg expansion using a target-specific method. | |
| virtual void | emitBitTestAtomicRMWIntrinsic (AtomicRMWInst *AI)const |
| Perform a bit test atomicrmw using a target-specific intrinsic. | |
| virtual void | emitCmpArithAtomicRMWIntrinsic (AtomicRMWInst *AI)const |
| Perform a atomicrmw which the result is only used by comparison, using a target-specific intrinsic. | |
| virtualValue * | emitMaskedAtomicCmpXchgIntrinsic (IRBuilderBase &Builder,AtomicCmpXchgInst *CI,Value *AlignedAddr,Value *CmpVal,Value *NewVal,Value *Mask,AtomicOrdering Ord)const |
| Perform a masked cmpxchg using a target-specific intrinsic. | |
KCFI check lowering. | |
| virtualMachineInstr * | EmitKCFICheck (MachineBasicBlock &MBB,MachineBasicBlock::instr_iterator &MBBI,constTargetInstrInfo *TII)const |
| virtualInstruction * | emitLeadingFence (IRBuilderBase &Builder,Instruction *Inst,AtomicOrdering Ord)const |
| Inserts in the IR a target-specific intrinsic specifying a fence. | |
| virtualInstruction * | emitTrailingFence (IRBuilderBase &Builder,Instruction *Inst,AtomicOrdering Ord)const |
Static Public Member Functions | |
| staticISD::NodeType | getExtendForContent (BooleanContentContent) |
Protected Member Functions | |
| void | initActions () |
| Initialize all of the actions to default values. | |
| Value * | getDefaultSafeStackPointerLocation (IRBuilderBase &IRB,bool UseTLS)const |
| void | setBooleanContents (BooleanContent Ty) |
| Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type. | |
| void | setBooleanContents (BooleanContent IntTy,BooleanContent FloatTy) |
| Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type. | |
| void | setBooleanVectorContents (BooleanContent Ty) |
| Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider type. | |
| void | setSchedulingPreference (Sched::Preference Pref) |
| Specify the target scheduling preference. | |
| void | setMinimumJumpTableEntries (unsigned Val) |
| Indicate the minimum number of blocks to generate jump tables. | |
| void | setMaximumJumpTableSize (unsigned) |
| Indicate the maximum number of entries in jump tables. | |
| void | setStackPointerRegisterToSaveRestore (Register R) |
| If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore. | |
| void | setHasMultipleConditionRegisters (bool hasManyRegs=true) |
| Tells the code generator that the target has multiple (allocatable) condition registers that can be used to store the results of comparisons for use by selects and conditional branches. | |
| void | setHasExtractBitsInsn (bool hasExtractInsn=true) |
| Tells the code generator that the target has BitExtract instructions. | |
| void | setJumpIsExpensive (bool isExpensive=true) |
| Tells the code generator not to expand logic operations on comparison predicates into separate sequences that increase the amount of flow control. | |
| void | addBypassSlowDiv (unsigned int SlowBitWidth,unsigned int FastBitWidth) |
| Tells the code generator which bitwidths to bypass. | |
| void | addRegisterClass (MVT VT,constTargetRegisterClass *RC) |
| Add the specified register class as an available regclass for the specified value type. | |
| virtual std::pair<constTargetRegisterClass *,uint8_t > | findRepresentativeClass (constTargetRegisterInfo *TRI,MVT VT)const |
| Return the largest legal super-reg register class of the register class for the specified type and its associated "cost". | |
| void | computeRegisterProperties (constTargetRegisterInfo *TRI) |
| Once all of the register classes are added, this allows us to compute derived properties we expose. | |
| void | setOperationAction (unsignedOp,MVT VT,LegalizeAction Action) |
| Indicate that the specified operation does not work with the specified type and indicate what to do about it. | |
| void | setOperationAction (ArrayRef<unsigned > Ops,MVT VT,LegalizeAction Action) |
| void | setOperationAction (ArrayRef<unsigned > Ops,ArrayRef<MVT > VTs,LegalizeAction Action) |
| void | setLoadExtAction (unsigned ExtType,MVT ValVT,MVT MemVT,LegalizeAction Action) |
| Indicate that the specified load with extension does not work with the specified type and indicate what to do about it. | |
| void | setLoadExtAction (ArrayRef<unsigned > ExtTypes,MVT ValVT,MVT MemVT,LegalizeAction Action) |
| void | setLoadExtAction (ArrayRef<unsigned > ExtTypes,MVT ValVT,ArrayRef<MVT > MemVTs,LegalizeAction Action) |
| void | setAtomicLoadExtAction (unsigned ExtType,MVT ValVT,MVT MemVT,LegalizeAction Action) |
| Let target indicate that an extending atomic load of the specified type is legal. | |
| void | setAtomicLoadExtAction (ArrayRef<unsigned > ExtTypes,MVT ValVT,MVT MemVT,LegalizeAction Action) |
| void | setAtomicLoadExtAction (ArrayRef<unsigned > ExtTypes,MVT ValVT,ArrayRef<MVT > MemVTs,LegalizeAction Action) |
| void | setTruncStoreAction (MVT ValVT,MVT MemVT,LegalizeAction Action) |
| Indicate that the specified truncating store does not work with the specified type and indicate what to do about it. | |
| void | setIndexedLoadAction (ArrayRef<unsigned > IdxModes,MVT VT,LegalizeAction Action) |
| Indicate that the specified indexed load does or does not work with the specified type and indicate what to do abort it. | |
| void | setIndexedLoadAction (ArrayRef<unsigned > IdxModes,ArrayRef<MVT > VTs,LegalizeAction Action) |
| void | setIndexedStoreAction (ArrayRef<unsigned > IdxModes,MVT VT,LegalizeAction Action) |
| Indicate that the specified indexed store does or does not work with the specified type and indicate what to do about it. | |
| void | setIndexedStoreAction (ArrayRef<unsigned > IdxModes,ArrayRef<MVT > VTs,LegalizeAction Action) |
| void | setIndexedMaskedLoadAction (unsigned IdxMode,MVT VT,LegalizeAction Action) |
| Indicate that the specified indexed masked load does or does not work with the specified type and indicate what to do about it. | |
| void | setIndexedMaskedStoreAction (unsigned IdxMode,MVT VT,LegalizeAction Action) |
| Indicate that the specified indexed masked store does or does not work with the specified type and indicate what to do about it. | |
| void | setCondCodeAction (ArrayRef<ISD::CondCode > CCs,MVT VT,LegalizeAction Action) |
| Indicate that the specified condition code is or isn't supported on the target and indicate what to do about it. | |
| void | setCondCodeAction (ArrayRef<ISD::CondCode > CCs,ArrayRef<MVT > VTs,LegalizeAction Action) |
| void | AddPromotedToType (unsigned Opc,MVT OrigVT,MVT DestVT) |
| If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/fp until it can find one that works. | |
| void | setOperationPromotedToType (unsigned Opc,MVT OrigVT,MVT DestVT) |
| Convenience method to set an operation to Promote and specify the type in a single call. | |
| void | setOperationPromotedToType (ArrayRef<unsigned > Ops,MVT OrigVT,MVT DestVT) |
| void | setTargetDAGCombine (ArrayRef<ISD::NodeType > NTs) |
| Targets should invoke this method for each target independent node that they want to provide a custom DAG combiner for by implementing the PerformDAGCombine virtual method. | |
| void | setMinFunctionAlignment (Align Alignment) |
| Set the target's minimum function alignment. | |
| void | setPrefFunctionAlignment (Align Alignment) |
| Set the target's preferred function alignment. | |
| void | setPrefLoopAlignment (Align Alignment) |
| Set the target's preferred loop alignment. | |
| void | setMaxBytesForAlignment (unsigned MaxBytes) |
| void | setMinStackArgumentAlignment (Align Alignment) |
| Set the minimum stack alignment of an argument. | |
| void | setMaxAtomicSizeInBitsSupported (unsigned SizeInBits) |
| Set the maximum atomic operation size supported by the backend. | |
| void | setMaxDivRemBitWidthSupported (unsigned SizeInBits) |
| Set the size in bits of the maximum div/rem the backend supports. | |
| void | setMaxLargeFPConvertBitWidthSupported (unsigned SizeInBits) |
| Set the size in bits of the maximum fp convert the backend supports. | |
| void | setMinCmpXchgSizeInBits (unsigned SizeInBits) |
| Sets the minimum cmpxchg or ll/sc size supported by the backend. | |
| void | setSupportsUnalignedAtomics (bool UnalignedSupported) |
| Sets whether unaligned atomic operations are supported. | |
| virtualbool | isExtFreeImpl (constInstruction *I)const |
Return true if the extension represented byI is free. | |
| bool | isLegalRC (constTargetRegisterInfo &TRI,constTargetRegisterClass &RC)const |
| Return true if the value types that can be represented by the specified register class are all legal. | |
| MachineBasicBlock * | emitPatchPoint (MachineInstr &MI,MachineBasicBlock *MBB)const |
| Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that is recognized by PrologEpilogInserter. | |
Protected Attributes | |
| unsigned | GatherAllAliasesMaxDepth |
| Depth that GatherAllAliases should continue looking for chain dependencies when trying to find a more preferable chain. | |
| unsigned | MaxStoresPerMemset |
| Specify maximum number of store instructions per memset call. | |
| unsigned | MaxStoresPerMemsetOptSize |
| Likewise for functions with the OptSize attribute. | |
| unsigned | MaxStoresPerMemcpy |
| Specify maximum number of store instructions per memcpy call. | |
| unsigned | MaxStoresPerMemcpyOptSize |
| Likewise for functions with the OptSize attribute. | |
| unsigned | MaxGluedStoresPerMemcpy = 0 |
| Specify max number of store instructions to glue in inlined memcpy. | |
| unsigned | MaxLoadsPerMemcmp |
| Specify maximum number of load instructions per memcmp call. | |
| unsigned | MaxLoadsPerMemcmpOptSize |
| Likewise for functions with the OptSize attribute. | |
| unsigned | MaxStoresPerMemmove |
| Specify maximum number of store instructions per memmove call. | |
| unsigned | MaxStoresPerMemmoveOptSize |
| Likewise for functions with the OptSize attribute. | |
| bool | PredictableSelectIsExpensive |
| Tells the code generator that select is more expensive than a branch if the branch is usually predicted right. | |
| bool | EnableExtLdPromotion |
| bool | IsStrictFPEnabled |
Detailed Description
This base class forTargetLowering contains the SelectionDAG-independent parts that can be used from the rest of CodeGen.
Definition at line195 of fileTargetLowering.h.
Member Typedef Documentation
◆ ArgListTy
| usingllvm::TargetLoweringBase::ArgListTy = std::vector<ArgListEntry> |
Definition at line329 of fileTargetLowering.h.
◆ LegalizeKind
| usingllvm::TargetLoweringBase::LegalizeKind = std::pair<LegalizeTypeAction,EVT> |
LegalizeKind holds the legalization kind that needs to happen toEVT in order to type-legalize it.
Definition at line231 of fileTargetLowering.h.
Member Enumeration Documentation
◆ AndOrSETCCFoldKind
Enum of different potentially desirable ways to fold (and/or (setcc ...), (setcc ...)).
| Enumerator | |
|---|---|
| None | |
| AddAnd | |
| NotAnd | |
| ABS | |
Definition at line290 of fileTargetLowering.h.
◆ AtomicExpansionKind
| strong |
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
Exists because different targets have different levels of support for these atomic instructions, and also have different options w.r.t. what they should expand to.
| Enumerator | |
|---|---|
| None | |
| CastToInteger | |
| LLSC | |
| LLOnly | |
| CmpXChg | |
| MaskedIntrinsic | |
| BitTestIntrinsic | |
| CmpArithIntrinsic | |
| Expand | |
| NotAtomic | |
Definition at line253 of fileTargetLowering.h.
◆ BooleanContent
Enum that describes how the target represents true/false values.
| Enumerator | |
|---|---|
| UndefinedBooleanContent | |
| ZeroOrOneBooleanContent | |
| ZeroOrNegativeOneBooleanContent | |
Definition at line234 of fileTargetLowering.h.
◆ LegalizeAction
This enum indicates whether operations are valid for a target, and if not, what action should be used to make them valid.
| Enumerator | |
|---|---|
| Legal | |
| Promote | |
| Expand | |
| LibCall | |
| Custom | |
Definition at line199 of fileTargetLowering.h.
◆ LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to make them valid.
Definition at line209 of fileTargetLowering.h.
◆ MulExpansionKind
| strong |
Enum that specifies when a multiplication should be expanded.
| Enumerator | |
|---|---|
| Always | |
| OnlyLegalOrCustom | |
Definition at line275 of fileTargetLowering.h.
◆ NegatibleCost
| strong |
Enum that specifies when a float negation is beneficial.
| Enumerator | |
|---|---|
| Cheaper | |
| Neutral | |
| Expensive | |
Definition at line282 of fileTargetLowering.h.
◆ ReciprocalEstimate
Reciprocal estimate status values used by the functions below.
| Enumerator | |
|---|---|
| Unspecified | |
| Disabled | |
| Enabled | |
Definition at line573 of fileTargetLowering.h.
◆ SelectSupportKind
Enum that describes what type of support for selects the target has.
| Enumerator | |
|---|---|
| ScalarValSelect | |
| ScalarCondVectorVal | |
| VectorMaskSelect | |
Definition at line241 of fileTargetLowering.h.
◆ ShiftLegalizationStrategy
| strong |
Return the preferred strategy to legalize tihs SHIFT instruction, withExpansionFactor being the recursion depth - how many expansion needed.
| Enumerator | |
|---|---|
| ExpandToParts | |
| ExpandThroughStack | |
| LowerToLibcall | |
Definition at line1077 of fileTargetLowering.h.
Constructor & Destructor Documentation
◆ TargetLoweringBase()[1/2]
| explicit |
NOTE: TheTargetMachine owns TLOF.
Definition at line620 of fileTargetLoweringBase.cpp.
ReferencesDisableStrictNodeMutation,EnableExtLdPromotion,GatherAllAliasesMaxDepth,llvm::Sched::ILP,initActions(),llvm::RTLIB::initCmpLibcallCCs(),IsStrictFPEnabled,JumpIsExpensiveOverride,llvm::IntegerType::MAX_INT_BITS,MaxGluedStoresPerMemcpy,MaxLoadsPerMemcmp,MaxLoadsPerMemcmpOptSize,MaxStoresPerMemcpy,MaxStoresPerMemcpyOptSize,MaxStoresPerMemmove,MaxStoresPerMemmoveOptSize,MaxStoresPerMemset,MaxStoresPerMemsetOptSize,PredictableSelectIsExpensive, andUndefinedBooleanContent.
◆ TargetLoweringBase()[2/2]
| delete |
◆ ~TargetLoweringBase()
| virtualdefault |
Member Function Documentation
◆ addBypassSlowDiv()
| inlineprotected |
Tells the code generator which bitwidths to bypass.
Definition at line2538 of fileTargetLowering.h.
Referenced byllvm::AMDGPUTargetLowering::AMDGPUTargetLowering(),llvm::NVPTXTargetLowering::NVPTXTargetLowering(), andllvm::X86TargetLowering::X86TargetLowering().
◆ AddPromotedToType()
| inlineprotected |
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/fp until it can find one that works.
If that default is insufficient, this method can be used by the target to override the default.
Definition at line2710 of fileTargetLowering.h.
Referencesllvm::MVT::SimpleTy.
Referenced byllvm::AMDGPUTargetLowering::AMDGPUTargetLowering(),llvm::HexagonTargetLowering::HexagonTargetLowering(),initActions(),llvm::MipsTargetLowering::MipsTargetLowering(),llvm::NVPTXTargetLowering::NVPTXTargetLowering(),llvm::PPCTargetLowering::PPCTargetLowering(),setOperationPromotedToType(), andllvm::SITargetLowering::SITargetLowering().
◆ addRegisterClass()
| inlineprotected |
Add the specified register class as an available regclass for the specified value type.
This indicates the selector can handle values of that class natively.
Definition at line2545 of fileTargetLowering.h.
Referencesassert(), andllvm::MVT::SimpleTy.
Referenced byllvm::AArch64TargetLowering::AArch64TargetLowering(),llvm::MipsSETargetLowering::addMSAFloatType(),llvm::MipsSETargetLowering::addMSAIntType(),llvm::ARCTargetLowering::ARCTargetLowering(),llvm::ARMTargetLowering::ARMTargetLowering(),llvm::AVRTargetLowering::AVRTargetLowering(),llvm::BPFTargetLowering::BPFTargetLowering(),llvm::CSKYTargetLowering::CSKYTargetLowering(),llvm::HexagonTargetLowering::HexagonTargetLowering(),llvm::LanaiTargetLowering::LanaiTargetLowering(),llvm::LoongArchTargetLowering::LoongArchTargetLowering(),llvm::M68kTargetLowering::M68kTargetLowering(),llvm::Mips16TargetLowering::Mips16TargetLowering(),llvm::MipsSETargetLowering::MipsSETargetLowering(),llvm::MSP430TargetLowering::MSP430TargetLowering(),llvm::NVPTXTargetLowering::NVPTXTargetLowering(),llvm::PPCTargetLowering::PPCTargetLowering(),llvm::R600TargetLowering::R600TargetLowering(),llvm::RISCVTargetLowering::RISCVTargetLowering(),llvm::SITargetLowering::SITargetLowering(),llvm::SparcTargetLowering::SparcTargetLowering(),llvm::SystemZTargetLowering::SystemZTargetLowering(),llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering(),llvm::X86TargetLowering::X86TargetLowering(),llvm::XCoreTargetLowering::XCoreTargetLowering(), andllvm::XtensaTargetLowering::XtensaTargetLowering().
◆ addressingModeSupportsTLS()
| inlinevirtual |
Returns true if the targets addressing mode can target thread local storage (TLS).
Reimplemented inllvm::X86TargetLowering.
Definition at line2841 of fileTargetLowering.h.
◆ aggressivelyPreferBuildVectorSources()
| inlinevirtual |
Reimplemented inllvm::AMDGPUTargetLowering, andllvm::NVPTXTargetLowering.
Definition at line3373 of fileTargetLowering.h.
◆ alignLoopsWithOptSize()
| inlinevirtual |
Should loops be aligned even when the function is marked OptSize (but not MinSize).
Reimplemented inllvm::ARMTargetLowering.
Definition at line2058 of fileTargetLowering.h.
◆ allowsMemoryAccess()[1/3]
| bool TargetLoweringBase::allowsMemoryAccess | ( | LLVMContext & | Context, |
| constDataLayout & | DL, | ||
| EVT | VT, | ||
| constMachineMemOperand & | MMO, | ||
| unsigned * | Fast =nullptr | ||
| ) | const |
Return true if the target supports a memory access of this type for the givenMachineMemOperand.
If the access is allowed, the optional final parameter returns the relative access speed (as defined by the target).
Definition at line1744 of fileTargetLoweringBase.cpp.
ReferencesallowsMemoryAccess(),DL,llvm::CallingConv::Fast,llvm::MachineMemOperand::getAddrSpace(),llvm::MachineMemOperand::getAlign(), andllvm::MachineMemOperand::getFlags().
◆ allowsMemoryAccess()[2/3]
| virtual |
Return true if the target supports a memory access of this type for the given address space and alignment.
If the access is allowed, the optional final parameter returns the relative speed of the access (as defined by the target).
Reimplemented inllvm::HexagonTargetLowering, andllvm::X86TargetLowering.
Definition at line1735 of fileTargetLoweringBase.cpp.
ReferencesallowsMemoryAccessForAlignment(),DL, andllvm::CallingConv::Fast.
Referenced byallowsMemoryAccess(),llvm::HexagonTargetLowering::allowsMemoryAccess(),combineLoad(),combineStore(),isLoadBitCastBeneficial(),llvm::LegalizerHelper::lowerLoad(),llvm::LegalizerHelper::lowerStore(),ShrinkLoadReplaceStoreWithStore(), andllvm::TargetLowering::SimplifySetCC().
◆ allowsMemoryAccess()[3/3]
| bool TargetLoweringBase::allowsMemoryAccess | ( | LLVMContext & | Context, |
| constDataLayout & | DL, | ||
| LLT | Ty, | ||
| constMachineMemOperand & | MMO, | ||
| unsigned * | Fast =nullptr | ||
| ) | const |
LLT handling variant.
Definition at line1752 of fileTargetLoweringBase.cpp.
ReferencesallowsMemoryAccess(),DL,llvm::CallingConv::Fast,llvm::MachineMemOperand::getAddrSpace(),llvm::MachineMemOperand::getAlign(),llvm::getApproximateEVTForLLT(), andllvm::MachineMemOperand::getFlags().
◆ allowsMemoryAccessForAlignment()[1/2]
| bool TargetLoweringBase::allowsMemoryAccessForAlignment | ( | LLVMContext & | Context, |
| constDataLayout & | DL, | ||
| EVT | VT, | ||
| constMachineMemOperand & | MMO, | ||
| unsigned * | Fast =nullptr | ||
| ) | const |
Return true if the memory access of this type is aligned or if the target allows this specific unaligned access for the givenMachineMemOperand.
If the access is allowed, the optional final parameter returns a relative speed of the access (as defined by the target).
Definition at line1728 of fileTargetLoweringBase.cpp.
ReferencesallowsMemoryAccessForAlignment(),DL,llvm::CallingConv::Fast,llvm::MachineMemOperand::getAddrSpace(),llvm::MachineMemOperand::getAlign(), andllvm::MachineMemOperand::getFlags().
◆ allowsMemoryAccessForAlignment()[2/2]
| bool TargetLoweringBase::allowsMemoryAccessForAlignment | ( | LLVMContext & | Context, |
| constDataLayout & | DL, | ||
| EVT | VT, | ||
| unsigned | AddrSpace =0, | ||
| Align | Alignment =Align(1), | ||
| MachineMemOperand::Flags | Flags =MachineMemOperand::MONone, | ||
| unsigned * | Fast =nullptr | ||
| ) | const |
This function returns true if the memory access is aligned or if the target allows this specific unaligned memory access.
If the access is allowed, the optional final parameter returns a relative speed of the access (as defined by the target).
Definition at line1708 of fileTargetLoweringBase.cpp.
ReferencesallowsMisalignedMemoryAccesses(),DL,llvm::CallingConv::Fast,llvm::EVT::getTypeForEVT(), andllvm::EVT::isZeroSized().
Referenced byallowsMemoryAccess(),allowsMemoryAccessForAlignment(),llvm::RISCVTargetLowering::isLegalInterleavedAccessType(),llvm::AMDGPUTargetLowering::isLoadBitCastBeneficial(),llvm::HexagonTargetLowering::LowerUnalignedLoad(), andllvm::RISCVTargetLowering::PerformDAGCombine().
◆ allowsMisalignedMemoryAccesses()[1/2]
| inlinevirtual |
Determine if the target supports unaligned memory accesses.
This function returns true if the target allows unaligned memory accesses of the specified type in the given address space. If true, it also returns a relative speed of the unaligned memory access in the last argument by reference. The higher the speed number the faster the operation comparing to a number returned by another such call. This is used, for example, in situations where an array copy/move/set is converted to a sequence of store operations. Its use helps to ensure that such replacements don't generate code that causes an alignment error (trap) on the target machine.
Reimplemented inllvm::ARMTargetLowering,llvm::HexagonTargetLowering,llvm::Mips16TargetLowering,llvm::PPCTargetLowering,llvm::AArch64TargetLowering,llvm::LoongArchTargetLowering,llvm::RISCVTargetLowering,llvm::VETargetLowering,llvm::SystemZTargetLowering,llvm::X86TargetLowering,llvm::R600TargetLowering,llvm::SITargetLowering, andllvm::MipsSETargetLowering.
Definition at line1918 of fileTargetLowering.h.
Referenced byallowsMemoryAccessForAlignment(),llvm::BasicTTIImplBase< T >::allowsMisalignedMemoryAccesses(),findGISelOptimalMemOpLowering(),llvm::TargetLowering::findOptimalMemOpLowering(),llvm::AMDGPUTargetLowering::performLoadCombine(), andllvm::AMDGPUTargetLowering::performStoreCombine().
◆ allowsMisalignedMemoryAccesses()[2/2]
| inlinevirtual |
LLT handling variant.
Reimplemented inllvm::AArch64TargetLowering, andllvm::SITargetLowering.
Definition at line1926 of fileTargetLowering.h.
◆ allowTruncateForTailCall()
| inlinevirtual |
Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail position.
Typically this means that both results would be assigned to the same register or stack slot, but it could mean the target performs adequate checks of its own before proceeding with the tail call. Targets must return false when FromTy <= ToTy.
Reimplemented inllvm::SystemZTargetLowering,llvm::ARMTargetLowering,llvm::HexagonTargetLowering, andllvm::X86TargetLowering.
Definition at line2981 of fileTargetLowering.h.
Referenced bygetNoopInput().
◆ areJTsAllowed()
Return true if lowering to a jump table is allowed.
Reimplemented inllvm::SPIRVTargetLowering, andllvm::X86TargetLowering.
Definition at line1385 of fileTargetLowering.h.
Referencesllvm::ISD::BR_JT,llvm::ISD::BRIND,llvm::Function::getFnAttribute(),llvm::Attribute::getValueAsBool(), andisOperationLegalOrCustom().
Referenced byllvm::X86TargetLowering::areJTsAllowed(),llvm::SwitchCG::SwitchLowering::findJumpTables(), andllvm::BasicTTIImplBase< T >::getEstimatedNumberOfCaseClusters().
◆ areTwoSDNodeTargetMMOFlagsMergeable()
| inlinevirtual |
Return true if it is valid to merge the TargetMMOFlags in two SDNodes.
Reimplemented inllvm::RISCVTargetLowering.
Definition at line762 of fileTargetLowering.h.
◆ canCombineStoreAndExtract()
| inlinevirtual |
Return true if the target can combine store(extractelement VectorTy,Idx).
Cost[out] gives the cost of that transformation when this is true.
Reimplemented inllvm::ARMTargetLowering.
Definition at line951 of fileTargetLowering.h.
◆ canCombineTruncStore()
| inlinevirtual |
Reimplemented inllvm::R600TargetLowering.
Definition at line1526 of fileTargetLowering.h.
ReferencesisTruncStoreLegal(), andisTruncStoreLegalOrCustom().
◆ canMergeStoresTo()
| inlinevirtual |
Returns if it's reasonable to merge stores to MemVT size.
Reimplemented inllvm::AArch64TargetLowering,llvm::ARMTargetLowering,llvm::X86TargetLowering,llvm::R600TargetLowering, andllvm::SITargetLowering.
Definition at line701 of fileTargetLowering.h.
◆ canOpTrap()
Returns true if the operation can trap for the value type.
VT must be a legal type. By default, we optimistically assume most operations don't trap except for integer divide and remainder.
Definition at line905 of fileTargetLoweringBase.cpp.
Referencesassert(),isTypeLegal(),llvm::ISD::SDIV,llvm::ISD::SREM,llvm::ISD::UDIV, andllvm::ISD::UREM.
◆ computeRegisterProperties()
| protected |
Once all of the register classes are added, this allows us to compute derived properties we expose.
computeRegisterProperties - Once all of the register classes are added, this allows us to compute derived properties we expose.
Definition at line1275 of fileTargetLoweringBase.cpp.
Referencesassert(),findRepresentativeClass(),llvm::MVT::getFixedSizeInBits(),llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(),llvm::MVT::getPow2VectorType(),getPreferredVectorAction(),llvm::MVT::getScalarSizeInBits(),llvm::MVT::getVectorElementCount(),llvm::MVT::getVectorElementType(),getVectorTypeBreakdownMVT(),llvm::isPowerOf2_32(),llvm::MVT::isScalableVector(),isTypeLegal(),llvm_unreachable,llvm::TargetLoweringBase::ValueTypeActionImpl::setTypeAction(),softPromoteHalfType(),TRI,TypeExpandFloat,TypeExpandInteger,TypePromoteFloat,TypePromoteInteger,TypeScalarizeScalableVector,TypeScalarizeVector,TypeSoftenFloat,TypeSoftPromoteHalf,TypeSplitVector,TypeWidenVector,useFPRegsForHalfType(), andllvm::MVT::VALUETYPE_SIZE.
Referenced byllvm::AArch64TargetLowering::AArch64TargetLowering(),llvm::ARCTargetLowering::ARCTargetLowering(),llvm::ARMTargetLowering::ARMTargetLowering(),llvm::AVRTargetLowering::AVRTargetLowering(),llvm::BPFTargetLowering::BPFTargetLowering(),llvm::CSKYTargetLowering::CSKYTargetLowering(),llvm::HexagonTargetLowering::HexagonTargetLowering(),llvm::LanaiTargetLowering::LanaiTargetLowering(),llvm::LoongArchTargetLowering::LoongArchTargetLowering(),llvm::M68kTargetLowering::M68kTargetLowering(),llvm::Mips16TargetLowering::Mips16TargetLowering(),llvm::MipsSETargetLowering::MipsSETargetLowering(),llvm::MSP430TargetLowering::MSP430TargetLowering(),llvm::NVPTXTargetLowering::NVPTXTargetLowering(),llvm::PPCTargetLowering::PPCTargetLowering(),llvm::R600TargetLowering::R600TargetLowering(),llvm::RISCVTargetLowering::RISCVTargetLowering(),llvm::SITargetLowering::SITargetLowering(),llvm::SparcTargetLowering::SparcTargetLowering(),llvm::SystemZTargetLowering::SystemZTargetLowering(),llvm::VETargetLowering::VETargetLowering(),llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering(),llvm::X86TargetLowering::X86TargetLowering(),llvm::XCoreTargetLowering::XCoreTargetLowering(), andllvm::XtensaTargetLowering::XtensaTargetLowering().
◆ convertSelectOfConstantsToMath()
Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops with the condition value.
For example: select Cond, C1, C1-1 --> add (zext Cond), C1-1
Reimplemented inllvm::LoongArchTargetLowering,llvm::PPCTargetLowering,llvm::RISCVTargetLowering, andllvm::X86TargetLowering.
Definition at line2422 of fileTargetLowering.h.
Referenced byshouldConvertSelectOfConstantsToMath().
◆ convertSetCCLogicToBitwiseLogic()
Use bitwise logic to make pairs of compares more efficient.
For example: and (seteq A, B), (seteq C, D) --> seteq (or (xor A, B), (xor C, D)), 0 This should be true when it takes more than one instruction to lower setcc (cmp+set on x86 scalar), when bitwise ops are faster than logic on condition bits (crand on PowerPC), and/or when reducing cmp+br is a win.
Reimplemented inllvm::ARMTargetLowering,llvm::PPCTargetLowering,llvm::RISCVTargetLowering,llvm::SystemZTargetLowering, andllvm::X86TargetLowering.
Definition at line772 of fileTargetLowering.h.
◆ createComplexDeinterleavingIR()
| inlinevirtual |
Create the IR node for the given complex deinterleaving operation.
If one cannot be created using all the given inputs, nullptr should be returned.
Reimplemented inllvm::AArch64TargetLowering, andllvm::ARMTargetLowering.
Definition at line3423 of fileTargetLowering.h.
◆ decomposeMulByConstant()
| inlinevirtual |
Return true if it is profitable to transform an integer multiplication-by-constant into simpler operations like shifts and adds.
This may be true if the target does not directly support the multiplication operation for the specified type or the sequence of simpler ops is faster than the multiply.
Reimplemented inllvm::LoongArchTargetLowering,llvm::PPCTargetLowering,llvm::RISCVTargetLowering,llvm::X86TargetLowering, andllvm::XtensaTargetLowering.
Definition at line2431 of fileTargetLowering.h.
◆ emitAtomicCmpXchgNoStoreLLBalance()
| inlinevirtual |
Reimplemented inllvm::AArch64TargetLowering, andllvm::ARMTargetLowering.
Definition at line2295 of fileTargetLowering.h.
◆ emitBitTestAtomicRMWIntrinsic()
| inlinevirtual |
Perform a bit test atomicrmw using a target-specific intrinsic.
This represents the combined bit test intrinsic which will be lowered at a late stage by the backend.
Definition at line2226 of fileTargetLowering.h.
Referencesllvm_unreachable.
◆ emitCmpArithAtomicRMWIntrinsic()
| inlinevirtual |
Perform a atomicrmw which the result is only used by comparison, using a target-specific intrinsic.
This represents the combined atomic and compare intrinsic which will be lowered at a late stage by the backend.
Definition at line2234 of fileTargetLowering.h.
Referencesllvm_unreachable.
◆ emitExpandAtomicCmpXchg()
| inlinevirtual |
Perform a cmpxchg expansion using a target-specific method.
Reimplemented inllvm::SITargetLowering.
Definition at line2219 of fileTargetLowering.h.
Referencesllvm_unreachable.
◆ emitExpandAtomicRMW()
| inlinevirtual |
Perform a atomicrmw expansion using a target-specific way.
This is expected to be called when masked atomicrmw and bit test atomicrmw don't work, and the target supports another way to lower atomicrmw.
Reimplemented inllvm::SITargetLowering, andllvm::LoongArchTargetLowering.
Definition at line2213 of fileTargetLowering.h.
Referencesllvm_unreachable.
◆ EmitKCFICheck()
| inlinevirtual |
Reimplemented inllvm::AArch64TargetLowering,llvm::RISCVTargetLowering, andllvm::X86TargetLowering.
Definition at line2253 of fileTargetLowering.h.
Referencesllvm_unreachable.
◆ emitLeadingFence()
| virtual |
Inserts in the IR a target-specific intrinsic specifying a fence.
It is called byAtomicExpandPass before expanding an AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad if shouldInsertFencesForAtomic returns true.
Inst is the original atomic instruction, prior to other expansions that may be performed.
This function should either return a nullptr, or a pointer to an IR-level Instruction*. Even complex fence sequences can be represented by a single Instruction* through an intrinsic to be lowered later.
The default implementation emits an IR fence before any release (or stronger) operation that stores, and after any acquire (or stronger) operation. This is generally a correct implementation, but backends may override if they wish to use alternative schemes (e.g. the PowerPC standard ABI uses a fence before a seq_cst load instead of after a seq_cst store).
Reimplemented inllvm::ARMTargetLowering,llvm::PPCTargetLowering,llvm::RISCVTargetLowering, andllvm::VETargetLowering.
Definition at line2307 of fileTargetLoweringBase.cpp.
Referencesllvm::IRBuilderBase::CreateFence(),llvm::Instruction::hasAtomicStore(), andllvm::isReleaseOrStronger().
◆ emitLoadLinked()
| inlinevirtual |
Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type.
This may entail some non-trivial operations to truncate or reconstruct types that will be illegal in the backend. See ARMISelLowering for an example implementation.
Reimplemented inllvm::AArch64TargetLowering,llvm::ARMTargetLowering, andllvm::HexagonTargetLowering.
Definition at line2186 of fileTargetLowering.h.
Referencesllvm_unreachable.
◆ emitMaskedAtomicCmpXchgIntrinsic()
| inlinevirtual |
Perform a masked cmpxchg using a target-specific intrinsic.
This represents the core LL/SC loop which will be lowered at a late stage by the backend. The target-specific intrinsic returns the loaded value and is not responsible for masking and shifting the result.
Reimplemented inllvm::LoongArchTargetLowering,llvm::PPCTargetLowering, andllvm::RISCVTargetLowering.
Definition at line2243 of fileTargetLowering.h.
Referencesllvm_unreachable.
◆ emitMaskedAtomicRMWIntrinsic()
| inlinevirtual |
Perform a masked atomicrmw using a target-specific intrinsic.
This represents the core LL/SC loop which will be lowered at a late stage by the backend. The target-specific intrinsic returns the loaded value and is not responsible for masking and shifting the result.
Reimplemented inllvm::LoongArchTargetLowering,llvm::PPCTargetLowering, andllvm::RISCVTargetLowering.
Definition at line2202 of fileTargetLowering.h.
Referencesllvm_unreachable.
◆ emitPatchPoint()
| protected |
Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that is recognized by PrologEpilogInserter.
Definition at line1155 of fileTargetLoweringBase.cpp.
Referencesllvm::MachineInstrBuilder::add(),llvm::MachineInstrBuilder::addImm(),llvm::MachineInstr::addMemOperand(),assert(),llvm::BuildMI(),llvm::MachineInstrBuilder::cloneMemRefs(),llvm::MachineFunction::getDataLayout(),llvm::MachinePointerInfo::getFixedStack(),llvm::MachineFunction::getFrameInfo(),llvm::MachineOperand::getIndex(),llvm::MachineFunction::getMachineMemOperand(),llvm::MachineInstr::getNumOperands(),llvm::MachineFrameInfo::getObjectAlign(),llvm::MachineFrameInfo::getObjectOffset(),llvm::MachineFrameInfo::getObjectSize(),llvm::DataLayout::getPointerSize(),llvm::MachineBasicBlock::insert(),llvm::MachineOperand::isFI(),llvm::MachineOperand::isReg(),llvm::MachineFrameInfo::isStatepointSpillSlotObjectIndex(),llvm::MachineOperand::isTied(),llvm::MachineInstr::mayLoad(),MBB,MI,llvm::MachineMemOperand::MOLoad,llvm::none_of(), andllvm::MachineInstr::tieOperands().
Referenced byllvm::RISCVTargetLowering::EmitInstrWithCustomInserter(),llvm::SystemZTargetLowering::EmitInstrWithCustomInserter(),llvm::AArch64TargetLowering::EmitInstrWithCustomInserter(),llvm::PPCTargetLowering::EmitInstrWithCustomInserter(), andllvm::X86TargetLowering::EmitInstrWithCustomInserter().
◆ emitStoreConditional()
| inlinevirtual |
Perform a store-conditional operation to Addr.
Return the status of the store. This should be 0 if the store succeeded, non-zero otherwise.
Reimplemented inllvm::AArch64TargetLowering,llvm::ARMTargetLowering, andllvm::HexagonTargetLowering.
Definition at line2193 of fileTargetLowering.h.
Referencesllvm_unreachable.
◆ emitTrailingFence()
| virtual |
Reimplemented inllvm::ARMTargetLowering,llvm::PPCTargetLowering,llvm::RISCVTargetLowering, andllvm::VETargetLowering.
Definition at line2316 of fileTargetLoweringBase.cpp.
Referencesllvm::IRBuilderBase::CreateFence(), andllvm::isAcquireOrStronger().
◆ enableAggressiveFMAFusion()[1/2]
Return true if target always benefits from combining into FMA for a given value type.
This must typically return false on targets where FMA takes more cycles to execute than FADD.
Reimplemented inllvm::AArch64TargetLowering,llvm::SITargetLowering,llvm::NVPTXTargetLowering, andllvm::PPCTargetLowering.
Definition at line974 of fileTargetLowering.h.
◆ enableAggressiveFMAFusion()[2/2]
Return true if target always benefits from combining into FMA for a given value type.
This must typically return false on targets where FMA takes more cycles to execute than FADD.
Reimplemented inllvm::SITargetLowering.
Definition at line979 of fileTargetLowering.h.
◆ enableExtLdPromotion()
| inline |
Return true if the target wants to use the optimization that turns ext(promotableInst1(...(promotableInstN(load)))) into promotedInst1(...(promotedInstN(ext(load)))).
Definition at line946 of fileTargetLowering.h.
ReferencesEnableExtLdPromotion.
◆ fallBackToDAGISel()
| inlinevirtual |
Reimplemented inllvm::AArch64TargetLowering, andllvm::RISCVTargetLowering.
Definition at line661 of fileTargetLowering.h.
◆ finalizeLowering()
| virtual |
Execute target specific actions to finalize target lowering.
This is used to set extra flags in MachineFrameInformation and freezing the set of reserved registers. The default implementation just freezes the set of reserved registers.
Reimplemented inllvm::SITargetLowering,llvm::ARMTargetLowering, andllvm::SPIRVTargetLowering.
Definition at line2246 of fileTargetLoweringBase.cpp.
Referencesllvm::MachineRegisterInfo::freezeReservedRegs(), andllvm::MachineFunction::getRegInfo().
Referenced byllvm::SITargetLowering::finalizeLowering(),llvm::ARMTargetLowering::finalizeLowering(),llvm::SPIRVTargetLowering::finalizeLowering(),runImpl(), andllvm::InstructionSelect::selectMachineFunction().
◆ findRepresentativeClass()
| protectedvirtual |
Return the largest legal super-reg register class of the register class for the specified type and its associated "cost".
findRepresentativeClass - Return the largest legal super-reg register class of the register class for the specified type and its associated "cost".
Reimplemented inllvm::ARMTargetLowering, andllvm::X86TargetLowering.
Definition at line1248 of fileTargetLoweringBase.cpp.
ReferencesisLegalRC(),llvm::SuperRegClassIterator::isValid(),llvm::BitVector::set_bits(),llvm::BitVector::setBitsInMask(),llvm::MVT::SimpleTy, andTRI.
Referenced bycomputeRegisterProperties(),llvm::ARMTargetLowering::findRepresentativeClass(), andllvm::X86TargetLowering::findRepresentativeClass().
◆ generateFMAsInMachineCombiner()
| inlinevirtual |
Reimplemented inllvm::AArch64TargetLowering.
Definition at line3297 of fileTargetLowering.h.
◆ getABIAlignmentForCallingConv()
| inlinevirtual |
Certain targets have context sensitive alignment requirements, where one type has the alignment requirement of another type.
Reimplemented inllvm::ARMTargetLowering, andllvm::MipsTargetLowering.
Definition at line1803 of fileTargetLowering.h.
ReferencesDL.
Referenced byllvm::TargetLowering::LowerCallTo().
◆ getAddrModeArguments()
| inlinevirtual |
CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the address.
This allows as much computation as possible to be done in the address mode for that operand. This hook lets targets also pass back when this should be done on intrinsics which load/store.
Reimplemented inllvm::SITargetLowering.
Definition at line2802 of fileTargetLowering.h.
◆ getAsmOperandValueType()
| inlinevirtual |
Reimplemented inllvm::AArch64TargetLowering.
Definition at line1668 of fileTargetLowering.h.
ReferencesDL, andgetValueType().
Referenced byllvm::AArch64TargetLowering::getAsmOperandValueType(),llvm::InlineAsmLowering::lowerInlineAsm(), andllvm::TargetLowering::ParseConstraints().
◆ getAtomicLoadExtAction()
| inline |
Same as getLoadExtAction, but for atomic loads.
Definition at line1479 of fileTargetLowering.h.
Referencesassert(),Expand,llvm::EVT::getSimpleVT(),llvm::EVT::isExtended(),llvm::ISD::LAST_LOADEXT_TYPE,Legal,llvm::MVT::SimpleTy, andllvm::MVT::VALUETYPE_SIZE.
Referenced byisAtomicLoadExtLegal().
◆ getAtomicMemOperandFlags()
| MachineMemOperand::Flags TargetLoweringBase::getAtomicMemOperandFlags | ( | constInstruction & | AI, |
| constDataLayout & | DL | ||
| ) | const |
Definition at line2289 of fileTargetLoweringBase.cpp.
ReferencesgetTargetMMOFlags(),llvm_unreachable,llvm::MachineMemOperand::MOLoad,llvm::MachineMemOperand::MOStore, andllvm::MachineMemOperand::MOVolatile.
◆ getBitWidthForCttzElements()
| unsigned TargetLoweringBase::getBitWidthForCttzElements | ( | Type * | RetTy, |
| ElementCount | EC, | ||
| bool | ZeroIsPoison, | ||
| constConstantRange * | VScaleRange | ||
| ) | const |
Return the minimum number of bits required to hold the maximum possible number of trailing zero vector elements.
Definition at line923 of fileTargetLoweringBase.cpp.
Referencesllvm::bit_ceil(),llvm::ConstantRange::getActiveBits(),RetTy,llvm::ConstantRange::subtract(), andllvm::ConstantRange::umul_sat().
Referenced byllvm::TargetLowering::expandVectorFindLastActive(), andllvm::BasicTTIImplBase< T >::getIntrinsicInstrCost().
◆ getBooleanContents()[1/2]
| inline |
For targets without i1 registers, this gives the nature of the high-bits of boolean values held in types wider than i1.
"Boolean values" are special true/false values produced by nodes like SETCC and consumed (as the condition) by nodes like SELECT and BRCOND. Not to be confused with general values promoted from i1. Some cpus distinguish between vectors of boolean and scalars; the isVec parameter selects between the two kinds. For example onX86 a scalar boolean should be zero extended from i1, while the elements of a vector of booleans should be sign extended from i1.
Some cpus also treat floating point types the same way as they treat vectors instead of the way they treat scalars.
Definition at line1004 of fileTargetLowering.h.
Referenced bycombineSelectAsExtAnd(),llvm::SelectionDAG::computeKnownBits(),llvm::GISelKnownBits::computeKnownBitsImpl(),llvm::GISelKnownBits::computeNumSignBits(),llvm::SelectionDAG::ComputeNumSignBits(),llvm::TargetLowering::expandABD(),llvm::TargetLowering::expandAddSubSat(),llvm::TargetLowering::expandCMP(),llvm::TargetLowering::expandDIVREMByConstant(),llvm::TargetLowering::expandIntMINMAX(),llvm::SelectionDAG::FoldConstantArithmetic(),llvm::SelectionDAG::FoldSetCC(),getAsCarry(),llvm::SelectionDAG::getBoolConstant(),getBooleanContents(),llvm::SelectionDAG::getBoolExtOrTrunc(),llvm::getICmpTrueVal(),llvm::SelectionDAG::isBoolConstant(),llvm::isConstFalseVal(),llvm::TargetLowering::isConstFalseVal(),llvm::isConstTrueVal(),llvm::TargetLowering::isConstTrueVal(),llvm::TargetLowering::isExtendedTrueVal(),llvm::TargetLowering::LowerAsmOperandForConstraint(),llvm::X86TargetLowering::LowerAsmOperandForConstraint(),llvm::LegalizerHelper::lowerThreewayCompare(),llvm::SDPatternMatch::m_False(),llvm::SDPatternMatch::m_True(),promoteTargetBoolean(),scalarizeExtractedBinOp(),llvm::TargetLowering::SimplifyDemandedBits(),llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), andllvm::TargetLowering::SimplifySetCC().
◆ getBooleanContents()[2/2]
| inline |
Definition at line1010 of fileTargetLowering.h.
ReferencesgetBooleanContents().
◆ getBypassSlowDivWidths()
| inline |
Returns map of slow types for division or remainder with corresponding fast types.
Definition at line608 of fileTargetLowering.h.
◆ getByValTypeAlignment()
| virtual |
Returns the desired alignment for ByVal or InAlloca aggregate function arguments in the caller parameter area.
Reimplemented inllvm::PPCTargetLowering, andllvm::X86TargetLowering.
Definition at line1703 of fileTargetLoweringBase.cpp.
ReferencesDL.
Referenced byllvm::FastISel::lowerCallTo(),llvm::TargetLowering::LowerCallTo(), andllvm::CallLowering::setArgFlags().
◆ getCmpLibcallCC()
| inline |
Get the CondCode that's to be used to test the result of the comparison libcall against zero.
FIXME: This can't be merged with 'RuntimeLibcallsInfo' because of theISD.
Definition at line3455 of fileTargetLowering.h.
Referenced byllvm::TargetLowering::softenSetCCOperands().
◆ getCmpLibcallReturnType()
| virtual |
Return the ValueType for comparison libcalls.
Comparison libcalls include floating point comparison calls, and Ordered/Unordered check calls on floating point numbers.
Reimplemented inllvm::AVRTargetLowering, andllvm::MSP430TargetLowering.
Definition at line1529 of fileTargetLoweringBase.cpp.
Referenced byllvm::TargetLowering::softenSetCCOperands().
◆ getCondCodeAction()
| inline |
Return how the condition code should be treated: either it is legal, needs to be expanded to some other code sequence, or the target has a custom expander for it.
Definition at line1616 of fileTargetLowering.h.
Referencesassert(),CC,Promote, andllvm::MVT::SimpleTy.
Referenced byisCondCodeLegal(),isCondCodeLegalOrCustom(), andllvm::TargetLowering::LegalizeSetCCCondCode().
◆ getCustomCtpopCost()
| inlinevirtual |
Return the maximum number of "x & (x - 1)" operations that can be done instead of deferring to a custom CTPOP.
Reimplemented inllvm::RISCVTargetLowering.
Definition at line728 of fileTargetLowering.h.
Referenced bysimplifySetCCWithCTPOP().
◆ getCustomOperationAction()
| inlinevirtual |
How to legalize this custom operation?
Reimplemented inllvm::VETargetLowering, andllvm::HexagonTargetLowering.
Definition at line1263 of fileTargetLowering.h.
ReferencesLegal.
◆ getDefaultSafeStackPointerLocation()
| protected |
Definition at line1856 of fileTargetLoweringBase.cpp.
ReferencesDL,llvm::GlobalValue::ExternalLinkage,llvm::IRBuilderBase::GetInsertBlock(),llvm::GlobalValue::getParent(),llvm::BasicBlock::getParent(),llvm::GlobalValue::InitialExecTLSModel,llvm::GlobalValue::NotThreadLocal, andllvm::report_fatal_error().
Referenced bygetSafeStackPointerLocation().
◆ getDivRefinementSteps()
| int TargetLoweringBase::getDivRefinementSteps | ( | EVT | VT, |
| MachineFunction & | MF | ||
| ) | const |
Return the refinement step count for a division of the given type based on the function's attributes.
If the operation is not overridden by the function's attributes, "Unspecified" is returned and target defaults are expected to be used for instruction selection.
Definition at line2213 of fileTargetLoweringBase.cpp.
ReferencesgetOpRefinementSteps(), andgetRecipEstimateForFunc().
◆ getExceptionPointerRegister()
| inlinevirtual |
If a physical register, this returns the register that receives the exception address on entry to an EH pad.
Reimplemented inllvm::AArch64TargetLowering,llvm::ARMTargetLowering,llvm::HexagonTargetLowering,llvm::LoongArchTargetLowering,llvm::M68kTargetLowering,llvm::MipsTargetLowering,llvm::PPCTargetLowering,llvm::RISCVTargetLowering,llvm::SparcTargetLowering,llvm::SystemZTargetLowering,llvm::X86TargetLowering, andllvm::XCoreTargetLowering.
Definition at line2022 of fileTargetLowering.h.
Referenced byGetEHSpillList(), andllvm::MachineBasicBlock::liveout_begin().
◆ getExceptionSelectorRegister()
| inlinevirtual |
If a physical register, this returns the register that receives the exception typeid on entry to a landing pad.
Reimplemented inllvm::AArch64TargetLowering,llvm::ARMTargetLowering,llvm::HexagonTargetLowering,llvm::LoongArchTargetLowering,llvm::M68kTargetLowering,llvm::MipsTargetLowering,llvm::PPCTargetLowering,llvm::RISCVTargetLowering,llvm::SparcTargetLowering,llvm::SystemZTargetLowering,llvm::X86TargetLowering, andllvm::XCoreTargetLowering.
Definition at line2029 of fileTargetLowering.h.
Referenced byGetEHSpillList(), andllvm::MachineBasicBlock::liveout_begin().
◆ getExtendForAtomicCmpSwapArg()
| inlinevirtual |
Returns how the platform's atomic compare and swap expects its comparison value to be extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND).
This is separate from getExtendForAtomicOps, which is concerned with the sign-extension of the instruction's output, whereas here we are concerned with the sign-extension of the input. For targets with compare-and-swap instructions (or sub-word comparisons in their LL/SC loop expansions), the input can be ANY_EXTEND, but the output will still have a specific extension.
Reimplemented inllvm::LoongArchTargetLowering,llvm::RISCVTargetLowering, andllvm::SystemZTargetLowering.
Definition at line2393 of fileTargetLowering.h.
Referencesllvm::ISD::ANY_EXTEND.
◆ getExtendForAtomicOps()
| inlinevirtual |
Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND).
Reimplemented inllvm::LoongArchTargetLowering,llvm::MipsTargetLowering,llvm::RISCVTargetLowering,llvm::SystemZTargetLowering, andllvm::VETargetLowering.
Definition at line2381 of fileTargetLowering.h.
Referencesllvm::ISD::ZERO_EXTEND.
Referenced byllvm::SelectionDAG::computeKnownBits(), andllvm::SelectionDAG::ComputeNumSignBits().
◆ getExtendForContent()
| inlinestatic |
Definition at line334 of fileTargetLowering.h.
Referencesllvm::ISD::ANY_EXTEND,Content,llvm_unreachable,llvm::ISD::SIGN_EXTEND,UndefinedBooleanContent,llvm::ISD::ZERO_EXTEND,ZeroOrNegativeOneBooleanContent, andZeroOrOneBooleanContent.
Referenced byllvm::SelectionDAG::FoldConstantArithmetic(),llvm::SelectionDAG::getBoolExtOrTrunc(),llvm::TargetLowering::LowerAsmOperandForConstraint(),llvm::X86TargetLowering::LowerAsmOperandForConstraint(),promoteTargetBoolean(), andllvm::TargetLowering::SimplifySetCC().
◆ getFenceOperandTy()
| inlinevirtual |
Return the type for operands of fence.
TODO: Let fence operands be of i32 type and remove this.
Reimplemented inllvm::AMDGPUTargetLowering.
Definition at line396 of fileTargetLowering.h.
ReferencesDL, andgetPointerTy().
◆ getFixedPointOperationAction()
| inline |
Some fixed point operations may be natively supported by the target but only for specific scales.
This method allows for checking if the width is supported by the target for a given operation that may depend on scale.
Definition at line1292 of fileTargetLowering.h.
ReferencesExpand,getOperationAction(),isSupportedFixedPointOperation(),Legal,llvm_unreachable,llvm::ISD::SDIVFIX,llvm::ISD::SDIVFIXSAT,llvm::ISD::SMULFIX,llvm::ISD::SMULFIXSAT,llvm::ISD::UDIVFIX,llvm::ISD::UDIVFIXSAT,llvm::ISD::UMULFIX, andllvm::ISD::UMULFIXSAT.
Referenced byexpandDivFix().
◆ getFrameIndexTy()
| inline |
Return the type for frame index, which is determined by the alloca address space specified through the data layout.
Definition at line384 of fileTargetLowering.h.
ReferencesDL, andgetPointerTy().
Referenced byllvm::SelectionDAG::CreateStackTemporary(),getAddressForMemoryInput(),llvm::SelectionDAGBuilder::getFrameIndexTy(),llvm::MSP430TargetLowering::getReturnAddressFrameIndex(),llvm::TargetLowering::LowerCallTo(), andllvm::XtensaTargetLowering::LowerFormalArguments().
◆ getGatherAllAliasesMaxDepth()
| inline |
Definition at line1850 of fileTargetLowering.h.
ReferencesGatherAllAliasesMaxDepth.
◆ getIndexedLoadAction()
| inline |
Return how the indexed load should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.
Definition at line1537 of fileTargetLowering.h.
Referenced byisIndexedLoadLegal().
◆ getIndexedMaskedLoadAction()
| inline |
Return how the indexed load should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.
Definition at line1565 of fileTargetLowering.h.
Referenced byisIndexedMaskedLoadLegal().
◆ getIndexedMaskedStoreAction()
| inline |
Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.
Definition at line1579 of fileTargetLowering.h.
Referenced byisIndexedMaskedStoreLegal().
◆ getIndexedStoreAction()
| inline |
Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.
Definition at line1551 of fileTargetLowering.h.
Referenced byisIndexedStoreLegal().
◆ getIRStackGuard()
| virtual |
If the target has a standard location for the stack protector guard, returns the address of that location.
Otherwise, returns nullptr. DEPRECATED: please override useLoadStackGuardNode and customize LOAD_STACK_GUARD, or customize @llvm.stackguard().
Reimplemented inllvm::AArch64TargetLowering,llvm::RISCVTargetLowering, andllvm::X86TargetLowering.
Definition at line1956 of fileTargetLoweringBase.cpp.
Referencesllvm::CallingConv::C,G,llvm::IRBuilderBase::GetInsertBlock(),llvm::GlobalValue::getParent(),llvm::BasicBlock::getParent(),getTargetMachine(),llvm::PointerType::getUnqual(), andllvm::GlobalValue::HiddenVisibility.
Referenced byllvm::AArch64TargetLowering::getIRStackGuard(),llvm::RISCVTargetLowering::getIRStackGuard(),llvm::X86TargetLowering::getIRStackGuard(), andgetStackGuard().
◆ getJumpConditionMergingParams()
| inlinevirtual |
Reimplemented inllvm::X86TargetLowering.
Definition at line649 of fileTargetLowering.h.
◆ getLibcallCallingConv()
| inline |
Get theCallingConv that should be used for the specified libcall.
Definition at line3466 of fileTargetLowering.h.
Referencesllvm::RTLIB::RuntimeLibcallsInfo::getLibcallCallingConv().
Referenced byllvm::HexagonSelectionDAGInfo::EmitTargetCodeForMemcpy(),llvm::XCoreSelectionDAGInfo::EmitTargetCodeForMemcpy(),llvm::SelectionDAG::expandMultipleResultFPLibCall(),llvm::SelectionDAG::getAtomicMemcpy(),llvm::SelectionDAG::getAtomicMemmove(),llvm::SelectionDAG::getAtomicMemset(),llvm::SelectionDAG::getMemcpy(),llvm::SelectionDAG::getMemmove(),llvm::SelectionDAG::getMemset(),llvm::TargetLowering::makeLibCall(), andllvm::SelectionDAG::makeStateFunctionCall().
◆ getLibcallName()
| inline |
Get the libcall routine name for the specified libcall.
Definition at line3440 of fileTargetLowering.h.
Referencesllvm::RTLIB::RuntimeLibcallsInfo::getLibcallName().
Referenced byllvm::AArch64TargetLowering::AArch64TargetLowering(),llvm::ARMTargetLowering::ARMTargetLowering(),canEmitLibcall(),llvm::SelectionDAG::expandMultipleResultFPLibCall(),llvm::TargetLowering::forceExpandWideMUL(),llvm::SelectionDAG::getAtomicMemcpy(),llvm::SelectionDAG::getAtomicMemmove(),llvm::SelectionDAG::getAtomicMemset(),llvm::SelectionDAG::getMemcpy(),llvm::SelectionDAG::getMemmove(),llvm::SelectionDAG::getMemset(),isDivRemLibcallAvailable(),isSinCosLibcallAvailable(),LowerF128_FPEXTEND(),LowerF128_FPROUND(),LowerFP_TO_SINT(),LowerFP_TO_UINT(),LowerFSINCOS(),llvm::SparcTargetLowering::LowerOperation(),LowerSINT_TO_FP(),LowerUINT_TO_FP(),llvm::TargetLowering::makeLibCall(),llvm::SelectionDAG::makeStateFunctionCall(),optimizeCall(),llvm::SparcTargetLowering::ReplaceNodeResults(), andllvm::X86TargetLowering::X86TargetLowering().
◆ getLoadExtAction()
| inline |
Return how this load with extension should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.
Definition at line1455 of fileTargetLowering.h.
Referencesassert(),Expand,llvm::EVT::getSimpleVT(),llvm::EVT::isExtended(),llvm::ISD::LAST_LOADEXT_TYPE,llvm::MVT::SimpleTy, andllvm::MVT::VALUETYPE_SIZE.
Referenced byisLoadExtLegal(), andisLoadExtLegalOrCustom().
◆ getLoadMemOperandFlags()
| MachineMemOperand::Flags TargetLoweringBase::getLoadMemOperandFlags | ( | constLoadInst & | LI, |
| constDataLayout & | DL, | ||
| AssumptionCache * | AC =nullptr, | ||
| constTargetLibraryInfo * | LibInfo =nullptr | ||
| ) | const |
Definition at line2250 of fileTargetLoweringBase.cpp.
ReferencesDL,llvm::LoadInst::getAlign(),llvm::LoadInst::getPointerOperand(),getTargetMMOFlags(),llvm::Value::getType(),llvm::Instruction::hasMetadata(),llvm::isDereferenceableAndAlignedPointer(),llvm::LoadInst::isVolatile(),llvm::MachineMemOperand::MODereferenceable,llvm::MachineMemOperand::MOInvariant,llvm::MachineMemOperand::MOLoad,llvm::MachineMemOperand::MONonTemporal, andllvm::MachineMemOperand::MOVolatile.
◆ getMaxAtomicSizeInBitsSupported()
| inline |
Returns the maximum atomic operation size (in bits) supported by the backend.
Atomic operations greater than this size (as well as ones that are not naturally aligned), will be expanded byAtomicExpandPass into an __atomic_* library call.
Definition at line2140 of fileTargetLowering.h.
Referenced byatomicSizeSupported().
◆ getMaxDivRemBitWidthSupported()
| inline |
Returns the size in bits of the maximum div/rem the backend supports.
Larger operations will be expanded by ExpandLargeDivRem.
Definition at line2146 of fileTargetLowering.h.
Referenced byrunImpl().
◆ getMaxExpandSizeMemcmp()
Get maximum # of load operations permitted for memcmp.
This function returns the maximum number of load operations permitted to replace a call to memcmp. The value is set by the target at the performance threshold for such a replacement. If OptSize is true, return the limit for functions that have OptSize attribute.
Definition at line1894 of fileTargetLowering.h.
ReferencesMaxLoadsPerMemcmp, andMaxLoadsPerMemcmpOptSize.
Referenced byllvm::AArch64TTIImpl::enableMemCmpExpansion(),llvm::BPFTTIImpl::enableMemCmpExpansion(),llvm::PPCTTIImpl::enableMemCmpExpansion(),llvm::RISCVTTIImpl::enableMemCmpExpansion(), andllvm::X86TTIImpl::enableMemCmpExpansion().
◆ getMaxGluedStoresPerMemcpy()
| inlinevirtual |
Get maximum # of store operations to be glued together.
This function returns the maximum number of store operations permitted to glue together during lowering of llvm.memcpy. The value is set by
Definition at line1884 of fileTargetLowering.h.
ReferencesMaxGluedStoresPerMemcpy.
Referenced bygetMemcpyLoadsAndStores().
◆ getMaximumJumpTableSize()
| unsigned TargetLoweringBase::getMaximumJumpTableSize | ( | ) | const |
Return upper limit for number of entries in a jump table.
Zero if no limit.
Definition at line2009 of fileTargetLoweringBase.cpp.
ReferencesMaximumJumpTableSize.
Referenced byllvm::AArch64TargetLowering::AArch64TargetLowering(), andisSuitableForJumpTable().
◆ getMaxLargeFPConvertBitWidthSupported()
| inline |
Returns the size in bits of the maximum larget fp convert the backend supports.
Larger operations will be expanded by ExpandLargeFPConvert.
Definition at line2152 of fileTargetLowering.h.
Referenced byrunImpl().
◆ getMaxPermittedBytesForAlignment()
| virtual |
Return the maximum amount of bytes allowed to be emitted when padding for alignment.
Definition at line2027 of fileTargetLoweringBase.cpp.
◆ getMaxStoresPerMemcpy()
Get maximum # of store operations permitted for llvm.memcpy.
This function returns the maximum number of store operations permitted to replace a call to llvm.memcpy. The value is set by the target at the performance threshold for such a replacement. If OptSize is true, return the limit for functions that have OptSize attribute.
Definition at line1875 of fileTargetLowering.h.
ReferencesMaxStoresPerMemcpy, andMaxStoresPerMemcpyOptSize.
Referenced bygetMemcpyLoadsAndStores(),llvm::ARMTTIImpl::getNumMemOps(), andllvm::LegalizerHelper::lowerMemCpyFamily().
◆ getMaxStoresPerMemmove()
Get maximum # of store operations permitted for llvm.memmove.
This function returns the maximum number of store operations permitted to replace a call to llvm.memmove. The value is set by the target at the performance threshold for such a replacement. If OptSize is true, return the limit for functions that have OptSize attribute.
Definition at line1904 of fileTargetLowering.h.
ReferencesMaxStoresPerMemmove, andMaxStoresPerMemmoveOptSize.
Referenced bygetMemmoveLoadsAndStores(), andllvm::ARMTTIImpl::getNumMemOps().
◆ getMaxStoresPerMemset()
Get maximum # of store operations permitted for llvm.memset.
This function returns the maximum number of store operations permitted to replace a call to llvm.memset. The value is set by the target at the performance threshold for such a replacement. If OptSize is true, return the limit for functions that have OptSize attribute.
Definition at line1865 of fileTargetLowering.h.
ReferencesMaxStoresPerMemset, andMaxStoresPerMemsetOptSize.
Referenced bygetMemsetStores(), andllvm::ARMTTIImpl::getNumMemOps().
◆ getMaxSupportedInterleaveFactor()
| inlinevirtual |
Get the maximum supported factor for interleaved memory accesses.
Default to be the minimum interleave factor: 2.
Reimplemented inllvm::AArch64TargetLowering,llvm::ARMTargetLowering,llvm::RISCVTargetLowering, andllvm::X86TargetLowering.
Definition at line3132 of fileTargetLowering.h.
Referenced byllvm::ARMTargetLowering::getMaxSupportedInterleaveFactor().
◆ getMemValueType()
| inline |
Definition at line1697 of fileTargetLowering.h.
ReferencesDL,llvm::Type::getContext(),llvm::EVT::getEVT(),getPointerMemTy(),getValueType(), andllvm::EVT::getVectorVT().
Referenced byllvm::ComputeValueVTs(),getAddressForMemoryInput(),setInfoSVEStN(), andllvm::SelectionDAGBuilder::visitSwitchCase().
◆ getMinCmpXchgSizeInBits()
| inline |
Returns the size of the smallest cmpxchg or ll/sc instruction the backend supports.
Any smaller operations are widened inAtomicExpandPass.
Note thatunlike operations above the maximum size, atomic ops are still natively supported below the minimum; they just require a more complex expansion.
Definition at line2163 of fileTargetLowering.h.
Referenced byllvm::RISCVTargetLowering::ComputeNumSignBitsForTargetNode().
◆ getMinFunctionAlignment()
| inline |
Return the minimum function alignment.
Definition at line2043 of fileTargetLowering.h.
◆ getMinimumJumpTableDensity()
Return lower limit of the density in a jump table.
Definition at line2005 of fileTargetLoweringBase.cpp.
ReferencesJumpTableDensity, andOptsizeJumpTableDensity.
Referenced byisSuitableForJumpTable().
◆ getMinimumJumpTableEntries()
| virtual |
Return lower limit for number of blocks in a jump table.
Reimplemented inllvm::VETargetLowering.
Definition at line1997 of fileTargetLoweringBase.cpp.
ReferencesMinimumJumpTableEntries.
Referenced byllvm::SwitchCG::SwitchLowering::findJumpTables(), andllvm::VETargetLowering::getMinimumJumpTableEntries().
◆ getMinStackArgumentAlignment()
| inline |
Return the minimum stack alignment of an argument.
Definition at line2038 of fileTargetLowering.h.
Referenced byllvm::SelectionDAG::expandVAArg(), andllvm::LegalizerHelper::lowerVAArg().
◆ getNumRegisters()
| inlinevirtual |
Return the number of registers that this ValueType will eventually require.
This is one for any types promoted to live in larger registers, but may be more than one for types (like i64) that are split into pieces. For types like i140, which are first promoted then expanded, it is the number of registers needed to hold all the bits of the original type. For an i140 on a 32 bit machine this means 5 registers.
RegisterVT may be passed as a way to override the default settings, for instance with i128 inline assembly operands onSystemZ.
Reimplemented inllvm::SystemZTargetLowering,llvm::RISCVTargetLowering, andllvm::SPIRVTargetLowering.
Definition at line1763 of fileTargetLowering.h.
Referencesassert(),llvm::BitWidth,getRegisterType(),llvm::EVT::getSimpleVT(),llvm::EVT::getSizeInBits(),llvm::MVT::getSizeInBits(),getVectorTypeBreakdown(),llvm::EVT::isInteger(),llvm::EVT::isSimple(),llvm::EVT::isVector(),llvm_unreachable, andllvm::MVT::SimpleTy.
Referenced byllvm::RegsForValue::AddInlineAsmOperands(),llvm::computeLegalValueVTs(),llvm::FunctionLoweringInfo::ComputePHILiveOutRegInfo(),llvm::FunctionLoweringInfo::CreateRegs(),llvm::SystemZTargetLowering::getNumRegisters(),llvm::RISCVTargetLowering::getNumRegisters(),getNumRegistersForCallingConv(),llvm::MipsTargetLowering::getNumRegistersForCallingConv(),getRegistersForValue(),llvm::BasicTTIImplBase< T >::getRegUsageForType(),llvm::FunctionLoweringInfo::getValueFromVirtualReg(),llvm::MipsTargetLowering::getVectorTypeBreakdownForCallingConv(),llvm::FastISel::lowerCallTo(),llvm::TargetLowering::LowerCallTo(),llvm::NVPTXTargetLowering::LowerFormalArguments(),llvm::RegsForValue::RegsForValue(),llvm::FastISel::selectExtractValue(), andllvm::FunctionLoweringInfo::set().
◆ getNumRegistersForCallingConv()
| inlinevirtual |
Certain targets require unusual breakdowns of certain types.
For MIPS, this occurs when a vector type is used, as vector are passed through the integer register set.
Reimplemented inllvm::AArch64TargetLowering,llvm::SITargetLowering,llvm::MipsTargetLowering,llvm::RISCVTargetLowering,llvm::SPIRVTargetLowering, andllvm::X86TargetLowering.
Definition at line1795 of fileTargetLowering.h.
ReferencesgetNumRegisters().
Referenced byllvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(),llvm::CallLowering::determineAssignments(),llvm::AArch64TargetLowering::getNumRegistersForCallingConv(),llvm::SITargetLowering::getNumRegistersForCallingConv(),llvm::RISCVTargetLowering::getNumRegistersForCallingConv(),llvm::X86TargetLowering::getNumRegistersForCallingConv(),llvm::CallLowering::getReturnInfo(),llvm::GetReturnInfo(),llvm::SystemZTargetLowering::LowerCall(),llvm::TargetLowering::LowerCallTo(), andllvm::RegsForValue::RegsForValue().
◆ getOperationAction()
| inline |
Return how this operation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.
Definition at line1270 of fileTargetLowering.h.
ReferencesCustom,Expand,llvm::EVT::getSimpleVT(),llvm::EVT::isExtended(), andllvm::MVT::SimpleTy.
Referenced byllvm::RISCVTTIImpl::getArithmeticInstrCost(),getFixedPointOperationAction(),getStrictFPOperationAction(),getTypeToPromoteTo(),isLoadBitCastBeneficial(),isOperationCustom(),isOperationExpand(),isOperationLegal(),isOperationLegalOrCustom(),isOperationLegalOrCustomOrPromote(),isOperationLegalOrPromote(),llvm::ARMTTIImpl::maybeLoweredToCall(),llvm::NVPTXTargetLowering::NVPTXTargetLowering(),llvm::TargetLowering::SimplifyDemandedBits(),llvm::SystemZTargetLowering::SystemZTargetLowering(), andtryToFoldExtendSelectLoad().
◆ getOptimalMemOpLLT()
| inlinevirtual |
LLT returning variant.
Reimplemented inllvm::AArch64TargetLowering.
Definition at line1987 of fileTargetLowering.h.
Referenced byfindGISelOptimalMemOpLowering().
◆ getOptimalMemOpType()
| inlinevirtual |
Returns the target specific optimal type for load and store operations as a result of memset, memcpy, and memmove lowering.
It returns EVT::Other if the type should be determined using generic target-independent logic.
Reimplemented inllvm::AArch64TargetLowering,llvm::SITargetLowering,llvm::ARMTargetLowering,llvm::HexagonTargetLowering,llvm::PPCTargetLowering,llvm::RISCVTargetLowering,llvm::SystemZTargetLowering, andllvm::X86TargetLowering.
Definition at line1980 of fileTargetLowering.h.
Referenced byllvm::TargetLowering::findOptimalMemOpLowering().
◆ getPointerMemTy()
| inlinevirtual |
Return the in-memory pointer type for the given address space, defaults to the pointer type from the data layout.
FIXME: The default needs to be removed once all the code is updated.
Reimplemented inllvm::WebAssemblyTargetLowering.
Definition at line378 of fileTargetLowering.h.
ReferencesDL, andllvm::MVT::getIntegerVT().
Referenced bygetLoadStackGuard(),getMemValueType(),llvm::WebAssemblyTargetLowering::getPointerMemTy(),llvm::SITargetLowering::getPointerMemTy(), andllvm::SelectionDAGBuilder::visitSPDescriptorParent().
◆ getPointerTy()
| inlinevirtual |
Return the pointer type for the given address space, defaults to the pointer type from the data layout.
FIXME: The default needs to be removed once all the code is updated.
Reimplemented inllvm::AArch64TargetLowering, andllvm::WebAssemblyTargetLowering.
Definition at line371 of fileTargetLowering.h.
ReferencesDL, andllvm::MVT::getIntegerVT().
Referenced byAddCombineBUILD_VECTORToVPADDL(),AddCombineToVPADD(),AddCombineVUZPToVPADDL(),llvm::X86TargetLowering::BuildFILD(),CheckType(),CheckValueType(),combineConcatVectorOps(),combineGatherScatter(),combineLoad(),combineStore(),combineTargetShuffle(),llvm::SwiftErrorValueTracking::createEntriesInEntryBlock(),createMMXBuildVector(),createSetFPEnvNodes(),llvm::TargetLowering::CTTZTableLookup(),llvm::PPCTargetLowering::emitEHSjLjLongJmp(),llvm::SystemZTargetLowering::emitEHSjLjLongJmp(),llvm::PPCTargetLowering::emitEHSjLjSetJmp(),llvm::SystemZTargetLowering::emitEHSjLjSetJmp(),llvm::X86TargetLowering::EmitInstrWithCustomInserter(),llvm::X86TargetLowering::emitStackGuardXorFP(),llvm::HexagonSelectionDAGInfo::EmitTargetCodeForMemcpy(),llvm::XCoreSelectionDAGInfo::EmitTargetCodeForMemcpy(),llvm::SelectionDAG::expandMultipleResultFPLibCall(),llvm::SelectionDAG::expandVAArg(),llvm::SelectionDAG::expandVACopy(),getADAEntry(),getAddressForMemoryInput(),llvm::SelectionDAG::getAtomicMemcpy(),llvm::SelectionDAG::getAtomicMemmove(),llvm::SelectionDAG::getAtomicMemset(),getAVX2GatherNode(),getCopyFromParts(),getFenceOperandTy(),getFrameIndexTy(),getGatherNode(),llvm::SelectionDAG::getIntPtrConstant(),llvm::SelectionDAG::getJumpTableDebugInfo(),llvm::TargetLowering::getJumpTableRegTy(),getLoadStackGuard(),llvm::SelectionDAG::getMemcpy(),llvm::SelectionDAG::getMemmove(),llvm::SelectionDAG::getMemset(),llvm::SwiftErrorValueTracking::getOrCreateVReg(),llvm::SwiftErrorValueTracking::getOrCreateVRegDefAt(),llvm::TargetLowering::getPICJumpTableRelocBase(),llvm::M68kTargetLowering::getPICJumpTableRelocBase(),llvm::PPCTargetLowering::getPICJumpTableRelocBase(),llvm::VETargetLowering::getPICJumpTableRelocBase(),llvm::X86TargetLowering::getPICJumpTableRelocBase(),llvm::WebAssemblyTargetLowering::getPointerTy(),llvm::SITargetLowering::getPointerTy(),getPrefetchNode(),getProgramPointerTy(),llvm::NVPTXTargetLowering::getPrototype(),llvm::X86TargetLowering::getReturnAddressFrameIndex(),getScatterNode(),getSetCCResultType(),llvm::ARMTargetLowering::getSetCCResultType(),llvm::LoongArchTargetLowering::getSetCCResultType(),llvm::RISCVTargetLowering::getSetCCResultType(),llvm::SelectionDAG::getSymbolFunctionGlobalAddress(),llvm::NVPTXTargetLowering::getTgtMemIntrinsic(),getUniformBase(),getVaListSizeInBits(),llvm::SelectionDAGBuilder::getValueImpl(),getValueType(),getVectorIdxTy(),getzOSCalleeAndADA(),isBLACompatibleAddress(),llvm::RISCVTTIImpl::isLegalMaskedGatherScatter(),llvm::HexagonTargetLowering::LowerBlockAddress(),lowerBuildVectorAsBroadcast(),llvm::NVPTXTargetLowering::LowerCall(),llvm::SystemZTargetLowering::LowerCall(),llvm::XtensaTargetLowering::LowerCall(),llvm::HexagonTargetLowering::LowerCall(),llvm::LoongArchTargetLowering::LowerCall(),llvm::RISCVTargetLowering::LowerCall(),llvm::VETargetLowering::LowerCall(),llvm::SparcTargetLowering::LowerCall_32(),llvm::SparcTargetLowering::LowerCall_64(),llvm::TargetLowering::LowerCallTo(),llvm::SelectionDAGBuilder::LowerCallTo(),LowerCTPOP(),llvm::HexagonTargetLowering::LowerEH_RETURN(),llvm::SparcTargetLowering::LowerF128_LibCallArg(),llvm::SparcTargetLowering::LowerF128Compare(),llvm::SparcTargetLowering::LowerF128Op(),llvm::LoongArchTargetLowering::LowerFormalArguments(),llvm::NVPTXTargetLowering::LowerFormalArguments(),llvm::RISCVTargetLowering::LowerFormalArguments(),llvm::SystemZTargetLowering::LowerFormalArguments(),llvm::VETargetLowering::LowerFormalArguments(),llvm::SparcTargetLowering::LowerFormalArguments_32(),llvm::SparcTargetLowering::LowerFormalArguments_64(),lowerFRAMEADDR(),LowerFSINCOS(),llvm::HexagonTargetLowering::LowerGLOBAL_OFFSET_TABLE(),llvm::HexagonTargetLowering::LowerGLOBALADDRESS(),llvm::LanaiTargetLowering::LowerGlobalAddress(),llvm::NVPTXTargetLowering::LowerGlobalAddress(),llvm::SparcTargetLowering::LowerGlobalTLSAddress(),llvm::SparcTargetLowering::LowerINTRINSIC_WO_CHAIN(),llvm::LanaiTargetLowering::LowerJumpTable(),LowerMemOpCallTo(),llvm::R600TargetLowering::LowerOperation(),llvm::SparcTargetLowering::LowerReturn_32(),LowerRETURNADDR(),llvm::NVPTXTargetLowering::LowerSTACKRESTORE(),llvm::NVPTXTargetLowering::LowerSTACKSAVE(),llvm::TargetLowering::LowerToTLSEmulatedModel(),llvm::HexagonTargetLowering::LowerToTLSGeneralDynamicModel(),llvm::HexagonTargetLowering::LowerToTLSInitialExecModel(),llvm::HexagonTargetLowering::LowerToTLSLocalExecModel(),LowerUINT_TO_FP_i64(),lowerUINT_TO_FP_vXi32(),LowerVASTART(),llvm::HexagonTargetLowering::LowerVASTART(),llvm::LanaiTargetLowering::LowerVASTART(),llvm::VETargetLowering::lowerVASTART(),llvm::SparcTargetLowering::makeAddress(),llvm::SystemZTargetLowering::makeExternalCall(),llvm::TargetLowering::makeLibCall(),llvm::SelectionDAG::makeStateFunctionCall(),llvm::PPCTargetLowering::PerformDAGCombine(),llvm::RISCVTargetLowering::PerformDAGCombine(),PerformTruncatingStoreCombine(),llvm::SwiftErrorValueTracking::propagateVRegs(),recoverFramePointer(),llvm::PPCTargetLowering::SelectAddressRegImm(),llvm::SelectionDAGISel::SelectCodeCommon(),llvm::PPCTargetLowering::SelectOptimalAddrMode(),transformCallee(),llvm::SelectionDAGBuilder::visitBitTestHeader(), andllvm::SelectionDAGBuilder::visitSPDescriptorParent().
◆ getPreferredLargeGEPBaseOffset()
| inlinevirtual |
Return the prefered common base offset.
Reimplemented inllvm::AArch64TargetLowering.
Definition at line2846 of fileTargetLowering.h.
Referenced byllvm::BasicTTIImplBase< T >::getPreferredLargeGEPBaseOffset().
◆ getPreferredShiftAmountTy()
| inlinevirtual |
Return the preferred type to use for a shift opcode, given the shifted amount type isShiftValueTy.
Reimplemented inllvm::SITargetLowering.
Definition at line414 of fileTargetLowering.h.
Referenced byllvm::CombinerHelper::applySDivByPow2(),llvm::CombinerHelper::applyUDivByPow2(),llvm::CombinerHelper::applyUMulHToLShr(),llvm::CombinerHelper::buildSDivUsingMul(),llvm::CombinerHelper::buildUDivUsingMul(),llvm::CombinerHelper::matchBitfieldExtractFromAnd(),llvm::CombinerHelper::matchBitfieldExtractFromSExtInReg(),llvm::CombinerHelper::matchBitfieldExtractFromShr(),llvm::CombinerHelper::matchBitfieldExtractFromShrAnd(),llvm::CombinerHelper::matchCombineShlOfExtend(), andllvm::CombinerHelper::matchUMulHToLShr().
◆ getPreferredSwitchConditionType()
| virtual |
Returns preferred type for switch condition.
Reimplemented inllvm::SPIRVTargetLowering, andllvm::X86TargetLowering.
Definition at line1652 of fileTargetLoweringBase.cpp.
ReferencesgetRegisterType().
Referenced byllvm::X86TargetLowering::getPreferredSwitchConditionType().
◆ getPreferredVectorAction()
| inlinevirtual |
Return the preferred vector type legalization action.
Reimplemented inllvm::AArch64TargetLowering,llvm::SITargetLowering,llvm::HexagonTargetLowering,llvm::MipsSETargetLowering,llvm::NVPTXTargetLowering,llvm::PPCTargetLowering,llvm::SystemZTargetLowering, andllvm::X86TargetLowering.
Definition at line517 of fileTargetLowering.h.
Referencesllvm::MVT::getVectorElementCount(),llvm::MVT::isPow2VectorType(),llvm::ElementCount::isScalar(),TypePromoteInteger,TypeScalarizeVector, andTypeWidenVector.
Referenced bycomputeRegisterProperties(),llvm::AArch64TargetLowering::getPreferredVectorAction(),llvm::SITargetLowering::getPreferredVectorAction(),llvm::MipsSETargetLowering::getPreferredVectorAction(),llvm::NVPTXTargetLowering::getPreferredVectorAction(),llvm::PPCTargetLowering::getPreferredVectorAction(),llvm::SystemZTargetLowering::getPreferredVectorAction(), andllvm::X86TargetLowering::getPreferredVectorAction().
◆ getPrefFunctionAlignment()
| inline |
Return the preferred function alignment.
Definition at line2046 of fileTargetLowering.h.
◆ getPrefLoopAlignment()
| virtual |
Return the preferred loop alignment.
Reimplemented inllvm::SITargetLowering,llvm::PPCTargetLowering, andllvm::X86TargetLowering.
Definition at line2021 of fileTargetLoweringBase.cpp.
Referencesllvm::TargetOptions::LoopAlignment, andllvm::TargetMachine::Options.
Referenced byllvm::SITargetLowering::getPrefLoopAlignment(),llvm::PPCTargetLowering::getPrefLoopAlignment(), andllvm::X86TargetLowering::getPrefLoopAlignment().
◆ getProgramPointerTy()
| inline |
Return the type for code pointers, which is determined by the program address space specified through the data layout.
Definition at line390 of fileTargetLowering.h.
ReferencesDL, andgetPointerTy().
◆ getRecipEstimateDivEnabled()
| int TargetLoweringBase::getRecipEstimateDivEnabled | ( | EVT | VT, |
| MachineFunction & | MF | ||
| ) | const |
Return a ReciprocalEstimate enum value for a division of the given type based on the function's attributes.
If the operation is not overridden by the function's attributes, "Unspecified" is returned and target defaults are expected to be used for instruction selection.
Definition at line2203 of fileTargetLoweringBase.cpp.
ReferencesgetOpEnabled(), andgetRecipEstimateForFunc().
◆ getRecipEstimateSqrtEnabled()
| int TargetLoweringBase::getRecipEstimateSqrtEnabled | ( | EVT | VT, |
| MachineFunction & | MF | ||
| ) | const |
Return a ReciprocalEstimate enum value for a square root of the given type based on the function's attributes.
If the operation is not overridden by the function's attributes, "Unspecified" is returned and target defaults are expected to be used for instruction selection.
Definition at line2198 of fileTargetLoweringBase.cpp.
ReferencesgetOpEnabled(), andgetRecipEstimateForFunc().
◆ getRegClassFor()
| inlinevirtual |
Return the register class that should be used for the specified value type.
Reimplemented inllvm::SITargetLowering, andllvm::ARMTargetLowering.
Definition at line1042 of fileTargetLowering.h.
Referencesassert(), andllvm::MVT::SimpleTy.
Referenced byallocateRVVReg(),llvm::CCState::analyzeMustTailForwardedRegisters(),llvm::SwiftErrorValueTracking::createEntriesInEntryBlock(),llvm::FunctionLoweringInfo::CreateReg(),llvm::PPCTargetLowering::emitEHSjLjSetJmp(),llvm::SystemZTargetLowering::emitEHSjLjSetJmp(),llvm::X86TargetLowering::EmitInstrWithCustomInserter(),llvm::FastISel::fastEmitInst_extractsubreg(),llvm::SwiftErrorValueTracking::getOrCreateVReg(),llvm::SwiftErrorValueTracking::getOrCreateVRegDefAt(),llvm::SITargetLowering::getRegClassFor(),llvm::ARMTargetLowering::getRegClassFor(),llvm::GenericScheduler::initPolicy(),llvm::NVPTXTargetLowering::LowerCall(),llvm::HexagonTargetLowering::LowerFormalArguments(),llvm::VETargetLowering::LowerFormalArguments(),llvm::SparcTargetLowering::LowerFormalArguments_64(),llvm::HexagonTargetLowering::LowerRETURNADDR(),llvm::LanaiTargetLowering::LowerRETURNADDR(),LowerRETURNADDR(),llvm::SwiftErrorValueTracking::propagateVRegs(),llvm::ResourcePriorityQueue::rawRegPressureDelta(),llvm::ResourcePriorityQueue::scheduledNode(),llvm::FastISel::selectFreeze(),llvm::FastISel::selectPatchpoint(),unpackFromRegLoc(), andllvm::X86TargetLowering::X86TargetLowering().
◆ getRegisterType()[1/2]
| inline |
Return the type of registers that this ValueType will eventually require.
Definition at line1734 of fileTargetLowering.h.
ReferencesgetRegisterType(),llvm::EVT::getSimpleVT(),getTypeToTransformTo(),getVectorTypeBreakdown(),llvm::EVT::isInteger(),llvm::EVT::isSimple(),llvm::EVT::isVector(), andllvm_unreachable.
◆ getRegisterType()[2/2]
Return the type of registers that this ValueType will eventually require.
Definition at line1728 of fileTargetLowering.h.
Referencesassert(), andllvm::MVT::SimpleTy.
Referenced byllvm::computeLegalValueVTs(),llvm::FunctionLoweringInfo::ComputePHILiveOutRegInfo(),llvm::FunctionLoweringInfo::CreateRegs(),llvm::TargetLowering::expandUnalignedLoad(),llvm::TargetLowering::expandUnalignedStore(),getNumRegisters(),getPreferredSwitchConditionType(),getRegisterType(),getRegisterTypeForCallingConv(),llvm::MipsTargetLowering::getRegisterTypeForCallingConv(),llvm::SPIRVTargetLowering::getRegisterTypeForCallingConv(),llvm::TargetLowering::getTypeForExtReturn(),llvm::MipsTargetLowering::getTypeForExtReturn(),getVectorTypeBreakdown(),llvm::AArch64TargetLowering::getVectorTypeBreakdownForCallingConv(),llvm::MipsTargetLowering::getVectorTypeBreakdownForCallingConv(),getVectorTypeBreakdownMVT(),llvm::FastISel::lowerCallTo(),llvm::TargetLowering::LowerCallTo(),llvm::RegsForValue::RegsForValue(), andshouldTransformMulToShiftsAddsSubs().
◆ getRegisterTypeForCallingConv()
| inlinevirtual |
Certain combinations of ABIs, Targets and features require that types are legal for some operations and not for other operations.
For MIPS all vector types must be passed through the integer register set.
Reimplemented inllvm::AArch64TargetLowering,llvm::SITargetLowering,llvm::MipsTargetLowering,llvm::RISCVTargetLowering,llvm::SPIRVTargetLowering,llvm::SystemZTargetLowering, andllvm::X86TargetLowering.
Definition at line1787 of fileTargetLowering.h.
ReferencesgetRegisterType().
Referenced byllvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(),llvm::CallLowering::determineAssignments(),llvm::RegsForValue::getCopyFromRegs(),llvm::RegsForValue::getCopyToRegs(),llvm::AArch64TargetLowering::getRegisterTypeForCallingConv(),llvm::SITargetLowering::getRegisterTypeForCallingConv(),llvm::RISCVTargetLowering::getRegisterTypeForCallingConv(),llvm::SystemZTargetLowering::getRegisterTypeForCallingConv(),llvm::X86TargetLowering::getRegisterTypeForCallingConv(),llvm::CallLowering::getReturnInfo(),llvm::GetReturnInfo(),llvm::TargetLowering::LowerCallTo(), andllvm::RegsForValue::RegsForValue().
◆ getRepRegClassCostFor()
Return the cost of the 'representative' register class for the specified value type.
Definition at line1071 of fileTargetLowering.h.
Referencesllvm::MVT::SimpleTy.
Referenced byGetCostForDef().
◆ getRepRegClassFor()
| inlinevirtual |
Return the 'representative' register class for the specified value type.
The 'representative' register class is the largest legal super-reg register class for the register class of the value type. For example, on i386 the rep register class for i8, i16, and i32 are GR32; while the rep register class is GR64 on x86_64.
Reimplemented inllvm::MipsSETargetLowering.
Definition at line1064 of fileTargetLowering.h.
Referencesllvm::MVT::SimpleTy.
Referenced byexpandBitCastF128ToI128(),expandBitCastI128ToF128(),GetCostForDef(), andllvm::MipsSETargetLowering::getRepRegClassFor().
◆ getSafeStackPointerLocation()
| virtual |
Returns the target-specific address of the unsafe stack pointer.
Reimplemented inllvm::AArch64TargetLowering, andllvm::X86TargetLowering.
Definition at line1892 of fileTargetLoweringBase.cpp.
Referencesllvm::IRBuilderBase::CreateCall(),getDefaultSafeStackPointerLocation(),llvm::IRBuilderBase::GetInsertBlock(),llvm::GlobalValue::getParent(),llvm::BasicBlock::getParent(),llvm::TargetMachine::getTargetTriple(),llvm::PointerType::getUnqual(), andllvm::Triple::isAndroid().
Referenced byllvm::AArch64TargetLowering::getSafeStackPointerLocation(), andllvm::X86TargetLowering::getSafeStackPointerLocation().
◆ getScalarShiftAmountTy()
| virtual |
Return the type to use for a scalar shift opcode, given the shifted amount type.
Targets should return a legal type if the input type is legal. Targets can return a type that is too small if the input type is illegal.
Reimplemented inllvm::AVRTargetLowering,llvm::XtensaTargetLowering,llvm::X86TargetLowering,llvm::SITargetLowering,llvm::BPFTargetLowering,llvm::M68kTargetLowering,llvm::MipsTargetLowering,llvm::MSP430TargetLowering,llvm::NVPTXTargetLowering,llvm::PPCTargetLowering,llvm::SparcTargetLowering,llvm::SystemZTargetLowering,llvm::VETargetLowering,llvm::AArch64TargetLowering, andllvm::XCoreTargetLowering.
Definition at line885 of fileTargetLoweringBase.cpp.
ReferencesDL, andllvm::MVT::getIntegerVT().
Referenced bygetShiftAmountTy().
◆ getSchedulingPreference()[1/2]
| inline |
Return target scheduling preference.
Definition at line1029 of fileTargetLowering.h.
Referenced byllvm::createDefaultScheduler(),llvm::PPCTargetLowering::getSchedulingPreference(), andllvm::ScheduleDAGSDNodes::newSUnit().
◆ getSchedulingPreference()[2/2]
| inlinevirtual |
Some scheduler, e.g.
hybrid, can switch to different scheduling heuristics for different nodes. This function returns the preference (or none) for the given node.
Reimplemented inllvm::ARMTargetLowering, andllvm::PPCTargetLowering.
Definition at line1036 of fileTargetLowering.h.
Referencesllvm::Sched::None.
◆ getSDagStackGuard()
Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nullptr.
Should be used only when getIRStackGuard returns nullptr.
Reimplemented inllvm::AArch64TargetLowering,llvm::ARMTargetLowering,llvm::PPCTargetLowering, andllvm::X86TargetLowering.
Definition at line1989 of fileTargetLoweringBase.cpp.
Referenced bygetLoadStackGuard(),llvm::AArch64TargetLowering::getSDagStackGuard(),llvm::ARMTargetLowering::getSDagStackGuard(),llvm::PPCTargetLowering::getSDagStackGuard(),llvm::X86TargetLowering::getSDagStackGuard(), andllvm::SelectionDAGBuilder::visitSPDescriptorParent().
◆ getSetCCResultType()
| virtual |
Return the ValueType of the result of SETCC operations.
Reimplemented inllvm::XtensaTargetLowering,llvm::HexagonTargetLowering,llvm::R600TargetLowering,llvm::SystemZTargetLowering,llvm::AArch64TargetLowering,llvm::SITargetLowering,llvm::ARMTargetLowering,llvm::AVRTargetLowering,llvm::BPFTargetLowering,llvm::CSKYTargetLowering,llvm::LoongArchTargetLowering,llvm::M68kTargetLowering,llvm::MipsTargetLowering,llvm::PPCTargetLowering,llvm::RISCVTargetLowering,llvm::SparcTargetLowering,llvm::VETargetLowering,llvm::X86TargetLowering, andllvm::NVPTXTargetLowering.
Definition at line1523 of fileTargetLoweringBase.cpp.
Referencesassert(),DL,getPointerTy(),llvm::EVT::isVector(), andllvm::MVT::SimpleTy.
Referenced byllvm::TargetLowering::buildSDIVPow2WithCMov(),llvm::TargetLowering::BuildUDIV(),combineFMinNumFMaxNum(),combinePredicateReduction(),combineShiftAnd1ToBitTest(),combineVSelectWithAllOnesOrZeros(),llvm::TargetLowering::CTTZTableLookup(),llvm::TargetLowering::expandABD(),llvm::TargetLowering::expandAddSubSat(),llvm::TargetLowering::expandCMP(),llvm::TargetLowering::expandCTLZ(),llvm::TargetLowering::expandCTTZ(),llvm::TargetLowering::expandDIVREMByConstant(),llvm::TargetLowering::expandFixedPointDiv(),llvm::TargetLowering::expandFixedPointMul(),llvm::TargetLowering::expandFMINIMUM_FMAXIMUM(),llvm::TargetLowering::expandFMINIMUMNUM_FMAXIMUMNUM(),llvm::TargetLowering::expandFP_ROUND(),llvm::TargetLowering::expandFP_TO_INT_SAT(),llvm::TargetLowering::expandFP_TO_UINT(),llvm::TargetLowering::expandIntMINMAX(),llvm::TargetLowering::expandMUL_LOHI(),llvm::TargetLowering::expandMULO(),llvm::SelectionDAG::expandMultipleResultFPLibCall(),llvm::TargetLowering::expandRoundInexactToOdd(),llvm::TargetLowering::expandSADDSUBO(),llvm::TargetLowering::expandShiftParts(),llvm::TargetLowering::expandShlSat(),llvm::TargetLowering::expandUADDSUBO(),foldXorTruncShiftIntoCmp(),llvm::AMDGPUTargetLowering::getIsFinite(),llvm::AMDGPUTargetLowering::getIsLtSmallestNormal(),llvm::AMDGPUTargetLowering::getScaledLogInput(),llvm::TargetLowering::getSqrtInputTest(),LowerADDSAT_SUBSAT(),llvm::AMDGPUTargetLowering::LowerDIVREM24(),llvm::AMDGPUTargetLowering::LowerFCEIL(),llvm::AMDGPUTargetLowering::lowerFEXP(),llvm::AMDGPUTargetLowering::lowerFEXP10Unsafe(),llvm::AMDGPUTargetLowering::lowerFEXP2(),llvm::AMDGPUTargetLowering::lowerFEXPUnsafe(),llvm::AMDGPUTargetLowering::LowerFFLOOR(),LowerFMINIMUM_FMAXIMUM(),llvm::AMDGPUTargetLowering::LowerFROUND(),llvm::AMDGPUTargetLowering::LowerFROUNDEVEN(),llvm::AMDGPUTargetLowering::LowerFTRUNC(),LowerMULO(),llvm::AMDGPUTargetLowering::LowerUDIVREM(),promoteTargetBoolean(),llvm::TargetLowering::SimplifySetCC(),llvm::TargetLowering::softenSetCCOperands(),llvm::SelectionDAG::UnrollVectorOverflowOp(),llvm::SelectionDAGBuilder::visitBitTestCase(),llvm::SelectionDAGBuilder::visitBitTestHeader(),llvm::SelectionDAGBuilder::visitJumpTableHeader(), andllvm::SelectionDAGBuilder::visitSPDescriptorParent().
◆ getShiftAmountTy()
| EVT TargetLoweringBase::getShiftAmountTy | ( | EVT | LHSTy, |
| constDataLayout & | DL | ||
| ) | const |
Returns the type for the shift amount of a shift opcode.
For vectors, returns the input type. For scalars, calls getScalarShiftAmountTy. If getScalarShiftAmountTy type cannot represent all possible shift amounts, returns MVT::i32.
Definition at line890 of fileTargetLoweringBase.cpp.
Referencesassert(),DL,getScalarShiftAmountTy(),llvm::EVT::getSizeInBits(),llvm::MVT::getSizeInBits(),llvm::EVT::isInteger(),llvm::EVT::isVector(), andllvm::Log2_32_Ceil().
Referenced byBuildExactSDIV(),BuildExactUDIV(),llvm::TargetLowering::BuildSDIV(),llvm::TargetLowering::BuildUDIV(),llvm::TargetLowering::expandBITREVERSE(),llvm::TargetLowering::expandBSWAP(),llvm::TargetLowering::expandCTLZ(),llvm::TargetLowering::expandCTPOP(),expandDivFix(),llvm::TargetLowering::expandFP_TO_SINT(),llvm::TargetLowering::expandVPBITREVERSE(),llvm::TargetLowering::expandVPBSWAP(),llvm::TargetLowering::expandVPCTLZ(),llvm::TargetLowering::expandVPCTPOP(),getCopyFromParts(),GetExponent(),getLimitedPrecisionExp2(),llvm::SelectionDAG::getShiftAmountConstant(),llvm::SelectionDAG::getShiftAmountOperand(), andllvm::AMDGPUTargetLowering::performTruncateCombine().
◆ getSimpleValueType()
| inline |
Return theMVT corresponding to this LLVM type. See getValueType.
Definition at line1718 of fileTargetLowering.h.
ReferencesDL,llvm::EVT::getSimpleVT(), andgetValueType().
Referenced byllvm::X86TTIImpl::getInterleavedMemoryOpCostAVX512(),llvm::InlineAsmLowering::lowerInlineAsm(), andllvm::FastISel::selectPatchpoint().
◆ getSqrtRefinementSteps()
| int TargetLoweringBase::getSqrtRefinementSteps | ( | EVT | VT, |
| MachineFunction & | MF | ||
| ) | const |
Return the refinement step count for a square root of the given type based on the function's attributes.
If the operation is not overridden by the function's attributes, "Unspecified" is returned and target defaults are expected to be used for instruction selection.
Definition at line2208 of fileTargetLoweringBase.cpp.
ReferencesgetOpRefinementSteps(), andgetRecipEstimateForFunc().
◆ getSSPStackGuardCheck()
If the target has a standard stack protection check function that performs validation and error handling, returns the function.
Otherwise, returns nullptr. Must be previously inserted by insertSSPDeclarations. Should be used only when getIRStackGuard returns nullptr.
Reimplemented inllvm::AArch64TargetLowering,llvm::ARMTargetLowering, andllvm::X86TargetLowering.
Definition at line1993 of fileTargetLoweringBase.cpp.
Referenced byllvm::AArch64TargetLowering::getSSPStackGuardCheck(),llvm::ARMTargetLowering::getSSPStackGuardCheck(),llvm::X86TargetLowering::getSSPStackGuardCheck(), andllvm::SelectionDAGBuilder::visitSPDescriptorParent().
◆ getStackPointerRegisterToSaveRestore()
| inline |
If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
Definition at line2015 of fileTargetLowering.h.
Referenced byllvm::RegsForValue::AddInlineAsmOperands(),llvm::calculateDbgEntityHistory(),TransferTracker::isEntryValueValue(),isRegOtherThanSPAndFP(),llvm::TargetInstrInfo::isSchedulingBoundary(),llvm::AMDGPULegalizerInfo::legalizeStackSave(),llvm::LanaiTargetLowering::LowerDYNAMIC_STACKALLOC(),llvm::LegalizerHelper::lowerDynStackAlloc(),llvm::LegalizerHelper::lowerStackRestore(),llvm::LegalizerHelper::lowerStackSave(),llvm::SITargetLowering::LowerSTACKSAVE(),LiveDebugValues::MLocTracker::MLocTracker(), andllvm::FunctionLoweringInfo::set().
◆ getStackProbeSymbolName()
| inlinevirtual |
Reimplemented inllvm::X86TargetLowering.
Definition at line2101 of fileTargetLowering.h.
◆ getStoreMemOperandFlags()
| MachineMemOperand::Flags TargetLoweringBase::getStoreMemOperandFlags | ( | constStoreInst & | SI, |
| constDataLayout & | DL | ||
| ) | const |
Definition at line2273 of fileTargetLoweringBase.cpp.
ReferencesgetTargetMMOFlags(),llvm::MachineMemOperand::MONonTemporal,llvm::MachineMemOperand::MOStore, andllvm::MachineMemOperand::MOVolatile.
◆ getStrictFPOperationAction()
| inline |
Definition at line1321 of fileTargetLowering.h.
ReferencesgetOperationAction(), andllvm_unreachable.
◆ getTargetMachine()
| inline |
Definition at line364 of fileTargetLowering.h.
Referenced byllvm::X86TargetLowering::addressingModeSupportsTLS(),llvm::BasicTTIImplBase< T >::areInlineCompatible(),llvm::GCNTTIImpl::areInlineCompatible(),llvm::ARMTTIImpl::areInlineCompatible(),llvm::X86TTIImpl::areInlineCompatible(),llvm::X86TTIImpl::areTypesABICompatible(),llvm::ARMTargetLowering::ARMTargetLowering(),llvm::WebAssembly::canLowerMultivalueReturn(),checkAddrSpaceIsValidForLibcall(),llvm::SystemZFrameLowering::create(),llvm::SITargetLowering::EmitInstrWithCustomInserter(),llvm::SITargetLowering::finalizeLowering(),llvm::GCNTTIImpl::getArithmeticInstrCost(),llvm::BasicTTIImplBase< T >::getAssumedAddrSpace(),llvm::NVPTXTargetLowering::getDivF32Level(),llvm::RISCVSubtarget::getInstructionSelector(),getIRStackGuard(),llvm::TargetLowering::getJumpTableEncoding(),llvm::RISCVTargetLowering::getJumpTableEncoding(),llvm::X86TargetLowering::getJumpTableEncoding(),llvm::PPCTargetLowering::getNegatedExpression(),llvm::PPCTargetLowering::getOptimalMemOpType(),llvm::NVPTXTargetLowering::getParamName(),llvm::PPCTargetLowering::getPICJumpTableRelocBase(),llvm::PPCTargetLowering::getPICJumpTableRelocBaseExpr(),llvm::X86TargetLowering::getPICJumpTableRelocBaseExpr(),llvm::BasicTTIImplBase< T >::getPredicatedAddrSpace(),llvm::PPCTargetLowering::getRegForInlineAsmConstraint(),llvm::SITargetLowering::getTgtMemIntrinsic(),getTM(),llvm::PPCTargetLowering::isAccessedAsGotIndirect(),llvm::SystemZSubtarget::isAddressedViaADA(),llvm::SITargetLowering::isFreeAddrSpaceCast(),isJumpTableRelative(),llvm::MipsTargetLowering::isJumpTableRelative(),llvm::X86TargetLowering::isLegalAddressingMode(),llvm::BasicTTIImplBase< T >::isNoopAddrSpaceCast(),llvm::TargetLowering::isOffsetFoldingLegal(),llvm::SystemZSubtarget::isPC32DBLSymbol(),llvm::TargetLowering::isPositionIndependent(),llvm::AArch64TargetLowering::isProfitableToHoist(),llvm::SITargetLowering::isProfitableToHoist(),llvm::PPCTargetLowering::isProfitableToHoist(),llvm::BasicTTIImplBase< T >::isSingleThreaded(),IsSmallObject(),llvm::M68kCallLowering::lowerCall(),llvm::LoongArchTargetLowering::LowerCall(),llvm::RISCVTargetLowering::LowerCall(),llvm::LanaiTargetLowering::LowerConstantPool(),llvm::RISCVTargetLowering::LowerCustomJumpTableEntry(),llvm::AMDGPUTargetLowering::lowerFEXP(),llvm::AMDGPUTargetLowering::LowerFLOGCommon(),llvm::SITargetLowering::LowerFormalArguments(),llvm::AMDGPUTargetLowering::LowerFP_TO_FP16(),llvm::HexagonTargetLowering::LowerGLOBALADDRESS(),llvm::LanaiTargetLowering::LowerGlobalAddress(),llvm::SparcTargetLowering::LowerGlobalTLSAddress(),llvm::LanaiTargetLowering::LowerJumpTable(),llvm::RISCVTargetLowering::LowerOperation(),llvm::SparcTargetLowering::makeAddress(),llvm::VETargetLowering::makeAddress(),llvm::AMDGPUTargetLowering::mayIgnoreSignedZero(),llvm::AArch64TargetLowering::PerformDAGCombine(),llvm::SITargetLowering::PerformDAGCombine(),llvm::GCNTTIImpl::rewriteIntrinsicWithAddressSpace(),llvm::RISCVTargetLowering::RISCVTargetLowering(),llvm::BasicTTIImplBase< T >::shouldBuildRelLookupTables(),llvm::SITargetLowering::shouldEmitFixup(),llvm::SITargetLowering::shouldEmitGOTReloc(),llvm::AArch64TargetLowering::shouldExpandAtomicCmpXchgInIR(),llvm::ARMTargetLowering::shouldExpandAtomicCmpXchgInIR(),llvm::AArch64TargetLowering::shouldExpandAtomicLoadInIR(),llvm::AArch64TargetLowering::shouldExpandAtomicRMWInIR(),llvm::ARMTargetLowering::shouldExpandAtomicRMWInIR(),llvm::SelectionDAGBuilder::shouldKeepJumpConditionsTogether(),llvm::HexagonTargetLowering::shouldReduceLoadWidth(),llvm::SITargetLowering::shouldUseLDSConstAddress(),llvm::CSKYSubtarget::useHardFloatABI(),llvm::NVPTXTargetLowering::usePrecSqrtF32(), andllvm::AArch64Subtarget::useSmallAddressing().
◆ getTargetMMOFlags()[1/2]
| inlinevirtual |
This callback is used to inspect load/store instructions and add target-specificMachineMemOperand flags to them.
The default implementation does nothing.
Reimplemented inllvm::AArch64TargetLowering,llvm::SITargetLowering, andllvm::RISCVTargetLowering.
Definition at line434 of fileTargetLowering.h.
Referencesllvm::MachineMemOperand::MONone.
Referenced bygetAtomicMemOperandFlags(),getLoadMemOperandFlags(), andgetStoreMemOperandFlags().
◆ getTargetMMOFlags()[2/2]
| inlinevirtual |
This callback is used to inspect load/storeSDNode.
The default implementation does nothing.
Reimplemented inllvm::RISCVTargetLowering.
Definition at line441 of fileTargetLowering.h.
Referencesllvm::MachineMemOperand::MONone.
◆ getTgtMemIntrinsic()
| inlinevirtual |
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (touches memory).
If this is the case, it returns true and store the intrinsic information into theIntrinsicInfo that was passed to the function.
Reimplemented inllvm::SITargetLowering,llvm::AArch64TargetLowering,llvm::ARMTargetLowering,llvm::HexagonTargetLowering,llvm::LoongArchTargetLowering,llvm::NVPTXTargetLowering,llvm::PPCTargetLowering,llvm::RISCVTargetLowering,llvm::SPIRVTargetLowering, andllvm::X86TargetLowering.
Definition at line1226 of fileTargetLowering.h.
◆ getTruncStoreAction()
| inline |
Return how this store with truncation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.
Definition at line1503 of fileTargetLowering.h.
Referencesassert(),Expand,llvm::EVT::getSimpleVT(),llvm::EVT::isExtended(),llvm::MVT::SimpleTy, andllvm::MVT::VALUETYPE_SIZE.
Referenced byisTruncStoreLegal(), andisTruncStoreLegalOrCustom().
◆ getTypeAction()[1/2]
| inline |
Return how we should legalize values of this type, either it is already legal (return 'Legal') or we need to promote it to a larger type (return 'Promote'), or we need to expand it into multiple registers of smaller integer type (return 'Expand').
'Custom' is not an option.
Definition at line1143 of fileTargetLowering.h.
ReferencesgetTypeConversion().
Referenced byllvm::TargetLowering::BuildSDIV(),llvm::TargetLowering::BuildUDIV(),llvm::X86TargetLowering::decomposeMulByConstant(),llvm::TargetLowering::expandVectorFindLastActive(),findMemType(),llvm::SelectionDAG::FoldConstantArithmetic(),llvm::BasicTTIImplBase< T >::getCastInstrCost(),llvm::AArch64TTIImpl::getCastInstrCost(),llvm::SelectionDAG::getConstant(),getCopyToPartsVector(),llvm::X86TargetLowering::getSetCCResultType(),getTypeToExpandTo(),getVectorTypeBreakdown(),LowerStore(),llvm::VETargetLowering::lowerVVP_LOAD_STORE(),OptimizeNoopCopyExpression(),llvm::LoongArchTargetLowering::ReplaceNodeResults(),llvm::RISCVTargetLowering::ReplaceNodeResults(),llvm::X86TargetLowering::ReplaceNodeResults(),shouldNormalizeToSelectSequence(), andwidenAbs().
◆ getTypeAction()[2/2]
| inline |
Definition at line1146 of fileTargetLowering.h.
Referencesllvm::TargetLoweringBase::ValueTypeActionImpl::getTypeAction().
◆ getTypeConversion()
| TargetLoweringBase::LegalizeKind TargetLoweringBase::getTypeConversion | ( | LLVMContext & | Context, |
| EVT | VT | ||
| ) | const |
Return pair that represents the legalization kind (first) that needs to happen toEVT (second) in order to type-legalize it.
First: how we should legalize values of this type, either it is already legal (return 'Legal') or we need to promote it to a larger type (return 'Promote'), or we need to expand it into multiple registers of smaller integer type (return 'Expand'). 'Custom' is not an option.
Second: for types supported by the target, this is an identity function. For types that must be promoted to larger types, this returns the larger type to promote to. For integer types that are larger than the largest integer register, this contains one step in the expansion to get to the smaller register. For illegal floating point types, this returns the integer type to transform to.
Definition at line948 of fileTargetLoweringBase.cpp.
Referencesassert(),llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::coefficientNextPowerOf2(),llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::divideCoefficientBy(),llvm::EVT::getHalfNumVectorElementsVT(),llvm::EVT::getIntegerVT(),llvm::EVT::getPow2VectorType(),llvm::EVT::getRoundIntegerType(),llvm::ElementCount::getScalable(),llvm::EVT::getSimpleVT(),llvm::EVT::getSizeInBits(),llvm::TargetLoweringBase::ValueTypeActionImpl::getTypeAction(),getTypeConversion(),llvm::EVT::getVectorElementCount(),llvm::EVT::getVectorElementType(),llvm::MVT::getVectorElementType(),llvm::EVT::getVectorVT(),llvm::MVT::getVectorVT(),llvm::EVT::isInteger(),llvm::EVT::isPow2VectorType(),llvm::isPowerOf2_32(),llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isScalable(),llvm::ElementCount::isScalar(),llvm::EVT::isSimple(),llvm::EVT::isVector(),llvm::MVT::isVector(),llvm::MVT::SimpleTy,TypeExpandInteger,TypeLegal,TypePromoteInteger,TypeScalarizeScalableVector,TypeScalarizeVector,TypeSoftenFloat,TypeSoftPromoteHalf,TypeSplitVector, andTypeWidenVector.
Referenced byllvm::AArch64TTIImpl::getIntrinsicInstrCost(),getTypeAction(),getTypeConversion(),llvm::BasicTTIImplBase< T >::getTypeLegalizationCost(),getTypeToTransformTo(), andgetVectorTypeBreakdown().
◆ getTypeToExpandTo()
| inline |
For types supported by the target, this is an identity function.
For types that must be expanded (i.e. integer types that are larger than the largest integer register or illegal floating point types), this returns the largest legal type it will be expanded to.
Definition at line1164 of fileTargetLowering.h.
Referencesassert(),getTypeAction(),getTypeToTransformTo(),llvm::EVT::isVector(),llvm_unreachable,TypeExpandInteger, andTypeLegal.
◆ getTypeToPromoteTo()
If the action for this operation is to promote, this method returns the ValueType to promote to.
Definition at line1643 of fileTargetLowering.h.
Referencesassert(),getOperationAction(),llvm::MVT::getScalarSizeInBits(),llvm::MVT::isFloatingPoint(),llvm::MVT::isInteger(),isTypeLegal(),Promote, andllvm::MVT::SimpleTy.
Referenced byllvm::RISCVTTIImpl::getArithmeticInstrCost(),llvm::RISCVTTIImpl::getIntrinsicInstrCost(), andisLoadBitCastBeneficial().
◆ getTypeToTransformTo()
| inlinevirtual |
For types supported by the target, this is an identity function.
For types that must be promoted to larger types, this returns the larger type to promote to. For integer types that are larger than the largest integer register, this contains one step in the expansion to get to the smaller register. For illegal floating point types, this returns the integer type to transform to.
Reimplemented inllvm::X86TargetLowering.
Definition at line1156 of fileTargetLowering.h.
ReferencesgetTypeConversion().
Referenced byllvm::TargetLowering::BuildSDIV(),llvm::TargetLowering::BuildUDIV(),combineMinNumMaxNumImpl(),combineShiftToMULH(),llvm::TargetLowering::expandCTPOP(),llvm::TargetLowering::expandVectorFindLastActive(),llvm::TargetLowering::expandVPCTPOP(),llvm::SelectionDAG::FoldConstantArithmetic(),llvm::SelectionDAG::getConstant(),getMemcpyLoadsAndStores(),getPTest(),llvm::FastISel::getRegForValue(),getRegisterType(),llvm::SelectionDAG::getSplatValue(),llvm::SelectionDAG::GetSplitDestVTs(),llvm::BasicTTIImplBase< T >::getStoreMinimumVF(),getTypeToExpandTo(),llvm::X86TargetLowering::getTypeToTransformTo(),getVectorTypeBreakdown(),LowerMSCATTER(),LowerStore(),llvm::VETargetLowering::lowerToVVP(),OptimizeNoopCopyExpression(),scalarizeBinOpOfSplats(),llvm::FastISel::selectBinaryOp(), andwidenAbs().
◆ getVaListSizeInBits()
| inlinevirtual |
Returns the size of the platform's va_list object.
Reimplemented inllvm::AArch64TargetLowering.
Definition at line1855 of fileTargetLowering.h.
ReferencesDL,getPointerTy(), andllvm::MVT::getSizeInBits().
◆ getValueType()
| inline |
Return theEVT corresponding to this LLVM type.
This is fixed by the LLVM operations except for the pointer size. If AllowUnknown is true, this will return MVT::Other for types with noEVT counterpart (e.g. structs), otherwise it will assert.
Definition at line1677 of fileTargetLowering.h.
ReferencesDL,llvm::Type::getContext(),llvm::EVT::getEVT(),getPointerTy(), andllvm::EVT::getVectorVT().
Referenced byanalyzeCallOperands(),llvm::X86TargetLowering::computeKnownBitsForTargetNode(),llvm::X86TargetLowering::ComputeNumSignBitsForTargetNode(),llvm::ComputeValueVTs(),foldFCmpToFPClassTest(),llvm::AArch64TTIImpl::getArithmeticInstrCost(),llvm::GCNTTIImpl::getArithmeticReductionCost(),llvm::X86TTIImpl::getArithmeticReductionCost(),llvm::ARMTTIImpl::getArithmeticReductionCost(),getAsmOperandValueType(),llvm::BasicTTIImplBase< T >::getCastInstrCost(),llvm::AArch64TTIImpl::getCastInstrCost(),llvm::ARMTTIImpl::getCastInstrCost(),llvm::X86TTIImpl::getCastInstrCost(),llvm::AArch64TTIImpl::getCmpSelInstrCost(),llvm::ARMTTIImpl::getCmpSelInstrCost(),llvm::ARMTTIImpl::getExtendedReductionCost(),llvm::AArch64TTIImpl::getExtractWithExtendCost(),llvm::BasicTTIImplBase< T >::getFPOpCost(),llvm::RISCVTTIImpl::getInterleavedMemoryOpCost(),llvm::X86TTIImpl::getInterleavedMemoryOpCost(),llvm::BasicTTIImplBase< T >::getIntrinsicInstrCost(),llvm::AArch64TTIImpl::getIntrinsicInstrCost(),llvm::ARMTTIImpl::getIntrinsicInstrCost(),llvm::RISCVTTIImpl::getIntrinsicInstrCost(),llvm::X86TTIImpl::getMaskedMemoryOpCost(),llvm::RISCVTTIImpl::getMemoryOpCost(),llvm::AArch64TTIImpl::getMemoryOpCost(),llvm::ARMTTIImpl::getMemoryOpCost(),llvm::PPCTTIImpl::getMemoryOpCost(),llvm::SystemZTTIImpl::getMemoryOpCost(),llvm::X86TTIImpl::getMemoryOpCost(),getMemValueType(),llvm::GCNTTIImpl::getMinMaxReductionCost(),llvm::ARMTTIImpl::getMinMaxReductionCost(),llvm::X86TTIImpl::getMinMaxReductionCost(),llvm::ARMTTIImpl::getMulAccReductionCost(),llvm::NVPTXTargetLowering::getPrototype(),llvm::FastISel::getRegForValue(),llvm::BasicTTIImplBase< T >::getRegUsageForType(),llvm::X86TTIImpl::getShuffleCost(),getSimpleValueType(),llvm::BasicTTIImplBase< T >::getStoreMinimumVF(),llvm::SITargetLowering::getTgtMemIntrinsic(),llvm::NVPTXTargetLowering::getTgtMemIntrinsic(),llvm::RISCVTargetLowering::getTgtMemIntrinsic(),llvm::BasicTTIImplBase< T >::getTypeBasedIntrinsicInstrCost(),llvm::BasicTTIImplBase< T >::getTypeLegalizationCost(),llvm::SelectionDAGBuilder::getValueImpl(),llvm::X86TTIImpl::getVectorInstrCost(),llvm::PPCTTIImpl::getVPMemoryOpCost(),llvm::MipsTTIImpl::hasDivRemOp(),llvm::SystemZTTIImpl::hasDivRemOp(),llvm::X86TTIImpl::hasDivRemOp(),llvm::BasicTTIImplBase< T >::haveFastSqrt(),llvm::RISCVTTIImpl::isElementTypeLegalForScalableVector(),isExtLoad(),llvm::AArch64TTIImpl::isExtPartOfAvgExpr(),llvm::BasicTTIImplBase< T >::isIndexedLoadLegal(),llvm::BasicTTIImplBase< T >::isIndexedStoreLegal(),llvm::ARMTargetLowering::isLegalAddressingMode(),llvm::RISCVTargetLowering::isLegalInterleavedAccessType(),llvm::RISCVTTIImpl::isLegalMaskedGatherScatter(),llvm::RISCVTTIImpl::isLegalMaskedLoadStore(),llvm::RISCVTTIImpl::isLegalStridedLoadStore(),llvm::RISCVTTIImpl::isLegalToVectorizeReduction(),llvm::AArch64TargetLowering::isProfitableToHoist(),llvm::PPCTargetLowering::isProfitableToHoist(),isPromotedInstructionLegal(),isSupportedType(),llvm::BasicTTIImplBase< T >::isTypeLegal(),llvm::SystemZTargetLowering::LowerCall(),llvm::TargetLowering::LowerCallTo(),llvm::NVPTXTargetLowering::LowerFormalArguments(),llvm::ARMTTIImpl::maybeLoweredToCall(),memVTFromLoadIntrData(),OptimizeExtractBits(),OptimizeNoopCopyExpression(),llvm::BasicTTIImplBase< T >::preferToKeepConstantsAttached(),llvm::FastISel::selectBitCast(),llvm::FastISel::selectCast(),llvm::FastISel::selectExtractValue(),llvm::FastISel::selectFNeg(),llvm::FastISel::selectFreeze(),llvm::FastISel::selectGetElementPtr(),llvm::FastISel::selectOperator(),llvm::TargetLowering::SimplifyDemandedVectorElts(),llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), andSinkShiftAndTruncate().
◆ getValueTypeActions()
| inline |
Definition at line1119 of fileTargetLowering.h.
◆ getVectorIdxTy()
| inlinevirtual |
Returns the type to be used for the index operand of:ISD::INSERT_VECTOR_ELT,ISD::EXTRACT_VECTOR_ELT,ISD::INSERT_SUBVECTOR, andISD::EXTRACT_SUBVECTOR.
Reimplemented inllvm::AMDGPUTargetLowering,llvm::SPIRVTargetLowering, andllvm::SystemZTargetLowering.
Definition at line421 of fileTargetLowering.h.
ReferencesDL, andgetPointerTy().
Referenced byllvm::MachineIRBuilder::buildExtractVectorElementConstant(),llvm::TargetLowering::expandVECTOR_COMPRESS(),llvm::SelectionDAG::getNode(),llvm::SelectionDAG::getVectorIdxConstant(),llvm::SparcTargetLowering::LowerCall_32(),llvm::SparcTargetLowering::LowerReturn_32(),llvm::LegalizerHelper::moreElementsVector(), andllvm::LegalizerHelper::scalarizeVectorBooleanStore().
◆ getVectorTypeBreakdown()
| unsigned TargetLoweringBase::getVectorTypeBreakdown | ( | LLVMContext & | Context, |
| EVT | VT, | ||
| EVT & | IntermediateVT, | ||
| unsigned & | NumIntermediates, | ||
| MVT & | RegisterVT | ||
| ) | const |
Vector types are broken down into some number of legal first class types.
getVectorTypeBreakdown - Vector types are broken down into some number of legal first class types.
For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8 promoted EVT::f64 values with theX86 FP stack. Similarly, EVT::v2i64 turns into 4 EVT::i32 values with bothPPC andX86.
This method returns the number of registers needed, and the VT for each register. It also returns the VT and quantity of the intermediate values before they are promoted/expanded.
For example, MVT::v8f32 maps to 2 MVT::v4f32 with Altivec or SSE1, or 8 promoted MVT::f64 values with theX86 FP stack. Similarly, MVT::v2i64 turns into 4 MVT::i32 values with bothPPC andX86.
This method returns the number of registers needed, and the VT for each register. It also returns the VT and quantity of the intermediate values before they are promoted/expanded.
Definition at line1541 of fileTargetLoweringBase.cpp.
Referencesllvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::coefficientNextPowerOf2(),llvm::divideCeil(),llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::divideCoefficientBy(),llvm::ElementCount::getFixed(),llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(),getRegisterType(),llvm::EVT::getSimpleVT(),llvm::EVT::getSizeInBits(),llvm::MVT::getSizeInBits(),getTypeAction(),getTypeConversion(),getTypeToTransformTo(),llvm::EVT::getVectorElementCount(),llvm::EVT::getVectorElementType(),llvm::EVT::getVectorVT(),llvm::isPowerOf2_32(),llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isScalable(),llvm::ElementCount::isScalar(),isTypeLegal(),llvm::EVT::isVector(),llvm::report_fatal_error(),TypeLegal,TypePromoteInteger, andTypeWidenVector.
Referenced bygetCopyFromPartsVector(),getCopyToPartsVector(),getNumRegisters(),llvm::SelectionDAG::getReducedAlign(),getRegisterType(), andgetVectorTypeBreakdownForCallingConv().
◆ getVectorTypeBreakdownForCallingConv()
| inlinevirtual |
Certain targets such as MIPS require that some types such as vectors are always broken down into scalars in some contexts.
This occurs even if the vector type is legal.
Reimplemented inllvm::AArch64TargetLowering,llvm::SITargetLowering,llvm::MipsTargetLowering,llvm::RISCVTargetLowering, andllvm::X86TargetLowering.
Definition at line1195 of fileTargetLowering.h.
ReferencesgetVectorTypeBreakdown().
Referenced bygetCopyFromPartsVector(),getCopyToPartsVector(),llvm::AArch64TargetLowering::getVectorTypeBreakdownForCallingConv(),llvm::SITargetLowering::getVectorTypeBreakdownForCallingConv(),llvm::RISCVTargetLowering::getVectorTypeBreakdownForCallingConv(), andllvm::X86TargetLowering::getVectorTypeBreakdownForCallingConv().
◆ getVPExplicitVectorLengthTy()
| inlinevirtual |
Returns the type to be used for the EVL/AVL operand of VP nodes: ISD::VP_ADD, ISD::VP_SUB, etc.
It must be a legal scalar integer type, and must be at least as large as i32. The EVL is implicitly zero-extended to any larger type.
Definition at line429 of fileTargetLowering.h.
◆ hasAndNot()
Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify select or other instructions.
Reimplemented inllvm::AArch64TargetLowering,llvm::LoongArchTargetLowering,llvm::VETargetLowering, andllvm::X86TargetLowering.
Definition at line804 of fileTargetLowering.h.
ReferenceshasAndNotCompare(), andX.
Referenced bycombineAndNotOrIntoAndNotAnd(), andfoldVSelectToSignBitSplatMask().
◆ hasAndNotCompare()
Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) != Y —> (~X & Y) != 0.
This may be profitable if the target has a bitwise and-not operation that sets comparison flags. A target may want to limit the transformation based on the type of Y or if Y is a constant.
Note that the transform will not occur if Y is known to be a power-of-2 because a mask and compare of a single bit can be handled by inverting the predicate, for example: (X & 8) == 8 —> (X & 8) != 0
Reimplemented inllvm::AArch64TargetLowering,llvm::LoongArchTargetLowering,llvm::RISCVTargetLowering,llvm::X86TargetLowering, andllvm::PPCTargetLowering.
Definition at line797 of fileTargetLowering.h.
Referenced byhasAndNot().
◆ hasBigEndianPartOrdering()
| inline |
When splitting a value of the specified type into parts, does the Lo or Hi part come first? This usually follows the endianness, except for ppcf128, where the Hi part always comes first.
Definition at line1839 of fileTargetLowering.h.
ReferencesDL.
Referenced bygetCopyFromParts(), andllvm::CallLowering::handleAssignments().
◆ hasBitTest()
Return true if the target has a bit-test instruction: (X & (1 << Y)) ==/!= 0 This knowledge can be used to prevent breaking the pattern, or creating it if it could be recognized.
Reimplemented inllvm::HexagonTargetLowering,llvm::MipsTargetLowering,llvm::RISCVTargetLowering, andllvm::X86TargetLowering.
Definition at line814 of fileTargetLowering.h.
Referenced bycombineShiftAnd1ToBitTest(), andshouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd().
◆ hasExtractBitsInsn()
| inline |
Return true if the target has BitExtract instructions.
Definition at line513 of fileTargetLowering.h.
◆ hasFastEqualityCompare()
Return the preferred operand type if the target has a quick way to compare integer values of the given size.
Assume that any legal integer type can be compared efficiently. Targets may override this to allow illegal wide types to return a vector type if there is support to compare that type.
Reimplemented inllvm::X86TargetLowering.
Definition at line780 of fileTargetLowering.h.
Referencesllvm::MVT::getIntegerVT(),llvm::MVT::INVALID_SIMPLE_VALUE_TYPE, andisTypeLegal().
◆ hasInlineStackProbe()
| inlinevirtual |
Reimplemented inllvm::AArch64TargetLowering,llvm::PPCTargetLowering,llvm::RISCVTargetLowering,llvm::SystemZTargetLowering, andllvm::X86TargetLowering.
Definition at line2099 of fileTargetLowering.h.
Referenced byllvm::SystemZELFFrameLowering::emitPrologue().
◆ hasMultipleConditionRegisters()
| inline |
Return true if multiple condition registers are available.
Definition at line508 of fileTargetLowering.h.
Referenced byshouldNormalizeToSelectSequence(), andsinkCmpExpression().
◆ hasPairedLoad()
Return true if the target supplies and combines to a paired load two loaded values of type LoadedType next to each other in memory.
RequiredAlignment gives the minimal alignment constraints that must be met to be able to select this paired load.
This information isnot used to generate actual paired loads, but it is used to generate a sequence of loads that is easier to combine into a paired load. For instance, something like this: a = load i64* addr b = trunc i64 a to i32 c = lshr i64 a, 32 d = trunc i64 c to i32 will be optimized into: b = load i32* addr1 d = load i32* addr2 Where addr1 = addr2 +/- sizeof(i32).
In other words, unless the target performs a post-isel load combining, this information should not be provided because it will generate more loads.
Reimplemented inllvm::AArch64TargetLowering.
Definition at line3122 of fileTargetLowering.h.
◆ hasStackProbeSymbol()
| inlinevirtual |
Returns the name of the symbol used to emit stack probes or the empty string if not applicable.
Reimplemented inllvm::X86TargetLowering.
Definition at line2097 of fileTargetLowering.h.
◆ hasStandaloneRem()
Return true if the target can handle a standalone remainder operation.
Reimplemented inllvm::ARMTargetLowering, andllvm::VETargetLowering.
Definition at line562 of fileTargetLowering.h.
◆ hasTargetDAGCombine()
| inline |
If true, the target has custom DAG combine transformations that it can perform for the specified node.
Definition at line1845 of fileTargetLowering.h.
Referencesassert().
◆ hasVectorBlend()
| inlinevirtual |
Return true if the target has a vector blend instruction.
Reimplemented inllvm::X86TargetLowering.
Definition at line3128 of fileTargetLowering.h.
Referenced byllvm::SelectionDAG::getVectorShuffle().
◆ initActions()
| protected |
Initialize all of the actions to default values.
Definition at line657 of fileTargetLoweringBase.cpp.
Referencesllvm::ISD::ABDS,llvm::ISD::ABDU,llvm::ISD::ABS,llvm::ISD::ADDC,llvm::ISD::ADDE,AddPromotedToType(),llvm::MVT::all_valuetypes(),llvm::ISD::ANY_EXTEND_VECTOR_INREG,llvm::ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS,llvm::ISD::ATOMIC_SWAP,llvm::ISD::AVGCEILS,llvm::ISD::AVGCEILU,llvm::ISD::AVGFLOORS,llvm::ISD::AVGFLOORU,llvm::ISD::BITREVERSE,llvm::ISD::BUILTIN_OP_END,llvm::ISD::CLEAR_CACHE,llvm::ISD::CONCAT_VECTORS,llvm::ISD::ConstantFP,llvm::ISD::CTLZ_ZERO_UNDEF,llvm::ISD::CTTZ_ZERO_UNDEF,llvm::ISD::DEBUGTRAP,llvm::ISD::DELETED_NODE,llvm::enum_seq(),Expand,llvm::ISD::EXTLOAD,llvm::ISD::FACOS,llvm::ISD::FASIN,llvm::ISD::FATAN,llvm::ISD::FATAN2,llvm::ISD::FCBRT,llvm::ISD::FCEIL,llvm::ISD::FCOPYSIGN,llvm::ISD::FCOSH,llvm::ISD::FEXP,llvm::ISD::FEXP10,llvm::ISD::FEXP2,llvm::ISD::FFLOOR,llvm::ISD::FFREXP,llvm::ISD::FGETSIGN,llvm::ISD::FLDEXP,llvm::ISD::FLOG,llvm::ISD::FLOG10,llvm::ISD::FLOG2,llvm::ISD::FMAD,llvm::ISD::FMAXIMUM,llvm::ISD::FMAXIMUMNUM,llvm::ISD::FMAXNUM,llvm::ISD::FMAXNUM_IEEE,llvm::ISD::FMINIMUM,llvm::ISD::FMINIMUMNUM,llvm::ISD::FMINNUM,llvm::ISD::FMINNUM_IEEE,llvm::ISD::FNEARBYINT,llvm::force_iteration_on_noniterable_enum,llvm::ISD::FP_TO_SINT_SAT,llvm::ISD::FP_TO_UINT_SAT,llvm::MVT::fp_valuetypes(),llvm::ISD::FPOWI,llvm::ISD::FRINT,llvm::ISD::FROUND,llvm::ISD::FROUNDEVEN,llvm::ISD::FSHL,llvm::ISD::FSHR,llvm::ISD::FSINCOS,llvm::ISD::FSINH,llvm::ISD::FTAN,llvm::ISD::FTANH,llvm::ISD::FTRUNC,llvm::ISD::GET_DYNAMIC_AREA_OFFSET,llvm::ISD::GET_FPENV,llvm::ISD::GET_FPENV_MEM,llvm::ISD::GET_FPMODE,llvm::MVT::getIntegerVT(),llvm::ISD::IS_FPCLASS,llvm::MVT::isValid(),llvm::ISD::LAST_INDEXED_MODE,LibCall,llvm::ISD::LLRINT,llvm::ISD::LLROUND,llvm::ISD::LRINT,llvm::ISD::LROUND,llvm::ISD::PARITY,llvm::ISD::PRE_INC,llvm::ISD::PREFETCH,Promote,llvm::ISD::READCYCLECOUNTER,llvm::ISD::READSTEADYCOUNTER,llvm::ISD::RESET_FPENV,llvm::ISD::RESET_FPMODE,llvm::ISD::SADDO,llvm::ISD::SADDO_CARRY,llvm::ISD::SADDSAT,llvm::ISD::SCMP,llvm::ISD::SDIVFIX,llvm::ISD::SDIVFIXSAT,llvm::ISD::SET_FPENV,llvm::ISD::SET_FPENV_MEM,llvm::ISD::SET_FPMODE,setAtomicLoadExtAction(),llvm::ISD::SETCCCARRY,setIndexedLoadAction(),setIndexedMaskedLoadAction(),setIndexedMaskedStoreAction(),setIndexedStoreAction(),setLoadExtAction(),setOperationAction(),setTruncStoreAction(),llvm::ISD::SEXTLOAD,llvm::ISD::SIGN_EXTEND_INREG,llvm::ISD::SIGN_EXTEND_VECTOR_INREG,llvm::ISD::SMAX,llvm::ISD::SMIN,llvm::ISD::SMULFIX,llvm::ISD::SMULFIXSAT,llvm::ISD::SMULO,llvm::ISD::SPLAT_VECTOR,llvm::ISD::SSHLSAT,llvm::ISD::SSUBO,llvm::ISD::SSUBO_CARRY,llvm::ISD::SSUBSAT,llvm::ISD::SUBC,llvm::ISD::SUBE,llvm::ISD::TRAP,llvm::ISD::TRUNCATE_SSAT_S,llvm::ISD::TRUNCATE_SSAT_U,llvm::ISD::TRUNCATE_USAT_U,llvm::ISD::UADDO,llvm::ISD::UADDO_CARRY,llvm::ISD::UADDSAT,llvm::ISD::UBSANTRAP,llvm::ISD::UCMP,llvm::ISD::UDIVFIX,llvm::ISD::UDIVFIXSAT,llvm::ISD::UMAX,llvm::ISD::UMIN,llvm::ISD::UMULFIX,llvm::ISD::UMULFIXSAT,llvm::ISD::UMULO,llvm::ISD::USHLSAT,llvm::ISD::USUBO,llvm::ISD::USUBO_CARRY,llvm::ISD::USUBSAT,llvm::ISD::VECREDUCE_ADD,llvm::ISD::VECREDUCE_AND,llvm::ISD::VECREDUCE_FADD,llvm::ISD::VECREDUCE_FMAX,llvm::ISD::VECREDUCE_FMAXIMUM,llvm::ISD::VECREDUCE_FMIN,llvm::ISD::VECREDUCE_FMINIMUM,llvm::ISD::VECREDUCE_FMUL,llvm::ISD::VECREDUCE_MUL,llvm::ISD::VECREDUCE_OR,llvm::ISD::VECREDUCE_SEQ_FADD,llvm::ISD::VECREDUCE_SEQ_FMUL,llvm::ISD::VECREDUCE_SMAX,llvm::ISD::VECREDUCE_SMIN,llvm::ISD::VECREDUCE_UMAX,llvm::ISD::VECREDUCE_UMIN,llvm::ISD::VECREDUCE_XOR,llvm::ISD::VECTOR_COMPRESS,llvm::ISD::VECTOR_FIND_LAST_ACTIVE,llvm::ISD::VECTOR_SPLICE,llvm::ISD::ZERO_EXTEND_VECTOR_INREG, andllvm::ISD::ZEXTLOAD.
Referenced byTargetLoweringBase().
◆ insertSSPDeclarations()
| virtual |
Inserts necessary declarations for SSP (stack protection) purpose.
Should be used only when getIRStackGuard returns nullptr.
Reimplemented inllvm::AArch64TargetLowering,llvm::ARMTargetLowering,llvm::PPCTargetLowering,llvm::SparcTargetLowering,llvm::SystemZTargetLowering, andllvm::X86TargetLowering.
Definition at line1970 of fileTargetLoweringBase.cpp.
Referencesllvm::GlobalValue::ExternalLinkage,llvm::TargetMachine::getRelocationModel(),llvm::TargetMachine::getTargetTriple(),llvm::PointerType::getUnqual(),llvm::Triple::isOSDarwin(),llvm::Triple::isOSFreeBSD(),llvm::Triple::isPPC64(),llvm::Triple::isWindowsGNUEnvironment(), andllvm::Reloc::Static.
Referenced bygetStackGuard(),llvm::AArch64TargetLowering::insertSSPDeclarations(),llvm::ARMTargetLowering::insertSSPDeclarations(),llvm::PPCTargetLowering::insertSSPDeclarations(),llvm::SparcTargetLowering::insertSSPDeclarations(), andllvm::X86TargetLowering::insertSSPDeclarations().
◆ InstructionOpcodeToISD()
| int TargetLoweringBase::InstructionOpcodeToISD | ( | unsigned | Opcode | ) | const |
Get theISD node that corresponds to theInstruction class opcode.
Definition at line1765 of fileTargetLoweringBase.cpp.
Referencesllvm::Add,llvm::ISD::ADD,llvm::ISD::ADDRSPACECAST,llvm::And,llvm::ISD::AND,llvm::ISD::BITCAST,llvm::ISD::EXTRACT_VECTOR_ELT,llvm::FAdd,llvm::ISD::FADD,llvm::ISD::FDIV,llvm::FMul,llvm::ISD::FMUL,llvm::ISD::FNEG,llvm::ISD::FP_EXTEND,llvm::ISD::FP_ROUND,llvm::ISD::FP_TO_SINT,llvm::ISD::FP_TO_UINT,llvm::ISD::FREEZE,llvm::ISD::FREM,llvm::ISD::FSUB,llvm::ISD::INSERT_VECTOR_ELT,llvm_unreachable,llvm::ISD::LOAD,llvm::ISD::MERGE_VALUES,llvm::Mul,llvm::ISD::MUL,llvm::Or,llvm::ISD::OR,PHI,llvm::ISD::SDIV,llvm::ISD::SELECT,Select,llvm::ISD::SETCC,llvm::ISD::SHL,llvm::ISD::SIGN_EXTEND,llvm::ISD::SINT_TO_FP,llvm::ISD::SRA,llvm::ISD::SREM,llvm::ISD::SRL,llvm::ISD::STORE,llvm::ISD::SUB,llvm::ISD::TRUNCATE,llvm::ISD::UDIV,llvm::ISD::UINT_TO_FP,llvm::ISD::UREM,llvm::ISD::VECTOR_SHUFFLE,llvm::Xor,llvm::ISD::XOR, andllvm::ISD::ZERO_EXTEND.
Referenced byllvm::AArch64TTIImpl::getArithmeticInstrCost(),llvm::GCNTTIImpl::getArithmeticInstrCost(),llvm::ARMTTIImpl::getArithmeticInstrCost(),llvm::NVPTXTTIImpl::getArithmeticInstrCost(),llvm::PPCTTIImpl::getArithmeticInstrCost(),llvm::RISCVTTIImpl::getArithmeticInstrCost(),llvm::X86TTIImpl::getArithmeticInstrCost(),llvm::AArch64TTIImpl::getArithmeticReductionCost(),llvm::RISCVTTIImpl::getArithmeticReductionCost(),llvm::X86TTIImpl::getArithmeticReductionCost(),llvm::ARMTTIImpl::getArithmeticReductionCost(),llvm::AArch64TTIImpl::getArithmeticReductionCostSVE(),llvm::BasicTTIImplBase< T >::getCastInstrCost(),llvm::AArch64TTIImpl::getCastInstrCost(),llvm::ARMTTIImpl::getCastInstrCost(),llvm::PPCTTIImpl::getCastInstrCost(),llvm::RISCVTTIImpl::getCastInstrCost(),llvm::X86TTIImpl::getCastInstrCost(),llvm::AArch64TTIImpl::getCmpSelInstrCost(),llvm::ARMTTIImpl::getCmpSelInstrCost(),llvm::X86TTIImpl::getCmpSelInstrCost(),llvm::ARMTTIImpl::getExtendedReductionCost(),llvm::PPCTTIImpl::getVectorInstrCost(),llvm::X86TTIImpl::getVectorInstrCost(),isPromotedInstructionLegal(),llvm::ARMTTIImpl::maybeLoweredToCall(),SinkShiftAndTruncate(), andllvm::PPCTTIImpl::vectorCostAdjustmentFactor().
◆ IntrinsicIDToISD()
| int TargetLoweringBase::IntrinsicIDToISD | ( | Intrinsic::ID | ID | ) | const |
Get theISD node that corresponds to theIntrinsic ID.
ReturnsISD::DELETED_NODE by default for an unsupportedIntrinsic ID.
Definition at line1844 of fileTargetLoweringBase.cpp.
Referencesllvm::ISD::DELETED_NODE,llvm::ISD::FEXP, andllvm::ISD::FEXP2.
◆ isAtomicLoadExtLegal()
| inline |
Return true if the specified atomic load with extension is legal on this target.
Definition at line1496 of fileTargetLowering.h.
ReferencesgetAtomicLoadExtAction(), andLegal.
Referenced bytryToFoldExtOfAtomicLoad().
◆ isBeneficialToExpandPowI()
| inline |
Return true if it is beneficial to expand an @llvm.powi.
- intrinsic. If not optimizing for size, expanding @llvm.powi.* intrinsics is always considered beneficial. If optimizing for size, expansion is only considered beneficial for upto 5 multiplies and a divide (if the exponent is negative).
Definition at line2465 of fileTargetLowering.h.
ReferencesE,llvm::Exponent,llvm::Log2_64(), andllvm::popcount().
Referenced byExpandPowI(),llvm::BasicTTIImplBase< T >::getIntrinsicInstrCost(), andllvm::CombinerHelper::matchFPowIExpansion().
◆ isBinOp()
Return true if the node is a math/logic binary operator.
Reimplemented inllvm::X86TargetLowering.
Definition at line2941 of fileTargetLowering.h.
Referencesllvm::ISD::FDIV,llvm::ISD::FREM,llvm::ISD::FSUB,isCommutativeBinOp(),llvm::ISD::ROTL,llvm::ISD::ROTR,llvm::ISD::SDIV,llvm::ISD::SHL,llvm::ISD::SRA,llvm::ISD::SREM,llvm::ISD::SRL,llvm::ISD::SSUBSAT,llvm::ISD::SUB,llvm::ISD::UDIV,llvm::ISD::UREM, andllvm::ISD::USUBSAT.
Referenced bycanonicalizeShuffleWithOp(),getKnownUndefForVectorBinop(),llvm::X86TargetLowering::isBinOp(),narrowExtractedVectorBinOp(),narrowInsertExtractVectorBinOp(),performBUILD_VECTORCombine(),performConcatVectorsCombine(),performINSERT_VECTOR_ELTCombine(),scalarizeExtractedBinOp(), andllvm::RISCVTargetLowering::shouldScalarizeBinop().
◆ isCheapToSpeculateCtlz()
Return true if it is cheap to speculate a call to intrinsic ctlz.
Reimplemented inllvm::AArch64TargetLowering,llvm::HexagonTargetLowering,llvm::SystemZTargetLowering,llvm::VETargetLowering,llvm::AMDGPUTargetLowering,llvm::ARMTargetLowering,llvm::LoongArchTargetLowering,llvm::MipsTargetLowering,llvm::NVPTXTargetLowering,llvm::PPCTargetLowering,llvm::RISCVTargetLowering, andllvm::X86TargetLowering.
Definition at line712 of fileTargetLowering.h.
Referenced bydespeculateCountZeros(), andllvm::BasicTTIImplBase< T >::getIntrinsicInstrCost().
◆ isCheapToSpeculateCttz()
Return true if it is cheap to speculate a call to intrinsic cttz.
Reimplemented inllvm::AArch64TargetLowering,llvm::HexagonTargetLowering,llvm::SystemZTargetLowering,llvm::AMDGPUTargetLowering,llvm::ARMTargetLowering,llvm::LoongArchTargetLowering,llvm::MipsTargetLowering,llvm::PPCTargetLowering,llvm::RISCVTargetLowering, andllvm::X86TargetLowering.
Definition at line707 of fileTargetLowering.h.
Referenced bydespeculateCountZeros(), andllvm::BasicTTIImplBase< T >::getIntrinsicInstrCost().
◆ isCommutativeBinOp()
Returns true if the opcode is a commutative binary operation.
Reimplemented inllvm::X86TargetLowering.
Definition at line2897 of fileTargetLowering.h.
Referencesllvm::ISD::ABDS,llvm::ISD::ABDU,llvm::ISD::ADD,llvm::ISD::ADDC,llvm::ISD::ADDE,llvm::ISD::AND,llvm::ISD::AVGCEILS,llvm::ISD::AVGCEILU,llvm::ISD::AVGFLOORS,llvm::ISD::AVGFLOORU,llvm::ISD::FADD,llvm::ISD::FMAXIMUM,llvm::ISD::FMAXIMUMNUM,llvm::ISD::FMAXNUM,llvm::ISD::FMAXNUM_IEEE,llvm::ISD::FMINIMUM,llvm::ISD::FMINIMUMNUM,llvm::ISD::FMINNUM,llvm::ISD::FMINNUM_IEEE,llvm::ISD::FMUL,llvm::ISD::MUL,llvm::ISD::MULHS,llvm::ISD::MULHU,llvm::ISD::OR,llvm::ISD::SADDO,llvm::ISD::SADDSAT,llvm::ISD::SMAX,llvm::ISD::SMIN,llvm::ISD::SMUL_LOHI,llvm::ISD::UADDO,llvm::ISD::UADDSAT,llvm::ISD::UMAX,llvm::ISD::UMIN,llvm::ISD::UMUL_LOHI, andllvm::ISD::XOR.
Referenced byllvm::SelectionDAG::canonicalizeCommutativeBinop(),llvm::SelectionDAG::FoldConstantArithmetic(),llvm::SelectionDAG::getNode(),isBinOp(),llvm::X86TargetLowering::isCommutativeBinOp(), andllvm::TargetLowering::SimplifySetCC().
◆ isComplexDeinterleavingOperationSupported()
| inlinevirtual |
Does this target support complex deinterleaving with the given operation and type.
Reimplemented inllvm::AArch64TargetLowering, andllvm::ARMTargetLowering.
Definition at line3415 of fileTargetLowering.h.
◆ isComplexDeinterleavingSupported()
| inlinevirtual |
Does this target support complex deinterleaving.
Reimplemented inllvm::AArch64TargetLowering, andllvm::ARMTargetLowering.
Definition at line3411 of fileTargetLowering.h.
◆ isCondCodeLegal()
| inline |
Return true if the specified condition code is legal for a comparison of the specified types on this target.
Definition at line1630 of fileTargetLowering.h.
ReferencesCC,getCondCodeAction(), andLegal.
Referenced byllvm::TargetLowering::createSelectForFMINNUM_FMAXNUM(),foldFCmpToFPClassTest(),llvm::SelectionDAG::FoldSetCC(),llvm::TargetLowering::LegalizeSetCCCondCode(),llvm::R600TargetLowering::PerformDAGCombine(), andllvm::TargetLowering::SimplifySetCC().
◆ isCondCodeLegalOrCustom()
| inline |
Return true if the specified condition code is legal or custom for a comparison of the specified types on this target.
Definition at line1636 of fileTargetLowering.h.
ReferencesCC,Custom,getCondCodeAction(), andLegal.
Referenced byllvm::TargetLowering::expandIS_FPCLASS(), andllvm::TargetLowering::LegalizeSetCCCondCode().
◆ isCtlzFast()
| inlinevirtual |
Return true if ctlz instruction is fast.
Reimplemented inllvm::HexagonTargetLowering,llvm::PPCTargetLowering,llvm::VETargetLowering, andllvm::X86TargetLowering.
Definition at line717 of fileTargetLowering.h.
Referenced byllvm::TargetLowering::lowerCmpEqZeroToCtlzSrl().
◆ isCtpopFast()
Return true if ctpop instruction is fast.
Reimplemented inllvm::RISCVTargetLowering.
Definition at line722 of fileTargetLowering.h.
Referencesllvm::ISD::CTPOP, andisOperationLegal().
Referenced bysimplifySetCCWithCTPOP().
◆ isEqualityCmpFoldedWithSignedCmp()
| inlinevirtual |
Return true if instruction generated for equality comparison is folded with instruction generated for signed comparison.
Reimplemented inllvm::PPCTargetLowering.
Definition at line734 of fileTargetLowering.h.
Referenced byfoldICmpWithDominatingICmp().
◆ isExtFree()
| inline |
Return true if the extension represented byI is free.
Unlikely the is[Z|FP]ExtFree family which is based on types, this method can use the context provided byI to decide whether or notI is free. This method extends the behavior of the is[Z|FP]ExtFree family. In other words, if is[Z|FP]Free returns true, then this method returns true as well. The converse is not true. The target can perform the adequate checks by overriding isExtFreeImpl.
- Precondition
Imust be a sign, zero, or fp extension.
Definition at line3008 of fileTargetLowering.h.
Referencesllvm::EVT::getEVT(),I,isExtFreeImpl(),isFPExtFree(),isZExtFree(), andllvm_unreachable.
◆ isExtFreeImpl()
| inlineprotectedvirtual |
Return true if the extension represented byI is free.
- Precondition
Iis a sign, zero, or fp extension and is[Z|FP]ExtFree of the related types is not true.
Definition at line3683 of fileTargetLowering.h.
Referenced byisExtFree().
◆ isExtLoad()
| inline |
Return true ifLoad andExt can form an ExtLoad.
For example, inAArch64 L = load i8, i8* ptr E = zext i8 L to i32 can be lowered into one load instruction ldrb w0, [x0]
Definition at line3033 of fileTargetLowering.h.
Referencesassert(),DL,getValueType(),isLoadExtLegal(),isTruncateFree(),isTypeLegal(),llvm::ISD::SEXTLOAD, andllvm::ISD::ZEXTLOAD.
◆ isExtractSubvectorCheap()
| inlinevirtual |
Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type from this source type with this index.
This is needed because EXTRACT_SUBVECTOR usually has custom lowering that depends on the index of the first element, and only the target knows which lowering is cheap.
Reimplemented inllvm::AArch64TargetLowering,llvm::SITargetLowering,llvm::ARMTargetLowering,llvm::HexagonTargetLowering,llvm::RISCVTargetLowering, andllvm::X86TargetLowering.
Definition at line3331 of fileTargetLowering.h.
Referenced byfoldExtractSubvectorFromShuffleVector(),llvm::SelectionDAG::matchBinOpReduction(), andnarrowExtractedVectorBinOp().
◆ isExtractVecEltCheap()
| inlinevirtual |
Return true if extraction of a scalar element from the given vector type at the given index is cheap.
For example, if scalar operations occur on the same register file as vector operations, then an extract element may be a sub-register rename rather than an actual instruction.
Reimplemented inllvm::SITargetLowering, andllvm::X86TargetLowering.
Definition at line3346 of fileTargetLowering.h.
Referenced byscalarizeBinOpOfSplats().
◆ isFAbsFree()
Return true if an fabs operation is free to the point where it is never worthwhile to replace it with a bitwise operation.
Reimplemented inllvm::AMDGPUTargetLowering.
Definition at line3223 of fileTargetLowering.h.
Referencesassert(), andllvm::EVT::isFloatingPoint().
Referenced byllvm::TargetLowering::expandIS_FPCLASS(),foldFCmpToFPClassTest(), andllvm::BasicTTIImplBase< T >::getTypeBasedIntrinsicInstrCost().
◆ isFMADLegal()[1/2]
| inlinevirtual |
Returns true ifMI can be combined with another instruction to form TargetOpcode::G_FMAD.
N may be an TargetOpcode::G_FADD, TargetOpcode::G_FSUB, or an TargetOpcode::G_FMUL which will be distributed into an fadd/fsub.
Reimplemented inllvm::SITargetLowering.
Definition at line3266 of fileTargetLowering.h.
Referencesassert(),llvm::LLT::getScalarSizeInBits(),isOperationLegal(), andMI.
◆ isFMADLegal()[2/2]
| inlinevirtual |
Returns true if be combined with to form anISD::FMAD.
N may be anISD::FADD,ISD::FSUB, or anISD::FMUL which will be distributed into an fadd/fsub.
Reimplemented inllvm::SITargetLowering.
Definition at line3288 of fileTargetLowering.h.
Referencesassert(),llvm::ISD::FADD,llvm::ISD::FMAD,llvm::ISD::FMUL,llvm::ISD::FSUB,isOperationLegal(), andN.
◆ isFMAFasterThanFMulAndFAdd()[1/3]
| inlinevirtual |
IR version.
Reimplemented inllvm::AArch64TargetLowering,llvm::SITargetLowering, andllvm::PPCTargetLowering.
Definition at line3258 of fileTargetLowering.h.
◆ isFMAFasterThanFMulAndFAdd()[2/3]
| inlinevirtual |
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
fmuladd intrinsics will be expanded to FMAs when this method returns true, otherwise fmuladd is expanded to fmul + fadd.
NOTE: This may be called before legalization on types for which FMAs are not legal, but should return true if those types will eventually legalize to types that support FMAs. After legalization, it will only be called on types that support FMAs (via Legal or Custom actions)
Targets that care about soft float support should return false when soft float code is being generated (i.e. use-soft-float).
Reimplemented inllvm::HexagonTargetLowering,llvm::AArch64TargetLowering,llvm::SITargetLowering,llvm::LoongArchTargetLowering,llvm::PPCTargetLowering,llvm::RISCVTargetLowering,llvm::SystemZTargetLowering,llvm::X86TargetLowering,llvm::NVPTXTargetLowering, andllvm::SPIRVTargetLowering.
Definition at line3239 of fileTargetLowering.h.
◆ isFMAFasterThanFMulAndFAdd()[3/3]
| inlinevirtual |
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
fmuladd intrinsics will be expanded to FMAs when this method returns true, otherwise fmuladd is expanded to fmul + fadd.
NOTE: This may be called before legalization on types for which FMAs are not legal, but should return true if those types will eventually legalize to types that support FMAs. After legalization, it will only be called on types that support FMAs (via Legal or Custom actions)
Reimplemented inllvm::SITargetLowering.
Definition at line3252 of fileTargetLowering.h.
◆ isFNegFree()
Return true if an fneg operation is free to the point where it is never worthwhile to replace it with a bitwise operation.
Reimplemented inllvm::AMDGPUTargetLowering, andllvm::ARMTargetLowering.
Definition at line3216 of fileTargetLowering.h.
Referencesassert(), andllvm::EVT::isFloatingPoint().
◆ isFPExtFoldable()[1/2]
| inlinevirtual |
Return true if an fpext operation input to anOpcode operation is free (for instance, because half-precision floating-point numbers are implicitly extended to float-precision) for an FMA instruction.
Reimplemented inllvm::SITargetLowering.
Definition at line3195 of fileTargetLowering.h.
◆ isFPExtFoldable()[2/2]
| inlinevirtual |
Return true if an fpext operation input to anOpcode operation is free (for instance, because half-precision floating-point numbers are implicitly extended to float-precision) for an FMA instruction.
Reimplemented inllvm::SITargetLowering.
Definition at line3203 of fileTargetLowering.h.
Referencesassert(),llvm::EVT::isFloatingPoint(), andisFPExtFree().
◆ isFPExtFree()
Return true if an fpext operation is free (for instance, because single-precision floating-point numbers are implicitly extended to double-precision).
Reimplemented inllvm::PPCTargetLowering.
Definition at line3186 of fileTargetLowering.h.
Referencesassert(), andllvm::EVT::isFloatingPoint().
Referenced byllvm::TargetLowering::getNegatedExpression(),isExtFree(), andisFPExtFoldable().
◆ isFPImmLegal()
| inlinevirtual |
Returns true if the target can instruction select the specified FP immediate natively.
If false, the legalizer will materialize the FP immediate as a load from a constant pool.
Reimplemented inllvm::AArch64TargetLowering,llvm::AMDGPUTargetLowering,llvm::HexagonTargetLowering,llvm::PPCTargetLowering,llvm::RISCVTargetLowering,llvm::SystemZTargetLowering,llvm::VETargetLowering,llvm::X86TargetLowering, andllvm::ARMTargetLowering.
Definition at line1235 of fileTargetLowering.h.
Referenced byllvm::TargetLowering::getNegatedExpression(), andllvm::TargetLowering::SimplifySetCC().
◆ isFreeAddrSpaceCast()
Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g.
we are happy to sink it into basic blocks. A cast may be free, but not necessarily a no-op. e.g. a free truncate from a 64-bit to 32-bit pointer.
Reimplemented inllvm::SITargetLowering.
Definition at line918 of fileTargetLoweringBase.cpp.
Referencesllvm::TargetMachine::isNoopAddrSpaceCast().
Referenced byllvm::BasicTTIImplBase< T >::getCastInstrCost(), andOptimizeNoopCopyExpression().
◆ isFsqrtCheap()
| inlinevirtual |
Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X).
Reimplemented inllvm::AMDGPUTargetLowering, andllvm::LoongArchTargetLowering.
Definition at line567 of fileTargetLowering.h.
◆ isIndexedLoadLegal()
Return true if the specified indexed load is legal on this target.
Definition at line1542 of fileTargetLowering.h.
ReferencesCustom,getIndexedLoadAction(),llvm::EVT::getSimpleVT(),llvm::EVT::isSimple(), andLegal.
Referenced bygetCombineLoadStoreParts(),llvm::BasicTTIImplBase< T >::isIndexedLoadLegal(), andllvm::AArch64TargetLowering::shouldFoldConstantShiftPairToMask().
◆ isIndexedMaskedLoadLegal()
Return true if the specified indexed load is legal on this target.
Definition at line1570 of fileTargetLowering.h.
ReferencesCustom,getIndexedMaskedLoadAction(),llvm::EVT::getSimpleVT(),llvm::EVT::isSimple(), andLegal.
Referenced bygetCombineLoadStoreParts().
◆ isIndexedMaskedStoreLegal()
Return true if the specified indexed load is legal on this target.
Definition at line1584 of fileTargetLowering.h.
ReferencesCustom,getIndexedMaskedStoreAction(),llvm::EVT::getSimpleVT(),llvm::EVT::isSimple(), andLegal.
Referenced bygetCombineLoadStoreParts().
◆ isIndexedStoreLegal()
Return true if the specified indexed load is legal on this target.
Definition at line1556 of fileTargetLowering.h.
ReferencesCustom,getIndexedStoreAction(),llvm::EVT::getSimpleVT(),llvm::EVT::isSimple(), andLegal.
Referenced bygetCombineLoadStoreParts(), andllvm::BasicTTIImplBase< T >::isIndexedStoreLegal().
◆ isIntDivCheap()
| inlinevirtual |
Return true if integer divide is usually cheaper than a sequence of several shifts, adds, and multiplies for this target.
The definition of "cheaper" may depend on whether we're optimizing for speed or for size.
Reimplemented inllvm::AArch64TargetLowering,llvm::RISCVTargetLowering,llvm::X86TargetLowering, andllvm::VETargetLowering.
Definition at line559 of fileTargetLowering.h.
Referenced byllvm::TargetLowering::BuildSDIVPow2(),llvm::TargetLowering::BuildSREMPow2(),llvm::BasicTTIImplBase< T >::preferToKeepConstantsAttached(), andllvm::TargetLowering::SimplifySetCC().
◆ isJumpExpensive()
| inline |
Return true if Flow Control is an expensive operation that should be avoided.
Definition at line617 of fileTargetLowering.h.
◆ isJumpTableRelative()
| virtual |
Reimplemented inllvm::MipsTargetLowering, andllvm::PPCTargetLowering.
Definition at line2017 of fileTargetLoweringBase.cpp.
ReferencesgetTargetMachine(), andllvm::TargetMachine::isPositionIndependent().
Referenced byllvm::VETargetLowering::getMinimumJumpTableEntries(), andllvm::PPCTargetLowering::isJumpTableRelative().
◆ isLegalAddImmediate()
| inlinevirtual |
Return true if the specified immediate is legal add immediate, that is the target has add instructions which can add a register with the immediate without having to materialize the immediate into a register.
Reimplemented inllvm::ARMTargetLowering,llvm::LoongArchTargetLowering,llvm::PPCTargetLowering,llvm::RISCVTargetLowering,llvm::SystemZTargetLowering,llvm::X86TargetLowering, andllvm::AArch64TargetLowering.
Definition at line2861 of fileTargetLowering.h.
Referenced byllvm::BasicTTIImplBase< T >::isLegalAddImmediate(), andperformAddCSelIntoCSinc().
◆ isLegalAddressingMode()
| virtual |
Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type.
isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type.
The type may be VoidTy, in which case only return true if the addressing mode is legal for a load/store of any legal type. TODO: Handle pre/postinc as well.
If the address space cannot be determined, it will be -1.
TODO: Remove default argument
Reimplemented inllvm::AArch64TargetLowering,llvm::SITargetLowering,llvm::ARCTargetLowering,llvm::ARMTargetLowering,llvm::AVRTargetLowering,llvm::HexagonTargetLowering,llvm::LoongArchTargetLowering,llvm::NVPTXTargetLowering,llvm::PPCTargetLowering,llvm::RISCVTargetLowering,llvm::SystemZTargetLowering,llvm::X86TargetLowering, andllvm::XCoreTargetLowering.
Definition at line1911 of fileTargetLoweringBase.cpp.
Referencesllvm::TargetLoweringBase::AddrMode::BaseGV,llvm::TargetLoweringBase::AddrMode::BaseOffs,llvm::TargetLoweringBase::AddrMode::HasBaseReg,llvm::TargetLoweringBase::AddrMode::ScalableOffset, andllvm::TargetLoweringBase::AddrMode::Scale.
Referenced bycanFoldInAddressingMode(), andllvm::BasicTTIImplBase< T >::isLegalAddressingMode().
◆ isLegalAddScalableImmediate()
| inlinevirtual |
Return true if adding the specified scalable immediate is legal, that is the target has add instructions which can add a register with the immediate (multiplied by vscale) without having to materialize the immediate into a register.
Reimplemented inllvm::AArch64TargetLowering.
Definition at line2869 of fileTargetLowering.h.
Referenced byllvm::BasicTTIImplBase< T >::isLegalAddScalableImmediate().
◆ isLegalICmpImmediate()
| inlinevirtual |
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register.
Reimplemented inllvm::ARMTargetLowering,llvm::HexagonTargetLowering,llvm::LoongArchTargetLowering,llvm::PPCTargetLowering,llvm::RISCVTargetLowering,llvm::SystemZTargetLowering,llvm::X86TargetLowering,llvm::AArch64TargetLowering, andllvm::MSP430TargetLowering.
Definition at line2854 of fileTargetLowering.h.
Referenced byllvm::BasicTTIImplBase< T >::isLegalICmpImmediate(),llvm::MSP430TargetLowering::isLegalICmpImmediate(), andllvm::TargetLowering::SimplifySetCC().
◆ isLegalRC()
| protected |
Return true if the value types that can be represented by the specified register class are all legal.
isLegalRC - Return true if the value types that can be represented by the specified register class are all legal.
Definition at line1144 of fileTargetLoweringBase.cpp.
ReferencesI,isTypeLegal(), andTRI.
Referenced byfindRepresentativeClass(), andllvm::TargetLowering::getRegForInlineAsmConstraint().
◆ isLegalScaleForGatherScatter()
| inlinevirtual |
Reimplemented inllvm::RISCVTargetLowering.
Definition at line1603 of fileTargetLowering.h.
Referenced bygetUniformBase().
◆ isLegalStoreImmediate()
| inlinevirtual |
Return true if the specified immediate is legal for the value input of a store instruction.
Reimplemented inllvm::X86TargetLowering.
Definition at line2873 of fileTargetLowering.h.
Referenced bygetMemsetValue().
◆ isLoadBitCastBeneficial()
| virtual |
Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On architectures that don't natively support some vector loads efficiently, casting the load to a smaller vector of larger types and loading is more efficient, however, this can be undone by optimizations in dag combiner.
Reimplemented inllvm::X86TargetLowering, andllvm::AMDGPUTargetLowering.
Definition at line2218 of fileTargetLoweringBase.cpp.
ReferencesallowsMemoryAccess(),llvm::CallingConv::Fast,llvm::SelectionDAG::getContext(),llvm::SelectionDAG::getDataLayout(),getOperationAction(),llvm::EVT::getSimpleVT(),getTypeToPromoteTo(),llvm::EVT::getVectorNumElements(),llvm::EVT::isFixedLengthVector(),llvm::EVT::isSimple(),llvm::ISD::LOAD, andPromote.
Referenced byllvm::X86TargetLowering::isLoadBitCastBeneficial(), andisStoreBitCastBeneficial().
◆ isLoadExtLegal()
Return true if the specified load with extension is legal on this target.
Definition at line1467 of fileTargetLowering.h.
ReferencesgetLoadExtAction(), andLegal.
Referenced bycombineEXTEND_VECTOR_INREG(),llvm::BasicTTIImplBase< T >::getCastInstrCost(),isExtLoad(),tryToFoldExtendSelectLoad(),tryToFoldExtOfExtload(), andtryToFoldExtOfLoad().
◆ isLoadExtLegalOrCustom()
| inline |
Return true if the specified load with extension is legal or custom on this target.
Definition at line1473 of fileTargetLowering.h.
ReferencesCustom,getLoadExtAction(), andLegal.
Referenced bytryToFoldExtOfMaskedLoad().
◆ isMaskAndCmp0FoldingBeneficial()
| inlinevirtual |
Return if the target supports combining a chain like:
into a single machine instruction of a form like:
Reimplemented inllvm::AArch64TargetLowering,llvm::ARMTargetLowering,llvm::RISCVTargetLowering,llvm::SystemZTargetLowering, andllvm::X86TargetLowering.
Definition at line756 of fileTargetLowering.h.
Referenced bysinkAndCmp0Expression().
◆ isMulAddWithConstProfitable()
| inlinevirtual |
Return true if it may be profitable to transform (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2).
This may not be true if c1 and c2 can be represented as immediates but c1*c2 cannot, for example. The target should check if c1, c2 and c1*c2 can be represented as immediates, or have to be materialized into registers. If it is not sure about some cases, a default true can be returned to let the DAGCombiner decide. AddNode is (add x, c1), and ConstNode is c2.
Reimplemented inllvm::AArch64TargetLowering,llvm::ARMTargetLowering, andllvm::RISCVTargetLowering.
Definition at line2445 of fileTargetLowering.h.
◆ isMultiStoresCheaperThanBitsMerge()
| inlinevirtual |
Return true if it is cheaper to split the store of a merged int val from a pair of smaller values into multiple stores.
Reimplemented inllvm::RISCVTargetLowering, andllvm::X86TargetLowering.
Definition at line742 of fileTargetLowering.h.
Referenced bysplitMergedValStore().
◆ isNarrowingProfitable()
| inlinevirtual |
Return true if it's profitable to narrow operations of type SrcVT to DestVT.
e.g. on x86, it's profitable to narrow from i32 to i8 but not from i32 to i16.
Reimplemented inllvm::AMDGPUTargetLowering, andllvm::X86TargetLowering.
Definition at line3305 of fileTargetLowering.h.
Referenced byllvm::TargetLowering::SimplifyDemandedBits().
◆ isOperationCustom()
Return true if the operation uses custom lowering, regardless of whether the type is legal or not.
Definition at line1380 of fileTargetLowering.h.
ReferencesCustom, andgetOperationAction().
Referenced byllvm::TargetLowering::BuildSDIV(),llvm::TargetLowering::BuildUDIV(),llvm::RISCVTTIImpl::getIntrinsicInstrCost(),llvm::RISCVTargetLowering::shouldScalarizeBinop(), andllvm::X86TargetLowering::X86TargetLowering().
◆ isOperationExpand()
Return true if the specified operation is illegal on this target or unlikely to be made legal with custom lowering.
This is used to help guide high-level lowering decisions.
Definition at line1442 of fileTargetLowering.h.
ReferencesExpand,getOperationAction(), andisTypeLegal().
Referenced byllvm::AArch64TargetLowering::AArch64TargetLowering(),llvm::ARMTargetLowering::ARMTargetLowering(),llvm::TargetLowering::BuildSDIV(),llvm::TargetLowering::BuildUDIV(),combineFMA(),llvm::TargetLowering::expandCTTZ(),llvm::BasicTTIImplBase< T >::getCastInstrCost(),llvm::BasicTTIImplBase< T >::getTypeBasedIntrinsicInstrCost(),performAddSubIntoVectorOp(),shouldFormOverflowOp(),llvm::X86TargetLowering::shouldFormOverflowOp(),llvm::PPCTTIImpl::vectorCostAdjustmentFactor(), andllvm::X86TargetLowering::X86TargetLowering().
◆ isOperationLegal()
Return true if the specified operation is legal on this target.
Definition at line1447 of fileTargetLowering.h.
ReferencesgetOperationAction(),isTypeLegal(), andLegal.
Referenced byllvm::TargetLowering::BuildSDIV(),llvm::TargetLowering::BuildUDIV(),combineLogicBlendIntoConditionalNegate(),combineSetCC(),combineShiftToAVG(),combineTruncatedArithmetic(),llvm::X86TargetLowering::decomposeMulByConstant(),EltsFromConsecutiveLoads(),llvm::TargetLowering::expandABD(),llvm::TargetLowering::expandABS(),llvm::TargetLowering::expandAddSubSat(),llvm::TargetLowering::expandCTTZ(),llvm::TargetLowering::expandFP_TO_INT_SAT(),llvm::TargetLowering::expandIntMINMAX(),llvm::TargetLowering::expandIS_FPCLASS(),llvm::TargetLowering::expandSADDSUBO(),foldAndOrOfSETCC(),foldExtendVectorInregToExtendOfSubvector(),foldFPToIntToFP(),llvm::SelectionDAG::getConstant(),llvm::X86TargetLowering::getNegatedExpression(),llvm::TargetLowering::getNegatedExpression(),llvm::PPCTargetLowering::getNegatedExpression(),llvm::X86TTIImpl::hasDivRemOp(),isCtpopFast(),llvm::X86TargetLowering::isDesirableToCombineLogicOpOfSETCC(),isFMADLegal(),llvm::EmptyMatchContext::isOperationLegal(),llvm::VPMatchContext::isOperationLegal(),isOperationLegalOrCustom(),isOperationLegalOrCustomOrPromote(),isOperationLegalOrPromote(),LowerADDSAT_SUBSAT(),LowerVSETCC(),llvm::SDPatternMatch::m_LegalOp(),llvm::AMDGPUTargetLowering::PerformDAGCombine(),llvm::R600TargetLowering::PerformDAGCombine(),llvm::RISCVTargetLowering::PerformDAGCombine(),llvm::AMDGPUTargetLowering::performShlCombine(),performXORCombine(),llvm::TargetLowering::SimplifyDemandedBits(),llvm::TargetLowering::SimplifySetCC(),stripModuloOnShift(), andtryFoldToZero().
◆ isOperationLegalOrCustom()
| inline |
Return true if the specified operation is legal on this target or can be made legal with custom lowering.
This is used to help guide high-level lowering decisions. LegalOnly is an optional convenience for code paths traversed pre and post legalisation.
Definition at line1339 of fileTargetLowering.h.
ReferencesCustom,getOperationAction(),isOperationLegal(),isTypeLegal(), andLegal.
Referenced byareJTsAllowed(),buildFromShuffleMostly(),llvm::TargetLowering::BuildSDIV(),llvm::TargetLowering::BuildUDIV(),canCombineShuffleToExtendVectorInreg(),canExpandVectorCTPOP(),combineCarryDiamond(),combineConcatVectorOfCasts(),combineConcatVectorOfShuffleAndItsOperands(),combineMinNumMaxNumImpl(),combineShiftToMULH(),combineShuffleOfBitcast(),combineVSelectToBLENDV(),llvm::TargetLowering::createSelectForFMINNUM_FMAXNUM(),llvm::TargetLowering::expandABD(),llvm::TargetLowering::expandABS(),llvm::TargetLowering::expandAddSubSat(),llvm::TargetLowering::expandCTLZ(),llvm::TargetLowering::expandCTTZ(),llvm::TargetLowering::expandDIVREMByConstant(),llvm::TargetLowering::expandFixedPointDiv(),llvm::TargetLowering::expandFixedPointMul(),llvm::TargetLowering::expandFMINIMUM_FMAXIMUM(),llvm::TargetLowering::expandFMINIMUMNUM_FMAXIMUMNUM(),llvm::TargetLowering::expandFMINNUM_FMAXNUM(),llvm::TargetLowering::expandFP_TO_UINT(),llvm::TargetLowering::expandFunnelShift(),llvm::TargetLowering::expandIntMINMAX(),llvm::TargetLowering::expandIS_FPCLASS(),llvm::TargetLowering::expandMUL_LOHI(),llvm::TargetLowering::expandMULO(),llvm::TargetLowering::expandREM(),llvm::TargetLowering::expandROT(),llvm::TargetLowering::expandRoundInexactToOdd(),llvm::TargetLowering::expandShlSat(),llvm::TargetLowering::expandUADDSUBO(),llvm::TargetLowering::expandUINT_TO_FP(),llvm::TargetLowering::expandUnalignedLoad(),llvm::TargetLowering::expandUnalignedStore(),llvm::TargetLowering::expandVecReduce(),llvm::TargetLowering::findOptimalMemOpLowering(),foldAndOrOfSETCC(),foldExtractSubvectorFromShuffleVector(),foldToSaturated(),llvm::AArch64TTIImpl::getArithmeticInstrCost(),getAsCarry(),llvm::TargetLowering::getNegatedExpression(),llvm::MipsTTIImpl::hasDivRemOp(),llvm::BasicTTIImplBase< T >::haveFastSqrt(),llvm::AArch64TargetLowering::isExtractSubvectorCheap(),llvm::SITargetLowering::isExtractSubvectorCheap(),llvm::ARMTargetLowering::isExtractSubvectorCheap(),llvm::RISCVTargetLowering::isExtractSubvectorCheap(),llvm::X86TargetLowering::isExtractSubvectorCheap(),llvm::HexagonTargetLowering::isFMAFasterThanFMulAndFAdd(),llvm::EmptyMatchContext::isOperationLegalOrCustom(),llvm::VPMatchContext::isOperationLegalOrCustom(),llvm::AArch64TargetLowering::isProfitableToHoist(),llvm::PPCTargetLowering::isProfitableToHoist(),isPromotedInstructionLegal(),lowerBitreverseShuffle(),matchBSwapHWordOrAndAnd(),narrowInsertExtractVectorBinOp(),performBUILD_VECTORCombine(),scalarizeBinOpOfSplats(),llvm::BasicTTIImplBase< T >::shouldBuildLookupTables(),shouldConvertFpToSat(),llvm::ARMTargetLowering::shouldConvertFpToSat(),llvm::RISCVTargetLowering::shouldConvertFpToSat(),llvm::X86TargetLowering::shouldConvertFpToSat(),shouldConvertSelectOfConstantsToMath(),llvm::TargetLowering::SimplifyDemandedBits(),llvm::TargetLowering::SimplifySetCC(),SinkShiftAndTruncate(), andwidenCtPop().
◆ isOperationLegalOrCustomOrPromote()
| inline |
Return true if the specified operation is legal on this target or can be made legal with custom lowering or using promotion.
This is used to help guide high-level lowering decisions. LegalOnly is an optional convenience for code paths traversed pre and post legalisation.
Definition at line1367 of fileTargetLowering.h.
ReferencesCustom,getOperationAction(),isOperationLegal(),isTypeLegal(),Legal, andPromote.
Referenced bycanExpandVectorCTPOP(),llvm::TargetLowering::expandABS(),llvm::TargetLowering::expandCTLZ(),llvm::TargetLowering::expandCTPOP(),llvm::TargetLowering::expandCTTZ(),llvm::TargetLowering::expandFP_TO_UINT(),llvm::TargetLowering::expandFunnelShift(),llvm::TargetLowering::expandROT(),llvm::TargetLowering::expandUINT_TO_FP(),llvm::TargetLowering::expandVectorNaryOpBySplitting(),llvm::TargetLowering::expandVPCTPOP(),llvm::ARMTTIImpl::getArithmeticInstrCost(),llvm::BasicTTIImplBase< T >::getFPOpCost(),narrowExtractedVectorBinOp(),llvm::RISCVTargetLowering::shouldScalarizeBinop(), andllvm::X86TargetLowering::shouldScalarizeBinop().
◆ isOperationLegalOrPromote()
| inline |
Return true if the specified operation is legal on this target or can be made legal using promotion.
This is used to help guide high-level lowering decisions. LegalOnly is an optional convenience for code paths traversed pre and post legalisation.
Definition at line1353 of fileTargetLowering.h.
ReferencesgetOperationAction(),isOperationLegal(),isTypeLegal(),Legal, andPromote.
Referenced byllvm::BasicTTIImplBase< T >::getCastInstrCost(),llvm::BasicTTIImplBase< T >::getTypeBasedIntrinsicInstrCost(),lowerBuildVectorToBitOp(), andPromoteMaskArithmetic().
◆ isPaddedAtMostSignificantBitsWhenStored()
Indicates if any padding is guaranteed to go at the most significant bits when storing the type to memory and the type size isn't equal to the store size.
Definition at line1832 of fileTargetLowering.h.
Referencesllvm::EVT::isByteSized(), andllvm::EVT::isScalarInteger().
Referenced byllvm::TargetLowering::SimplifySetCC().
◆ isPredictableSelectExpensive()
| inline |
Return true if selects are only cheaper than branches if the branch is unlikely to be predicted right.
Definition at line657 of fileTargetLowering.h.
ReferencesPredictableSelectIsExpensive.
Referenced byisFormingBranchFromSelectProfitable().
◆ isProfitableToCombineMinNumMaxNum()
Definition at line2417 of fileTargetLowering.h.
Referenced byisLegalToCombineMinNumMaxNum().
◆ isProfitableToHoist()
| inlinevirtual |
Reimplemented inllvm::AArch64TargetLowering,llvm::SITargetLowering, andllvm::PPCTargetLowering.
Definition at line2997 of fileTargetLowering.h.
Referenced byllvm::BasicTTIImplBase< T >::isProfitableToHoist().
◆ isSafeMemOpType()
Returns true if it's safe to use load / store of the specified type to expand memcpy / memset inline.
This is mostly true for all types except for some special cases. For example, onX86 targets without SSE2 f64 load / store are done with fldl / fstpl which also does type conversion. Note the specified type doesn't have to be legal as the hook is used before type legalization.
Reimplemented inllvm::X86TargetLowering.
Definition at line1999 of fileTargetLowering.h.
Referenced byllvm::TargetLowering::findOptimalMemOpLowering().
◆ isSelectSupported()
| inlinevirtual |
Reimplemented inllvm::ARMTargetLowering,llvm::PPCTargetLowering, andllvm::AMDGPUTargetLowering.
Definition at line454 of fileTargetLowering.h.
◆ isSExtCheaperThanZExt()
| inlinevirtual |
Return true if sign-extension from FromTy to ToTy is cheaper than zero-extension.
Reimplemented inllvm::LoongArchTargetLowering, andllvm::RISCVTargetLowering.
Definition at line3085 of fileTargetLowering.h.
Referenced byllvm::SelectionDAG::FoldConstantArithmetic(),llvm::SelectionDAG::getConstant(),llvm::TargetLowering::SimplifySetCC(), andllvm::LegalizerHelper::widenScalar().
◆ isShuffleMaskLegal()
Targets can use this to indicate that they only supportsome VECTOR_SHUFFLE operations, those with specific masks.
By default, if a target supports the VECTOR_SHUFFLE node, all mask values are assumed to be legal.
Reimplemented inllvm::AArch64TargetLowering,llvm::ARMTargetLowering,llvm::RISCVTargetLowering,llvm::HexagonTargetLowering,llvm::LoongArchTargetLowering,llvm::MipsSETargetLowering,llvm::X86TargetLowering, andllvm::SITargetLowering.
Definition at line1244 of fileTargetLowering.h.
Referenced byllvm::TargetLowering::buildLegalVectorShuffle(),combineConcatVectorOfShuffleAndItsOperands(),combineShuffleOfBitcast(),ExpandBVWithShuffles(),foldExtractSubvectorFromShuffleVector(),foldShuffleOfConcatUndefs(), andformSplatFromShuffles().
◆ isSlowDivBypassed()
| inline |
Returns true if target has indicated at least one type should be bypassed.
Definition at line604 of fileTargetLowering.h.
Referencesllvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::empty().
◆ isStoreBitCastBeneficial()
| inlinevirtual |
Return true if the following transform is beneficial: (store (y (conv x)), y*)) -> (store x, (x*))
Definition at line677 of fileTargetLowering.h.
ReferencesisLoadBitCastBeneficial().
◆ isStrictFPEnabled()
| inline |
Return true if the target support strict float operation.
Definition at line355 of fileTargetLowering.h.
ReferencesIsStrictFPEnabled.
◆ isSuitableForBitTests()
| inline |
Return true if lowering to a bit test is suitable for a set of case clusters which containsNumDests unique destinations,Low andHigh as its lowest and highest case values, and expectsNumCmps case value comparisons.
Check if the number of destinations, comparison metric, and range are all suitable.
Definition at line1417 of fileTargetLowering.h.
ReferencesDL,High,llvm::Low, andrangeFitsInWord().
Referenced byllvm::BasicTTIImplBase< T >::getEstimatedNumberOfCaseClusters().
◆ isSuitableForJumpTable()
| virtual |
Return true if lowering to a jump table is suitable for a set of case clusters which may containNumCases cases,Range range of values.
Definition at line1631 of fileTargetLoweringBase.cpp.
ReferencesgetMaximumJumpTableSize(),getMinimumJumpTableDensity(),Range, andllvm::shouldOptimizeForSize().
Referenced byllvm::SwitchCG::SwitchLowering::findJumpTables(), andllvm::BasicTTIImplBase< T >::getEstimatedNumberOfCaseClusters().
◆ isSupportedFixedPointOperation()
| inlinevirtual |
Custom method defined by each target to indicate if an operation which may require a scale is supported natively by the target.
If not, the operation is illegal.
Definition at line1283 of fileTargetLowering.h.
Referenced bygetFixedPointOperationAction().
◆ isTruncateFree()[1/4]
Reimplemented inllvm::AMDGPUTargetLowering,llvm::ARMTargetLowering,llvm::RISCVTargetLowering,llvm::AArch64TargetLowering,llvm::HexagonTargetLowering,llvm::MSP430TargetLowering,llvm::PPCTargetLowering,llvm::X86TargetLowering, andllvm::SystemZTargetLowering.
Definition at line2985 of fileTargetLowering.h.
◆ isTruncateFree()[2/4]
| inlinevirtual |
Definition at line2986 of fileTargetLowering.h.
Referencesllvm::getApproximateEVTForLLT(), andisTruncateFree().
◆ isTruncateFree()[3/4]
Return true if truncating the specific node Val to type VT2 is free.
Reimplemented inllvm::RISCVTargetLowering.
Definition at line2992 of fileTargetLowering.h.
Referencesllvm::SDValue::getValueType(), andisTruncateFree().
◆ isTruncateFree()[4/4]
Return true if it's free to truncate a value of type FromTy to type ToTy.
e.g. On x86 it's free to truncate a i32 value in register EAX to i16 by referencing its sub-register AX. Targets must return false when FromTy <= ToTy.
Reimplemented inllvm::SystemZTargetLowering,llvm::AMDGPUTargetLowering,llvm::ARMTargetLowering,llvm::NVPTXTargetLowering,llvm::RISCVTargetLowering,llvm::AArch64TargetLowering,llvm::HexagonTargetLowering,llvm::MSP430TargetLowering,llvm::PPCTargetLowering, andllvm::X86TargetLowering.
Definition at line2972 of fileTargetLowering.h.
Referenced byllvm::TargetLowering::expandAVG(),ExtendUsesToFormExtLoad(),llvm::BasicTTIImplBase< T >::getCastInstrCost(),getMemsetStores(),isExtLoad(),isTruncateFree(),llvm::RISCVTargetLowering::isTruncateFree(),llvm::BasicTTIImplBase< T >::isTruncateFree(),llvm::CombinerHelper::matchHoistLogicOpWithSameOpcodeHands(),llvm::TargetLowering::ShrinkDemandedOp(), andllvm::TargetLowering::SimplifyDemandedBits().
◆ isTruncStoreLegal()
Return true if the specified store with truncation is legal on this target.
Definition at line1514 of fileTargetLowering.h.
ReferencesgetTruncStoreAction(),isTypeLegal(), andLegal.
Referenced bycanCombineTruncStore(),llvm::R600TargetLowering::canCombineTruncStore(),combineMaskedStore(),combineStore(),llvm::BasicTTIImplBase< T >::getStoreMinimumVF(), andShrinkLoadReplaceStoreWithStore().
◆ isTruncStoreLegalOrCustom()
Return true if the specified store with truncation has solution on this target.
Definition at line1520 of fileTargetLowering.h.
ReferencesCustom,getTruncStoreAction(),isTypeLegal(), andLegal.
Referenced bycanCombineTruncStore().
◆ isTypeLegal()
Return true if the target has native support for the specified value type.
This means that it has a register that directly holds it without promotions or expansions.
Definition at line1093 of fileTargetLowering.h.
Referencesassert(),llvm::EVT::getSimpleVT(),llvm::EVT::isSimple(), andllvm::MVT::SimpleTy.
Referenced byllvm::ARMTargetLowering::allowTruncateForTailCall(),llvm::X86TargetLowering::allowTruncateForTailCall(),llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(),llvm::ARCTargetLowering::ARCTargetLowering(),llvm::TargetLowering::BuildSDIV(),llvm::TargetLowering::BuildUDIV(),canCombineShuffleToExtendVectorInreg(),canOpTrap(),CollectOpsToWiden(),combineAdd(),combineAddOrSubToADCOrSBB(),combineAnd(),combineAndnp(),combineAndShuffleNot(),combineBinOpOfZExt(),combineBitcast(),combineBitcastToBoolVector(),combineBITREVERSE(),combineCMP(),combineCONCAT_VECTORS(),combineConcatVectorOfCasts(),combineConcatVectorOfConcatVectors(),combineConcatVectorOfScalars(),combineConcatVectorOfShuffleAndItsOperands(),combineConcatVectorOps(),combineEXTEND_VECTOR_INREG(),combineEXTRACT_SUBVECTOR(),combineExtractVectorElt(),combineFMA(),combineFMinNumFMaxNum(),combineFneg(),combineKSHIFT(),combineLoad(),combineOr(),combinePredicateReduction(),combinePTESTCC(),combineScalarAndWithMaskSetcc(),combineSelect(),combineSelectOfTwoConstants(),combineSetCC(),combineShiftAnd1ToBitTest(),combineShuffle(),combineShuffleToFMAddSub(),combineShuffleToZeroExtendVectorInReg(),combineStore(),combineTargetShuffle(),combineTruncateWithSat(),combineTruncSelectToSMaxUSat(),combineVectorMulToSraBitcast(),combineVSelectWithAllOnesOrZeros(),combineX86ShuffleChain(),combineX86ShuffleChainWithExtract(),combineX86ShufflesConstants(),combineXor(),computeRegisterProperties(),EltsFromConsecutiveLoads(),llvm::TargetLowering::expandABD(),llvm::TargetLowering::expandAVG(),expandBitCastF128ToI128(),expandBitCastI128ToF128(),expandDivFix(),llvm::TargetLowering::expandFixedPointDiv(),llvm::TargetLowering::expandMULO(),llvm::TargetLowering::expandUnalignedLoad(),llvm::TargetLowering::expandUnalignedStore(),llvm::TargetLowering::expandVectorNaryOpBySplitting(),llvm::TargetLowering::findOptimalMemOpLowering(),getAVX512Node(),getAVX512TruncNode(),getBT(),llvm::AArch64TTIImpl::getCastInstrCost(),llvm::AArch64TTIImpl::getCmpSelInstrCost(),getConstVector(),getContainerForFixedLengthVector(),getCopyFromPartsVector(),getCopyToParts(),llvm::AArch64TTIImpl::getExtractWithExtendCost(),getMemsetStores(),llvm::X86TargetLowering::getNegatedExpression(),llvm::PPCTargetLowering::getNegatedExpression(),llvm::X86TargetLowering::getNumRegistersForCallingConv(),getPredicateForFixedLengthVector(),getPredicateForScalableVector(),getPromotedVectorElementType(),getPTest(),llvm::SelectionDAG::getReducedAlign(),llvm::SITargetLowering::getRegForInlineAsmConstraint(),llvm::FastISel::getRegForValue(),llvm::X86TargetLowering::getRegisterTypeForCallingConv(),llvm::SelectionDAG::getSplatValue(),getSVEPredicateBitCast(),getTypeToPromoteTo(),getVectorTypeBreakdown(),llvm::AArch64TargetLowering::getVectorTypeBreakdownForCallingConv(),llvm::X86TargetLowering::getVectorTypeBreakdownForCallingConv(),getVectorTypeBreakdownMVT(),getZeroVector(),llvm::SystemZTTIImpl::hasDivRemOp(),hasFastEqualityCompare(),llvm::X86TargetLowering::hasFastEqualityCompare(),llvm::BasicTTIImplBase< T >::haveFastSqrt(),llvm::GenericScheduler::initPolicy(),isAddSubOrSubAdd(),llvm::RISCVTargetLowering::isCtpopFast(),isExtLoad(),llvm::AArch64TTIImpl::isExtPartOfAvgExpr(),isLegalBitRotate(),llvm::RISCVTargetLowering::isLegalInterleavedAccessType(),isLegalRC(),llvm::X86TargetLowering::isLoadBitCastBeneficial(),isNoopBitcast(),IsNOT(),isOperationExpand(),isOperationLegal(),isOperationLegalOrCustom(),isOperationLegalOrCustomOrPromote(),isOperationLegalOrPromote(),isPackedVectorType(),llvm::RISCVTargetLowering::isShuffleMaskLegal(),llvm::X86TargetLowering::isShuffleMaskLegal(),isTruncStoreLegal(),isTruncStoreLegalOrCustom(),llvm::X86TargetLowering::isTypeDesirableForOp(),llvm::TargetLowering::isTypeDesirableForOp(),llvm::BasicTTIImplBase< T >::isTypeLegal(),llvm::ARMTargetLowering::isVectorLoadExtDesirable(),LowerABD(),LowerADDSUBO_CARRY(),LowerATOMIC_STORE(),lowerBitreverseShuffle(),LowerCTPOP(),LowerFABSorFNEG(),lowerFCMPIntrinsic(),LowerFCOPYSIGN(),LowerFMINIMUM_FMAXIMUM(),LowerFP_TO_SINT(),LowerFP_TO_UINT(),lowerGR128ToI128(),lowerI128ToGR128(),lowerICMPIntrinsic(),llvm::ARMTargetLowering::lowerInterleavedLoad(),llvm::ARMTargetLowering::lowerInterleavedStore(),llvm::RISCVTargetLowering::LowerOperation(),LowerRotate(),lowerShuffleAsElementInsertion(),lowerShuffleAsShift(),LowerSINT_TO_FP(),lowerStatepointMetaArgs(),llvm::AMDGPUTargetLowering::LowerUDIVREM64(),LowerUINT_TO_FP(),lowerVECTOR_SHUFFLE(),LowerVectorAllEqual(),LowerXALUO(),llvm::SDPatternMatch::m_LegalType(),narrowShuffle(),OptimizeExtractBits(),performANDCombine(),PerformANDCombine(),PerformARMBUILD_VECTORCombine(),performBUILD_VECTORCombine(),performBuildVectorCombine(),performCONCAT_VECTORSCombine(),llvm::RISCVTargetLowering::PerformDAGCombine(),performExtBinopLoadFold(),PerformExtendCombine(),PerformExtractEltToVMOVRRD(),performFP_TO_INT_SATCombine(),performFP_TO_INTCombine(),performFpToIntCombine(),PerformInsertSubvectorCombine(),performInsertSubvectorCombine(),llvm::AMDGPUTargetLowering::performLoadCombine(),PerformLOADCombine(),performORCombine(),PerformORCombine(),performSelectCombine(),PerformShiftCombine(),llvm::AMDGPUTargetLowering::performStoreCombine(),PerformSTORECombine(),PerformTruncatingStoreCombine(),PerformVDUPLANECombine(),PerformVECTOR_SHUFFLECombine(),performVECTOR_SHUFFLECombine(),PerformVSetCCToVCTPCombine(),PerformXORCombine(),llvm::ResourcePriorityQueue::rawRegPressureDelta(),llvm::SITargetLowering::ReplaceNodeResults(),llvm::RISCVTargetLowering::ReplaceNodeResults(),llvm::X86TargetLowering::ReplaceNodeResults(),llvm::RISCVTargetLowering::RISCVTargetLowering(),scalarizeBinOpOfSplats(),llvm::ResourcePriorityQueue::scheduledNode(),llvm::FastISel::selectBinaryOp(),llvm::FastISel::selectBitCast(),llvm::FastISel::selectCast(),llvm::FastISel::selectExtractValue(),llvm::FastISel::selectFNeg(),llvm::FastISel::selectFreeze(),llvm::AMDGPUTargetLowering::shouldCombineMemoryType(),llvm::RISCVTargetLowering::shouldExpandCttzElements(),llvm::AArch64TargetLowering::shouldFoldSelectWithIdentityConstant(),llvm::ARMTargetLowering::shouldFoldSelectWithIdentityConstant(),llvm::RISCVTargetLowering::shouldFoldSelectWithIdentityConstant(),llvm::RISCVTargetLowering::shouldRemoveExtendFromGSIndex(),llvm::X86TargetLowering::shouldSplatInsEltVarIndex(),ShrinkLoadReplaceStoreWithStore(),llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(),llvm::TargetLowering::SimplifySetCC(),llvm::SITargetLowering::SITargetLowering(),llvm::SystemZTargetLowering::SystemZTargetLowering(),llvm::X86TargetLowering::targetShrinkDemandedConstant(),tryToFoldExtendOfConstant(),tryWidenMaskForShuffle(),vectorToScalarBitmask(),llvm::SelectionDAGBuilder::visitBitTestHeader(),widenVectorToPartType(), andllvm::X86TargetLowering::X86TargetLowering().
◆ isVectorClearMaskLegal()
| inlinevirtual |
Similar to isShuffleMaskLegal.
Targets can use this to indicate if there is a suitable VECTOR_SHUFFLE that can be used to replace a VAND with a constant pool entry.
Reimplemented inllvm::AArch64TargetLowering, andllvm::X86TargetLowering.
Definition at line1257 of fileTargetLowering.h.
◆ isVectorLoadExtDesirable()
Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable.
Reimplemented inllvm::ARMTargetLowering, andllvm::X86TargetLowering.
Definition at line3212 of fileTargetLowering.h.
Referenced bytryToFoldExtOfLoad(), andtryToFoldExtOfMaskedLoad().
◆ isVScaleKnownToBeAPowerOfTwo()
| inlinevirtual |
Return true only if vscale must be a power of two.
Reimplemented inllvm::AArch64TargetLowering, andllvm::RISCVTargetLowering.
Definition at line613 of fileTargetLowering.h.
◆ isZExtFree()[1/4]
Reimplemented inllvm::AMDGPUTargetLowering,llvm::AArch64TargetLowering,llvm::MSP430TargetLowering, andllvm::X86TargetLowering.
Definition at line3070 of fileTargetLowering.h.
◆ isZExtFree()[2/4]
| inlinevirtual |
Definition at line3071 of fileTargetLowering.h.
Referencesllvm::getApproximateEVTForLLT(), andisZExtFree().
◆ isZExtFree()[3/4]
Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicitly zero-extended such asARM ldrb / ldrh or because it's folded such asX86 zero-extending loads).
Reimplemented inllvm::AArch64TargetLowering,llvm::ARMTargetLowering,llvm::LoongArchTargetLowering,llvm::PPCTargetLowering,llvm::RISCVTargetLowering,llvm::X86TargetLowering, andllvm::XCoreTargetLowering.
Definition at line3079 of fileTargetLowering.h.
Referencesllvm::SDValue::getValueType(), andisZExtFree().
◆ isZExtFree()[4/4]
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the value to ToTy in the result register.
The function should return true when it is likely that the truncate can be freely folded with an instruction defining a value of FromTy. If the defining instruction is unknown (because you're looking at a function argument, PHI, etc.) then the target may require an explicit truncate, which is not necessarily free, but this function does not deal with those cases. Targets must return false when FromTy >= ToTy.
Reimplemented inllvm::AMDGPUTargetLowering,llvm::AArch64TargetLowering,llvm::MSP430TargetLowering, andllvm::X86TargetLowering.
Definition at line3066 of fileTargetLowering.h.
Referenced bycombineShuffleOfScalars(),foldCONCAT_VECTORS(),llvm::BasicTTIImplBase< T >::getCastInstrCost(),llvm::RegsForValue::getCopyToRegs(),hasSameExtUse(),isExtFree(),isZExtFree(),llvm::LoongArchTargetLowering::isZExtFree(),llvm::PPCTargetLowering::isZExtFree(),llvm::RISCVTargetLowering::isZExtFree(),llvm::CombinerHelper::matchHoistLogicOpWithSameOpcodeHands(),llvm::TargetLowering::ShrinkDemandedOp(),llvm::TargetLowering::SimplifyDemandedBits(), andtryToFoldExtendOfConstant().
◆ lowerDeinterleaveIntrinsicToLoad()
| inlinevirtual |
Lower a deinterleave intrinsic to a target specific load intrinsic.
Return true on success. Currently only supports llvm.vector.deinterleave2
LI is the accompanying load instruction.DeinterleaveValues contains the deinterleaved values.
Reimplemented inllvm::AArch64TargetLowering, andllvm::RISCVTargetLowering.
Definition at line3166 of fileTargetLowering.h.
◆ lowerIdempotentRMWIntoFencedLoad()
| inlinevirtual |
On some platforms, an AtomicRMW that never actually modifies the value (such as fetch_add of 0) can be turned into a fence followed by an atomic load.
This may sound useless, but it makes it possible for the processor to keep the cacheline shared, dramatically improving performance. And such idempotent RMWs are useful for implementing some kinds of locks, see for example (justification + benchmarks):http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf This method tries doing that transformation, returning the atomic load if it succeeds, and nullptr otherwise. If shouldExpandAtomicLoadInIR returns true on that load, it will undergo another round of expansion.
Reimplemented inllvm::SITargetLowering.
Definition at line2375 of fileTargetLowering.h.
◆ lowerInterleavedLoad()
| inlinevirtual |
Lower an interleaved load to target specific intrinsics.
Return true on success.
LI is the vector load instruction.Shuffles is the shufflevector list to DE-interleave the loaded vector.Indices is the corresponding indices for each shufflevector.Factor is the interleave factor.
Reimplemented inllvm::AArch64TargetLowering,llvm::ARMTargetLowering,llvm::RISCVTargetLowering, andllvm::X86TargetLowering.
Definition at line3141 of fileTargetLowering.h.
◆ lowerInterleavedStore()
| inlinevirtual |
Lower an interleaved store to target specific intrinsics.
Return true on success.
SI is the vector store instruction.SVI is the shufflevector to RE-interleave the stored vector.Factor is the interleave factor.
Reimplemented inllvm::AArch64TargetLowering,llvm::ARMTargetLowering,llvm::RISCVTargetLowering, andllvm::X86TargetLowering.
Definition at line3154 of fileTargetLowering.h.
◆ lowerInterleaveIntrinsicToStore()
| inlinevirtual |
Lower an interleave intrinsic to a target specific store intrinsic.
Return true on success. Currently only supports llvm.vector.interleave2
SI is the accompanying store instructionInterleaveValues contains the interleaved values.
Reimplemented inllvm::AArch64TargetLowering, andllvm::RISCVTargetLowering.
Definition at line3178 of fileTargetLowering.h.
◆ markLibCallAttributes()
| inlinevirtual |
Reimplemented inllvm::X86TargetLowering.
Definition at line331 of fileTargetLowering.h.
Referenced byllvm::FastISel::lowerCallTo(), andllvm::TargetLowering::CallLoweringInfo::setLibCallee().
◆ mergeStoresAfterLegalization()
Allow store merging for the specified type after legalization in addition to before legalization.
This may transform stores that do not exist earlier (for example, stores created from intrinsics).
Reimplemented inllvm::X86TargetLowering,llvm::AArch64TargetLowering, andllvm::AMDGPUTargetLowering.
Definition at line696 of fileTargetLowering.h.
◆ needsFixedCatchObjects()
| inlinevirtual |
Reimplemented inllvm::AArch64TargetLowering, andllvm::X86TargetLowering.
Definition at line2033 of fileTargetLowering.h.
Referencesllvm::report_fatal_error().
Referenced byllvm::FunctionLoweringInfo::set().
◆ operator=()
| delete |
◆ optimizeExtendOrTruncateConversion()
| inlinevirtual |
Try to optimize extending or truncating conversion instructions (like zext, trunc, fptoui, uitofp) for the target.
Reimplemented inllvm::AArch64TargetLowering.
Definition at line3096 of fileTargetLowering.h.
◆ optimizeFMulOrFDivAsShiftAddBitcast()
| inlinevirtual |
Definition at line892 of fileTargetLowering.h.
Referencesllvm::ISD::FDIV, andN.
◆ preferABDSToABSWithNSW()
Reimplemented inllvm::X86TargetLowering.
Definition at line928 of fileTargetLowering.h.
◆ preferedOpcodeForCmpEqPiecesOfOperand()
| inlinevirtual |
Reimplemented inllvm::X86TargetLowering.
Definition at line909 of fileTargetLowering.h.
◆ preferIncOfAddToSubOfNot()
These two forms are equivalent: sub y, (xor x, -1) add (add x, 1), y The variant with two add's is IR-canonical.
Some targets may prefer one to the other.
Reimplemented inllvm::AArch64TargetLowering,llvm::ARMTargetLowering, andllvm::PPCTargetLowering.
Definition at line921 of fileTargetLowering.h.
◆ preferredShiftLegalizationStrategy()
| inlinevirtual |
Reimplemented inllvm::AArch64TargetLowering,llvm::ARMTargetLowering,llvm::AVRTargetLowering,llvm::RISCVTargetLowering, andllvm::X86TargetLowering.
Definition at line1083 of fileTargetLowering.h.
ReferencesExpandThroughStack, andExpandToParts.
Referenced byllvm::AArch64TargetLowering::preferredShiftLegalizationStrategy(),llvm::ARMTargetLowering::preferredShiftLegalizationStrategy(),llvm::RISCVTargetLowering::preferredShiftLegalizationStrategy(), andllvm::X86TargetLowering::preferredShiftLegalizationStrategy().
◆ preferScalarizeSplat()
Reimplemented inllvm::RISCVTargetLowering, andllvm::X86TargetLowering.
Definition at line933 of fileTargetLowering.h.
◆ preferSextInRegOfTruncate()
| inlinevirtual |
Reimplemented inllvm::X86TargetLowering.
Definition at line939 of fileTargetLowering.h.
◆ preferZeroCompareBranch()
| inlinevirtual |
Return true if the heuristic to prefer icmp eq zero should be used in code gen prepare.
Reimplemented inllvm::ARMTargetLowering,llvm::RISCVTargetLowering, andllvm::SystemZTargetLowering.
Definition at line738 of fileTargetLowering.h.
Referenced byoptimizeBranch().
◆ promoteTargetBoolean()
| inline |
Promote the given target boolean to a target boolean of the given type.
A target boolean is an integer value, not necessarily of type i1, the bits of which conform to getBooleanContents.
ValVT is the type of values that produced the boolean.
Definition at line1019 of fileTargetLowering.h.
ReferencesBool,getBooleanContents(),llvm::SelectionDAG::getContext(),llvm::SelectionDAG::getDataLayout(),getExtendForContent(),llvm::SelectionDAG::getNode(), andgetSetCCResultType().
◆ rangeFitsInWord()
| inline |
Check whether the range [Low,High] fits in a machine word.
Definition at line1394 of fileTargetLowering.h.
ReferencesDL,High,llvm::Low,Range, andUINT64_MAX.
Referenced byisSuitableForBitTests().
◆ reduceSelectOfFPConstantLoads()
Return true if it is profitable to convert a select of FP constants into a constant pool load whose address depends on the select condition.
The parameter may be used to differentiate a select with FP compare from integer compare.
Reimplemented inllvm::X86TargetLowering.
Definition at line503 of fileTargetLowering.h.
◆ requiresUniformRegister()
| inlinevirtual |
Allows target to decide about the register class of the specific value that is live outside the defining block.
Returns true if the value needs uniform register class.
Reimplemented inllvm::SITargetLowering.
Definition at line1052 of fileTargetLowering.h.
Referenced byllvm::FunctionLoweringInfo::CreateRegs().
◆ setAtomicLoadExtAction()[1/3]
| inlineprotected |
Definition at line2617 of fileTargetLowering.h.
ReferencessetAtomicLoadExtAction().
◆ setAtomicLoadExtAction()[2/3]
| inlineprotected |
Definition at line2612 of fileTargetLowering.h.
ReferencessetAtomicLoadExtAction().
◆ setAtomicLoadExtAction()[3/3]
| inlineprotected |
Let target indicate that an extending atomic load of the specified type is legal.
Definition at line2601 of fileTargetLowering.h.
Referencesassert(),llvm::MVT::isValid(),llvm::ISD::LAST_LOADEXT_TYPE, andllvm::MVT::SimpleTy.
Referenced byinitActions(),setAtomicLoadExtAction(), andllvm::SystemZTargetLowering::SystemZTargetLowering().
◆ setBooleanContents()[1/2]
| inlineprotected |
Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type.
See getBooleanContents.
Definition at line2486 of fileTargetLowering.h.
◆ setBooleanContents()[2/2]
| inlineprotected |
Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type.
See getBooleanContents.
Definition at line2479 of fileTargetLowering.h.
Referenced byllvm::AArch64TargetLowering::AArch64TargetLowering(),llvm::ARCTargetLowering::ARCTargetLowering(),llvm::ARMTargetLowering::ARMTargetLowering(),llvm::AVRTargetLowering::AVRTargetLowering(),llvm::BPFTargetLowering::BPFTargetLowering(),llvm::CSKYTargetLowering::CSKYTargetLowering(),llvm::HexagonTargetLowering::HexagonTargetLowering(),llvm::LanaiTargetLowering::LanaiTargetLowering(),llvm::LoongArchTargetLowering::LoongArchTargetLowering(),llvm::M68kTargetLowering::M68kTargetLowering(),llvm::MipsTargetLowering::MipsTargetLowering(),llvm::MSP430TargetLowering::MSP430TargetLowering(),llvm::NVPTXTargetLowering::NVPTXTargetLowering(),llvm::PPCTargetLowering::PPCTargetLowering(),llvm::R600TargetLowering::R600TargetLowering(),llvm::RISCVTargetLowering::RISCVTargetLowering(),llvm::SITargetLowering::SITargetLowering(),llvm::SparcTargetLowering::SparcTargetLowering(),llvm::SystemZTargetLowering::SystemZTargetLowering(),llvm::VETargetLowering::VETargetLowering(),llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering(),llvm::X86TargetLowering::X86TargetLowering(),llvm::XCoreTargetLowering::XCoreTargetLowering(), andllvm::XtensaTargetLowering::XtensaTargetLowering().
◆ setBooleanVectorContents()
| inlineprotected |
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider type.
See getBooleanContents.
Definition at line2493 of fileTargetLowering.h.
Referenced byllvm::AArch64TargetLowering::AArch64TargetLowering(),llvm::ARCTargetLowering::ARCTargetLowering(),llvm::ARMTargetLowering::ARMTargetLowering(),llvm::AVRTargetLowering::AVRTargetLowering(),llvm::CSKYTargetLowering::CSKYTargetLowering(),llvm::HexagonTargetLowering::HexagonTargetLowering(),llvm::LoongArchTargetLowering::LoongArchTargetLowering(),llvm::MipsTargetLowering::MipsTargetLowering(),llvm::MSP430TargetLowering::MSP430TargetLowering(),llvm::NVPTXTargetLowering::NVPTXTargetLowering(),llvm::PPCTargetLowering::PPCTargetLowering(),llvm::R600TargetLowering::R600TargetLowering(),llvm::RISCVTargetLowering::RISCVTargetLowering(),llvm::SITargetLowering::SITargetLowering(),llvm::SparcTargetLowering::SparcTargetLowering(),llvm::SystemZTargetLowering::SystemZTargetLowering(),llvm::VETargetLowering::VETargetLowering(),llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering(),llvm::X86TargetLowering::X86TargetLowering(), andllvm::XCoreTargetLowering::XCoreTargetLowering().
◆ setCmpLibcallCC()
| inline |
Override the default CondCode to be used to test the result of the comparison libcall against zero.
FIXME: This can't be merged with 'RuntimeLibcallsInfo' because of theISD.
Definition at line3447 of fileTargetLowering.h.
ReferencesCC.
Referenced byllvm::ARMTargetLowering::ARMTargetLowering(), andllvm::MSP430TargetLowering::MSP430TargetLowering().
◆ setCondCodeAction()[1/2]
| inlineprotected |
Definition at line2700 of fileTargetLowering.h.
ReferencessetCondCodeAction().
◆ setCondCodeAction()[2/2]
| inlineprotected |
Indicate that the specified condition code is or isn't supported on the target and indicate what to do about it.
The lower 3 bits of the SimpleTy index into Nth 4bit set from the 32-bit value and the upper 29 bits index into the second dimension of the array to select what 32-bit value to use.
Definition at line2686 of fileTargetLowering.h.
Referencesassert(),CC,llvm::MVT::isValid(), andllvm::MVT::SimpleTy.
Referenced byllvm::AArch64TargetLowering::AArch64TargetLowering(),llvm::MipsSETargetLowering::addMSAFloatType(),llvm::MipsSETargetLowering::addMSAIntType(),llvm::CSKYTargetLowering::CSKYTargetLowering(),llvm::HexagonTargetLowering::HexagonTargetLowering(),llvm::LoongArchTargetLowering::LoongArchTargetLowering(),llvm::MipsSETargetLowering::MipsSETargetLowering(),llvm::NVPTXTargetLowering::NVPTXTargetLowering(),llvm::PPCTargetLowering::PPCTargetLowering(),llvm::R600TargetLowering::R600TargetLowering(),llvm::RISCVTargetLowering::RISCVTargetLowering(),setCondCodeAction(),llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering(),llvm::X86TargetLowering::X86TargetLowering(), andllvm::XtensaTargetLowering::XtensaTargetLowering().
◆ setHasExtractBitsInsn()
Tells the code generator that the target has BitExtract instructions.
The code generator will aggressively sink "shift"s into the blocks of their users if the users will generate "and" instructions which can be combined with "shift" to BitExtract instructions.
Definition at line2528 of fileTargetLowering.h.
Referenced byllvm::AArch64TargetLowering::AArch64TargetLowering(),llvm::R600TargetLowering::R600TargetLowering(), andllvm::SITargetLowering::SITargetLowering().
◆ setHasMultipleConditionRegisters()
| inlineprotected |
Tells the code generator that the target has multiple (allocatable) condition registers that can be used to store the results of comparisons for use by selects and conditional branches.
With multiple condition registers, the code generator will not aggressively sink comparisons into the blocks of their users.
Definition at line2520 of fileTargetLowering.h.
Referenced byllvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), andllvm::PPCTargetLowering::PPCTargetLowering().
◆ setIndexedLoadAction()[1/2]
| inlineprotected |
Definition at line2641 of fileTargetLowering.h.
ReferencessetIndexedLoadAction().
◆ setIndexedLoadAction()[2/2]
| inlineprotected |
Indicate that the specified indexed load does or does not work with the specified type and indicate what to do abort it.
NOTE: All indexed mode loads are initialized to Expand inTargetLowering.cpp
Definition at line2635 of fileTargetLowering.h.
Referenced byllvm::AArch64TargetLowering::AArch64TargetLowering(),llvm::ARMTargetLowering::ARMTargetLowering(),llvm::AVRTargetLowering::AVRTargetLowering(),llvm::HexagonTargetLowering::HexagonTargetLowering(),initActions(),llvm::MSP430TargetLowering::MSP430TargetLowering(),llvm::PPCTargetLowering::PPCTargetLowering(),llvm::RISCVTargetLowering::RISCVTargetLowering(), andsetIndexedLoadAction().
◆ setIndexedMaskedLoadAction()
| inlineprotected |
Indicate that the specified indexed masked load does or does not work with the specified type and indicate what to do about it.
NOTE: All indexed mode masked loads are initialized to Expand inTargetLowering.cpp
Definition at line2669 of fileTargetLowering.h.
Referenced byinitActions().
◆ setIndexedMaskedStoreAction()
| inlineprotected |
Indicate that the specified indexed masked store does or does not work with the specified type and indicate what to do about it.
NOTE: All indexed mode masked stores are initialized to Expand inTargetLowering.cpp
Definition at line2679 of fileTargetLowering.h.
Referenced byinitActions().
◆ setIndexedStoreAction()[1/2]
| inlineprotected |
Definition at line2658 of fileTargetLowering.h.
ReferencessetIndexedStoreAction().
◆ setIndexedStoreAction()[2/2]
| inlineprotected |
Indicate that the specified indexed store does or does not work with the specified type and indicate what to do about it.
NOTE: All indexed mode stores are initialized to Expand inTargetLowering.cpp
Definition at line2652 of fileTargetLowering.h.
Referenced byllvm::AArch64TargetLowering::AArch64TargetLowering(),llvm::ARMTargetLowering::ARMTargetLowering(),llvm::AVRTargetLowering::AVRTargetLowering(),llvm::HexagonTargetLowering::HexagonTargetLowering(),initActions(),llvm::PPCTargetLowering::PPCTargetLowering(),llvm::RISCVTargetLowering::RISCVTargetLowering(), andsetIndexedStoreAction().
◆ setJumpIsExpensive()
Tells the code generator not to expand logic operations on comparison predicates into separate sequences that increase the amount of flow control.
Definition at line941 of fileTargetLoweringBase.cpp.
Referencesllvm::cl::Option::getNumOccurrences(), andJumpIsExpensiveOverride.
Referenced byllvm::AMDGPUTargetLowering::AMDGPUTargetLowering(),llvm::LanaiTargetLowering::LanaiTargetLowering(),llvm::NVPTXTargetLowering::NVPTXTargetLowering(), andllvm::PPCTargetLowering::PPCTargetLowering().
◆ setLibcallCallingConv()
| inline |
Set theCallingConv that should be used for the specified libcall.
Definition at line3461 of fileTargetLowering.h.
ReferencesCC, andllvm::RTLIB::RuntimeLibcallsInfo::setLibcallCallingConv().
Referenced byllvm::ARMTargetLowering::ARMTargetLowering(),llvm::AVRTargetLowering::AVRTargetLowering(),llvm::LanaiTargetLowering::LanaiTargetLowering(),llvm::MSP430TargetLowering::MSP430TargetLowering(), andllvm::X86TargetLowering::X86TargetLowering().
◆ setLibcallName()[1/2]
| inline |
Definition at line3435 of fileTargetLowering.h.
ReferencesName, andllvm::RTLIB::RuntimeLibcallsInfo::setLibcallName().
◆ setLibcallName()[2/2]
| inline |
Rename the default libcall routine name for the specified libcall.
Definition at line3431 of fileTargetLowering.h.
ReferencesName, andllvm::RTLIB::RuntimeLibcallsInfo::setLibcallName().
Referenced byllvm::AArch64TargetLowering::AArch64TargetLowering(),llvm::ARMTargetLowering::ARMTargetLowering(),llvm::AVRTargetLowering::AVRTargetLowering(),llvm::HexagonTargetLowering::HexagonTargetLowering(),llvm::MSP430TargetLowering::MSP430TargetLowering(),llvm::PPCTargetLowering::PPCTargetLowering(),llvm::RISCVTargetLowering::RISCVTargetLowering(),llvm::SparcTargetLowering::SparcTargetLowering(),llvm::SystemZTargetLowering::SystemZTargetLowering(),llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering(), andllvm::X86TargetLowering::X86TargetLowering().
◆ setLoadExtAction()[1/3]
| inlineprotected |
Definition at line2593 of fileTargetLowering.h.
ReferencessetLoadExtAction().
◆ setLoadExtAction()[2/3]
| inlineprotected |
Definition at line2588 of fileTargetLowering.h.
ReferencessetLoadExtAction().
◆ setLoadExtAction()[3/3]
| inlineprotected |
Indicate that the specified load with extension does not work with the specified type and indicate what to do about it.
Definition at line2579 of fileTargetLowering.h.
Referencesassert(),llvm::MVT::isValid(),llvm::ISD::LAST_LOADEXT_TYPE, andllvm::MVT::SimpleTy.
Referenced byllvm::AArch64TargetLowering::AArch64TargetLowering(),llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(),llvm::ARMTargetLowering::ARMTargetLowering(),llvm::AVRTargetLowering::AVRTargetLowering(),llvm::BPFTargetLowering::BPFTargetLowering(),llvm::CSKYTargetLowering::CSKYTargetLowering(),llvm::HexagonTargetLowering::HexagonTargetLowering(),initActions(),llvm::LanaiTargetLowering::LanaiTargetLowering(),llvm::LoongArchTargetLowering::LoongArchTargetLowering(),llvm::M68kTargetLowering::M68kTargetLowering(),llvm::MipsSETargetLowering::MipsSETargetLowering(),llvm::MipsTargetLowering::MipsTargetLowering(),llvm::MSP430TargetLowering::MSP430TargetLowering(),llvm::NVPTXTargetLowering::NVPTXTargetLowering(),llvm::PPCTargetLowering::PPCTargetLowering(),llvm::R600TargetLowering::R600TargetLowering(),llvm::RISCVTargetLowering::RISCVTargetLowering(),setLoadExtAction(),llvm::SparcTargetLowering::SparcTargetLowering(),llvm::SystemZTargetLowering::SystemZTargetLowering(),llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering(),llvm::X86TargetLowering::X86TargetLowering(),llvm::XCoreTargetLowering::XCoreTargetLowering(), andllvm::XtensaTargetLowering::XtensaTargetLowering().
◆ setMaxAtomicSizeInBitsSupported()
| inlineprotected |
Set the maximum atomic operation size supported by the backend.
Atomic operations greater than this size (as well as ones that are not naturally aligned), will be expanded byAtomicExpandPass into an __atomic_* library call.
Definition at line2766 of fileTargetLowering.h.
Referenced byllvm::AArch64TargetLowering::AArch64TargetLowering(),llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(),llvm::ARCTargetLowering::ARCTargetLowering(),llvm::ARMTargetLowering::ARMTargetLowering(),llvm::BPFTargetLowering::BPFTargetLowering(),llvm::CSKYTargetLowering::CSKYTargetLowering(),llvm::HexagonTargetLowering::HexagonTargetLowering(),llvm::LanaiTargetLowering::LanaiTargetLowering(),llvm::LoongArchTargetLowering::LoongArchTargetLowering(),llvm::M68kTargetLowering::M68kTargetLowering(),llvm::MipsTargetLowering::MipsTargetLowering(),llvm::MSP430TargetLowering::MSP430TargetLowering(),llvm::NVPTXTargetLowering::NVPTXTargetLowering(),llvm::PPCTargetLowering::PPCTargetLowering(),llvm::RISCVTargetLowering::RISCVTargetLowering(),llvm::SparcTargetLowering::SparcTargetLowering(),llvm::SystemZTargetLowering::SystemZTargetLowering(),llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering(),llvm::X86TargetLowering::X86TargetLowering(), andllvm::XCoreTargetLowering::XCoreTargetLowering().
◆ setMaxBytesForAlignment()
| inlineprotected |
Definition at line2753 of fileTargetLowering.h.
Referenced byllvm::AArch64TargetLowering::AArch64TargetLowering(), andllvm::LoongArchTargetLowering::LoongArchTargetLowering().
◆ setMaxDivRemBitWidthSupported()
| inlineprotected |
Set the size in bits of the maximum div/rem the backend supports.
Larger operations will be expanded by ExpandLargeDivRem.
Definition at line2772 of fileTargetLowering.h.
Referenced byllvm::AArch64TargetLowering::AArch64TargetLowering(),llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(),llvm::ARMTargetLowering::ARMTargetLowering(),llvm::NVPTXTargetLowering::NVPTXTargetLowering(), andllvm::X86TargetLowering::X86TargetLowering().
◆ setMaximumJumpTableSize()
| protected |
Indicate the maximum number of entries in jump tables.
Set to zero to generate unlimited jump tables.
Definition at line2013 of fileTargetLoweringBase.cpp.
ReferencesMaximumJumpTableSize.
Referenced byllvm::AArch64TargetLowering::AArch64TargetLowering().
◆ setMaxLargeFPConvertBitWidthSupported()
| inlineprotected |
Set the size in bits of the maximum fp convert the backend supports.
Larger operations will be expanded by ExpandLargeFPConvert.
Definition at line2778 of fileTargetLowering.h.
Referenced byllvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), andllvm::X86TargetLowering::X86TargetLowering().
◆ setMinCmpXchgSizeInBits()
| inlineprotected |
Sets the minimum cmpxchg or ll/sc size supported by the backend.
Definition at line2783 of fileTargetLowering.h.
Referenced byllvm::AMDGPUTargetLowering::AMDGPUTargetLowering(),llvm::HexagonTargetLowering::HexagonTargetLowering(),llvm::LoongArchTargetLowering::LoongArchTargetLowering(),llvm::NVPTXTargetLowering::NVPTXTargetLowering(),llvm::RISCVTargetLowering::RISCVTargetLowering(), andllvm::SparcTargetLowering::SparcTargetLowering().
◆ setMinFunctionAlignment()
| inlineprotected |
Set the target's minimum function alignment.
Definition at line2739 of fileTargetLowering.h.
Referenced byllvm::AArch64TargetLowering::AArch64TargetLowering(),llvm::ARMTargetLowering::ARMTargetLowering(),llvm::AVRTargetLowering::AVRTargetLowering(),llvm::BPFTargetLowering::BPFTargetLowering(),llvm::CSKYTargetLowering::CSKYTargetLowering(),llvm::HexagonTargetLowering::HexagonTargetLowering(),llvm::LanaiTargetLowering::LanaiTargetLowering(),llvm::LoongArchTargetLowering::LoongArchTargetLowering(),llvm::M68kTargetLowering::M68kTargetLowering(),llvm::MipsTargetLowering::MipsTargetLowering(),llvm::MSP430TargetLowering::MSP430TargetLowering(),llvm::PPCTargetLowering::PPCTargetLowering(),llvm::RISCVTargetLowering::RISCVTargetLowering(),llvm::SparcTargetLowering::SparcTargetLowering(),llvm::SystemZTargetLowering::SystemZTargetLowering(),llvm::VETargetLowering::VETargetLowering(),llvm::XCoreTargetLowering::XCoreTargetLowering(), andllvm::XtensaTargetLowering::XtensaTargetLowering().
◆ setMinimumJumpTableEntries()
| protected |
Indicate the minimum number of blocks to generate jump tables.
Definition at line2001 of fileTargetLoweringBase.cpp.
ReferencesMinimumJumpTableEntries.
Referenced byllvm::AVRTargetLowering::AVRTargetLowering(),llvm::HexagonTargetLowering::HexagonTargetLowering(),llvm::LanaiTargetLowering::LanaiTargetLowering(),llvm::PPCTargetLowering::PPCTargetLowering(), andllvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering().
◆ setMinStackArgumentAlignment()
| inlineprotected |
Set the minimum stack alignment of an argument.
Definition at line2758 of fileTargetLowering.h.
Referenced byllvm::ARMTargetLowering::ARMTargetLowering(),llvm::MipsTargetLowering::MipsTargetLowering(),llvm::PPCTargetLowering::PPCTargetLowering(), andllvm::VETargetLowering::VETargetLowering().
◆ setOperationAction()[1/3]
| inlineprotected |
Definition at line2571 of fileTargetLowering.h.
ReferencessetOperationAction().
◆ setOperationAction()[2/3]
| inlineprotected |
Definition at line2566 of fileTargetLowering.h.
ReferencessetOperationAction().
◆ setOperationAction()[3/3]
| inlineprotected |
Indicate that the specified operation does not work with the specified type and indicate what to do about it.
Note that VT may refer to either the type of a result or that of an operand of Op.
Definition at line2562 of fileTargetLowering.h.
Referencesassert(), andllvm::MVT::SimpleTy.
Referenced byllvm::AArch64TargetLowering::AArch64TargetLowering(),llvm::MipsSETargetLowering::addMSAFloatType(),llvm::MipsSETargetLowering::addMSAIntType(),llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(),llvm::ARCTargetLowering::ARCTargetLowering(),llvm::ARMTargetLowering::ARMTargetLowering(),llvm::AVRTargetLowering::AVRTargetLowering(),llvm::BPFTargetLowering::BPFTargetLowering(),llvm::CSKYTargetLowering::CSKYTargetLowering(),llvm::HexagonTargetLowering::HexagonTargetLowering(),initActions(),llvm::LanaiTargetLowering::LanaiTargetLowering(),llvm::LoongArchTargetLowering::LoongArchTargetLowering(),llvm::M68kTargetLowering::M68kTargetLowering(),llvm::Mips16TargetLowering::Mips16TargetLowering(),llvm::MipsSETargetLowering::MipsSETargetLowering(),llvm::MipsTargetLowering::MipsTargetLowering(),llvm::MSP430TargetLowering::MSP430TargetLowering(),llvm::NVPTXTargetLowering::NVPTXTargetLowering(),llvm::PPCTargetLowering::PPCTargetLowering(),llvm::R600TargetLowering::R600TargetLowering(),llvm::RISCVTargetLowering::RISCVTargetLowering(),setOperationAction(),setOperationPromotedToType(),llvm::SITargetLowering::SITargetLowering(),llvm::SparcTargetLowering::SparcTargetLowering(),llvm::SystemZTargetLowering::SystemZTargetLowering(),llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering(),llvm::X86TargetLowering::X86TargetLowering(),llvm::XCoreTargetLowering::XCoreTargetLowering(), andllvm::XtensaTargetLowering::XtensaTargetLowering().
◆ setOperationPromotedToType()[1/2]
| inlineprotected |
Definition at line2720 of fileTargetLowering.h.
ReferencesAddPromotedToType(),Promote, andsetOperationAction().
◆ setOperationPromotedToType()[2/2]
| inlineprotected |
Convenience method to set an operation to Promote and specify the type in a single call.
Definition at line2716 of fileTargetLowering.h.
ReferencesAddPromotedToType(),Promote, andsetOperationAction().
Referenced byllvm::AArch64TargetLowering::AArch64TargetLowering(),llvm::NVPTXTargetLowering::NVPTXTargetLowering(),llvm::RISCVTargetLowering::RISCVTargetLowering(), andllvm::X86TargetLowering::X86TargetLowering().
◆ setPrefFunctionAlignment()
| inlineprotected |
Set the target's preferred function alignment.
This should be set if there is a performance benefit to higher-than-minimum alignment
Definition at line2745 of fileTargetLowering.h.
Referenced byllvm::AArch64TargetLowering::AArch64TargetLowering(),llvm::ARMTargetLowering::ARMTargetLowering(),llvm::BPFTargetLowering::BPFTargetLowering(),llvm::HexagonTargetLowering::HexagonTargetLowering(),llvm::LanaiTargetLowering::LanaiTargetLowering(),llvm::LoongArchTargetLowering::LoongArchTargetLowering(),llvm::MSP430TargetLowering::MSP430TargetLowering(),llvm::PPCTargetLowering::PPCTargetLowering(),llvm::RISCVTargetLowering::RISCVTargetLowering(),llvm::SystemZTargetLowering::SystemZTargetLowering(),llvm::X86TargetLowering::X86TargetLowering(), andllvm::XCoreTargetLowering::XCoreTargetLowering().
◆ setPrefLoopAlignment()
| inlineprotected |
Set the target's preferred loop alignment.
Default alignment is one, it means the target does not care about loop alignment. The target may also override getPrefLoopAlignment to provide per-loop values.
Definition at line2752 of fileTargetLowering.h.
Referenced byllvm::AArch64TargetLowering::AArch64TargetLowering(),llvm::ARMTargetLowering::ARMTargetLowering(),llvm::HexagonTargetLowering::HexagonTargetLowering(),llvm::LoongArchTargetLowering::LoongArchTargetLowering(),llvm::PPCTargetLowering::PPCTargetLowering(),llvm::RISCVTargetLowering::RISCVTargetLowering(), andllvm::X86TargetLowering::X86TargetLowering().
◆ setSchedulingPreference()
| inlineprotected |
Specify the target scheduling preference.
Definition at line2498 of fileTargetLowering.h.
Referenced byllvm::AArch64TargetLowering::AArch64TargetLowering(),llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(),llvm::ARCTargetLowering::ARCTargetLowering(),llvm::ARMTargetLowering::ARMTargetLowering(),llvm::AVRTargetLowering::AVRTargetLowering(),llvm::CSKYTargetLowering::CSKYTargetLowering(),llvm::HexagonTargetLowering::HexagonTargetLowering(),llvm::NVPTXTargetLowering::NVPTXTargetLowering(),llvm::PPCTargetLowering::PPCTargetLowering(),llvm::R600TargetLowering::R600TargetLowering(),llvm::SITargetLowering::SITargetLowering(),llvm::SystemZTargetLowering::SystemZTargetLowering(),llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering(),llvm::X86TargetLowering::X86TargetLowering(),llvm::XCoreTargetLowering::XCoreTargetLowering(), andllvm::XtensaTargetLowering::XtensaTargetLowering().
◆ setStackPointerRegisterToSaveRestore()
| inlineprotected |
If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
Definition at line2511 of fileTargetLowering.h.
Referenced byllvm::AArch64TargetLowering::AArch64TargetLowering(),llvm::ARCTargetLowering::ARCTargetLowering(),llvm::ARMTargetLowering::ARMTargetLowering(),llvm::AVRTargetLowering::AVRTargetLowering(),llvm::BPFTargetLowering::BPFTargetLowering(),llvm::CSKYTargetLowering::CSKYTargetLowering(),llvm::HexagonTargetLowering::HexagonTargetLowering(),llvm::LanaiTargetLowering::LanaiTargetLowering(),llvm::LoongArchTargetLowering::LoongArchTargetLowering(),llvm::M68kTargetLowering::M68kTargetLowering(),llvm::MipsTargetLowering::MipsTargetLowering(),llvm::MSP430TargetLowering::MSP430TargetLowering(),llvm::PPCTargetLowering::PPCTargetLowering(),llvm::RISCVTargetLowering::RISCVTargetLowering(),llvm::SITargetLowering::SITargetLowering(),llvm::SparcTargetLowering::SparcTargetLowering(),llvm::SystemZTargetLowering::SystemZTargetLowering(),llvm::VETargetLowering::VETargetLowering(),llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering(),llvm::X86TargetLowering::X86TargetLowering(),llvm::XCoreTargetLowering::XCoreTargetLowering(), andllvm::XtensaTargetLowering::XtensaTargetLowering().
◆ setSupportsUnalignedAtomics()
| inlineprotected |
Sets whether unaligned atomic operations are supported.
Definition at line2788 of fileTargetLowering.h.
Referenced byllvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), andllvm::AVRTargetLowering::AVRTargetLowering().
◆ setTargetDAGCombine()
| inlineprotected |
Targets should invoke this method for each target independent node that they want to provide a custom DAG combiner for by implementing the PerformDAGCombine virtual method.
Definition at line2731 of fileTargetLowering.h.
Referencesassert().
Referenced byllvm::AArch64TargetLowering::AArch64TargetLowering(),llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(),llvm::ARMTargetLowering::ARMTargetLowering(),llvm::HexagonTargetLowering::HexagonTargetLowering(),llvm::LanaiTargetLowering::LanaiTargetLowering(),llvm::LoongArchTargetLowering::LoongArchTargetLowering(),llvm::MipsSETargetLowering::MipsSETargetLowering(),llvm::MipsTargetLowering::MipsTargetLowering(),llvm::NVPTXTargetLowering::NVPTXTargetLowering(),llvm::PPCTargetLowering::PPCTargetLowering(),llvm::R600TargetLowering::R600TargetLowering(),llvm::RISCVTargetLowering::RISCVTargetLowering(),llvm::SITargetLowering::SITargetLowering(),llvm::SparcTargetLowering::SparcTargetLowering(),llvm::SystemZTargetLowering::SystemZTargetLowering(),llvm::VETargetLowering::VETargetLowering(),llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering(),llvm::X86TargetLowering::X86TargetLowering(), andllvm::XCoreTargetLowering::XCoreTargetLowering().
◆ setTruncStoreAction()
| inlineprotected |
Indicate that the specified truncating store does not work with the specified type and indicate what to do about it.
Definition at line2625 of fileTargetLowering.h.
Referencesassert(),llvm::MVT::isValid(), andllvm::MVT::SimpleTy.
Referenced byllvm::AArch64TargetLowering::AArch64TargetLowering(),llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(),llvm::ARMTargetLowering::ARMTargetLowering(),llvm::AVRTargetLowering::AVRTargetLowering(),llvm::CSKYTargetLowering::CSKYTargetLowering(),llvm::HexagonTargetLowering::HexagonTargetLowering(),initActions(),llvm::LoongArchTargetLowering::LoongArchTargetLowering(),llvm::M68kTargetLowering::M68kTargetLowering(),llvm::MipsSETargetLowering::MipsSETargetLowering(),llvm::MipsTargetLowering::MipsTargetLowering(),llvm::MSP430TargetLowering::MSP430TargetLowering(),llvm::NVPTXTargetLowering::NVPTXTargetLowering(),llvm::PPCTargetLowering::PPCTargetLowering(),llvm::R600TargetLowering::R600TargetLowering(),llvm::RISCVTargetLowering::RISCVTargetLowering(),llvm::SITargetLowering::SITargetLowering(),llvm::SparcTargetLowering::SparcTargetLowering(),llvm::SystemZTargetLowering::SystemZTargetLowering(),llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering(), andllvm::X86TargetLowering::X86TargetLowering().
◆ shallExtractConstSplatVectorElementToStore()
| inlinevirtual |
Return true if the target shall perform extract vector element and store given that the vector is known to be splat of constant.
Index[out] gives the index of the vector element to be extracted when this is true.
Reimplemented inllvm::PPCTargetLowering.
Definition at line960 of fileTargetLowering.h.
Referenced bygetMemsetStores().
◆ shouldAlignPointerArgs()
| inlinevirtual |
Return true if the pointer arguments to CI should be aligned by aligning the object whose address is being passed.
If so then MinSize is set to the minimum size the object must be to be aligned and PrefAlign is set to the preferred alignment.
Reimplemented inllvm::ARMTargetLowering, andllvm::LoongArchTargetLowering.
Definition at line2114 of fileTargetLowering.h.
◆ shouldAvoidTransformToShift()
| inlinevirtual |
Return true if creating a shift of the type by the given amount is not profitable.
Reimplemented inllvm::MSP430TargetLowering.
Definition at line3384 of fileTargetLowering.h.
Referenced byfoldExtendedSignBitTest(),shouldFoldSelectWithSingleBitTest(), andllvm::TargetLowering::SimplifySetCC().
◆ shouldCastAtomicLoadInIR()
| inlinevirtual |
Returns how the given (atomic) load should be cast by the IR-level AtomicExpand pass.
Reimplemented inllvm::AMDGPUTargetLowering,llvm::NVPTXTargetLowering, andllvm::SystemZTargetLowering.
Definition at line2315 of fileTargetLowering.h.
ReferencesCastToInteger,llvm::Value::getType(),llvm::Type::isFloatingPointTy(), andNone.
◆ shouldCastAtomicRMWIInIR()
| inlinevirtual |
Returns how the given atomic atomicrmw should be cast by the IR-level AtomicExpand pass.
Reimplemented inllvm::AMDGPUTargetLowering.
Definition at line2354 of fileTargetLowering.h.
ReferencesCastToInteger,llvm::AtomicRMWInst::getOperation(),llvm::Value::getType(),llvm::AtomicRMWInst::getValOperand(),llvm::Type::isFloatingPointTy(),llvm::Type::isPointerTy(),None, andllvm::AtomicRMWInst::Xchg.
◆ shouldCastAtomicStoreInIR()
| inlinevirtual |
Returns how the given (atomic) store should be cast by the IR-level AtomicExpand pass into.
For instanceAtomicExpansionKind::CastToInteger will try to cast the operands to integer values.
Reimplemented inllvm::AMDGPUTargetLowering,llvm::NVPTXTargetLowering, andllvm::SystemZTargetLowering.
Definition at line2331 of fileTargetLowering.h.
ReferencesCastToInteger, andNone.
◆ shouldConsiderGEPOffsetSplit()
| inlinevirtual |
Reimplemented inllvm::AArch64TargetLowering,llvm::LoongArchTargetLowering,llvm::RISCVTargetLowering, andllvm::SystemZTargetLowering.
Definition at line3380 of fileTargetLowering.h.
◆ shouldConvertConstantLoadToIntImm()
| inlinevirtual |
Return true if it is beneficial to convert a load of a constant to just the constant itself.
On some targets it might be more efficient to use a combination of arithmetic instructions to materialize the constant instead of loading it from a constant pool.
Reimplemented inllvm::AArch64TargetLowering,llvm::SITargetLowering,llvm::ARMTargetLowering,llvm::PPCTargetLowering,llvm::RISCVTargetLowering, andllvm::X86TargetLowering.
Definition at line3322 of fileTargetLowering.h.
Referenced bygetMemsetStringVal().
◆ shouldConvertFpToSat()
| inlinevirtual |
Should we generate fp_to_si_sat and fp_to_ui_sat from type FPVT to type VT from min(max(fptoi)) saturation patterns.
Reimplemented inllvm::AArch64TargetLowering,llvm::ARMTargetLowering,llvm::RISCVTargetLowering, andllvm::X86TargetLowering.
Definition at line3402 of fileTargetLowering.h.
ReferencesisOperationLegalOrCustom().
Referenced byPerformMinMaxFpToSatCombine(),PerformUMinFpToSatCombine(), andllvm::AArch64TargetLowering::shouldConvertFpToSat().
◆ shouldConvertPhiType()
| inlinevirtual |
Given a set in interconnected phis of type 'From' that are loaded/stored or bitcast to type 'To', return true if the set should be converted to 'To'.
Reimplemented inllvm::X86TargetLowering.
Definition at line2891 of fileTargetLowering.h.
ReferencesFrom,llvm::Type::isFloatingPointTy(), andllvm::Type::isIntegerTy().
Referenced byllvm::X86TargetLowering::shouldConvertPhiType().
◆ shouldConvertSplatType()
| inlinevirtual |
Given a shuffle vector SVI representing a vector splat, return a new scalar type of size equal to SVI's scalar type if the new type is more profitable.
Returns nullptr otherwise. For example under MVE float splats are converted to integer to prevent the need to move from SPR to GPR registers.
Reimplemented inllvm::ARMTargetLowering.
Definition at line2884 of fileTargetLowering.h.
◆ shouldExpandAtomicCmpXchgInIR()
| inlinevirtual |
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
Reimplemented inllvm::AArch64TargetLowering,llvm::SITargetLowering,llvm::ARMTargetLowering,llvm::HexagonTargetLowering,llvm::PPCTargetLowering,llvm::LoongArchTargetLowering, andllvm::RISCVTargetLowering.
Definition at line2340 of fileTargetLowering.h.
ReferencesNone.
Referenced byllvm::PPCTargetLowering::shouldExpandAtomicCmpXchgInIR().
◆ shouldExpandAtomicLoadInIR()
| inlinevirtual |
Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass.
Reimplemented inllvm::AArch64TargetLowering,llvm::SITargetLowering,llvm::ARMTargetLowering, andllvm::HexagonTargetLowering.
Definition at line2309 of fileTargetLowering.h.
ReferencesNone.
◆ shouldExpandAtomicRMWInIR()
| inlinevirtual |
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
Default is to never expand.
Reimplemented inllvm::SITargetLowering,llvm::AArch64TargetLowering,llvm::ARMTargetLowering,llvm::HexagonTargetLowering,llvm::LoongArchTargetLowering,llvm::NVPTXTargetLowering,llvm::PPCTargetLowering,llvm::RISCVTargetLowering,llvm::SparcTargetLowering,llvm::VETargetLowering,llvm::M68kTargetLowering, andllvm::SystemZTargetLowering.
Definition at line2346 of fileTargetLowering.h.
ReferencesCmpXChg,llvm::AtomicRMWInst::isFloatingPointOperation(), andNone.
Referenced byllvm::PPCTargetLowering::shouldExpandAtomicRMWInIR().
◆ shouldExpandAtomicStoreInIR()
| inlinevirtual |
Returns how the given (atomic) store should be expanded by the IR-level AtomicExpand pass into.
For instanceAtomicExpansionKind::Expand will try to use an atomicrmw xchg.
Reimplemented inllvm::AArch64TargetLowering,llvm::SITargetLowering,llvm::ARMTargetLowering, andllvm::HexagonTargetLowering.
Definition at line2324 of fileTargetLowering.h.
ReferencesNone.
◆ shouldExpandBuildVectorWithShuffles()
| inlinevirtual |
Reimplemented inllvm::HexagonTargetLowering,llvm::PPCTargetLowering, andllvm::RISCVTargetLowering.
Definition at line550 of fileTargetLowering.h.
Referenced byllvm::PPCTargetLowering::shouldExpandBuildVectorWithShuffles().
◆ shouldExpandCmpUsingSelects()
Should we expand [US]CMP nodes using two selects and two compares, or by doing arithmetic on boolean types.
Reimplemented inllvm::AArch64TargetLowering, andllvm::SystemZTargetLowering.
Definition at line3408 of fileTargetLowering.h.
Referenced byllvm::TargetLowering::expandCMP(),llvm::BasicTTIImplBase< T >::getTypeBasedIntrinsicInstrCost(), andllvm::LegalizerHelper::lowerThreewayCompare().
◆ shouldExpandCttzElements()
Return true if the @llvm.experimental.cttz.elts intrinsic should be expanded using generic code inSelectionDAGBuilder.
Reimplemented inllvm::AArch64TargetLowering, andllvm::RISCVTargetLowering.
Definition at line478 of fileTargetLowering.h.
◆ shouldExpandGetActiveLaneMask()
| inlinevirtual |
Return true if the @llvm.get.active.lane.mask intrinsic should be expanded using generic code inSelectionDAGBuilder.
Reimplemented inllvm::AArch64TargetLowering.
Definition at line467 of fileTargetLowering.h.
◆ shouldExpandGetVectorLength()
| inlinevirtual |
Definition at line471 of fileTargetLowering.h.
◆ shouldExpandPartialReductionIntrinsic()
| inlinevirtual |
Return true if the @llvm.experimental.vector.partial.reduce.
- intrinsic should be expanded using generic code inSelectionDAGBuilder.
Reimplemented inllvm::AArch64TargetLowering.
Definition at line461 of fileTargetLowering.h.
◆ shouldExpandVectorMatch()
| inlinevirtual |
Return true if the @llvm.experimental.vector.match intrinsic should be expanded for vector type ‘VT’ and search size ‘SearchSize’ using generic code inSelectionDAGBuilder.
Reimplemented inllvm::AArch64TargetLowering.
Definition at line489 of fileTargetLowering.h.
◆ shouldExtendGSIndex()
Returns true if the index type for a masked gather/scatter requires extending.
Definition at line1592 of fileTargetLowering.h.
◆ shouldExtendTypeInLibCall()
Returns true if arguments should be extended in lib calls.
Reimplemented inllvm::LoongArchTargetLowering, andllvm::RISCVTargetLowering.
Definition at line2303 of fileTargetLowering.h.
Referenced byllvm::TargetLowering::makeLibCall().
◆ shouldFoldConstantShiftPairToMask()
| inlinevirtual |
Return true if it is profitable to fold a pair of shifts into a mask.
This is usually true on most targets. But some targets, like Thumb1, have immediate shift instructions, but no immediate "and" instruction; this makes the fold unprofitable.
Reimplemented inllvm::AArch64TargetLowering,llvm::ARMTargetLowering,llvm::MipsTargetLowering, andllvm::X86TargetLowering.
Definition at line830 of fileTargetLowering.h.
Referenced byllvm::X86TargetLowering::shouldFoldConstantShiftPairToMask().
◆ shouldFoldMaskToVariableShiftPair()
| inlinevirtual |
There are two ways to clear extreme bits (either low or high): Mask: x & (-1 << y) (the instcombine canonical form) Shifts: x >> y << y Return true if the variant with 2 variable shifts is preferred.
Return false if there is no preference.
Reimplemented inllvm::X86TargetLowering.
Definition at line821 of fileTargetLowering.h.
◆ shouldFoldSelectWithIdentityConstant()
| inlinevirtual |
Return true if pulling a binary operation into a select with an identity constant is profitable.
This is the inverse of an IR transform. Example: X + (Cond ? Y : 0) --> Cond ? (X + Y) : X
Reimplemented inllvm::AArch64TargetLowering,llvm::ARMTargetLowering,llvm::RISCVTargetLowering, andllvm::X86TargetLowering.
Definition at line3312 of fileTargetLowering.h.
◆ shouldFoldSelectWithSingleBitTest()
| inlinevirtual |
Definition at line3390 of fileTargetLowering.h.
Referencesllvm::APInt::getBitWidth(), andshouldAvoidTransformToShift().
◆ shouldFormOverflowOp()
| inlinevirtual |
Try to convert math with an overflow comparison into the corresponding DAG node operation.
Targets may want to override this independently of whether the operation is legal/custom for the given type because it may obscure matching of other patterns.
Reimplemented inllvm::AArch64TargetLowering,llvm::ARMTargetLowering,llvm::RISCVTargetLowering,llvm::SystemZTargetLowering, andllvm::X86TargetLowering.
Definition at line3354 of fileTargetLowering.h.
ReferencesisOperationExpand(),llvm::EVT::isSimple(),llvm::EVT::isVector(), andllvm::ISD::UADDO.
Referenced byllvm::AArch64TargetLowering::shouldFormOverflowOp(),llvm::ARMTargetLowering::shouldFormOverflowOp(), andllvm::RISCVTargetLowering::shouldFormOverflowOp().
◆ shouldInsertFencesForAtomic()
| inlinevirtual |
WhetherAtomicExpandPass should automatically insert fences and reduce ordering for this atomic.
This should be true for most architectures with weak memory ordering. Defaults to false.
Reimplemented inllvm::AArch64TargetLowering,llvm::ARMTargetLowering,llvm::PPCTargetLowering,llvm::RISCVTargetLowering,llvm::SparcTargetLowering, andllvm::VETargetLowering.
Definition at line2171 of fileTargetLowering.h.
◆ shouldInsertTrailingFenceForAtomicStore()
| inlinevirtual |
WhetherAtomicExpandPass should automatically insert a trailing fence without reducing the ordering for this atomic.
Defaults to false.
Reimplemented inllvm::AArch64TargetLowering.
Definition at line2178 of fileTargetLowering.h.
◆ shouldKeepZExtForFP16Conv()
| inlinevirtual |
Does this target require the clearing of high-order bits in a register passed to the fp16 to fp conversion library function.
Reimplemented inllvm::PPCTargetLowering.
Definition at line3398 of fileTargetLowering.h.
◆ shouldLocalize()
| virtual |
Check whether or notMI needs to be moved close to its uses.
Definition at line2329 of fileTargetLoweringBase.cpp.
Referencesllvm::TargetTransformInfo::getGISelRematGlobalCost(),llvm_unreachable,MI, andMRI.
◆ shouldNormalizeToSelectSequence()
| inlinevirtual |
Returns true if we should normalize select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely that it saves us from materializing N0 and N1 in an integer register.
Targets that are able to perform and/or on flags should return false here.
Definition at line2404 of fileTargetLowering.h.
ReferencesgetTypeAction(),hasMultipleConditionRegisters(),TypeExpandFloat,TypeExpandInteger, andTypeSplitVector.
◆ shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd()
| inlinevirtual |
Given the pattern (X & (C l>>/<< Y)) ==/!= 0 return true if it should be transformed into: ((X <</l>> Y) & C) ==/!= 0 WARNING: if 'X' is a constant, the fold may deadlock! FIXME: we could avoid passing XC, but we can't useisConstOrConstSplat() here because it can end up being not linked in.
Reimplemented inllvm::AArch64TargetLowering,llvm::RISCVTargetLowering, andllvm::X86TargetLowering.
Definition at line855 of fileTargetLowering.h.
ReferencesCC,hasBitTest(),llvm::ISD::SHL,X, andY.
Referenced byllvm::AArch64TargetLowering::shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(), andllvm::X86TargetLowering::shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd().
◆ shouldReassociateReduction()
| inlinevirtual |
Reimplemented inllvm::ARMTargetLowering.
Definition at line495 of fileTargetLowering.h.
◆ shouldReduceLoadWidth()
| inlinevirtual |
Return true if it is profitable to reduce a load to a smaller type.
Example: (i16 (trunc (i32 (load x))) -> i16 load x
Reimplemented inllvm::AArch64TargetLowering,llvm::HexagonTargetLowering,llvm::X86TargetLowering, andllvm::AMDGPUTargetLowering.
Definition at line1815 of fileTargetLowering.h.
Referencesllvm::EVT::isVector().
Referenced bynarrowExtractedVectorLoad(),llvm::AArch64TargetLowering::shouldReduceLoadWidth(),llvm::HexagonTargetLowering::shouldReduceLoadWidth(),llvm::AMDGPUTargetLowering::shouldReduceLoadWidth(), andllvm::TargetLowering::SimplifySetCC().
◆ shouldRemoveExtendFromGSIndex()
| inlinevirtual |
Reimplemented inllvm::RISCVTargetLowering.
Definition at line1596 of fileTargetLowering.h.
Referenced byrefineIndexType().
◆ shouldRemoveRedundantExtend()
Return true (the default) if it is profitable to remove a sext_inreg(x) where the sext is redundant, and use x directly.
Reimplemented inllvm::AArch64TargetLowering.
Definition at line1827 of fileTargetLowering.h.
Referenced byllvm::TargetLowering::SimplifyMultipleUseDemandedBits().
◆ shouldScalarizeBinop()
Try to convert an extract element of a vector binary operation into an extract element followed by a scalar operation.
Reimplemented inllvm::RISCVTargetLowering, andllvm::X86TargetLowering.
Definition at line3338 of fileTargetLowering.h.
Referenced byscalarizeExtractedBinOp().
◆ ShouldShrinkFPConstant()
If true, then instruction selection should seek to shrink the FP constant of the specified type to a smaller type in order to save space and / or reduce runtime.
Reimplemented inllvm::AMDGPUTargetLowering,llvm::SparcTargetLowering,llvm::SystemZTargetLowering, andllvm::X86TargetLowering.
Definition at line1811 of fileTargetLowering.h.
◆ shouldSignExtendTypeInLibCall()
| inlinevirtual |
Returns true if arguments should be sign-extended in lib calls.
Reimplemented inllvm::LoongArchTargetLowering, andllvm::RISCVTargetLowering.
Definition at line2298 of fileTargetLowering.h.
Referenced byconversionLibcall(),llvm::SystemZTargetLowering::makeExternalCall(), andllvm::TargetLowering::makeLibCall().
◆ shouldSplatInsEltVarIndex()
Return true if inserting a scalar into a variable element of an undef vector is more efficiently handled by splatting the scalar instead.
Reimplemented inllvm::X86TargetLowering.
Definition at line967 of fileTargetLowering.h.
◆ shouldTransformSignedTruncationCheck()
| inlinevirtual |
Should we tranform the IR-optimal check for whether given truncation down into KeptBits would be truncating or not: (add x, (1 << (KeptBits-1))) srccond (1 << KeptBits) Into it's more traditional form: ((x << C) a>> C) dstcond x Return true if we should transform.
Return false if there is no preference.
Reimplemented inllvm::AArch64TargetLowering,llvm::RISCVTargetLowering, andllvm::X86TargetLowering.
Definition at line842 of fileTargetLowering.h.
◆ shouldUseStrictFP_TO_INT()
| inlinevirtual |
Return true if it is more correct/profitable to use strict FP_TO_INT conversion operations - canonicalizing the FP source value instead of converting all cases and then selecting based on value.
This may be true if the target throws exceptions for out of bounds conversions or has fast FP CMOV.
Definition at line2455 of fileTargetLowering.h.
Referenced byllvm::TargetLowering::expandFP_TO_UINT().
◆ signExtendConstant()
| inlinevirtual |
Return true if this constant should be sign extended when promoting to a larger type.
Reimplemented inllvm::LoongArchTargetLowering, andllvm::RISCVTargetLowering.
Definition at line3091 of fileTargetLowering.h.
Referenced byllvm::FunctionLoweringInfo::ComputePHILiveOutRegInfo().
◆ softPromoteHalfType()
| inlinevirtual |
Reimplemented inllvm::ARMTargetLowering,llvm::MipsTargetLowering,llvm::RISCVTargetLowering, andllvm::X86TargetLowering.
Definition at line532 of fileTargetLowering.h.
Referenced bycomputeRegisterProperties().
◆ storeOfVectorConstantIsCheap()
| inlinevirtual |
Return true if it is expected to be cheaper to do a store of vector constant with the given size and type for the address space than to store the individual scalar element constants.
Reimplemented inllvm::RISCVTargetLowering,llvm::X86TargetLowering, andllvm::AMDGPUTargetLowering.
Definition at line687 of fileTargetLowering.h.
◆ supportsUnalignedAtomics()
| inline |
Whether the target supports unaligned atomic operations.
Definition at line2166 of fileTargetLowering.h.
◆ useFPRegsForHalfType()
| inlinevirtual |
Reimplemented inllvm::ARMTargetLowering.
Definition at line538 of fileTargetLowering.h.
Referenced bycomputeRegisterProperties().
◆ useSoftFloat()
| inlinevirtual |
Reimplemented inllvm::ARMTargetLowering,llvm::PPCTargetLowering,llvm::SparcTargetLowering,llvm::SystemZTargetLowering, andllvm::X86TargetLowering.
Definition at line366 of fileTargetLowering.h.
Referenced bysinkCmpExpression().
◆ useStackGuardXorFP()
| inlinevirtual |
If this function returns true, stack protection checks should XOR the frame pointer (or whichever pointer is used to address locals) into the stack guard value before checking it.
getIRStackGuard must return nullptr if this returns true.
Reimplemented inllvm::X86TargetLowering.
Definition at line2079 of fileTargetLowering.h.
Referenced byllvm::SelectionDAGBuilder::visitSPDescriptorParent().
Member Data Documentation
◆ EnableExtLdPromotion
| protected |
- See also
- enableExtLdPromotion.
Definition at line3760 of fileTargetLowering.h.
Referenced byllvm::AArch64TargetLowering::AArch64TargetLowering(),enableExtLdPromotion(),llvm::RISCVTargetLowering::RISCVTargetLowering(),TargetLoweringBase(), andllvm::X86TargetLowering::X86TargetLowering().
◆ GatherAllAliasesMaxDepth
| protected |
Depth that GatherAllAliases should continue looking for chain dependencies when trying to find a more preferable chain.
As an approximation, this should be more than the number of consecutive stores expected to be merged.
Definition at line3689 of fileTargetLowering.h.
Referenced byllvm::AMDGPUTargetLowering::AMDGPUTargetLowering(),getGatherAllAliasesMaxDepth(),llvm::PPCTargetLowering::PPCTargetLowering(), andTargetLoweringBase().
◆ IsStrictFPEnabled
| protected |
Definition at line3772 of fileTargetLowering.h.
Referenced byllvm::AArch64TargetLowering::AArch64TargetLowering(),isStrictFPEnabled(),llvm::PPCTargetLowering::PPCTargetLowering(),llvm::RISCVTargetLowering::RISCVTargetLowering(),llvm::SystemZTargetLowering::SystemZTargetLowering(),TargetLoweringBase(), andllvm::X86TargetLowering::X86TargetLowering().
◆ MaxGluedStoresPerMemcpy
| protected |
Specify max number of store instructions to glue in inlined memcpy.
When memcpy is inlined based on MaxStoresPerMemcpy, specify maximum number of store instructions to keep together. This helps in pairing and
Definition at line3724 of fileTargetLowering.h.
Referenced byllvm::AArch64TargetLowering::AArch64TargetLowering(),llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(),getMaxGluedStoresPerMemcpy(),llvm::RISCVTargetLowering::RISCVTargetLowering(), andTargetLoweringBase().
◆ MaxLoadsPerMemcmp
| protected |
Specify maximum number of load instructions per memcmp call.
When lowering @llvm.memcmp this field specifies the maximum number of pairs of load operations that may be substituted for a call to memcmp. Targets must set this value based on the cost threshold for that target. Targets should assume that the memcmp will be done using as many of the largest load operations first, followed by smaller ones, if necessary, per alignment restrictions. For example, loading 7 bytes on a 32-bit machine with 32-bit alignment would result in one 4-byte load, a one 2-byte load and one 1-byte load. This only applies to copying a constant array of constant size.
Definition at line3737 of fileTargetLowering.h.
Referenced byllvm::AArch64TargetLowering::AArch64TargetLowering(),llvm::BPFTargetLowering::BPFTargetLowering(),getMaxExpandSizeMemcmp(),llvm::PPCTargetLowering::PPCTargetLowering(),llvm::RISCVTargetLowering::RISCVTargetLowering(),TargetLoweringBase(), andllvm::X86TargetLowering::X86TargetLowering().
◆ MaxLoadsPerMemcmpOptSize
| protected |
Likewise for functions with the OptSize attribute.
Definition at line3739 of fileTargetLowering.h.
Referenced byllvm::AArch64TargetLowering::AArch64TargetLowering(),llvm::BPFTargetLowering::BPFTargetLowering(),getMaxExpandSizeMemcmp(),llvm::PPCTargetLowering::PPCTargetLowering(),llvm::RISCVTargetLowering::RISCVTargetLowering(),TargetLoweringBase(), andllvm::X86TargetLowering::X86TargetLowering().
◆ MaxStoresPerMemcpy
| protected |
Specify maximum number of store instructions per memcpy call.
When lowering @llvm.memcpy this field specifies the maximum number of store operations that may be substituted for a call to memcpy. Targets must set this value based on the cost threshold for that target. Targets should assume that the memcpy will be done using as many of the largest store operations first, followed by smaller ones, if necessary, per alignment restrictions. For example, storing 7 bytes on a 32-bit machine with 32-bit alignment would result in one 4-byte store, a one 2-byte store and one 1-byte store. This only applies to copying a constant array of constant size.
Definition at line3716 of fileTargetLowering.h.
Referenced byllvm::AArch64TargetLowering::AArch64TargetLowering(),llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(),llvm::ARMTargetLowering::ARMTargetLowering(),llvm::BPFTargetLowering::BPFTargetLowering(),getMaxStoresPerMemcpy(),llvm::HexagonTargetLowering::HexagonTargetLowering(),llvm::LanaiTargetLowering::LanaiTargetLowering(),llvm::MipsTargetLowering::MipsTargetLowering(),llvm::NVPTXTargetLowering::NVPTXTargetLowering(),llvm::PPCTargetLowering::PPCTargetLowering(),llvm::RISCVTargetLowering::RISCVTargetLowering(),llvm::SystemZTargetLowering::SystemZTargetLowering(),TargetLoweringBase(),llvm::X86TargetLowering::X86TargetLowering(), andllvm::XCoreTargetLowering::XCoreTargetLowering().
◆ MaxStoresPerMemcpyOptSize
| protected |
Likewise for functions with the OptSize attribute.
Definition at line3718 of fileTargetLowering.h.
Referenced byllvm::AArch64TargetLowering::AArch64TargetLowering(),llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(),llvm::ARMTargetLowering::ARMTargetLowering(),llvm::BPFTargetLowering::BPFTargetLowering(),getMaxStoresPerMemcpy(),llvm::HexagonTargetLowering::HexagonTargetLowering(),llvm::LanaiTargetLowering::LanaiTargetLowering(),llvm::NVPTXTargetLowering::NVPTXTargetLowering(),llvm::PPCTargetLowering::PPCTargetLowering(),llvm::RISCVTargetLowering::RISCVTargetLowering(),llvm::SystemZTargetLowering::SystemZTargetLowering(),TargetLoweringBase(),llvm::X86TargetLowering::X86TargetLowering(), andllvm::XCoreTargetLowering::XCoreTargetLowering().
◆ MaxStoresPerMemmove
| protected |
Specify maximum number of store instructions per memmove call.
When lowering @llvm.memmove this field specifies the maximum number of store instructions that may be substituted for a call to memmove. Targets must set this value based on the cost threshold for that target. Targets should assume that the memmove will be done using as many of the largest store operations first, followed by smaller ones, if necessary, per alignment restrictions. For example, moving 9 bytes on a 32-bit machine with 8-bit alignment would result in nine 1-byte stores. This only applies to copying a constant array of constant size.
Definition at line3751 of fileTargetLowering.h.
Referenced byllvm::AArch64TargetLowering::AArch64TargetLowering(),llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(),llvm::ARMTargetLowering::ARMTargetLowering(),llvm::BPFTargetLowering::BPFTargetLowering(),getMaxStoresPerMemmove(),llvm::HexagonTargetLowering::HexagonTargetLowering(),llvm::LanaiTargetLowering::LanaiTargetLowering(),llvm::NVPTXTargetLowering::NVPTXTargetLowering(),llvm::PPCTargetLowering::PPCTargetLowering(),llvm::RISCVTargetLowering::RISCVTargetLowering(),TargetLoweringBase(),llvm::X86TargetLowering::X86TargetLowering(), andllvm::XCoreTargetLowering::XCoreTargetLowering().
◆ MaxStoresPerMemmoveOptSize
| protected |
Likewise for functions with the OptSize attribute.
Definition at line3753 of fileTargetLowering.h.
Referenced byllvm::AArch64TargetLowering::AArch64TargetLowering(),llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(),llvm::ARMTargetLowering::ARMTargetLowering(),llvm::BPFTargetLowering::BPFTargetLowering(),getMaxStoresPerMemmove(),llvm::HexagonTargetLowering::HexagonTargetLowering(),llvm::LanaiTargetLowering::LanaiTargetLowering(),llvm::NVPTXTargetLowering::NVPTXTargetLowering(),llvm::PPCTargetLowering::PPCTargetLowering(),llvm::RISCVTargetLowering::RISCVTargetLowering(),TargetLoweringBase(),llvm::X86TargetLowering::X86TargetLowering(), andllvm::XCoreTargetLowering::XCoreTargetLowering().
◆ MaxStoresPerMemset
| protected |
Specify maximum number of store instructions per memset call.
When lowering @llvm.memset this field specifies the maximum number of store operations that may be substituted for the call to memset. Targets must set this value based on the cost threshold for that target. Targets should assume that the memset will be done using as many of the largest store operations first, followed by smaller ones, if necessary, per alignment restrictions. For example, storing 9 bytes on a 32-bit machine with 16-bit alignment would result in four 2-byte stores and one 1-byte store. This only applies to setting a constant array of a constant size.
Definition at line3701 of fileTargetLowering.h.
Referenced byllvm::AArch64TargetLowering::AArch64TargetLowering(),llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(),llvm::ARMTargetLowering::ARMTargetLowering(),llvm::BPFTargetLowering::BPFTargetLowering(),getMaxStoresPerMemset(),llvm::HexagonTargetLowering::HexagonTargetLowering(),llvm::LanaiTargetLowering::LanaiTargetLowering(),llvm::NVPTXTargetLowering::NVPTXTargetLowering(),llvm::PPCTargetLowering::PPCTargetLowering(),llvm::RISCVTargetLowering::RISCVTargetLowering(),llvm::SystemZTargetLowering::SystemZTargetLowering(),TargetLoweringBase(),llvm::X86TargetLowering::X86TargetLowering(), andllvm::XCoreTargetLowering::XCoreTargetLowering().
◆ MaxStoresPerMemsetOptSize
| protected |
Likewise for functions with the OptSize attribute.
Definition at line3703 of fileTargetLowering.h.
Referenced byllvm::AArch64TargetLowering::AArch64TargetLowering(),llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(),llvm::ARMTargetLowering::ARMTargetLowering(),llvm::BPFTargetLowering::BPFTargetLowering(),getMaxStoresPerMemset(),llvm::HexagonTargetLowering::HexagonTargetLowering(),llvm::LanaiTargetLowering::LanaiTargetLowering(),llvm::NVPTXTargetLowering::NVPTXTargetLowering(),llvm::PPCTargetLowering::PPCTargetLowering(),llvm::RISCVTargetLowering::RISCVTargetLowering(),llvm::SystemZTargetLowering::SystemZTargetLowering(),TargetLoweringBase(),llvm::X86TargetLowering::X86TargetLowering(), andllvm::XCoreTargetLowering::XCoreTargetLowering().
◆ PredictableSelectIsExpensive
| protected |
Tells the code generator that select is more expensive than a branch if the branch is usually predicted right.
Definition at line3757 of fileTargetLowering.h.
Referenced byllvm::AArch64TargetLowering::AArch64TargetLowering(),llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(),llvm::ARMTargetLowering::ARMTargetLowering(),isPredictableSelectExpensive(),llvm::PPCTargetLowering::PPCTargetLowering(),llvm::RISCVTargetLowering::RISCVTargetLowering(),TargetLoweringBase(), andllvm::X86TargetLowering::X86TargetLowering().
The documentation for this class was generated from the following files:
- include/llvm/CodeGen/TargetLowering.h
- lib/CodeGen/TargetLoweringBase.cpp
