LLVM 20.0.0git |
This is used to represent a portion of an LLVM function in a low-level DataDependence DAG representation suitable for instruction selection.More...
#include "llvm/CodeGen/SelectionDAG.h"
Classes | |
struct | DAGNodeDeletedListener |
struct | DAGNodeInsertedListener |
struct | DAGUpdateListener |
Clients of various APIs that cause global effects on the DAG can optionally implement this interface.More... | |
class | FlagInserter |
Help to insertSDNodeFlags automatically in transforming.More... | |
Public Types | |
enum | OverflowKind {OFK_Never,OFK_Sometime,OFK_Always } |
Used to represent the possible overflow behavior of an operation.More... | |
using | allnodes_const_iterator =ilist<SDNode >::const_iterator |
using | allnodes_iterator =ilist<SDNode >::iterator |
Public Member Functions | |
SelectionDAG (constTargetMachine &TM,CodeGenOptLevel) | |
SelectionDAG (constSelectionDAG &)=delete | |
SelectionDAG & | operator= (constSelectionDAG &)=delete |
~SelectionDAG () | |
void | init (MachineFunction &NewMF,OptimizationRemarkEmitter &NewORE,Pass *PassPtr,constTargetLibraryInfo *LibraryInfo,UniformityInfo *UA,ProfileSummaryInfo *PSIin,BlockFrequencyInfo *BFIin,MachineModuleInfo &MMI,FunctionVarLocsconst *FnVarLocs) |
Prepare thisSelectionDAG to process code in the givenMachineFunction. | |
void | init (MachineFunction &NewMF,OptimizationRemarkEmitter &NewORE,MachineFunctionAnalysisManager &AM,constTargetLibraryInfo *LibraryInfo,UniformityInfo *UA,ProfileSummaryInfo *PSIin,BlockFrequencyInfo *BFIin,MachineModuleInfo &MMI,FunctionVarLocsconst *FnVarLocs) |
void | setFunctionLoweringInfo (FunctionLoweringInfo *FuncInfo) |
void | clear () |
Clear state and free memory necessary to make thisSelectionDAG ready to process a new block. | |
MachineFunction & | getMachineFunction ()const |
constPass * | getPass ()const |
MachineFunctionAnalysisManager * | getMFAM () |
CodeGenOptLevel | getOptLevel ()const |
constDataLayout & | getDataLayout ()const |
constTargetMachine & | getTarget ()const |
constTargetSubtargetInfo & | getSubtarget ()const |
template<typename STC > | |
const STC & | getSubtarget ()const |
constTargetLowering & | getTargetLoweringInfo ()const |
constTargetLibraryInfo & | getLibInfo ()const |
constSelectionDAGTargetInfo & | getSelectionDAGInfo ()const |
constUniformityInfo * | getUniformityInfo ()const |
constFunctionVarLocs * | getFunctionVarLocs ()const |
Returns the result of theAssignmentTrackingAnalysis pass if it's available, otherwise return nullptr. | |
LLVMContext * | getContext ()const |
OptimizationRemarkEmitter & | getORE ()const |
ProfileSummaryInfo * | getPSI ()const |
BlockFrequencyInfo * | getBFI ()const |
MachineModuleInfo * | getMMI ()const |
FlagInserter * | getFlagInserter () |
void | setFlagInserter (FlagInserter *FI) |
LLVM_DUMP_METHOD void | dumpDotGraph (constTwine &FileName,constTwine &Title) |
Just dump dot graph to a user-provided path and title. | |
void | viewGraph (const std::string &Title) |
Pop up a GraphViz/gv window with the DAG rendered using 'dot'. | |
void | viewGraph () |
void | clearGraphAttrs () |
Clear all previously defined node graph attributes. | |
void | setGraphAttrs (constSDNode *N,constchar *Attrs) |
Set graph attributes for a node. (eg. "color=red".) | |
std::string | getGraphAttrs (constSDNode *N)const |
Get graph attributes for a node. | |
void | setGraphColor (constSDNode *N,constchar *Color) |
Convenience for setting node color attribute. | |
void | setSubgraphColor (SDNode *N,constchar *Color) |
Convenience for setting subgraph color attribute. | |
allnodes_const_iterator | allnodes_begin ()const |
allnodes_const_iterator | allnodes_end ()const |
allnodes_iterator | allnodes_begin () |
allnodes_iterator | allnodes_end () |
ilist<SDNode >::size_type | allnodes_size ()const |
iterator_range<allnodes_iterator > | allnodes () |
iterator_range<allnodes_const_iterator > | allnodes ()const |
constSDValue & | getRoot ()const |
Return the root tag of theSelectionDAG. | |
SDValue | getEntryNode ()const |
Return the token chain corresponding to the entry of the function. | |
constSDValue & | setRoot (SDValueN) |
Set the current root tag of theSelectionDAG. | |
void | Combine (CombineLevel Level,BatchAAResults *BatchAA,CodeGenOptLevel OptLevel) |
This iterates over the nodes in theSelectionDAG, folding certain types of nodes together, or eliminating superfluous nodes. | |
bool | LegalizeTypes () |
This transforms theSelectionDAG into aSelectionDAG that only uses types natively supported by the target. | |
void | Legalize () |
This transforms theSelectionDAG into aSelectionDAG that is compatible with the target instruction selector, as indicated by theTargetLowering object. | |
bool | LegalizeOp (SDNode *N,SmallSetVector<SDNode *, 16 > &UpdatedNodes) |
Transforms aSelectionDAG node and any operands to it into a node that is compatible with the target instruction selector, as indicated by theTargetLowering object. | |
bool | LegalizeVectors () |
This transforms theSelectionDAG into aSelectionDAG that only uses vector math operations supported by the target. | |
void | RemoveDeadNodes () |
This method deletes all unreachable nodes in theSelectionDAG. | |
void | DeleteNode (SDNode *N) |
Remove the specified node from the system. | |
SDVTList | getVTList (EVT VT) |
Return anSDVTList that represents the list of values specified. | |
SDVTList | getVTList (EVT VT1,EVT VT2) |
SDVTList | getVTList (EVT VT1,EVT VT2,EVT VT3) |
SDVTList | getVTList (EVT VT1,EVT VT2,EVT VT3,EVT VT4) |
SDVTList | getVTList (ArrayRef<EVT > VTs) |
SDValue | getGlobalAddress (constGlobalValue *GV,constSDLoc &DL,EVT VT, int64_t offset=0,bool isTargetGA=false,unsigned TargetFlags=0) |
SDValue | getTargetGlobalAddress (constGlobalValue *GV,constSDLoc &DL,EVT VT, int64_t offset=0,unsigned TargetFlags=0) |
SDValue | getFrameIndex (int FI,EVT VT,bool isTarget=false) |
SDValue | getTargetFrameIndex (int FI,EVT VT) |
SDValue | getJumpTable (int JTI,EVT VT,bool isTarget=false,unsigned TargetFlags=0) |
SDValue | getTargetJumpTable (int JTI,EVT VT,unsigned TargetFlags=0) |
SDValue | getJumpTableDebugInfo (int JTI,SDValue Chain,constSDLoc &DL) |
SDValue | getConstantPool (constConstant *C,EVT VT,MaybeAlignAlign=std::nullopt, int Offs=0,bool isT=false,unsigned TargetFlags=0) |
SDValue | getTargetConstantPool (constConstant *C,EVT VT,MaybeAlignAlign=std::nullopt, intOffset=0,unsigned TargetFlags=0) |
SDValue | getConstantPool (MachineConstantPoolValue *C,EVT VT,MaybeAlignAlign=std::nullopt, int Offs=0,bool isT=false,unsigned TargetFlags=0) |
SDValue | getTargetConstantPool (MachineConstantPoolValue *C,EVT VT,MaybeAlignAlign=std::nullopt, intOffset=0,unsigned TargetFlags=0) |
SDValue | getBasicBlock (MachineBasicBlock *MBB) |
SDValue | getExternalSymbol (constchar *Sym,EVT VT) |
SDValue | getTargetExternalSymbol (constchar *Sym,EVT VT,unsigned TargetFlags=0) |
SDValue | getMCSymbol (MCSymbol *Sym,EVT VT) |
SDValue | getValueType (EVT) |
SDValue | getRegister (RegisterReg,EVT VT) |
SDValue | getRegisterMask (constuint32_t *RegMask) |
SDValue | getEHLabel (constSDLoc &dl,SDValue Root,MCSymbol *Label) |
SDValue | getLabelNode (unsigned Opcode,constSDLoc &dl,SDValue Root,MCSymbol *Label) |
SDValue | getBlockAddress (constBlockAddress *BA,EVT VT, int64_tOffset=0,bool isTarget=false,unsigned TargetFlags=0) |
SDValue | getTargetBlockAddress (constBlockAddress *BA,EVT VT, int64_tOffset=0,unsigned TargetFlags=0) |
SDValue | getCopyToReg (SDValue Chain,constSDLoc &dl,RegisterReg,SDValueN) |
SDValue | getCopyToReg (SDValue Chain,constSDLoc &dl,RegisterReg,SDValueN,SDValue Glue) |
SDValue | getCopyToReg (SDValue Chain,constSDLoc &dl,SDValueReg,SDValueN,SDValue Glue) |
SDValue | getCopyFromReg (SDValue Chain,constSDLoc &dl,RegisterReg,EVT VT) |
SDValue | getCopyFromReg (SDValue Chain,constSDLoc &dl,RegisterReg,EVT VT,SDValue Glue) |
SDValue | getCondCode (ISD::CondCodeCond) |
SDValue | getVectorShuffle (EVT VT,constSDLoc &dl,SDValue N1,SDValue N2,ArrayRef< int > Mask) |
Return anISD::VECTOR_SHUFFLE node. | |
SDValue | getBuildVector (EVT VT,constSDLoc &DL,ArrayRef<SDValue > Ops) |
Return anISD::BUILD_VECTOR node. | |
SDValue | getBuildVector (EVT VT,constSDLoc &DL,ArrayRef<SDUse > Ops) |
Return anISD::BUILD_VECTOR node. | |
SDValue | getSplatBuildVector (EVT VT,constSDLoc &DL,SDValueOp) |
Return a splatISD::BUILD_VECTOR node, consisting of Op splatted to all elements. | |
SDValue | getSplatVector (EVT VT,constSDLoc &DL,SDValueOp) |
SDValue | getSplat (EVT VT,constSDLoc &DL,SDValueOp) |
Returns a node representing a splat of one value into all lanes of the provided vector type. | |
SDValue | getStepVector (constSDLoc &DL,EVT ResVT,constAPInt &StepVal) |
Returns a vector of type ResVT whose elements contain the linear sequence <0, Step, Step * 2, Step * 3, ...> | |
SDValue | getStepVector (constSDLoc &DL,EVT ResVT) |
Returns a vector of type ResVT whose elements contain the linear sequence <0, 1, 2, 3, ...> | |
SDValue | getCommutedVectorShuffle (constShuffleVectorSDNode &SV) |
Returns anISD::VECTOR_SHUFFLE node semantically equivalent to the shuffle node in input but with swapped operands. | |
SDValue | getFPExtendOrRound (SDValueOp,constSDLoc &DL,EVT VT) |
Convert Op, which must be of float type, to the float type VT, by either extending or rounding (by truncation). | |
std::pair<SDValue,SDValue > | getStrictFPExtendOrRound (SDValueOp,SDValue Chain,constSDLoc &DL,EVT VT) |
Convert Op, which must be a STRICT operation of float type, to the float type VT, by either extending or rounding (by truncation). | |
SDValue | getAnyExtOrTrunc (SDValueOp,constSDLoc &DL,EVT VT) |
Convert Op, which must be of integer type, to the integer type VT, by either any-extending or truncating it. | |
SDValue | getSExtOrTrunc (SDValueOp,constSDLoc &DL,EVT VT) |
Convert Op, which must be of integer type, to the integer type VT, by either sign-extending or truncating it. | |
SDValue | getZExtOrTrunc (SDValueOp,constSDLoc &DL,EVT VT) |
Convert Op, which must be of integer type, to the integer type VT, by either zero-extending or truncating it. | |
SDValue | getExtOrTrunc (SDValueOp,constSDLoc &DL,EVT VT,unsigned Opcode) |
Convert Op, which must be of integer type, to the integer type VT, by either any/sign/zero-extending (depending on IsAny / IsSigned) or truncating it. | |
SDValue | getExtOrTrunc (bool IsSigned,SDValueOp,constSDLoc &DL,EVT VT) |
Convert Op, which must be of integer type, to the integer type VT, by either sign/zero-extending (depending on IsSigned) or truncating it. | |
SDValue | getBitcastedAnyExtOrTrunc (SDValueOp,constSDLoc &DL,EVT VT) |
Convert Op, which must be of integer type, to the integer type VT, by first bitcasting (from potential vector) to corresponding scalar type then either any-extending or truncating it. | |
SDValue | getBitcastedSExtOrTrunc (SDValueOp,constSDLoc &DL,EVT VT) |
Convert Op, which must be of integer type, to the integer type VT, by first bitcasting (from potential vector) to corresponding scalar type then either sign-extending or truncating it. | |
SDValue | getBitcastedZExtOrTrunc (SDValueOp,constSDLoc &DL,EVT VT) |
Convert Op, which must be of integer type, to the integer type VT, by first bitcasting (from potential vector) to corresponding scalar type then either zero-extending or truncating it. | |
SDValue | getZeroExtendInReg (SDValueOp,constSDLoc &DL,EVT VT) |
Return the expression required to zero extend the Op value assuming it was the smaller SrcTy value. | |
SDValue | getVPZeroExtendInReg (SDValueOp,SDValue Mask,SDValue EVL,constSDLoc &DL,EVT VT) |
Return the expression required to zero extend the Op value assuming it was the smaller SrcTy value. | |
SDValue | getPtrExtOrTrunc (SDValueOp,constSDLoc &DL,EVT VT) |
Convert Op, which must be of integer type, to the integer type VT, by either truncating it or performing either zero or sign extension as appropriate extension for the pointer's semantics. | |
SDValue | getPtrExtendInReg (SDValueOp,constSDLoc &DL,EVT VT) |
Return the expression required to extend the Op as a pointer value assuming it was the smaller SrcTy value. | |
SDValue | getBoolExtOrTrunc (SDValueOp,constSDLoc &SL,EVT VT,EVT OpVT) |
Convert Op, which must be of integer type, to the integer type VT, by using an extension appropriate for the target's BooleanContent for type OpVT or truncating it. | |
SDValue | getNegative (SDValue Val,constSDLoc &DL,EVT VT) |
Create negative operation as (SUB 0, Val). | |
SDValue | getNOT (constSDLoc &DL,SDValue Val,EVT VT) |
Create a bitwise NOT operation as (XOR Val, -1). | |
SDValue | getLogicalNOT (constSDLoc &DL,SDValue Val,EVT VT) |
Create a logical NOT operation as (XOR Val, BooleanOne). | |
SDValue | getVPLogicalNOT (constSDLoc &DL,SDValue Val,SDValue Mask,SDValue EVL,EVT VT) |
Create a vector-predicated logical NOT operation as (VP_XOR Val, BooleanOne, Mask, EVL). | |
SDValue | getVPZExtOrTrunc (constSDLoc &DL,EVT VT,SDValueOp,SDValue Mask,SDValue EVL) |
Convert a vector-predicated Op, which must be an integer vector, to the vector-type VT, by performing either vector-predicated zext or truncating it. | |
SDValue | getVPPtrExtOrTrunc (constSDLoc &DL,EVT VT,SDValueOp,SDValue Mask,SDValue EVL) |
Convert a vector-predicated Op, which must be of integer type, to the vector-type integer type VT, by either truncating it or performing either vector-predicated zero or sign extension as appropriate extension for the pointer's semantics. | |
SDValue | getMemBasePlusOffset (SDValueBase,TypeSizeOffset,constSDLoc &DL,constSDNodeFlags Flags=SDNodeFlags()) |
Returns sum of the base pointer and offset. | |
SDValue | getMemBasePlusOffset (SDValueBase,SDValueOffset,constSDLoc &DL,constSDNodeFlags Flags=SDNodeFlags()) |
SDValue | getObjectPtrOffset (constSDLoc &SL,SDValuePtr,TypeSizeOffset) |
Create an add instruction with appropriate flags when used for addressing some offset of an object. | |
SDValue | getObjectPtrOffset (constSDLoc &SL,SDValuePtr,SDValueOffset) |
SDValue | getCALLSEQ_START (SDValue Chain,uint64_t InSize,uint64_t OutSize,constSDLoc &DL) |
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside CALLSEQ_START..CALLSEQ_END sequence and OutSize specifies part of the frame set up prior to the sequence. | |
SDValue | getCALLSEQ_END (SDValue Chain,SDValue Op1,SDValue Op2,SDValue InGlue,constSDLoc &DL) |
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd). | |
SDValue | getCALLSEQ_END (SDValue Chain,uint64_t Size1,uint64_t Size2,SDValue Glue,constSDLoc &DL) |
bool | isUndef (unsigned Opcode,ArrayRef<SDValue > Ops) |
Return true if the result of this operation is always undefined. | |
SDValue | getUNDEF (EVT VT) |
Return an UNDEF node. UNDEF does not have a usefulSDLoc. | |
SDValue | getVScale (constSDLoc &DL,EVT VT,APInt MulImm,bool ConstantFold=true) |
Return a node that represents the runtime scaling 'MulImm * RuntimeVL'. | |
SDValue | getElementCount (constSDLoc &DL,EVT VT,ElementCount EC,bool ConstantFold=true) |
SDValue | getGLOBAL_OFFSET_TABLE (EVT VT) |
Return a GLOBAL_OFFSET_TABLE node. This does not have a usefulSDLoc. | |
SDValue | getNode (unsigned Opcode,constSDLoc &DL,EVT VT,ArrayRef<SDUse > Ops) |
Gets or creates the specified node. | |
SDValue | getNode (unsigned Opcode,constSDLoc &DL,EVT VT,ArrayRef<SDValue > Ops,constSDNodeFlags Flags) |
SDValue | getNode (unsigned Opcode,constSDLoc &DL,ArrayRef<EVT > ResultTys,ArrayRef<SDValue > Ops) |
SDValue | getNode (unsigned Opcode,constSDLoc &DL,SDVTList VTList,ArrayRef<SDValue > Ops,constSDNodeFlags Flags) |
SDValue | getNode (unsigned Opcode,constSDLoc &DL,EVT VT,ArrayRef<SDValue > Ops) |
SDValue | getNode (unsigned Opcode,constSDLoc &DL,SDVTList VTList,ArrayRef<SDValue > Ops) |
SDValue | getNode (unsigned Opcode,constSDLoc &DL,EVT VT,SDValue Operand) |
SDValue | getNode (unsigned Opcode,constSDLoc &DL,EVT VT,SDValue N1,SDValue N2) |
SDValue | getNode (unsigned Opcode,constSDLoc &DL,EVT VT,SDValue N1,SDValue N2,SDValue N3) |
SDValue | getNode (unsigned Opcode,constSDLoc &DL,EVT VT) |
Gets or creates the specified node. | |
SDValue | getNode (unsigned Opcode,constSDLoc &DL,EVT VT,SDValue Operand,constSDNodeFlags Flags) |
SDValue | getNode (unsigned Opcode,constSDLoc &DL,EVT VT,SDValue N1,SDValue N2,constSDNodeFlags Flags) |
SDValue | getNode (unsigned Opcode,constSDLoc &DL,EVT VT,SDValue N1,SDValue N2,SDValue N3,constSDNodeFlags Flags) |
SDValue | getNode (unsigned Opcode,constSDLoc &DL,EVT VT,SDValue N1,SDValue N2,SDValue N3,SDValue N4) |
SDValue | getNode (unsigned Opcode,constSDLoc &DL,EVT VT,SDValue N1,SDValue N2,SDValue N3,SDValue N4,constSDNodeFlags Flags) |
SDValue | getNode (unsigned Opcode,constSDLoc &DL,EVT VT,SDValue N1,SDValue N2,SDValue N3,SDValue N4,SDValue N5) |
SDValue | getNode (unsigned Opcode,constSDLoc &DL,EVT VT,SDValue N1,SDValue N2,SDValue N3,SDValue N4,SDValue N5,constSDNodeFlags Flags) |
SDValue | getNode (unsigned Opcode,constSDLoc &DL,SDVTList VTList) |
SDValue | getNode (unsigned Opcode,constSDLoc &DL,SDVTList VTList,SDValueN) |
SDValue | getNode (unsigned Opcode,constSDLoc &DL,SDVTList VTList,SDValue N1,SDValue N2) |
SDValue | getNode (unsigned Opcode,constSDLoc &DL,SDVTList VTList,SDValue N1,SDValue N2,SDValue N3) |
SDValue | getNode (unsigned Opcode,constSDLoc &DL,SDVTList VTList,SDValue N1,SDValue N2,SDValue N3,SDValue N4) |
SDValue | getNode (unsigned Opcode,constSDLoc &DL,SDVTList VTList,SDValue N1,SDValue N2,SDValue N3,SDValue N4,SDValue N5) |
SDValue | getStackArgumentTokenFactor (SDValue Chain) |
Compute a TokenFactor to force all the incoming stack arguments to be loaded from the stack. | |
SDValue | getMemcpy (SDValue Chain,constSDLoc &dl,SDValue Dst,SDValue Src,SDValueSize,Align Alignment,bool isVol,bool AlwaysInline,constCallInst *CI, std::optional<bool > OverrideTailCall,MachinePointerInfo DstPtrInfo,MachinePointerInfo SrcPtrInfo,constAAMDNodes &AAInfo=AAMDNodes(),BatchAAResults *BatchAA=nullptr) |
SDValue | getMemmove (SDValue Chain,constSDLoc &dl,SDValue Dst,SDValue Src,SDValueSize,Align Alignment,bool isVol,constCallInst *CI, std::optional<bool > OverrideTailCall,MachinePointerInfo DstPtrInfo,MachinePointerInfo SrcPtrInfo,constAAMDNodes &AAInfo=AAMDNodes(),BatchAAResults *BatchAA=nullptr) |
SDValue | getMemset (SDValue Chain,constSDLoc &dl,SDValue Dst,SDValue Src,SDValueSize,Align Alignment,bool isVol,bool AlwaysInline,constCallInst *CI,MachinePointerInfo DstPtrInfo,constAAMDNodes &AAInfo=AAMDNodes()) |
SDValue | getAtomicMemcpy (SDValue Chain,constSDLoc &dl,SDValue Dst,SDValue Src,SDValueSize,Type *SizeTy,unsigned ElemSz,bool isTailCall,MachinePointerInfo DstPtrInfo,MachinePointerInfo SrcPtrInfo) |
SDValue | getAtomicMemmove (SDValue Chain,constSDLoc &dl,SDValue Dst,SDValue Src,SDValueSize,Type *SizeTy,unsigned ElemSz,bool isTailCall,MachinePointerInfo DstPtrInfo,MachinePointerInfo SrcPtrInfo) |
SDValue | getAtomicMemset (SDValue Chain,constSDLoc &dl,SDValue Dst,SDValueValue,SDValueSize,Type *SizeTy,unsigned ElemSz,bool isTailCall,MachinePointerInfo DstPtrInfo) |
SDValue | getSetCC (constSDLoc &DL,EVT VT,SDValueLHS,SDValueRHS,ISD::CondCodeCond,SDValue Chain=SDValue(),bool IsSignaling=false) |
Helper function to make it easier to build SetCC's if you just have anISD::CondCode instead of anSDValue. | |
SDValue | getSetCCVP (constSDLoc &DL,EVT VT,SDValueLHS,SDValueRHS,ISD::CondCodeCond,SDValue Mask,SDValue EVL) |
Helper function to make it easier to build VP_SETCCs if you just have anISD::CondCode instead of anSDValue. | |
SDValue | getSelect (constSDLoc &DL,EVT VT,SDValueCond,SDValueLHS,SDValueRHS,SDNodeFlags Flags=SDNodeFlags()) |
Helper function to make it easier to build Select's if you just have operands and don't want to check for vector. | |
SDValue | getSelectCC (constSDLoc &DL,SDValueLHS,SDValueRHS,SDValue True,SDValue False,ISD::CondCodeCond) |
Helper function to make it easier to build SelectCC's if you just have anISD::CondCode instead of anSDValue. | |
SDValue | simplifySelect (SDValueCond,SDValue TVal,SDValue FVal) |
Try to simplify a select/vselect into 1 of its operands or a constant. | |
SDValue | simplifyShift (SDValueX,SDValueY) |
Try to simplify a shift into 1 of its operands or a constant. | |
SDValue | simplifyFPBinop (unsigned Opcode,SDValueX,SDValueY,SDNodeFlags Flags) |
Try to simplify a floating-point binary operation into 1 of its operands or a constant. | |
SDValue | getVAArg (EVT VT,constSDLoc &dl,SDValue Chain,SDValuePtr,SDValue SV,unsignedAlign) |
VAArg produces a result and token chain, and takes a pointer and a source value as input. | |
SDValue | getAtomicCmpSwap (unsigned Opcode,constSDLoc &dl,EVT MemVT,SDVTList VTs,SDValue Chain,SDValuePtr,SDValue Cmp,SDValue Swp,MachineMemOperand *MMO) |
Gets a node for an atomic cmpxchg op. | |
SDValue | getAtomic (unsigned Opcode,constSDLoc &dl,EVT MemVT,SDValue Chain,SDValuePtr,SDValue Val,MachineMemOperand *MMO) |
Gets a node for an atomic op, produces result (if relevant) and chain and takes 2 operands. | |
SDValue | getAtomic (unsigned Opcode,constSDLoc &dl,EVT MemVT,EVT VT,SDValue Chain,SDValuePtr,MachineMemOperand *MMO) |
Gets a node for an atomic op, produces result and chain and takes 1 operand. | |
SDValue | getAtomic (unsigned Opcode,constSDLoc &dl,EVT MemVT,SDVTList VTList,ArrayRef<SDValue > Ops,MachineMemOperand *MMO) |
Gets a node for an atomic op, produces result and chain and takes N operands. | |
SDValue | getMemIntrinsicNode (unsigned Opcode,constSDLoc &dl,SDVTList VTList,ArrayRef<SDValue > Ops,EVT MemVT,MachinePointerInfo PtrInfo,Align Alignment,MachineMemOperand::Flags Flags=MachineMemOperand::MOLoad|MachineMemOperand::MOStore,LocationSizeSize=0,constAAMDNodes &AAInfo=AAMDNodes()) |
Creates a MemIntrinsicNode that may produce a result and takes a list of operands. | |
SDValue | getMemIntrinsicNode (unsigned Opcode,constSDLoc &dl,SDVTList VTList,ArrayRef<SDValue > Ops,EVT MemVT,MachinePointerInfo PtrInfo,MaybeAlign Alignment=std::nullopt,MachineMemOperand::Flags Flags=MachineMemOperand::MOLoad|MachineMemOperand::MOStore,LocationSizeSize=0,constAAMDNodes &AAInfo=AAMDNodes()) |
SDValue | getMemIntrinsicNode (unsigned Opcode,constSDLoc &dl,SDVTList VTList,ArrayRef<SDValue > Ops,EVT MemVT,MachineMemOperand *MMO) |
SDValue | getLifetimeNode (bool IsStart,constSDLoc &dl,SDValue Chain, int FrameIndex, int64_tSize, int64_tOffset=-1) |
Creates aLifetimeSDNode that starts (IsStart==true ) or ends (IsStart==false ) the lifetime of the portion ofFrameIndex between offsetsOffset andOffset + Size . | |
SDValue | getPseudoProbeNode (constSDLoc &Dl,SDValue Chain,uint64_tGuid,uint64_tIndex,uint32_t Attr) |
Creates aPseudoProbeSDNode with function GUIDGuid and the index of the blockIndex it is probing, as well as the attributesattr of the probe. | |
SDValue | getMergeValues (ArrayRef<SDValue > Ops,constSDLoc &dl) |
Create a MERGE_VALUES node from the given operands. | |
SDValue | getLoad (EVT VT,constSDLoc &dl,SDValue Chain,SDValuePtr,MachinePointerInfo PtrInfo,MaybeAlign Alignment=MaybeAlign(),MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone,constAAMDNodes &AAInfo=AAMDNodes(),constMDNode *Ranges=nullptr) |
Loads are not normal binary operators: their result type is not determined by their operands, and they produce a value AND a token chain. | |
SDValue | getLoad (EVT VT,constSDLoc &dl,SDValue Chain,SDValuePtr,MachineMemOperand *MMO) |
SDValue | getExtLoad (ISD::LoadExtType ExtType,constSDLoc &dl,EVT VT,SDValue Chain,SDValuePtr,MachinePointerInfo PtrInfo,EVT MemVT,MaybeAlign Alignment=MaybeAlign(),MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone,constAAMDNodes &AAInfo=AAMDNodes()) |
SDValue | getExtLoad (ISD::LoadExtType ExtType,constSDLoc &dl,EVT VT,SDValue Chain,SDValuePtr,EVT MemVT,MachineMemOperand *MMO) |
SDValue | getIndexedLoad (SDValue OrigLoad,constSDLoc &dl,SDValueBase,SDValueOffset,ISD::MemIndexedMode AM) |
SDValue | getLoad (ISD::MemIndexedMode AM,ISD::LoadExtType ExtType,EVT VT,constSDLoc &dl,SDValue Chain,SDValuePtr,SDValueOffset,MachinePointerInfo PtrInfo,EVT MemVT,Align Alignment,MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone,constAAMDNodes &AAInfo=AAMDNodes(),constMDNode *Ranges=nullptr) |
SDValue | getLoad (ISD::MemIndexedMode AM,ISD::LoadExtType ExtType,EVT VT,constSDLoc &dl,SDValue Chain,SDValuePtr,SDValueOffset,MachinePointerInfo PtrInfo,EVT MemVT,MaybeAlign Alignment=MaybeAlign(),MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone,constAAMDNodes &AAInfo=AAMDNodes(),constMDNode *Ranges=nullptr) |
SDValue | getLoad (ISD::MemIndexedMode AM,ISD::LoadExtType ExtType,EVT VT,constSDLoc &dl,SDValue Chain,SDValuePtr,SDValueOffset,EVT MemVT,MachineMemOperand *MMO) |
SDValue | getStore (SDValue Chain,constSDLoc &dl,SDValue Val,SDValuePtr,MachinePointerInfo PtrInfo,Align Alignment,MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone,constAAMDNodes &AAInfo=AAMDNodes()) |
Helper function to buildISD::STORE nodes. | |
SDValue | getStore (SDValue Chain,constSDLoc &dl,SDValue Val,SDValuePtr,MachinePointerInfo PtrInfo,MaybeAlign Alignment=MaybeAlign(),MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone,constAAMDNodes &AAInfo=AAMDNodes()) |
SDValue | getStore (SDValue Chain,constSDLoc &dl,SDValue Val,SDValuePtr,MachineMemOperand *MMO) |
SDValue | getTruncStore (SDValue Chain,constSDLoc &dl,SDValue Val,SDValuePtr,MachinePointerInfo PtrInfo,EVT SVT,Align Alignment,MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone,constAAMDNodes &AAInfo=AAMDNodes()) |
SDValue | getTruncStore (SDValue Chain,constSDLoc &dl,SDValue Val,SDValuePtr,MachinePointerInfo PtrInfo,EVT SVT,MaybeAlign Alignment=MaybeAlign(),MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone,constAAMDNodes &AAInfo=AAMDNodes()) |
SDValue | getTruncStore (SDValue Chain,constSDLoc &dl,SDValue Val,SDValuePtr,EVT SVT,MachineMemOperand *MMO) |
SDValue | getIndexedStore (SDValue OrigStore,constSDLoc &dl,SDValueBase,SDValueOffset,ISD::MemIndexedMode AM) |
SDValue | getLoadVP (ISD::MemIndexedMode AM,ISD::LoadExtType ExtType,EVT VT,constSDLoc &dl,SDValue Chain,SDValuePtr,SDValueOffset,SDValue Mask,SDValue EVL,MachinePointerInfo PtrInfo,EVT MemVT,Align Alignment,MachineMemOperand::Flags MMOFlags,constAAMDNodes &AAInfo,constMDNode *Ranges=nullptr,bool IsExpanding=false) |
SDValue | getLoadVP (ISD::MemIndexedMode AM,ISD::LoadExtType ExtType,EVT VT,constSDLoc &dl,SDValue Chain,SDValuePtr,SDValueOffset,SDValue Mask,SDValue EVL,MachinePointerInfo PtrInfo,EVT MemVT,MaybeAlign Alignment=MaybeAlign(),MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone,constAAMDNodes &AAInfo=AAMDNodes(),constMDNode *Ranges=nullptr,bool IsExpanding=false) |
SDValue | getLoadVP (ISD::MemIndexedMode AM,ISD::LoadExtType ExtType,EVT VT,constSDLoc &dl,SDValue Chain,SDValuePtr,SDValueOffset,SDValue Mask,SDValue EVL,EVT MemVT,MachineMemOperand *MMO,bool IsExpanding=false) |
SDValue | getLoadVP (EVT VT,constSDLoc &dl,SDValue Chain,SDValuePtr,SDValue Mask,SDValue EVL,MachinePointerInfo PtrInfo,MaybeAlign Alignment,MachineMemOperand::Flags MMOFlags,constAAMDNodes &AAInfo,constMDNode *Ranges=nullptr,bool IsExpanding=false) |
SDValue | getLoadVP (EVT VT,constSDLoc &dl,SDValue Chain,SDValuePtr,SDValue Mask,SDValue EVL,MachineMemOperand *MMO,bool IsExpanding=false) |
SDValue | getExtLoadVP (ISD::LoadExtType ExtType,constSDLoc &dl,EVT VT,SDValue Chain,SDValuePtr,SDValue Mask,SDValue EVL,MachinePointerInfo PtrInfo,EVT MemVT,MaybeAlign Alignment,MachineMemOperand::Flags MMOFlags,constAAMDNodes &AAInfo,bool IsExpanding=false) |
SDValue | getExtLoadVP (ISD::LoadExtType ExtType,constSDLoc &dl,EVT VT,SDValue Chain,SDValuePtr,SDValue Mask,SDValue EVL,EVT MemVT,MachineMemOperand *MMO,bool IsExpanding=false) |
SDValue | getIndexedLoadVP (SDValue OrigLoad,constSDLoc &dl,SDValueBase,SDValueOffset,ISD::MemIndexedMode AM) |
SDValue | getStoreVP (SDValue Chain,constSDLoc &dl,SDValue Val,SDValuePtr,SDValueOffset,SDValue Mask,SDValue EVL,EVT MemVT,MachineMemOperand *MMO,ISD::MemIndexedMode AM,bool IsTruncating=false,bool IsCompressing=false) |
SDValue | getTruncStoreVP (SDValue Chain,constSDLoc &dl,SDValue Val,SDValuePtr,SDValue Mask,SDValue EVL,MachinePointerInfo PtrInfo,EVT SVT,Align Alignment,MachineMemOperand::Flags MMOFlags,constAAMDNodes &AAInfo,bool IsCompressing=false) |
SDValue | getTruncStoreVP (SDValue Chain,constSDLoc &dl,SDValue Val,SDValuePtr,SDValue Mask,SDValue EVL,EVT SVT,MachineMemOperand *MMO,bool IsCompressing=false) |
SDValue | getIndexedStoreVP (SDValue OrigStore,constSDLoc &dl,SDValueBase,SDValueOffset,ISD::MemIndexedMode AM) |
SDValue | getStridedLoadVP (ISD::MemIndexedMode AM,ISD::LoadExtType ExtType,EVT VT,constSDLoc &DL,SDValue Chain,SDValuePtr,SDValueOffset,SDValue Stride,SDValue Mask,SDValue EVL,EVT MemVT,MachineMemOperand *MMO,bool IsExpanding=false) |
SDValue | getStridedLoadVP (EVT VT,constSDLoc &DL,SDValue Chain,SDValuePtr,SDValue Stride,SDValue Mask,SDValue EVL,MachineMemOperand *MMO,bool IsExpanding=false) |
SDValue | getExtStridedLoadVP (ISD::LoadExtType ExtType,constSDLoc &DL,EVT VT,SDValue Chain,SDValuePtr,SDValue Stride,SDValue Mask,SDValue EVL,EVT MemVT,MachineMemOperand *MMO,bool IsExpanding=false) |
SDValue | getStridedStoreVP (SDValue Chain,constSDLoc &DL,SDValue Val,SDValuePtr,SDValueOffset,SDValue Stride,SDValue Mask,SDValue EVL,EVT MemVT,MachineMemOperand *MMO,ISD::MemIndexedMode AM,bool IsTruncating=false,bool IsCompressing=false) |
SDValue | getTruncStridedStoreVP (SDValue Chain,constSDLoc &DL,SDValue Val,SDValuePtr,SDValue Stride,SDValue Mask,SDValue EVL,EVT SVT,MachineMemOperand *MMO,bool IsCompressing=false) |
SDValue | getGatherVP (SDVTList VTs,EVT VT,constSDLoc &dl,ArrayRef<SDValue > Ops,MachineMemOperand *MMO,ISD::MemIndexType IndexType) |
SDValue | getScatterVP (SDVTList VTs,EVT VT,constSDLoc &dl,ArrayRef<SDValue > Ops,MachineMemOperand *MMO,ISD::MemIndexType IndexType) |
SDValue | getMaskedLoad (EVT VT,constSDLoc &dl,SDValue Chain,SDValueBase,SDValueOffset,SDValue Mask,SDValue Src0,EVT MemVT,MachineMemOperand *MMO,ISD::MemIndexedMode AM,ISD::LoadExtType,bool IsExpanding=false) |
SDValue | getIndexedMaskedLoad (SDValue OrigLoad,constSDLoc &dl,SDValueBase,SDValueOffset,ISD::MemIndexedMode AM) |
SDValue | getMaskedStore (SDValue Chain,constSDLoc &dl,SDValue Val,SDValueBase,SDValueOffset,SDValue Mask,EVT MemVT,MachineMemOperand *MMO,ISD::MemIndexedMode AM,bool IsTruncating=false,bool IsCompressing=false) |
SDValue | getIndexedMaskedStore (SDValue OrigStore,constSDLoc &dl,SDValueBase,SDValueOffset,ISD::MemIndexedMode AM) |
SDValue | getMaskedGather (SDVTList VTs,EVT MemVT,constSDLoc &dl,ArrayRef<SDValue > Ops,MachineMemOperand *MMO,ISD::MemIndexType IndexType,ISD::LoadExtType ExtTy) |
SDValue | getMaskedScatter (SDVTList VTs,EVT MemVT,constSDLoc &dl,ArrayRef<SDValue > Ops,MachineMemOperand *MMO,ISD::MemIndexType IndexType,bool IsTruncating=false) |
SDValue | getMaskedHistogram (SDVTList VTs,EVT MemVT,constSDLoc &dl,ArrayRef<SDValue > Ops,MachineMemOperand *MMO,ISD::MemIndexType IndexType) |
SDValue | getGetFPEnv (SDValue Chain,constSDLoc &dl,SDValuePtr,EVT MemVT,MachineMemOperand *MMO) |
SDValue | getSetFPEnv (SDValue Chain,constSDLoc &dl,SDValuePtr,EVT MemVT,MachineMemOperand *MMO) |
SDValue | getSrcValue (constValue *v) |
Construct a node to track a Value* through the backend. | |
SDValue | getMDNode (constMDNode *MD) |
Return anMDNodeSDNode which holds anMDNode. | |
SDValue | getBitcast (EVT VT,SDValue V) |
Return a bitcast using theSDLoc of the value operand, and casting to the provided type. | |
SDValue | getAddrSpaceCast (constSDLoc &dl,EVT VT,SDValuePtr,unsigned SrcAS,unsigned DestAS) |
Return anAddrSpaceCastSDNode. | |
SDValue | getFreeze (SDValue V) |
Return a freeze using theSDLoc of the value operand. | |
SDValue | getAssertAlign (constSDLoc &DL,SDValue V,AlignA) |
Return anAssertAlignSDNode. | |
void | canonicalizeCommutativeBinop (unsigned Opcode,SDValue &N1,SDValue &N2)const |
Swap N1 and N2 if Opcode is a commutative binary opcode and the canonical form expects the opposite order. | |
SDValue | getShiftAmountOperand (EVT LHSTy,SDValueOp) |
Return the specified value casted to the target's desired shift amount type. | |
SDValue | getPartialReduceAdd (SDLocDL,EVT ReducedTy,SDValue Op1,SDValue Op2) |
Create the DAG equivalent of vector_partial_reduce where Op1 and Op2 are its operands and ReducedTY is the intrinsic's return type. | |
bool | expandMultipleResultFPLibCall (RTLIB::Libcall LC,SDNode *Node,SmallVectorImpl<SDValue > &Results, std::optional<unsigned > CallRetResNo={}) |
Expands a node with multiple results to an FP or vector libcall. | |
SDValue | expandVAArg (SDNode *Node) |
Expand the specifiedISD::VAARG node as the Legalize pass would. | |
SDValue | expandVACopy (SDNode *Node) |
Expand the specifiedISD::VACOPY node as the Legalize pass would. | |
SDValue | getSymbolFunctionGlobalAddress (SDValueOp,Function **TargetFunction=nullptr) |
Return a GlobalAddress of the function from the current module with name matching the given ExternalSymbol. | |
SDNode * | UpdateNodeOperands (SDNode *N,SDValueOp) |
Mutate the specified node in-place to have the specified operands. | |
SDNode * | UpdateNodeOperands (SDNode *N,SDValue Op1,SDValue Op2) |
SDNode * | UpdateNodeOperands (SDNode *N,SDValue Op1,SDValue Op2,SDValue Op3) |
SDNode * | UpdateNodeOperands (SDNode *N,SDValue Op1,SDValue Op2,SDValue Op3,SDValue Op4) |
SDNode * | UpdateNodeOperands (SDNode *N,SDValue Op1,SDValue Op2,SDValue Op3,SDValue Op4,SDValue Op5) |
SDNode * | UpdateNodeOperands (SDNode *N,ArrayRef<SDValue > Ops) |
SDValue | getTokenFactor (constSDLoc &DL,SmallVectorImpl<SDValue > &Vals) |
Creates a new TokenFactor containingVals . | |
void | setNodeMemRefs (MachineSDNode *N,ArrayRef<MachineMemOperand * > NewMemRefs) |
Mutate the specified machine node's memory references to the provided list. | |
bool | calculateDivergence (SDNode *N) |
void | updateDivergence (SDNode *N) |
SDNode * | SelectNodeTo (SDNode *N,unsigned MachineOpc,EVT VT) |
These are used for target selectors tomutate the specified node to have the specified return type,Target opcode, and operands. | |
SDNode * | SelectNodeTo (SDNode *N,unsigned MachineOpc,EVT VT,SDValue Op1) |
SDNode * | SelectNodeTo (SDNode *N,unsigned MachineOpc,EVT VT,SDValue Op1,SDValue Op2) |
SDNode * | SelectNodeTo (SDNode *N,unsigned MachineOpc,EVT VT,SDValue Op1,SDValue Op2,SDValue Op3) |
SDNode * | SelectNodeTo (SDNode *N,unsigned MachineOpc,EVT VT,ArrayRef<SDValue > Ops) |
SDNode * | SelectNodeTo (SDNode *N,unsigned MachineOpc,EVT VT1,EVT VT2) |
SDNode * | SelectNodeTo (SDNode *N,unsigned MachineOpc,EVT VT1,EVT VT2,ArrayRef<SDValue > Ops) |
SDNode * | SelectNodeTo (SDNode *N,unsigned MachineOpc,EVT VT1,EVT VT2,EVT VT3,ArrayRef<SDValue > Ops) |
SDNode * | SelectNodeTo (SDNode *N,unsigned MachineOpc,EVT VT1,EVT VT2,SDValue Op1,SDValue Op2) |
SDNode * | SelectNodeTo (SDNode *N,unsigned MachineOpc,SDVTList VTs,ArrayRef<SDValue > Ops) |
SDNode * | MorphNodeTo (SDNode *N,unsigned Opc,SDVTList VTs,ArrayRef<SDValue > Ops) |
Thismutates the specified node to have the specified return type, opcode, and operands. | |
SDNode * | mutateStrictFPToFP (SDNode *Node) |
Mutate the specified strict FP node to its non-strict equivalent, unlinking the node from its chain and dropping the metadata arguments. | |
MachineSDNode * | getMachineNode (unsigned Opcode,constSDLoc &dl,EVT VT) |
These are used for target selectors to create a new node with specified return type(s),MachineInstr opcode, and operands. | |
MachineSDNode * | getMachineNode (unsigned Opcode,constSDLoc &dl,EVT VT,SDValue Op1) |
MachineSDNode * | getMachineNode (unsigned Opcode,constSDLoc &dl,EVT VT,SDValue Op1,SDValue Op2) |
MachineSDNode * | getMachineNode (unsigned Opcode,constSDLoc &dl,EVT VT,SDValue Op1,SDValue Op2,SDValue Op3) |
MachineSDNode * | getMachineNode (unsigned Opcode,constSDLoc &dl,EVT VT,ArrayRef<SDValue > Ops) |
MachineSDNode * | getMachineNode (unsigned Opcode,constSDLoc &dl,EVT VT1,EVT VT2,SDValue Op1,SDValue Op2) |
MachineSDNode * | getMachineNode (unsigned Opcode,constSDLoc &dl,EVT VT1,EVT VT2,SDValue Op1,SDValue Op2,SDValue Op3) |
MachineSDNode * | getMachineNode (unsigned Opcode,constSDLoc &dl,EVT VT1,EVT VT2,ArrayRef<SDValue > Ops) |
MachineSDNode * | getMachineNode (unsigned Opcode,constSDLoc &dl,EVT VT1,EVT VT2,EVT VT3,SDValue Op1,SDValue Op2) |
MachineSDNode * | getMachineNode (unsigned Opcode,constSDLoc &dl,EVT VT1,EVT VT2,EVT VT3,SDValue Op1,SDValue Op2,SDValue Op3) |
MachineSDNode * | getMachineNode (unsigned Opcode,constSDLoc &dl,EVT VT1,EVT VT2,EVT VT3,ArrayRef<SDValue > Ops) |
MachineSDNode * | getMachineNode (unsigned Opcode,constSDLoc &dl,ArrayRef<EVT > ResultTys,ArrayRef<SDValue > Ops) |
MachineSDNode * | getMachineNode (unsigned Opcode,constSDLoc &dl,SDVTList VTs,ArrayRef<SDValue > Ops) |
SDValue | getTargetExtractSubreg (int SRIdx,constSDLoc &DL,EVT VT,SDValue Operand) |
A convenience function for creating TargetInstrInfo::EXTRACT_SUBREG nodes. | |
SDValue | getTargetInsertSubreg (int SRIdx,constSDLoc &DL,EVT VT,SDValue Operand,SDValue Subreg) |
A convenience function for creating TargetInstrInfo::INSERT_SUBREG nodes. | |
SDNode * | getNodeIfExists (unsigned Opcode,SDVTList VTList,ArrayRef<SDValue > Ops,constSDNodeFlags Flags) |
Get the specified node if it's already available, or else return NULL. | |
SDNode * | getNodeIfExists (unsigned Opcode,SDVTList VTList,ArrayRef<SDValue > Ops) |
getNodeIfExists - Get the specified node if it's already available, or else return NULL. | |
bool | doesNodeExist (unsigned Opcode,SDVTList VTList,ArrayRef<SDValue > Ops) |
Check if a node exists without modifying its flags. | |
SDDbgValue * | getDbgValue (DIVariable *Var,DIExpression *Expr,SDNode *N,unsigned R,bool IsIndirect,constDebugLoc &DL,unsigned O) |
Creates aSDDbgValue node. | |
SDDbgValue * | getConstantDbgValue (DIVariable *Var,DIExpression *Expr,constValue *C,constDebugLoc &DL,unsigned O) |
Creates a constantSDDbgValue node. | |
SDDbgValue * | getFrameIndexDbgValue (DIVariable *Var,DIExpression *Expr,unsigned FI,bool IsIndirect,constDebugLoc &DL,unsigned O) |
Creates a FrameIndexSDDbgValue node. | |
SDDbgValue * | getFrameIndexDbgValue (DIVariable *Var,DIExpression *Expr,unsigned FI,ArrayRef<SDNode * > Dependencies,bool IsIndirect,constDebugLoc &DL,unsigned O) |
Creates a FrameIndexSDDbgValue node. | |
SDDbgValue * | getVRegDbgValue (DIVariable *Var,DIExpression *Expr,unsigned VReg,bool IsIndirect,constDebugLoc &DL,unsigned O) |
Creates a VRegSDDbgValue node. | |
SDDbgValue * | getDbgValueList (DIVariable *Var,DIExpression *Expr,ArrayRef<SDDbgOperand > Locs,ArrayRef<SDNode * > Dependencies,bool IsIndirect,constDebugLoc &DL,unsigned O,bool IsVariadic) |
Creates aSDDbgValue node from a list of locations. | |
SDDbgLabel * | getDbgLabel (DILabel *Label,constDebugLoc &DL,unsigned O) |
Creates aSDDbgLabel node. | |
void | transferDbgValues (SDValueFrom,SDValue To,unsigned OffsetInBits=0,unsigned SizeInBits=0,bool InvalidateDbg=true) |
Transfer debug values from one node to another, while optionally generating fragment expressions for split-up values. | |
void | RemoveDeadNode (SDNode *N) |
Remove the specified node from the system. | |
void | RemoveDeadNodes (SmallVectorImpl<SDNode * > &DeadNodes) |
This method deletes the unreachable nodes in the given list, and any nodes that become unreachable as a result. | |
void | ReplaceAllUsesWith (SDValueFrom,SDValue To) |
Modify anything using 'From' to use 'To' instead. | |
void | ReplaceAllUsesWith (SDNode *From,SDNode *To) |
ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. | |
void | ReplaceAllUsesWith (SDNode *From,constSDValue *To) |
ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. | |
void | ReplaceAllUsesOfValueWith (SDValueFrom,SDValue To) |
Replace any uses of From with To, leaving uses of other values produced by From.getNode() alone. | |
void | ReplaceAllUsesOfValuesWith (constSDValue *From,constSDValue *To,unsigned Num) |
Like ReplaceAllUsesOfValueWith, but for multiple values at once. | |
SDValue | makeEquivalentMemoryOrdering (SDValue OldChain,SDValue NewMemOpChain) |
If an existing load has uses of its chain, create a token factor node with that chain and the new memory node's chain and update users of the old chain to the token factor. | |
SDValue | makeEquivalentMemoryOrdering (LoadSDNode *OldLoad,SDValue NewMemOp) |
If an existing load has uses of its chain, create a token factor node with that chain and the new memory node's chain and update users of the old chain to the token factor. | |
unsigned | AssignTopologicalOrder () |
Topological-sort the AllNodes list and a assign a unique node id for each node in the DAG based on their topological order. | |
void | RepositionNode (allnodes_iterator Position,SDNode *N) |
Move node N in the AllNodes list to be immediately before the given iterator Position. | |
void | AddDbgValue (SDDbgValue *DB,bool isParameter) |
Add a dbg_valueSDNode. | |
void | AddDbgLabel (SDDbgLabel *DB) |
Add a dbg_labelSDNode. | |
ArrayRef<SDDbgValue * > | GetDbgValues (constSDNode *SD)const |
Get the debug values which reference the givenSDNode. | |
bool | hasDebugValues ()const |
Return true if there are anySDDbgValue nodes associated with thisSelectionDAG. | |
SDDbgInfo::DbgIterator | DbgBegin ()const |
SDDbgInfo::DbgIterator | DbgEnd ()const |
SDDbgInfo::DbgIterator | ByvalParmDbgBegin ()const |
SDDbgInfo::DbgIterator | ByvalParmDbgEnd ()const |
SDDbgInfo::DbgLabelIterator | DbgLabelBegin ()const |
SDDbgInfo::DbgLabelIterator | DbgLabelEnd ()const |
void | salvageDebugInfo (SDNode &N) |
To be invoked on anSDNode that is slated to be erased. | |
void | dump ()const |
Align | getReducedAlign (EVT VT,bool UseABI) |
In most cases this function returns the ABI alignment for a given type, except for illegal vector types where the alignment exceeds that of the stack. | |
SDValue | CreateStackTemporary (TypeSize Bytes,Align Alignment) |
Create a stack temporary based on the size in bytes and the alignment. | |
SDValue | CreateStackTemporary (EVT VT,unsigned minAlign=1) |
Create a stack temporary, suitable for holding the specified value type. | |
SDValue | CreateStackTemporary (EVT VT1,EVT VT2) |
Create a stack temporary suitable for holding either of the specified value types. | |
SDValue | FoldSymbolOffset (unsigned Opcode,EVT VT,constGlobalAddressSDNode *GA,constSDNode *N2) |
SDValue | FoldConstantArithmetic (unsigned Opcode,constSDLoc &DL,EVT VT,ArrayRef<SDValue > Ops,SDNodeFlags Flags=SDNodeFlags()) |
SDValue | foldConstantFPMath (unsigned Opcode,constSDLoc &DL,EVT VT,ArrayRef<SDValue > Ops) |
Fold floating-point operations when all operands are constants and/or undefined. | |
SDValue | FoldSetCC (EVT VT,SDValue N1,SDValue N2,ISD::CondCodeCond,constSDLoc &dl) |
Constant fold a setcc to true or false. | |
bool | SignBitIsZero (SDValueOp,unsignedDepth=0)const |
Return true if the sign bit of Op is known to be zero. | |
bool | MaskedValueIsZero (SDValueOp,constAPInt &Mask,unsignedDepth=0)const |
Return true if 'Op & Mask' is known to be zero. | |
bool | MaskedValueIsZero (SDValueOp,constAPInt &Mask,constAPInt &DemandedElts,unsignedDepth=0)const |
Return true if 'Op & Mask' is known to be zero in DemandedElts. | |
bool | MaskedVectorIsZero (SDValueOp,constAPInt &DemandedElts,unsignedDepth=0)const |
Return true if 'Op' is known to be zero in DemandedElts. | |
bool | MaskedValueIsAllOnes (SDValueOp,constAPInt &Mask,unsignedDepth=0)const |
Return true if '(Op & Mask) == Mask'. | |
APInt | computeVectorKnownZeroElements (SDValueOp,constAPInt &DemandedElts,unsignedDepth=0)const |
For each demanded element of a vector, see if it is known to be zero. | |
KnownBits | computeKnownBits (SDValueOp,unsignedDepth=0)const |
Determine which bits of Op are known to be either zero or one and return them in Known. | |
KnownBits | computeKnownBits (SDValueOp,constAPInt &DemandedElts,unsignedDepth=0)const |
Determine which bits of Op are known to be either zero or one and return them in Known. | |
OverflowKind | computeOverflowForSignedAdd (SDValue N0,SDValue N1)const |
Determine if the result of the signed addition of 2 nodes can overflow. | |
OverflowKind | computeOverflowForUnsignedAdd (SDValue N0,SDValue N1)const |
Determine if the result of the unsigned addition of 2 nodes can overflow. | |
OverflowKind | computeOverflowForAdd (bool IsSigned,SDValue N0,SDValue N1)const |
Determine if the result of the addition of 2 nodes can overflow. | |
bool | willNotOverflowAdd (bool IsSigned,SDValue N0,SDValue N1)const |
Determine if the result of the addition of 2 nodes can never overflow. | |
OverflowKind | computeOverflowForSignedSub (SDValue N0,SDValue N1)const |
Determine if the result of the signed sub of 2 nodes can overflow. | |
OverflowKind | computeOverflowForUnsignedSub (SDValue N0,SDValue N1)const |
Determine if the result of the unsigned sub of 2 nodes can overflow. | |
OverflowKind | computeOverflowForSub (bool IsSigned,SDValue N0,SDValue N1)const |
Determine if the result of the sub of 2 nodes can overflow. | |
bool | willNotOverflowSub (bool IsSigned,SDValue N0,SDValue N1)const |
Determine if the result of the sub of 2 nodes can never overflow. | |
OverflowKind | computeOverflowForSignedMul (SDValue N0,SDValue N1)const |
Determine if the result of the signed mul of 2 nodes can overflow. | |
OverflowKind | computeOverflowForUnsignedMul (SDValue N0,SDValue N1)const |
Determine if the result of the unsigned mul of 2 nodes can overflow. | |
OverflowKind | computeOverflowForMul (bool IsSigned,SDValue N0,SDValue N1)const |
Determine if the result of the mul of 2 nodes can overflow. | |
bool | willNotOverflowMul (bool IsSigned,SDValue N0,SDValue N1)const |
Determine if the result of the mul of 2 nodes can never overflow. | |
bool | isKnownToBeAPowerOfTwo (SDValue Val,unsignedDepth=0)const |
Test if the given value is known to have exactly one bit set. | |
bool | isKnownToBeAPowerOfTwoFP (SDValue Val,unsignedDepth=0)const |
Test if the givenfp value is known to be an integer power-of-2, either positive or negative. | |
unsigned | ComputeNumSignBits (SDValueOp,unsignedDepth=0)const |
Return the number of times the sign bit of the register is replicated into the other bits. | |
unsigned | ComputeNumSignBits (SDValueOp,constAPInt &DemandedElts,unsignedDepth=0)const |
Return the number of times the sign bit of the register is replicated into the other bits. | |
unsigned | ComputeMaxSignificantBits (SDValueOp,unsignedDepth=0)const |
Get the upper bound on bit size for thisValueOp as a signed integer. | |
unsigned | ComputeMaxSignificantBits (SDValueOp,constAPInt &DemandedElts,unsignedDepth=0)const |
Get the upper bound on bit size for thisValueOp as a signed integer. | |
bool | isGuaranteedNotToBeUndefOrPoison (SDValueOp,boolPoisonOnly=false,unsignedDepth=0)const |
Return true if this function can prove thatOp is never poison and, ifPoisonOnly is false, does not have undef bits. | |
bool | isGuaranteedNotToBeUndefOrPoison (SDValueOp,constAPInt &DemandedElts,boolPoisonOnly=false,unsignedDepth=0)const |
Return true if this function can prove thatOp is never poison and, ifPoisonOnly is false, does not have undef bits. | |
bool | isGuaranteedNotToBePoison (SDValueOp,unsignedDepth=0)const |
Return true if this function can prove thatOp is never poison. | |
bool | isGuaranteedNotToBePoison (SDValueOp,constAPInt &DemandedElts,unsignedDepth=0)const |
Return true if this function can prove thatOp is never poison. | |
bool | canCreateUndefOrPoison (SDValueOp,constAPInt &DemandedElts,boolPoisonOnly=false,bool ConsiderFlags=true,unsignedDepth=0)const |
Return true if Op can create undef or poison from non-undef & non-poison operands. | |
bool | canCreateUndefOrPoison (SDValueOp,boolPoisonOnly=false,bool ConsiderFlags=true,unsignedDepth=0)const |
Return true if Op can create undef or poison from non-undef & non-poison operands. | |
bool | isADDLike (SDValueOp,bool NoWrap=false)const |
Return true if the specified operand is anISD::OR orISD::XOR node that can be treated as anISD::ADD node. | |
bool | isBaseWithConstantOffset (SDValueOp)const |
Return true if the specified operand is anISD::ADD with aConstantSDNode on the right-hand side, or if it is anISD::OR with aConstantSDNode that is guaranteed to have the same semantics as an ADD. | |
bool | isKnownNeverNaN (SDValueOp,bool SNaN=false,unsignedDepth=0)const |
Test whether the givenSDValue (or all elements of it, if it is a vector) is known to never be NaN. | |
bool | isKnownNeverSNaN (SDValueOp,unsignedDepth=0)const |
bool | isKnownNeverZeroFloat (SDValueOp)const |
Test whether the given floating pointSDValue is known to never be positive or negative zero. | |
bool | isKnownNeverZero (SDValueOp,unsignedDepth=0)const |
Test whether the givenSDValue is known to contain non-zerovalue(s). | |
bool | cannotBeOrderedNegativeFP (SDValueOp)const |
Test whether the given float value is known to be positive. | |
bool | isEqualTo (SDValueA,SDValueB)const |
Test whether two SDValues are known to compare equal. | |
bool | haveNoCommonBitsSet (SDValueA,SDValueB)const |
Return true if A and B have no common bits set. | |
bool | isSplatValue (SDValue V,constAPInt &DemandedElts,APInt &UndefElts,unsignedDepth=0)const |
Test whetherV has a splatted value for all the demanded elements. | |
bool | isSplatValue (SDValue V,bool AllowUndefs=false)const |
Test whetherV has a splatted value. | |
SDValue | getSplatSourceVector (SDValue V, int &SplatIndex) |
If V is a splatted value, return the source vector and its splat index. | |
SDValue | getSplatValue (SDValue V,bool LegalTypes=false) |
If V is a splat vector, return its scalar source operand by extracting that element from the source vector. | |
std::optional<ConstantRange > | getValidShiftAmountRange (SDValue V,constAPInt &DemandedElts,unsignedDepth)const |
If a SHL/SRA/SRL nodeV has shift amounts that are all less than the element bit-width of the shift node, return the valid constant range. | |
std::optional<uint64_t > | getValidShiftAmount (SDValue V,constAPInt &DemandedElts,unsignedDepth=0)const |
If a SHL/SRA/SRL nodeV has a uniform shift amount that is less than the element bit-width of the shift node, return it. | |
std::optional<uint64_t > | getValidShiftAmount (SDValue V,unsignedDepth=0)const |
If a SHL/SRA/SRL nodeV has a uniform shift amount that is less than the element bit-width of the shift node, return it. | |
std::optional<uint64_t > | getValidMinimumShiftAmount (SDValue V,constAPInt &DemandedElts,unsignedDepth=0)const |
If a SHL/SRA/SRL nodeV has shift amounts that are all less than the element bit-width of the shift node, return the minimum possible value. | |
std::optional<uint64_t > | getValidMinimumShiftAmount (SDValue V,unsignedDepth=0)const |
If a SHL/SRA/SRL nodeV has shift amounts that are all less than the element bit-width of the shift node, return the minimum possible value. | |
std::optional<uint64_t > | getValidMaximumShiftAmount (SDValue V,constAPInt &DemandedElts,unsignedDepth=0)const |
If a SHL/SRA/SRL nodeV has shift amounts that are all less than the element bit-width of the shift node, return the maximum possible value. | |
std::optional<uint64_t > | getValidMaximumShiftAmount (SDValue V,unsignedDepth=0)const |
If a SHL/SRA/SRL nodeV has shift amounts that are all less than the element bit-width of the shift node, return the maximum possible value. | |
SDValue | matchBinOpReduction (SDNode *Extract,ISD::NodeType &BinOp,ArrayRef<ISD::NodeType > CandidateBinOps,bool AllowPartials=false) |
Match a binop + shuffle pyramid that represents a horizontal reduction over the elements of a vector starting from the EXTRACT_VECTOR_ELT node /p Extract. | |
SDValue | UnrollVectorOp (SDNode *N,unsigned ResNE=0) |
Utility function used by legalize and lowering to "unroll" a vector operation by splitting out the scalars and operating on each element individually. | |
std::pair<SDValue,SDValue > | UnrollVectorOverflowOp (SDNode *N,unsigned ResNE=0) |
LikeUnrollVectorOp(), but for the [US](ADD|SUB|MUL)O family of opcodes. | |
bool | areNonVolatileConsecutiveLoads (LoadSDNode *LD,LoadSDNode *Base,unsigned Bytes, int Dist)const |
Return true if loads are next to each other and can be merged. | |
MaybeAlign | InferPtrAlign (SDValuePtr)const |
Infer alignment of a load / store address. | |
std::pair<SDValue,SDValue > | SplitScalar (constSDValue &N,constSDLoc &DL,constEVT &LoVT,constEVT &HiVT) |
Split the scalar node with EXTRACT_ELEMENT using the provided VTs and return the low/high part. | |
std::pair<EVT,EVT > | GetSplitDestVTs (constEVT &VT)const |
Compute the VTs needed for the low/hi parts of a type which is split (or expanded) into two not necessarily identical pieces. | |
std::pair<EVT,EVT > | GetDependentSplitDestVTs (constEVT &VT,constEVT &EnvVT,bool *HiIsEmpty)const |
Compute the VTs needed for the low/hi parts of a type, dependent on an enveloping VT that has been split into two identical pieces. | |
std::pair<SDValue,SDValue > | SplitVector (constSDValue &N,constSDLoc &DL,constEVT &LoVT,constEVT &HiVT) |
Split the vector with EXTRACT_SUBVECTOR using the provided VTs and return the low/high part. | |
std::pair<SDValue,SDValue > | SplitVector (constSDValue &N,constSDLoc &DL) |
Split the vector with EXTRACT_SUBVECTOR and return the low/high part. | |
std::pair<SDValue,SDValue > | SplitEVL (SDValueN,EVT VecVT,constSDLoc &DL) |
Split the explicit vector length parameter of a VP operation. | |
std::pair<SDValue,SDValue > | SplitVectorOperand (constSDNode *N,unsigned OpNo) |
Split the node's operand with EXTRACT_SUBVECTOR and return the low/high part. | |
SDValue | WidenVector (constSDValue &N,constSDLoc &DL) |
Widen the vector up to the next power of two using INSERT_SUBVECTOR. | |
void | ExtractVectorElements (SDValueOp,SmallVectorImpl<SDValue > &Args,unsigned Start=0,unsigned Count=0,EVT EltVT=EVT()) |
Append the extracted elements from Start to Count out of the vector Op in Args. | |
Align | getEVTAlign (EVT MemoryVT)const |
Compute the default alignment value for the given type. | |
bool | isConstantIntBuildVectorOrConstantInt (SDValueN,bool AllowOpaques=true)const |
Test whether the given value is a constant int or similar node. | |
bool | isConstantFPBuildVectorOrConstantFP (SDValueN)const |
Test whether the given value is a constant FP or similar node. | |
bool | isConstantValueOfAnyType (SDValueN)const |
std::optional<bool > | isBoolConstant (SDValueN,bool AllowTruncation=false)const |
Check if a value \op N is a constant using the target's BooleanContent for its type. | |
void | addCallSiteInfo (constSDNode *Node,CallSiteInfo &&CallInfo) |
Set CallSiteInfo to be associated withNode. | |
CallSiteInfo | getCallSiteInfo (constSDNode *Node) |
Return CallSiteInfo associated withNode, or a default if none exists. | |
void | addHeapAllocSite (constSDNode *Node,MDNode *MD) |
Set HeapAllocSite to be associated withNode. | |
MDNode * | getHeapAllocSite (constSDNode *Node)const |
Return HeapAllocSite associated withNode, or nullptr if none exists. | |
void | addPCSections (constSDNode *Node,MDNode *MD) |
Set PCSections to be associated withNode. | |
void | addMMRAMetadata (constSDNode *Node,MDNode *MMRA) |
SetMMRAMetadata to be associated withNode. | |
MDNode * | getPCSections (constSDNode *Node)const |
Return PCSections associated withNode, or nullptr if none exists. | |
MDNode * | getMMRAMetadata (constSDNode *Node)const |
Return the MMRAMDNode associated withNode, or nullptr if none exists. | |
void | addCalledGlobal (constSDNode *Node,constGlobalValue *GV,unsigned OpFlags) |
Set CalledGlobal to be associated withNode. | |
std::optional<CalledGlobalInfo > | getCalledGlobal (constSDNode *Node) |
Return CalledGlobal associated withNode, or a nullopt if none exists. | |
void | addNoMergeSiteInfo (constSDNode *Node,bool NoMerge) |
Set NoMergeSiteInfo to be associated withNode if NoMerge is true. | |
bool | getNoMergeSiteInfo (constSDNode *Node)const |
Return NoMerge info associated withNode. | |
void | copyExtraInfo (SDNode *From,SDNode *To) |
Copy extra info associated with one node to another. | |
DenormalMode | getDenormalMode (EVT VT)const |
Return the current function's default denormal handling kind for the given floating point type. | |
bool | shouldOptForSize ()const |
SDValue | getNeutralElement (unsigned Opcode,constSDLoc &DL,EVT VT,SDNodeFlags Flags) |
Get the (commutative) neutral element for the given opcode, if it exists. | |
bool | isSafeToSpeculativelyExecute (unsigned Opcode)const |
Some opcodes may create immediate undefined behavior when used with some values (integer division-by-zero for example). | |
bool | isSafeToSpeculativelyExecuteNode (constSDNode *N)const |
Check if the provided node is save to speculatively executed given its current arguments. | |
SDValue | makeStateFunctionCall (unsignedLibFunc,SDValuePtr,SDValue InChain,constSDLoc &DLoc) |
Helper used to make a call to a library function that has one argument of pointer type. | |
SDValue | getConstant (uint64_t Val,constSDLoc &DL,EVT VT,bool isTarget=false,bool isOpaque=false) |
Create aConstantSDNode wrapping a constant value. | |
SDValue | getConstant (constAPInt &Val,constSDLoc &DL,EVT VT,bool isTarget=false,bool isOpaque=false) |
SDValue | getSignedConstant (int64_t Val,constSDLoc &DL,EVT VT,bool isTarget=false,bool isOpaque=false) |
SDValue | getAllOnesConstant (constSDLoc &DL,EVT VT,bool IsTarget=false,bool IsOpaque=false) |
SDValue | getConstant (constConstantInt &Val,constSDLoc &DL,EVT VT,bool isTarget=false,bool isOpaque=false) |
SDValue | getIntPtrConstant (uint64_t Val,constSDLoc &DL,bool isTarget=false) |
SDValue | getShiftAmountConstant (uint64_t Val,EVT VT,constSDLoc &DL) |
SDValue | getShiftAmountConstant (constAPInt &Val,EVT VT,constSDLoc &DL) |
SDValue | getVectorIdxConstant (uint64_t Val,constSDLoc &DL,bool isTarget=false) |
SDValue | getTargetConstant (uint64_t Val,constSDLoc &DL,EVT VT,bool isOpaque=false) |
SDValue | getTargetConstant (constAPInt &Val,constSDLoc &DL,EVT VT,bool isOpaque=false) |
SDValue | getTargetConstant (constConstantInt &Val,constSDLoc &DL,EVT VT,bool isOpaque=false) |
SDValue | getSignedTargetConstant (int64_t Val,constSDLoc &DL,EVT VT,bool isOpaque=false) |
SDValue | getBoolConstant (bool V,constSDLoc &DL,EVT VT,EVT OpVT) |
Create a true or false constant of typeVT using the target's BooleanContent for typeOpVT . | |
SDValue | getConstantFP (double Val,constSDLoc &DL,EVT VT,bool isTarget=false) |
Create aConstantFPSDNode wrapping a constant value. | |
SDValue | getConstantFP (constAPFloat &Val,constSDLoc &DL,EVT VT,bool isTarget=false) |
SDValue | getConstantFP (constConstantFP &V,constSDLoc &DL,EVT VT,bool isTarget=false) |
SDValue | getTargetConstantFP (double Val,constSDLoc &DL,EVT VT) |
SDValue | getTargetConstantFP (constAPFloat &Val,constSDLoc &DL,EVT VT) |
SDValue | getTargetConstantFP (constConstantFP &Val,constSDLoc &DL,EVT VT) |
Static Public Member Functions | |
staticunsigned | getHasPredecessorMaxSteps () |
staticunsigned | getOpcode_EXTEND (unsigned Opcode) |
Convert *_EXTEND_VECTOR_INREG to *_EXTEND opcode. | |
staticunsigned | getOpcode_EXTEND_VECTOR_INREG (unsigned Opcode) |
Convert *_EXTEND to *_EXTEND_VECTOR_INREG opcode. | |
Public Attributes | |
bool | NewNodesMustHaveLegalTypes = false |
When true, additional steps are taken to ensure thatgetConstant() and similar functions return DAG nodes that have legal types. | |
Static Public Attributes | |
static constexprunsigned | MaxRecursionDepth = 6 |
Friends | |
struct | DAGUpdateListener |
DAGUpdateListener is a friend so it can manipulate the listener stack. | |
This is used to represent a portion of an LLVM function in a low-level DataDependence DAG representation suitable for instruction selection.
This DAG is constructed as the first step of instruction selection in order to allow implementation of machine specific optimizations and code simplifications.
The representation used by theSelectionDAG is a target-independent representation, which has some similarities to the GCC RTL representation, but is significantly more simple, powerful, and is a graph form instead of a linear form.
Definition at line228 of fileSelectionDAG.h.
Definition at line555 of fileSelectionDAG.h.
usingllvm::SelectionDAG::allnodes_iterator =ilist<SDNode>::iterator |
Definition at line560 of fileSelectionDAG.h.
Used to represent the possible overflow behavior of an operation.
Never: the operation cannot overflow. Always: the operation will always overflow. Sometime: the operation may or may not overflow.
Enumerator | |
---|---|
OFK_Never | |
OFK_Sometime | |
OFK_Always |
Definition at line1980 of fileSelectionDAG.h.
| explicit |
Definition at line1366 of fileSelectionDAG.cpp.
| delete |
SelectionDAG::~SelectionDAG | ( | ) |
Definition at line1394 of fileSelectionDAG.cpp.
Referencesassert().
| inline |
Set CalledGlobal to be associated withNode.
Definition at line2382 of fileSelectionDAG.h.
| inline |
Set CallSiteInfo to be associated withNode.
Definition at line2345 of fileSelectionDAG.h.
void SelectionDAG::AddDbgLabel | ( | SDDbgLabel * | DB | ) |
Add a dbg_labelSDNode.
Definition at line12150 of fileSelectionDAG.cpp.
Referencesllvm::SDDbgInfo::add().
Referenced byllvm::SelectionDAGBuilder::visitDbgInfo().
void SelectionDAG::AddDbgValue | ( | SDDbgValue * | DB, |
bool | isParameter | ||
) |
Add a dbg_valueSDNode.
AddDbgValue - Add a dbg_valueSDNode.
If SD is non-null that means the value is produced by SD.
Definition at line12140 of fileSelectionDAG.cpp.
Referencesllvm::SDDbgInfo::add(),assert(), andllvm::SDDbgInfo::getSDDbgValues().
Referenced byhandleDanglingVariadicDebugInfo(),llvm::SelectionDAGBuilder::handleDebugDeclare(),llvm::SelectionDAGBuilder::handleDebugValue(),llvm::SelectionDAGBuilder::resolveDanglingDebugInfo(),salvageDebugInfo(),llvm::SelectionDAGBuilder::salvageUnresolvedDbgValue(), andtransferDbgValues().
Set HeapAllocSite to be associated withNode.
Definition at line2354 of fileSelectionDAG.h.
SetMMRAMetadata to be associated withNode.
Definition at line2367 of fileSelectionDAG.h.
Referenced byllvm::SelectionDAGBuilder::visit().
Set NoMergeSiteInfo to be associated withNode if NoMerge is true.
Definition at line2394 of fileSelectionDAG.h.
Referenced byllvm::SystemZTargetLowering::LowerCall(),llvm::LoongArchTargetLowering::LowerCall(), andllvm::RISCVTargetLowering::LowerCall().
Set PCSections to be associated withNode.
Definition at line2363 of fileSelectionDAG.h.
Referenced byllvm::SelectionDAGBuilder::visit().
| inline |
Definition at line569 of fileSelectionDAG.h.
Referencesallnodes_begin(),allnodes_end(), andllvm::make_range().
Referenced byAssignTopologicalOrder(),dump(),llvm::HexagonDAGToDAGISel::PreprocessISelDAG(),RemoveDeadNodes(), andllvm::DAGTypeLegalizer::run().
| inline |
Definition at line572 of fileSelectionDAG.h.
Referencesallnodes_begin(),allnodes_end(), andllvm::make_range().
| inline |
Definition at line562 of fileSelectionDAG.h.
| inline |
| inline |
Definition at line563 of fileSelectionDAG.h.
| inline |
Definition at line565 of fileSelectionDAG.h.
Referenced byAssignTopologicalOrder(), andllvm::HexagonDAGToDAGISel::PreprocessISelDAG().
bool SelectionDAG::areNonVolatileConsecutiveLoads | ( | LoadSDNode * | LD, |
LoadSDNode * | Base, | ||
unsigned | Bytes, | ||
int | Dist | ||
) | const |
Return true if loads are next to each other and can be merged.
Check that both are nonvolatile and if LD is loading 'Bytes' bytes from a location that is 'Dist' units away from the location that the 'Base' load is loading from.
Definition at line12882 of fileSelectionDAG.cpp.
Referencesllvm::sampleprof::Base,llvm::EVT::getSizeInBits(),llvm::BaseIndexOffset::match(), andllvm::Offset.
Referenced byareLoadedOffsetButOtherwiseSame(),combineBVOfConsecutiveLoads(),combineINSERT_SUBVECTOR(),EltsFromConsecutiveLoads(), andlowerShuffleAsVTRUNC().
unsigned SelectionDAG::AssignTopologicalOrder | ( | ) |
Topological-sort the AllNodes list and a assign a unique node id for each node in the DAG based on their topological order.
AssignTopologicalOrder - Assign a unique node id for each node in the DAG based on their topological order.
Returns the number of nodes.
It returns the maximum id and a vector of the SDNodes* in assigned order by reference.
Definition at line12054 of fileSelectionDAG.cpp.
Referencesallnodes(),allnodes_begin(),allnodes_size(),assert(),llvm::checkForCycles(),llvm::dbgs(),llvm::SDNode::dumprFull(),llvm::ISD::EntryToken,I,llvm_unreachable,llvm::make_early_inc_range(),N, andP.
Referenced byLegalize().
| inline |
Definition at line1877 of fileSelectionDAG.h.
Referencesllvm::SDDbgInfo::ByvalParmDbgBegin().
Referenced bydump(), andllvm::ScheduleDAGSDNodes::EmitSchedule().
| inline |
Definition at line1880 of fileSelectionDAG.h.
Referencesllvm::SDDbgInfo::ByvalParmDbgEnd().
Referenced bydump(), andllvm::ScheduleDAGSDNodes::EmitSchedule().
Definition at line11924 of fileSelectionDAG.cpp.
Referencesassert(),gluePropagatesDivergence(),llvm::TargetLowering::isSDNodeAlwaysUniform(),llvm::TargetLowering::isSDNodeSourceOfDivergence(), andN.
Referenced byupdateDivergence().
bool SelectionDAG::canCreateUndefOrPoison | ( | SDValue | Op, |
bool | PoisonOnly =false , | ||
bool | ConsiderFlags =true , | ||
unsigned | Depth =0 | ||
) | const |
Return true if Op can create undef or poison from non-undef & non-poison operands.
ConsiderFlags
controls whether poison producing flags on the instruction are considered. This can be used to see if the instruction could still introduce undef or poison even without poison generating flags which might be on the instruction. (i.e. could the result of Op->dropPoisonGeneratingFlags() still create poison or undef)
Definition at line5529 of fileSelectionDAG.cpp.
ReferencescanCreateUndefOrPoison(),llvm::Depth,llvm::APInt::getAllOnes(),llvm::EVT::getVectorNumElements(),llvm::EVT::isFixedLengthVector(), andPoisonOnly.
bool SelectionDAG::canCreateUndefOrPoison | ( | SDValue | Op, |
constAPInt & | DemandedElts, | ||
bool | PoisonOnly =false , | ||
bool | ConsiderFlags =true , | ||
unsigned | Depth =0 | ||
) | const |
Return true if Op can create undef or poison from non-undef & non-poison operands.
The DemandedElts argument limits the check to the requested vector elements.
ConsiderFlags
controls whether poison producing flags on the instruction are considered. This can be used to see if the instruction could still introduce undef or poison even without poison generating flags which might be on the instruction. (i.e. could the result of Op->dropPoisonGeneratingFlags() still create poison or undef)
Definition at line5540 of fileSelectionDAG.cpp.
Referencesllvm::ISD::ADD,llvm::ISD::AND,llvm::ISD::BITCAST,llvm::ISD::BITREVERSE,llvm::ISD::BSWAP,llvm::ISD::BUILD_PAIR,llvm::ISD::BUILD_VECTOR,llvm::ISD::BUILTIN_OP_END,llvm::TargetLowering::canCreateUndefOrPoisonForTargetNode(),computeKnownBits(),llvm::ISD::CONCAT_VECTORS,llvm::ISD::CTPOP,llvm::Depth,llvm::enumerate(),llvm::ISD::EXTRACT_VECTOR_ELT,llvm::ISD::FREEZE,llvm::ISD::FSHL,llvm::ISD::FSHR,llvm::KnownBits::getMaxValue(),getTarget(),getValidMaximumShiftAmount(),llvm::EVT::getVectorMinNumElements(),Idx,llvm::ISD::INSERT_SUBVECTOR,llvm::ISD::INSERT_VECTOR_ELT,llvm::ISD::INTRINSIC_VOID,llvm::ISD::INTRINSIC_W_CHAIN,llvm::ISD::INTRINSIC_WO_CHAIN,isGuaranteedNotToBeUndefOrPoison(),llvm::ISD::MUL,llvm::ISD::MULHS,llvm::ISD::MULHU,llvm::TargetMachine::Options,Options,llvm::ISD::OR,llvm::ISD::PARITY,PoisonOnly,llvm::ISD::ROTL,llvm::ISD::ROTR,llvm::ISD::SADDSAT,llvm::ISD::SCALAR_TO_VECTOR,llvm::ISD::SELECT_CC,llvm::ISD::SETCC,llvm::ISD::SHL,llvm::ISD::SIGN_EXTEND,llvm::ISD::SIGN_EXTEND_INREG,llvm::ISD::SIGN_EXTEND_VECTOR_INREG,llvm::ISD::SMAX,llvm::ISD::SMIN,llvm::ISD::SPLAT_VECTOR,llvm::ISD::SRA,llvm::ISD::SRL,llvm::ISD::SSUBSAT,llvm::ISD::SUB,llvm::ISD::TRUNCATE,llvm::ISD::UADDSAT,llvm::APInt::uge(),llvm::APInt::ugt(),llvm::ISD::UMAX,llvm::ISD::UMIN,llvm::ISD::USUBSAT,llvm::ISD::VECTOR_SHUFFLE,llvm::ISD::XOR,llvm::ISD::ZERO_EXTEND, andllvm::ISD::ZERO_EXTEND_VECTOR_INREG.
Referenced bycanCreateUndefOrPoison(), andisGuaranteedNotToBeUndefOrPoison().
Test whether the given float value is known to be positive.
+0.0, +inf and +nan are considered positive, -0.0, -inf and -nan are not.
Definition at line5968 of fileSelectionDAG.cpp.
Referencesllvm::ISD::FABS, andllvm::isConstOrConstSplatFP().
Swap N1 and N2 if Opcode is a commutative binary opcode and the canonical form expects the opposite order.
Definition at line7217 of fileSelectionDAG.cpp.
Referencesllvm::SDValue::getOpcode(),llvm::TargetLoweringBase::isCommutativeBinOp(),isConstantFPBuildVectorOrConstantFP(),isConstantIntBuildVectorOrConstantInt(),llvm::ISD::SPLAT_VECTOR,llvm::ISD::STEP_VECTOR, andstd::swap().
Referenced bygetNode().
void SelectionDAG::clear | ( | ) |
Clear state and free memory necessary to make thisSelectionDAG ready to process a new block.
Definition at line1455 of fileSelectionDAG.cpp.
Referencesllvm::SDDbgInfo::clear(),getEntryNode(), andllvm::BumpPtrAllocatorImpl< AllocatorT, SlabSize, SizeThreshold, GrowthDelay >::Reset().
void SelectionDAG::clearGraphAttrs | ( | ) |
Clear all previously defined node graph attributes.
clearGraphAttrs - Clear all previously defined node graph attributes.
Intended to be used from a debugging tool (eg. gdb).
Definition at line179 of fileSelectionDAGPrinter.cpp.
Referencesllvm::errs().
void SelectionDAG::Combine | ( | CombineLevel | Level, |
BatchAAResults * | BatchAA, | ||
CodeGenOptLevel | OptLevel | ||
) |
This iterates over the nodes in theSelectionDAG, folding certain types of nodes together, or eliminating superfluous nodes.
This is the entry point for the file.
The Level argument controls whether Combine is allowed to produce nodes and types that are illegal on the target.
This is the main entry point to this class.
Definition at line29243 of fileDAGCombiner.cpp.
KnownBits SelectionDAG::computeKnownBits | ( | SDValue | Op, |
constAPInt & | DemandedElts, | ||
unsigned | Depth =0 | ||
) | const |
Determine which bits of Op are known to be either zero or one and return them in Known.
The DemandedElts argument allows us to only collect the known bits that are shared by the requested vector elements. Targets can implement the computeKnownBitsForTargetNode method in theTargetLowering class to allow target nodes to be understood.
The DemandedElts argument allows us to only collect the known bits that are shared by the requested vector elements.
Definition at line3430 of fileSelectionDAG.cpp.
Referencesllvm::ISD::ABDS,llvm::KnownBits::abds(),llvm::ISD::ABDU,llvm::KnownBits::abdu(),llvm::ISD::ABS,llvm::KnownBits::abs(),llvm::ISD::ADD,llvm::ISD::ADDC,llvm::ISD::ADDE,llvm::ISD::AND,llvm::ISD::ANY_EXTEND,llvm::ISD::ANY_EXTEND_VECTOR_INREG,llvm::KnownBits::anyext(),llvm::KnownBits::ashr(),assert(),llvm::ISD::AssertAlign,llvm::ISD::AssertZext,llvm::ISD::ATOMIC_CMP_SWAP,llvm::ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS,llvm::ISD::ATOMIC_LOAD,llvm::ISD::ATOMIC_LOAD_ADD,llvm::ISD::ATOMIC_LOAD_AND,llvm::ISD::ATOMIC_LOAD_CLR,llvm::ISD::ATOMIC_LOAD_MAX,llvm::ISD::ATOMIC_LOAD_MIN,llvm::ISD::ATOMIC_LOAD_NAND,llvm::ISD::ATOMIC_LOAD_OR,llvm::ISD::ATOMIC_LOAD_SUB,llvm::ISD::ATOMIC_LOAD_UMAX,llvm::ISD::ATOMIC_LOAD_UMIN,llvm::ISD::ATOMIC_LOAD_XOR,llvm::ISD::ATOMIC_SWAP,llvm::ISD::AVGCEILS,llvm::KnownBits::avgCeilS(),llvm::ISD::AVGCEILU,llvm::KnownBits::avgCeilU(),llvm::ISD::AVGFLOORS,llvm::KnownBits::avgFloorS(),llvm::ISD::AVGFLOORU,llvm::KnownBits::avgFloorU(),llvm::bit_width(),llvm::ISD::BITCAST,llvm::ISD::BITREVERSE,llvm::BitWidth,llvm::ISD::BSWAP,llvm::ISD::BUILD_VECTOR,llvm::ISD::BUILTIN_OP_END,llvm::KnownBits::byteSwap(),llvm::CallingConv::C,llvm::APInt::clearAllBits(),llvm::APInt::clearBit(),llvm::APInt::clearLowBits(),llvm::KnownBits::computeForAddCarry(),llvm::KnownBits::computeForAddSub(),llvm::KnownBits::computeForSubBorrow(),computeKnownBits(),llvm::TargetLowering::computeKnownBitsForFrameIndex(),llvm::TargetLowering::computeKnownBitsForTargetNode(),llvm::computeKnownBitsFromRangeMetadata(),ComputeNumSignBits(),llvm::KnownBits::concat(),llvm::ISD::CONCAT_VECTORS,llvm::APInt::countl_zero(),llvm::KnownBits::countMaxLeadingZeros(),llvm::KnownBits::countMaxPopulation(),llvm::KnownBits::countMaxTrailingZeros(),llvm::ISD::CTLZ,llvm::ISD::CTLZ_ZERO_UNDEF,llvm::ISD::CTPOP,llvm::ISD::CTTZ,llvm::ISD::CTTZ_ZERO_UNDEF,llvm::Depth,llvm::enumerate(),llvm::ISD::EXTRACT_ELEMENT,llvm::ISD::EXTRACT_SUBVECTOR,llvm::ISD::EXTRACT_VECTOR_ELT,llvm::APInt::extractBits(),llvm::KnownBits::extractBits(),F,llvm::ISD::FGETSIGN,llvm::ISD::FP_TO_UINT_SAT,llvm::ISD::FrameIndex,llvm::ISD::FSHL,llvm::ISD::FSHR,llvm::Constant::getAggregateElement(),llvm::getAlign(),llvm::APInt::getAllOnes(),llvm::ConstantSDNode::getAPIntValue(),llvm::APInt::getBitsSetFrom(),llvm::APInt::getBitWidth(),llvm::KnownBits::getBitWidth(),llvm::TargetLoweringBase::getBooleanContents(),getDataLayout(),llvm::TargetLoweringBase::getExtendForAtomicOps(),llvm::MachineFunction::getFunction(),llvm::APInt::getHiBits(),llvm::APInt::getLowBitsSet(),getMachineFunction(),llvm::ShuffleVectorSDNode::getMask(),llvm::DWARFExpression::Operation::getNumOperands(),llvm::APInt::getNumSignBits(),llvm::APInt::getOneBitSet(),llvm::Type::getPrimitiveSizeInBits(),llvm::EVT::getScalarSizeInBits(),llvm::Type::getScalarSizeInBits(),llvm::getShuffleDemandedElts(),llvm::EVT::getSizeInBits(),llvm::Constant::getSplatValue(),llvm::TargetLowering::getTargetConstantFromLoad(),llvm::Value::getType(),llvm::ConstantRange::getUnsignedMax(),getValidMinimumShiftAmount(),llvm::SDValue::getValueSizeInBits(),llvm::SDValue::getValueType(),llvm::EVT::getVectorNumElements(),llvm::getVScaleRange(),llvm::APInt::getZero(),I,Idx,llvm::ISD::INSERT_SUBVECTOR,llvm::ISD::INSERT_VECTOR_ELT,llvm::APInt::insertBits(),llvm::KnownBits::insertBits(),llvm::KnownBits::intersectWith(),llvm::ISD::INTRINSIC_VOID,llvm::ISD::INTRINSIC_W_CHAIN,llvm::ISD::INTRINSIC_WO_CHAIN,llvm::isConstOrConstSplat(),llvm::ISD::isEXTLoad(),llvm::EVT::isFloatingPoint(),isGuaranteedNotToBeUndefOrPoison(),llvm::EVT::isInteger(),llvm::DataLayout::isLittleEndian(),llvm::APInt::isNegative(),llvm::KnownBits::isNegative(),llvm::ISD::isNON_EXTLoad(),llvm::APInt::isNonNegative(),llvm::KnownBits::isNonNegative(),llvm::KnownBits::isNonZero(),llvm::APInt::isPowerOf2(),llvm::EVT::isScalableVector(),llvm::ISD::isSEXTLoad(),llvm::isUIntN(),llvm::KnownBits::isUnknown(),llvm::EVT::isVector(),llvm::Type::isVectorTy(),llvm::ISD::isZEXTLoad(),LHS,llvm::ISD::LOAD,llvm::Log2(),llvm::APInt::logBase2(),llvm::KnownBits::lshr(),llvm::APInt::lshrInPlace(),llvm::KnownBits::makeConstant(),llvm::KnownBits::makeNegative(),llvm::KnownBits::makeNonNegative(),MaxRecursionDepth,llvm::ISD::MERGE_VALUES,llvm::ISD::MGATHER,llvm::ISD::MLOAD,llvm::ISD::MUL,llvm::KnownBits::mul(),llvm::ISD::MULHS,llvm::KnownBits::mulhs(),llvm::ISD::MULHU,llvm::KnownBits::mulhu(),llvm::ConstantRange::multiply(),llvm::Offset,llvm::KnownBits::One,llvm::ISD::OR,llvm::ISD::PARITY,llvm::KnownBits::resetAll(),llvm::KnownBits::reverseBits(),RHS,llvm::ISD::SADDO,llvm::ISD::SADDO_CARRY,llvm::ISD::SCALAR_TO_VECTOR,llvm::APIntOps::ScaleBitMask(),llvm::ISD::SDIV,llvm::KnownBits::sdiv(),llvm::ISD::SELECT,llvm::ISD::SELECT_CC,llvm::APInt::setAllBits(),llvm::KnownBits::setAllZero(),llvm::APInt::setBit(),llvm::APInt::setBitsFrom(),llvm::ISD::SETCC,llvm::ISD::SETCCCARRY,llvm::APInt::setHighBits(),llvm::APInt::setLowBits(),llvm::KnownBits::sext(),llvm::KnownBits::sextInReg(),llvm::APInt::shl(),llvm::ISD::SHL,llvm::KnownBits::shl(),llvm::ISD::SHL_PARTS,llvm::ISD::SIGN_EXTEND,llvm::ISD::SIGN_EXTEND_INREG,llvm::ISD::SIGN_EXTEND_VECTOR_INREG,llvm::ISD::SINT_TO_FP,llvm::ArrayRef< T >::size(),llvm::APInt::sle(),llvm::ISD::SMAX,llvm::KnownBits::smax(),llvm::ISD::SMIN,llvm::KnownBits::smin(),llvm::ISD::SMUL_LOHI,llvm::ISD::SMULO,llvm::Splat,llvm::ISD::SPLAT_VECTOR,llvm::ISD::SPLAT_VECTOR_PARTS,llvm::ISD::SRA,llvm::ISD::SRA_PARTS,llvm::ISD::SREM,llvm::KnownBits::srem(),llvm::ISD::SRL,llvm::ISD::SRL_PARTS,llvm::ISD::SSUBO,llvm::ISD::SSUBO_CARRY,llvm::ISD::STEP_VECTOR,llvm::ISD::STRICT_FSETCC,llvm::ISD::STRICT_FSETCCS,llvm::ISD::SUB,llvm::ISD::SUBC,std::swap(),llvm::ISD::TargetFrameIndex,llvm::ConstantRange::toKnownBits(),llvm::KnownBits::trunc(),llvm::ISD::TRUNCATE,llvm::ISD::UADDO,llvm::ISD::UADDO_CARRY,llvm::ISD::UDIV,llvm::KnownBits::udiv(),llvm::ISD::UINT_TO_FP,llvm::ISD::UMAX,llvm::KnownBits::umax(),llvm::ISD::UMIN,llvm::KnownBits::umin(),llvm::ISD::UMUL_LOHI,llvm::APInt::umul_ov(),umul_ov(),llvm::ISD::UMULO,llvm::KnownBits::unionWith(),llvm::ISD::UREM,llvm::KnownBits::urem(),llvm::KnownBits::usub_sat(),llvm::ISD::USUBO,llvm::ISD::USUBO_CARRY,llvm::ISD::USUBSAT,llvm::ISD::VECTOR_SHUFFLE,llvm::ISD::VSCALE,llvm::ISD::VSELECT,llvm::ISD::XOR,llvm::KnownBits::Zero,llvm::ISD::ZERO_EXTEND,llvm::ISD::ZERO_EXTEND_VECTOR_INREG,llvm::TargetLoweringBase::ZeroOrOneBooleanContent,llvm::KnownBits::zext(),llvm::APInt::zext(),llvm::ISD::ZEXTLOAD, andllvm::KnownBits::zextOrTrunc().
Determine which bits of Op are known to be either zero or one and return them in Known.
For vectors, the known bits are those that are shared by every vector element. Targets can implement the computeKnownBitsForTargetNode method in theTargetLowering class to allow target nodes to be understood.
For vectors, the known bits are those that are shared by every vector element.
Definition at line3415 of fileSelectionDAG.cpp.
ReferencescomputeKnownBits(),llvm::Depth,llvm::APInt::getAllOnes(),llvm::EVT::getVectorNumElements(), andllvm::EVT::isFixedLengthVector().
Referenced byadjustForRedundantAnd(),llvm::TargetLowering::BuildUDIV(),canCreateUndefOrPoison(),cannotBeIntMin(),checkDot4MulSignedness(),llvm::SelectionDAGISel::CheckOrMask(),checkZExtBool(),combineArithReduction(),combineFaddCFmul(),combineFMulcFCMulc(),combineMOVMSK(),combineMul(),combinePMULH(),combineSCALAR_TO_VECTOR(),combineSetCC(),combineShiftToAVG(),computeKnownBits(),computeKnownBitsBinOp(),computeKnownBitsForHorizontalOperation(),computeKnownBitsForPMADDUBSW(),computeKnownBitsForPMADDWD(),computeKnownBitsForPSADBW(),llvm::ARMTargetLowering::computeKnownBitsForTargetNode(),llvm::RISCVTargetLowering::computeKnownBitsForTargetNode(),llvm::AArch64TargetLowering::computeKnownBitsForTargetNode(),llvm::AMDGPUTargetLowering::computeKnownBitsForTargetNode(),llvm::SITargetLowering::computeKnownBitsForTargetNode(),llvm::LanaiTargetLowering::computeKnownBitsForTargetNode(),llvm::SparcTargetLowering::computeKnownBitsForTargetNode(),llvm::SystemZTargetLowering::computeKnownBitsForTargetNode(),llvm::X86TargetLowering::computeKnownBitsForTargetNode(),ComputeNumSignBits(),computeOverflowForSignedMul(),computeOverflowForSignedSub(),computeOverflowForUnsignedAdd(),computeOverflowForUnsignedMul(),computeOverflowForUnsignedSub(),detectExtMul(),llvm::TargetLowering::expandAddSubSat(),llvm::TargetLowering::expandAVG(),llvm::TargetLowering::expandFixedPointDiv(),getPack(),getValidShiftAmountRange(),haveNoCommonBitsSet(),isBitfieldPositioningOp(),isKnownNeverZero(),isTruncateOf(),isWordAligned(),LowerAndToBT(),LowerAndToBTST(),LowerCTPOP(),LowerMUL(),llvm::SITargetLowering::lowerSET_ROUNDING(),LowerShift(),lowerShuffleWithVPMOV(),LowerVectorAllEqual(),MaskedValueIsAllOnes(),MaskedValueIsZero(),MaskedVectorIsZero(),matchBinaryShuffle(),matchTruncateWithPACK(),narrowIndex(),llvm::AMDGPUTargetLowering::numBitsUnsigned(),performANDCombine(),llvm::ARMTargetLowering::PerformCMOVCombine(),llvm::ARMTargetLowering::PerformCMOVToBFICombine(),performORCombine(),llvm::AMDGPUTargetLowering::performShlCombine(),performSIGN_EXTEND_INREGCombine(),llvm::AMDGPUTargetLowering::performTruncateCombine(),provablyDisjointOr(),llvm::X86TargetLowering::ReplaceNodeResults(),llvm::PPCTargetLowering::SelectAddressRegImm(),llvm::PPCTargetLowering::SelectAddressRegImm34(),llvm::PPCTargetLowering::SelectAddressRegReg(),llvm::LoongArchDAGToDAGISel::selectShiftMask(),llvm::RISCVDAGToDAGISel::selectShiftMask(),llvm::TargetLowering::SimplifyDemandedBits(),llvm::TargetLowering::SimplifyMultipleUseDemandedBits(),llvm::X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode(),llvm::TargetLowering::SimplifySetCC(),tryBitfieldInsertOpFromOr(), andtryBitfieldInsertOpFromOrAndImm().
unsigned SelectionDAG::ComputeMaxSignificantBits | ( | SDValue | Op, |
constAPInt & | DemandedElts, | ||
unsigned | Depth =0 | ||
) | const |
Get the upper bound on bit size for thisValueOp
as a signed integer.
i.e. x == sext(trunc(x to MaxSignedBits) to bitwidth(x)). Similar to theAPInt::getSignificantBits function. Helper wrapper to ComputeNumSignBits.
Definition at line5423 of fileSelectionDAG.cpp.
ReferencesComputeNumSignBits(), andllvm::Depth.
Get the upper bound on bit size for thisValueOp
as a signed integer.
i.e. x == sext(trunc(x to MaxSignedBits) to bitwidth(x)). Similar to theAPInt::getSignificantBits function. Helper wrapper to ComputeNumSignBits.
Definition at line5417 of fileSelectionDAG.cpp.
ReferencesComputeNumSignBits(), andllvm::Depth.
Referenced bycombineConcatVectorOps(),combineMulToPMADDWD(),combinePMULH(),detectExtMul(),EmitCmp(),llvm::TargetLowering::expandMUL_LOHI(),getPack(),lowerBuildVectorOfConstants(),llvm::AMDGPUTargetLowering::numBitsSigned(), andllvm::TargetLowering::SimplifyDemandedBits().
unsigned SelectionDAG::ComputeNumSignBits | ( | SDValue | Op, |
constAPInt & | DemandedElts, | ||
unsigned | Depth =0 | ||
) | const |
Return the number of times the sign bit of the register is replicated into the other bits.
We know that at least 1 bit is always equal to the sign bit (itself), but other cases can give us information. For example, immediately after an "SRA X, 2", we know that the top 3 bits are all equal to each other, so we return 3. The DemandedElts argument allows us to only collect the minimum sign bits of the requested vector elements. Targets can implement the ComputeNumSignBitsForTarget method in theTargetLowering class to allow target nodes to be understood.
Definition at line4751 of fileSelectionDAG.cpp.
Referencesllvm::ISD::ADD,llvm::ISD::ADDC,llvm::ISD::AND,assert(),llvm::ISD::AssertSext,llvm::ISD::AssertZext,llvm::ISD::ATOMIC_CMP_SWAP,llvm::ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS,llvm::ISD::ATOMIC_LOAD,llvm::ISD::ATOMIC_LOAD_ADD,llvm::ISD::ATOMIC_LOAD_AND,llvm::ISD::ATOMIC_LOAD_CLR,llvm::ISD::ATOMIC_LOAD_MAX,llvm::ISD::ATOMIC_LOAD_MIN,llvm::ISD::ATOMIC_LOAD_NAND,llvm::ISD::ATOMIC_LOAD_OR,llvm::ISD::ATOMIC_LOAD_SUB,llvm::ISD::ATOMIC_LOAD_UMAX,llvm::ISD::ATOMIC_LOAD_UMIN,llvm::ISD::ATOMIC_LOAD_XOR,llvm::ISD::ATOMIC_SWAP,llvm::ISD::AVGCEILS,llvm::ISD::AVGFLOORS,llvm::ISD::BITCAST,llvm::BitWidth,llvm::ISD::BUILD_VECTOR,llvm::ISD::BUILTIN_OP_END,llvm::CallingConv::C,llvm::APInt::clearBit(),computeKnownBits(),ComputeNumSignBits(),llvm::TargetLowering::ComputeNumSignBitsForTargetNode(),llvm::ISD::CONCAT_VECTORS,llvm::KnownBits::countMinSignBits(),llvm::Depth,llvm::ISD::EXTRACT_ELEMENT,llvm::ISD::EXTRACT_SUBVECTOR,llvm::ISD::EXTRACT_VECTOR_ELT,llvm::APInt::extractBits(),llvm::ISD::FP_TO_SINT_SAT,llvm::Constant::getAggregateElement(),llvm::APInt::getAllOnes(),llvm::ConstantSDNode::getAPIntValue(),llvm::APInt::getBitWidth(),llvm::ConstantRange::getBitWidth(),llvm::TargetLoweringBase::getBooleanContents(),llvm::getConstantRangeFromMetadata(),getDataLayout(),llvm::TargetLoweringBase::getExtendForAtomicOps(),llvm::ShuffleVectorSDNode::getMask(),llvm::DWARFExpression::Operation::getNumOperands(),llvm::APInt::getNumSignBits(),llvm::APInt::getOneBitSet(),llvm::Type::getPrimitiveSizeInBits(),llvm::EVT::getScalarSizeInBits(),llvm::Type::getScalarSizeInBits(),llvm::SDValue::getScalarValueSizeInBits(),llvm::getShuffleDemandedElts(),llvm::ConstantRange::getSignedMax(),llvm::ConstantRange::getSignedMin(),llvm::TargetLowering::getTargetConstantFromLoad(),getValidMinimumShiftAmount(),getValidShiftAmountRange(),llvm::SDValue::getValueType(),llvm::EVT::getVectorNumElements(),llvm::APInt::getZero(),Idx,llvm::ISD::INSERT_SUBVECTOR,llvm::ISD::INSERT_VECTOR_ELT,llvm::APInt::insertBits(),llvm::ISD::INTRINSIC_VOID,llvm::ISD::INTRINSIC_W_CHAIN,llvm::ISD::INTRINSIC_WO_CHAIN,llvm::isConstOrConstSplat(),llvm::ISD::isExtOpcode(),llvm::EVT::isFloatingPoint(),llvm::EVT::isInteger(),llvm::DataLayout::isLittleEndian(),llvm::KnownBits::isNonNegative(),llvm::EVT::isScalableVector(),llvm::EVT::isVector(),llvm::Type::isVectorTy(),llvm::ISD::LOAD,MaxRecursionDepth,llvm::ISD::MERGE_VALUES,llvm::ISD::MUL,llvm::ISD::NON_EXTLOAD,llvm::ISD::OR,llvm::ISD::ROTL,llvm::ISD::ROTR,llvm::ISD::SADDO,llvm::ISD::SADDO_CARRY,llvm::APIntOps::ScaleBitMask(),llvm::ISD::SELECT,llvm::ISD::SELECT_CC,llvm::ISD::SETCC,llvm::ISD::SETCCCARRY,llvm::ISD::SEXTLOAD,llvm::APInt::shl(),llvm::ISD::SHL,llvm::ISD::SIGN_EXTEND,llvm::ISD::SIGN_EXTEND_INREG,llvm::ISD::SIGN_EXTEND_VECTOR_INREG,llvm::ConstantRange::signExtend(),llvm::ArrayRef< T >::size(),llvm::APInt::sle(),llvm::ISD::SMAX,llvm::ISD::SMIN,llvm::ISD::SMULO,llvm::ISD::SPLAT_VECTOR,llvm::ISD::SRA,llvm::ISD::SREM,llvm::ISD::SSUBO,llvm::ISD::SSUBO_CARRY,llvm::ISD::STRICT_FSETCC,llvm::ISD::STRICT_FSETCCS,llvm::ISD::SUB,std::swap(),llvm::ISD::TRUNCATE,llvm::ISD::UADDO,llvm::ISD::UADDO_CARRY,llvm::ISD::UMAX,llvm::ISD::UMIN,llvm::ISD::UMULO,llvm::ISD::USUBO,llvm::ISD::USUBO_CARRY,llvm::ISD::VECTOR_SHUFFLE,llvm::ISD::VSELECT,llvm::ISD::XOR,llvm::KnownBits::Zero,llvm::ISD::ZERO_EXTEND,llvm::ConstantRange::zeroExtend(),llvm::TargetLoweringBase::ZeroOrNegativeOneBooleanContent,llvm::APInt::zext(), andllvm::ISD::ZEXTLOAD.
Return the number of times the sign bit of the register is replicated into the other bits.
We know that at least 1 bit is always equal to the sign bit (itself), but other cases can give us information. For example, immediately after an "SRA X, 2", we know that the top 3 bits are all equal to each other, so we return 3. Targets can implement the ComputeNumSignBitsForTarget method in theTargetLowering class to allow target nodes to be understood.
Definition at line4739 of fileSelectionDAG.cpp.
ReferencesComputeNumSignBits(),llvm::Depth,llvm::APInt::getAllOnes(),llvm::EVT::getVectorNumElements(), andllvm::EVT::isFixedLengthVector().
Referenced bycanReduceVMulWidth(),combineAnd(),combineAndMaskToShift(),combineAndnp(),combineBitOpWithPACK(),combineGatherScatter(),combineLogicBlendIntoConditionalNegate(),combineLogicBlendIntoPBLENDV(),combineMulToPMULDQ(),combinePredicateReduction(),combinePTESTCC(),combineSelect(),combineSetCCMOVMSK(),combineShiftToAVG(),combineSIntToFP(),combineVectorCompareAndMaskUnaryOp(),combineVectorPack(),combineVSelectWithAllOnesOrZeros(),computeKnownBits(),ComputeMaxSignificantBits(),ComputeNumSignBits(),computeNumSignBitsBinOp(),llvm::AArch64TargetLowering::ComputeNumSignBitsForTargetNode(),llvm::RISCVTargetLowering::ComputeNumSignBitsForTargetNode(),llvm::SystemZTargetLowering::ComputeNumSignBitsForTargetNode(),llvm::X86TargetLowering::ComputeNumSignBitsForTargetNode(),llvm::AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(),computeOverflowForSignedAdd(),computeOverflowForSignedMul(),computeOverflowForSignedSub(),llvm::TargetLowering::expandAVG(),llvm::TargetLowering::expandFixedPointDiv(),foldAddSubMasked1(),getFauxShuffleMask(),isS16(),LowerADDSAT_SUBSAT(),llvm::AMDGPUTargetLowering::LowerDIVREM24(),LowerEXTEND_VECTOR_INREG(),llvm::AMDGPUTargetLowering::LowerSDIVREM(),LowerShiftByScalarImmediate(),lowerShuffleWithVPMOV(),LowerTruncateVecI1(),lowerVectorIntrinsicScalars(),LowerVSETCC(),matchBinaryShuffle(),matchShuffleWithPACK(),matchTruncateWithPACK(),matchUnaryShuffle(),llvm::AMDGPUTargetLowering::PerformDAGCombine(),performVectorShiftCombine(),llvm::RISCVTargetLowering::ReplaceNodeResults(),llvm::RISCVDAGToDAGISel::selectSExtBits(),llvm::LoongArchDAGToDAGISel::selectSExti32(),selectUmullSmull(),llvm::TargetLowering::SimplifyDemandedBits(),llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(),llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), andllvm::X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode().
| inline |
Determine if the result of the addition of 2 nodes can overflow.
Definition at line1993 of fileSelectionDAG.h.
ReferencescomputeOverflowForSignedAdd(), andcomputeOverflowForUnsignedAdd().
Referenced bywillNotOverflowAdd().
| inline |
Determine if the result of the mul of 2 nodes can overflow.
Definition at line2029 of fileSelectionDAG.h.
ReferencescomputeOverflowForSignedMul(), andcomputeOverflowForUnsignedMul().
Referenced bywillNotOverflowMul().
SelectionDAG::OverflowKind SelectionDAG::computeOverflowForSignedAdd | ( | SDValue | N0, |
SDValue | N1 | ||
) | const |
Determine if the result of the signed addition of 2 nodes can overflow.
Definition at line4534 of fileSelectionDAG.cpp.
ReferencesComputeNumSignBits(),llvm::isNullConstant(),OFK_Never, andOFK_Sometime.
Referenced bycomputeOverflowForAdd().
SelectionDAG::OverflowKind SelectionDAG::computeOverflowForSignedMul | ( | SDValue | N0, |
SDValue | N1 | ||
) | const |
Determine if the result of the signed mul of 2 nodes can overflow.
Definition at line4616 of fileSelectionDAG.cpp.
Referencesllvm::BitWidth,computeKnownBits(),ComputeNumSignBits(),llvm::SDValue::getScalarValueSizeInBits(),llvm::KnownBits::isNonNegative(),llvm::isNullConstant(),llvm::isOneConstant(),OFK_Never, andOFK_Sometime.
Referenced bycomputeOverflowForMul().
SelectionDAG::OverflowKind SelectionDAG::computeOverflowForSignedSub | ( | SDValue | N0, |
SDValue | N1 | ||
) | const |
Determine if the result of the signed sub of 2 nodes can overflow.
Definition at line4572 of fileSelectionDAG.cpp.
ReferencescomputeKnownBits(),ComputeNumSignBits(),llvm::ConstantRange::fromKnownBits(),llvm::isNullConstant(),mapOverflowResult(),OFK_Never, andllvm::ConstantRange::signedSubMayOverflow().
Referenced bycomputeOverflowForSub().
| inline |
Determine if the result of the sub of 2 nodes can overflow.
Definition at line2011 of fileSelectionDAG.h.
ReferencescomputeOverflowForSignedSub(), andcomputeOverflowForUnsignedSub().
Referenced bywillNotOverflowSub().
SelectionDAG::OverflowKind SelectionDAG::computeOverflowForUnsignedAdd | ( | SDValue | N0, |
SDValue | N1 | ||
) | const |
Determine if the result of the unsigned addition of 2 nodes can overflow.
Definition at line4549 of fileSelectionDAG.cpp.
ReferencescomputeKnownBits(),llvm::ConstantRange::fromKnownBits(),llvm::KnownBits::getMaxValue(),llvm::SDValue::getOpcode(),llvm::SDValue::getResNo(),llvm::isNullConstant(),mapOverflowResult(),OFK_Never,llvm::APInt::ult(),llvm::ISD::UMUL_LOHI, andllvm::ConstantRange::unsignedAddMayOverflow().
Referenced bycomputeOverflowForAdd().
SelectionDAG::OverflowKind SelectionDAG::computeOverflowForUnsignedMul | ( | SDValue | N0, |
SDValue | N1 | ||
) | const |
Determine if the result of the unsigned mul of 2 nodes can overflow.
Definition at line4603 of fileSelectionDAG.cpp.
ReferencescomputeKnownBits(),llvm::ConstantRange::fromKnownBits(),llvm::isNullConstant(),llvm::isOneConstant(),mapOverflowResult(),OFK_Never, andllvm::ConstantRange::unsignedMulMayOverflow().
Referenced bycomputeOverflowForMul().
SelectionDAG::OverflowKind SelectionDAG::computeOverflowForUnsignedSub | ( | SDValue | N0, |
SDValue | N1 | ||
) | const |
Determine if the result of the unsigned sub of 2 nodes can overflow.
Definition at line4590 of fileSelectionDAG.cpp.
ReferencescomputeKnownBits(),llvm::ConstantRange::fromKnownBits(),llvm::isNullConstant(),mapOverflowResult(),OFK_Never, andllvm::ConstantRange::unsignedSubMayOverflow().
Referenced bycomputeOverflowForSub().
APInt SelectionDAG::computeVectorKnownZeroElements | ( | SDValue | Op, |
constAPInt & | DemandedElts, | ||
unsigned | Depth =0 | ||
) | const |
For each demanded element of a vector, see if it is known to be zero.
Definition at line3004 of fileSelectionDAG.cpp.
Referencesassert(),llvm::Depth,llvm::APInt::getBitWidth(),llvm::APInt::getOneBitSet(),llvm::EVT::getVectorNumElements(),llvm::APInt::getZero(),llvm::EVT::isScalableVector(),llvm::EVT::isVector(),MaskedVectorIsZero(), andllvm::APInt::setBit().
Referenced bycombineShuffleToZeroExtendVectorInReg().
Copy extra info associated with one node to another.
Definition at line13629 of fileSelectionDAG.cpp.
Referencesassert(),llvm::SmallPtrSetImplBase::clear(),llvm::detail::DenseSetImpl< ValueT, MapTy, ValueInfoT >::contains(),llvm::dbgs(),llvm::errs(),From,getEntryNode(),llvm::SDValue::getNode(),I,llvm::detail::DenseSetImpl< ValueT, MapTy, ValueInfoT >::insert(),llvm::SmallPtrSetImpl< PtrType >::insert(),LLVM_DEBUG,LLVM_LIKELY,N, andstd::swap().
Referenced byReplaceAllUsesOfValuesWith(),ReplaceAllUsesOfValueWith(), andReplaceAllUsesWith().
Create a stack temporary, suitable for holding the specified value type.
If minAlign is specified, the slot size will have at least that alignment.
Definition at line2789 of fileSelectionDAG.cpp.
ReferencesCreateStackTemporary(),getContext(),getDataLayout(),getPrefTypeAlign(),llvm::EVT::getStoreSize(), andllvm::EVT::getTypeForEVT().
Create a stack temporary suitable for holding either of the specified value types.
Definition at line2796 of fileSelectionDAG.cpp.
Referencesassert(),CreateStackTemporary(),DL,getContext(),getDataLayout(),llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(),llvm::EVT::getStoreSize(),llvm::EVT::getTypeForEVT(), andllvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isScalable().
Create a stack temporary based on the size in bytes and the alignment.
Definition at line2776 of fileSelectionDAG.cpp.
Referencesllvm::MachineFrameInfo::CreateStackObject(),getDataLayout(),getFrameIndex(),llvm::TargetLoweringBase::getFrameIndexTy(),llvm::MachineFunction::getFrameInfo(),llvm::TargetSubtargetInfo::getFrameLowering(),llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(),llvm::TargetFrameLowering::getStackIDForScalableVectors(),llvm::MachineFunction::getSubtarget(), andllvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isScalable().
Referenced byllvm::StatepointLoweringState::allocateStackSlot(),CreateStackTemporary(),expandMultipleResultFPLibCall(),llvm::TargetLowering::expandUnalignedLoad(),llvm::TargetLowering::expandUnalignedStore(),llvm::TargetLowering::expandVECTOR_COMPRESS(),llvm::TargetLowering::expandVectorSplice(),LowerATOMIC_STORE(),llvm::SystemZTargetLowering::LowerCall(),llvm::LoongArchTargetLowering::LowerCall(),llvm::RISCVTargetLowering::LowerCall(),llvm::ARMTargetLowering::PerformMVEExtCombine(),llvm::ARMTargetLowering::PerformMVETruncCombine(),llvm::RISCVDAGToDAGISel::PreprocessISelDAG(), andllvm::X86TargetLowering::ReplaceNodeResults().
| inline |
Definition at line1874 of fileSelectionDAG.h.
Referencesllvm::SDDbgInfo::DbgBegin().
Referenced bydump(), andllvm::ScheduleDAGSDNodes::EmitSchedule().
| inline |
Definition at line1875 of fileSelectionDAG.h.
Referencesllvm::SDDbgInfo::DbgEnd().
Referenced bydump(), andllvm::ScheduleDAGSDNodes::EmitSchedule().
| inline |
Definition at line1884 of fileSelectionDAG.h.
Referencesllvm::SDDbgInfo::DbgLabelBegin().
Referenced byllvm::ScheduleDAGSDNodes::EmitSchedule().
| inline |
Definition at line1887 of fileSelectionDAG.h.
Referencesllvm::SDDbgInfo::DbgLabelEnd().
Referenced byllvm::ScheduleDAGSDNodes::EmitSchedule().
void SelectionDAG::DeleteNode | ( | SDNode * | N | ) |
Remove the specified node from the system.
This node must have no referrers.
Definition at line1095 of fileSelectionDAG.cpp.
ReferencesN.
Referenced byLegalize(), andllvm::SelectionDAGBuilder::LowerAsSTATEPOINT().
Check if a node exists without modifying its flags.
doesNodeExist -Check if a node exists without modifying its flags.
Definition at line11311 of fileSelectionDAG.cpp.
ReferencesAddNodeIDNode(),llvm::SDVTList::NumVTs, andllvm::SDVTList::VTs.
Referenced byllvm::TargetLowering::expandIntMINMAX(),foldAndOrOfSETCC(),performCSELCombine(), andllvm::TargetLowering::SimplifySetCC().
LLVM_DUMP_METHOD void SelectionDAG::dump | ( | ) | const |
Definition at line1038 of fileSelectionDAGDumper.cpp.
Referencesallnodes(),ByvalParmDbgBegin(),ByvalParmDbgEnd(),DbgBegin(),DbgEnd(),llvm::dbgs(),DumpNodes(),getNode(),getRoot(),llvm::make_range(),N,shouldPrintInline(), andVerboseDAGDumping.
Referenced byNewSDValueDbgMsg(),llvm::AMDGPUDAGToDAGISel::PreprocessISelDAG(), andllvm::HexagonDAGToDAGISel::PreprocessISelDAG().
LLVM_DUMP_METHOD void SelectionDAG::dumpDotGraph | ( | constTwine & | FileName, |
constTwine & | Title | ||
) |
Just dump dot graph to a user-provided path and title.
This doesn't open the dot viewer program and helps visualization when outside debugging session. FileName expects absolute path. If provided without any path separators then the file will be created in the current directory.Error will be emitted if the path is insane.
Definition at line171 of fileSelectionDAGPrinter.cpp.
Referencesllvm::dumpDotGraphToFile().
bool SelectionDAG::expandMultipleResultFPLibCall | ( | RTLIB::Libcall | LC, |
SDNode * | Node, | ||
SmallVectorImpl<SDValue > & | Results, | ||
std::optional<unsigned > | CallRetResNo ={} | ||
) |
Expands a node with multiple results to an FP or vector libcall.
The libcall is expected to take all the operands of theNode
followed by output pointers for each of the results.CallRetResNo
can be optionally set to indicate that one of the results comes from the libcall's return value.
Definition at line2550 of fileSelectionDAG.cpp.
ReferencescanFoldStoreIntoLibCallOutputPointers(),CreateStackTemporary(),llvm::StringRef::data(),DL,llvm::enumerate(),getBoolConstant(),getContext(),getDataLayout(),getEntryNode(),getExternalSymbol(),llvm::MachinePointerInfo::getFixedStack(),llvm::TargetLoweringBase::getLibcallCallingConv(),llvm::TargetLoweringBase::getLibcallName(),getLibInfo(),getLoad(),getMachineFunction(),getMergeValues(),getNode(),llvm::TargetLoweringBase::getPointerTy(),llvm::SDValue::getResNo(),getRoot(),llvm::Type::getScalarType(),llvm::TargetLoweringBase::getSetCCResultType(),llvm::EVT::getTypeForEVT(),llvm::PointerType::getUnqual(),llvm::SDValue::getValueType(),llvm::EVT::getVectorElementCount(),llvm::VecDesc::getVectorFnName(),llvm::TargetLibraryInfo::getVectorMappingInfo(),llvm::Type::getVoidTy(),llvm::VecDesc::isMasked(),llvm::ISD::isNormalStore(),llvm::EVT::isVector(),llvm::TargetLowering::LowerCallTo(),llvm::Masked,ReplaceAllUsesOfValueWith(),Results,llvm::TargetLowering::CallLoweringInfo::setChain(),llvm::TargetLowering::CallLoweringInfo::setDebugLoc(),llvm::TargetLowering::CallLoweringInfo::setLibCallee(),setRoot(), andllvm::ISD::TokenFactor.
Expand the specifiedISD::VAARG
node as the Legalize pass would.
Definition at line2695 of fileSelectionDAG.cpp.
Referencesllvm::ISD::ADD,llvm::ISD::AND,getConstant(),getContext(),getDataLayout(),getLoad(),llvm::TargetLoweringBase::getMinStackArgumentAlignment(),getNode(),llvm::TargetLoweringBase::getPointerTy(),getSignedConstant(),getStore(),getTargetLoweringInfo(),llvm::EVT::getTypeForEVT(),llvm::SDValue::getValue(), andllvm::SDValue::getValueType().
Expand the specifiedISD::VACOPY
node as the Legalize pass would.
Definition at line2729 of fileSelectionDAG.cpp.
ReferencesgetDataLayout(),getLoad(),llvm::TargetLoweringBase::getPointerTy(),getStore(),getTargetLoweringInfo(), andllvm::SDValue::getValue().
Referenced byLowerVACOPY().
void SelectionDAG::ExtractVectorElements | ( | SDValue | Op, |
SmallVectorImpl<SDValue > & | Args, | ||
unsigned | Start =0 , | ||
unsigned | Count =0 , | ||
EVT | EltVT =EVT() | ||
) |
Append the extracted elements from Start to Count out of the vector Op in Args.
If Count is 0, all of the elements will be extracted. The extracted elements will have typeEVT if it is provided, and otherwise their type will be Op's element type.
Definition at line13053 of fileSelectionDAG.cpp.
Referencesllvm::ISD::EXTRACT_VECTOR_ELT,getNode(),llvm::EVT::getVectorElementType(),getVectorIdxConstant(), andllvm::EVT::getVectorNumElements().
Referenced byadjustLoadValueTypeImpl(),llvm::TargetLowering::expandVecReduce(),llvm::TargetLowering::expandVecReduceSeq(),getDWordFromOffset(),llvm::AMDGPUTargetLowering::LowerCONCAT_VECTORS(),llvm::AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(),llvm::AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(),padEltsToUndef(),ReplaceLoadVector(),scalarizeBinOpOfSplats(),UnrollVectorOverflowOp(),unrollVectorShift(), andwidenVectorToPartType().
SDValue SelectionDAG::FoldConstantArithmetic | ( | unsigned | Opcode, |
constSDLoc & | DL, | ||
EVT | VT, | ||
ArrayRef<SDValue > | Ops, | ||
SDNodeFlags | Flags =SDNodeFlags() | ||
) |
Definition at line6672 of fileSelectionDAG.cpp.
Referencesllvm::APInt::abs(),llvm::ISD::ABS,llvm::all_of(),llvm::ISD::ANY_EXTEND,llvm::APInt::ashrInPlace(),assert(),llvm::ISD::BF16_TO_FP,llvm::APFloatBase::BFloat(),llvm::ISD::BITCAST,llvm::ISD::BITREVERSE,llvm::EVT::bitsGT(),llvm::EVT::bitsLT(),llvm::ISD::BSWAP,llvm::ISD::BUILD_VECTOR,llvm::ISD::BUILTIN_OP_END,llvm::APInt::byteSwap(),llvm::CallingConv::C,llvm::ISD::CONCAT_VECTORS,llvm::ISD::CONDCODE,llvm::ISD::Constant,llvm::ISD::ConstantFP,llvm::APFloat::convert(),llvm::APFloat::convertFromAPInt(),llvm::APInt::countl_zero(),llvm::APInt::countr_zero(),llvm::ISD::CTLZ,llvm::ISD::CTLZ_ZERO_UNDEF,llvm::ISD::CTPOP,llvm::ISD::CTTZ,llvm::ISD::CTTZ_ZERO_UNDEF,DL,llvm::ISD::FABS,llvm::ISD::FCEIL,llvm::ISD::FFLOOR,llvm::ISD::FNEG,foldConstantFPMath(),FoldSTEP_VECTOR(),FoldSymbolOffset(),FoldValue(),FoldValueWithUndef(),llvm::ISD::FP16_TO_FP,llvm::ISD::FP_EXTEND,llvm::ISD::FP_TO_BF16,llvm::ISD::FP_TO_FP16,llvm::ISD::FP_TO_SINT,llvm::ISD::FP_TO_UINT,llvm::ISD::FTRUNC,getBitcast(),llvm::APInt::getBitWidth(),llvm::TargetLoweringBase::getBooleanContents(),getBuildVector(),getConstant(),getConstantFP(),getContext(),getDataLayout(),llvm::TargetLoweringBase::getExtendForContent(),llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getFixedValue(),llvm::EVT::getFltSemantics(),getNode(),llvm::SDValue::getOpcode(),getOpcode(),llvm::EVT::getScalarSizeInBits(),llvm::EVT::getScalarType(),llvm::EVT::getSizeInBits(),getSplatVector(),getStepVector(),llvm::TargetLoweringBase::getTypeAction(),llvm::TargetLoweringBase::getTypeToTransformTo(),getUNDEF(),llvm::SDValue::getValueType(),getValueType(),llvm::EVT::getVectorElementCount(),llvm::EVT::getVectorNumElements(),llvm::APInt::getZero(),I,llvm::APFloatBase::IEEEdouble(),llvm::APFloatBase::IEEEhalf(),llvm::APFloatBase::IEEEquad(),llvm::APFloatBase::IEEEsingle(),ignored(),llvm::ISD::isBuildVectorOfConstantSDNodes(),llvm::TargetLoweringBase::isCommutativeBinOp(),llvm::ISD::isConstantSplatVector(),llvm::EVT::isFixedLengthVector(),llvm::EVT::isInteger(),llvm::DataLayout::isLittleEndian(),llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isScalable(),llvm::TargetLoweringBase::isSExtCheaperThanZExt(),llvm::SDValue::isUndef(),isUndef(),llvm::EVT::isVector(),llvm::ISD::MUL,NewNodesMustHaveLegalTypes,NewSDValueDbgMsg(),llvm::APFloatBase::opInexact,llvm::APFloatBase::opInvalidOp,llvm::APFloatBase::opOK,llvm::peekThroughBitcasts(),llvm::APInt::popcount(),llvm::SmallVectorTemplateBase< T, bool >::push_back(),llvm::BuildVectorSDNode::recastRawBits(),llvm::APInt::reverseBits(),llvm::APFloatBase::rmNearestTiesToEven,llvm::APFloatBase::rmTowardNegative,llvm::APFloatBase::rmTowardPositive,llvm::APFloatBase::rmTowardZero,llvm::ISD::SETCC,llvm::APInt::sextOrTrunc(),llvm::ISD::SHL,llvm::ISD::SIGN_EXTEND,llvm::ISD::SIGN_EXTEND_INREG,llvm::ISD::SINT_TO_FP,llvm::ArrayRef< T >::size(),llvm::SmallVectorBase< Size_T >::size(),llvm::ISD::SPLAT_VECTOR,llvm::ISD::STEP_VECTOR,llvm::APInt::trunc(),llvm::ISD::TRUNCATE,llvm::TargetLoweringBase::TypeLegal,llvm::ISD::UINT_TO_FP,llvm::ISD::ZERO_EXTEND, andllvm::APInt::zextOrTrunc().
Referenced byfoldAddSubOfSignBit(),foldBinOpIntoSelectIfProfitable(),getNode(),getTargetVShiftByConstNode(),getTargetVShiftNode(),LowerRotate(),PromoteMaskArithmetic(),llvm::TargetLowering::SimplifyDemandedBits(), andllvm::TargetLowering::SimplifyDemandedVectorElts().
SDValue SelectionDAG::foldConstantFPMath | ( | unsigned | Opcode, |
constSDLoc & | DL, | ||
EVT | VT, | ||
ArrayRef<SDValue > | Ops | ||
) |
Fold floating-point operations when all operands are constants and/or undefined.
Definition at line7097 of fileSelectionDAG.cpp.
Referencesllvm::APFloat::add(),llvm::APFloat::convert(),llvm::APFloat::copySign(),llvm::APFloat::divide(),DL,llvm::ISD::FADD,llvm::ISD::FCOPYSIGN,llvm::ISD::FDIV,llvm::ISD::FMAXIMUM,llvm::ISD::FMAXIMUMNUM,llvm::ISD::FMAXNUM,llvm::ISD::FMINIMUM,llvm::ISD::FMINIMUMNUM,llvm::ISD::FMINNUM,llvm::ISD::FMUL,llvm::ISD::FP_ROUND,llvm::ISD::FREM,llvm::ISD::FSUB,getConstantFP(),llvm::EVT::getFltSemantics(),llvm::APFloat::getNaN(),getUNDEF(),llvm::ConstantFPSDNode::getValueAPF(),llvm::isConstOrConstSplatFP(),llvm::SDValue::isUndef(),llvm::maximum(),llvm::maximumnum(),llvm::maxnum(),llvm::minimum(),llvm::minimumnum(),llvm::minnum(),llvm::APFloat::mod(),llvm::APFloat::multiply(),llvm::APFloatBase::rmNearestTiesToEven,llvm::ArrayRef< T >::size(), andllvm::APFloat::subtract().
Referenced byFoldConstantArithmetic().
Constant fold a setcc to true or false.
Definition at line2813 of fileSelectionDAG.cpp.
Referencesassert(),llvm::APFloatBase::cmpEqual,llvm::APFloatBase::cmpGreaterThan,llvm::APFloatBase::cmpLessThan,llvm::APFloatBase::cmpUnordered,llvm::ICmpInst::compare(),Cond,getBoolConstant(),llvm::TargetLoweringBase::getBooleanContents(),getConstant(),llvm::getICmpCondCode(),llvm::EVT::getScalarType(),getSetCC(),llvm::ISD::getSetCCSwappedOperands(),llvm::EVT::getSimpleVT(),getUNDEF(),llvm::ISD::getUnorderedFlavor(),llvm::SDValue::getValueType(),llvm::TargetLoweringBase::isCondCodeLegal(),llvm::EVT::isFloatingPoint(),llvm::EVT::isInteger(),llvm::EVT::isSimple(),llvm::ISD::isTrueWhenEqual(),llvm::SDValue::isUndef(),llvm_unreachable,llvm::ISD::SETEQ,llvm::ISD::SETFALSE,llvm::ISD::SETFALSE2,llvm::ISD::SETGE,llvm::ISD::SETGT,llvm::ISD::SETLE,llvm::ISD::SETLT,llvm::ISD::SETNE,llvm::ISD::SETO,llvm::ISD::SETOEQ,llvm::ISD::SETOGE,llvm::ISD::SETOGT,llvm::ISD::SETOLE,llvm::ISD::SETOLT,llvm::ISD::SETONE,llvm::ISD::SETTRUE,llvm::ISD::SETTRUE2,llvm::ISD::SETUEQ,llvm::ISD::SETUGE,llvm::ISD::SETUGT,llvm::ISD::SETULE,llvm::ISD::SETULT,llvm::ISD::SETUNE,llvm::ISD::SETUO, andllvm::TargetLoweringBase::UndefinedBooleanContent.
Referenced bygetNode(), andllvm::TargetLowering::SimplifySetCC().
SDValue SelectionDAG::FoldSymbolOffset | ( | unsigned | Opcode, |
EVT | VT, | ||
constGlobalAddressSDNode * | GA, | ||
constSDNode * | N2 | ||
) |
Definition at line6627 of fileSelectionDAG.cpp.
Referencesllvm::ISD::ADD,llvm::GlobalAddressSDNode::getGlobal(),getGlobalAddress(),llvm::GlobalAddressSDNode::getOffset(),llvm::SDNode::getOpcode(),llvm::ISD::GlobalAddress,llvm::TargetLowering::isOffsetFoldingLegal(),llvm::Offset, andllvm::ISD::SUB.
Referenced byFoldConstantArithmetic().
SDValue SelectionDAG::getAddrSpaceCast | ( | constSDLoc & | dl, |
EVT | VT, | ||
SDValue | Ptr, | ||
unsigned | SrcAS, | ||
unsigned | DestAS | ||
) |
Return anAddrSpaceCastSDNode.
Definition at line2440 of fileSelectionDAG.cpp.
ReferencesAddNodeIDNode(),llvm::ISD::ADDRSPACECAST,llvm::SDLoc::getDebugLoc(),llvm::SDLoc::getIROrder(),getVTList(),N, andPtr.
Referenced bycombineLoad(),combineStore(),llvm::SITargetLowering::LowerFormalArguments(),llvm::NVPTXTargetLowering::LowerSTACKRESTORE(),llvm::NVPTXTargetLowering::LowerSTACKSAVE(), andUnrollVectorOp().
SDValue SelectionDAG::getAllOnesConstant | ( | constSDLoc & | DL, |
EVT | VT, | ||
bool | IsTarget =false , | ||
bool | IsOpaque =false | ||
) |
Definition at line1800 of fileSelectionDAG.cpp.
ReferencesDL,llvm::APInt::getAllOnes(),getConstant(), andllvm::EVT::getScalarSizeInBits().
Referenced bycombineAddOrSubToADCOrSBB(),combineAndLoadToBZHI(),combineBitcastToBoolVector(),combineMinMaxReduction(),combinePTESTCC(),combineSelectToBinOp(),combineSetCC(),combineSetCCMOVMSK(),combineVectorCompare(),combineVectorShiftImm(),llvm::TargetLowering::expandAddSubSat(),llvm::TargetLowering::expandCMP(),llvm::TargetLowering::expandRoundInexactToOdd(),llvm::TargetLowering::expandVPCTLZ(),llvm::TargetLowering::expandVPCTTZ(),expandVPFunnelShift(),foldBoolSelectToLogic(),foldSubCtlzNot(),foldXorTruncShiftIntoCmp(),getBoolConstant(),llvm::VECustomDAG::getConstantMask(),getNeutralElement(),getNode(),getNOT(),getOnesVector(),getTargetVShiftNode(),getWideningInterleave(),isConditionalZeroOrAllOnes(),LowerADDSUBO_CARRY(),LowerBUILD_VECTORvXi1(),llvm::AMDGPUTargetLowering::LowerSDIVREM(),LowerShift(),LowerShiftByScalarImmediate(),LowerShiftByScalarVariable(),lowerShuffleAsBitBlend(),lowerShuffleAsBitMask(),LowerSIGN_EXTEND_Mask(),LowerVectorAllEqual(),LowerVSETCC(),MatchVectorAllEqualTest(),performAddCSelIntoCSinc(),llvm::R600TargetLowering::PerformDAGCombine(),llvm::RISCVTargetLowering::PerformDAGCombine(),llvm::RISCVDAGToDAGISel::selectShiftMask(),llvm::TargetLowering::SimplifyDemandedBits(),llvm::TargetLowering::SimplifyDemandedVectorElts(),llvm::TargetLowering::SimplifySetCC(),simplifySetCCWithCTPOP(), andllvm::VPMatchContext::VPMatchContext().
Convert Op, which must be of integer type, to the integer type VT, by either any-extending or truncating it.
Definition at line1496 of fileSelectionDAG.cpp.
Referencesllvm::ISD::ANY_EXTEND,llvm::EVT::bitsGT(),DL,getNode(), andllvm::ISD::TRUNCATE.
Referenced bycombineBitcast(),combineExtractVectorElt(),combineSCALAR_TO_VECTOR(),combineStore(),combineToExtendBoolVectorInReg(),createMMXBuildVector(),llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemset(),llvm::WebAssemblySelectionDAGInfo::EmitTargetCodeForMemset(),getBitcastedAnyExtOrTrunc(),getCopyFromPartsVector(),getCopyToPartsVector(),getExtOrTrunc(),getNode(),getVectorBitwiseReduce(),LowerBuildVectorAsInsert(),LowerBuildVectorv16i8(),LowerFunnelShift(),lowerLaneOp(),LowerMUL(),LowervXi8MulWithUNPCK(),performBuildShuffleExtendCombine(),PerformVSELECTCombine(), andllvm::HexagonTargetLowering::ReplaceNodeResults().
Return anAssertAlignSDNode.
Definition at line7180 of fileSelectionDAG.cpp.
ReferencesA,AddNodeIDNode(),assert(),llvm::ISD::AssertAlign,DL,llvm::SDValue::getValueType(),getVTList(),llvm::EVT::isInteger(),N, andNewSDValueDbgMsg().
SDValue SelectionDAG::getAtomic | ( | unsigned | Opcode, |
constSDLoc & | dl, | ||
EVT | MemVT, | ||
EVT | VT, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
MachineMemOperand * | MMO | ||
) |
Gets a node for an atomic op, produces result and chain and takes 1 operand.
Definition at line9023 of fileSelectionDAG.cpp.
Referencesassert(),llvm::ISD::ATOMIC_LOAD,getAtomic(),getVTList(), andPtr.
SDValue SelectionDAG::getAtomic | ( | unsigned | Opcode, |
constSDLoc & | dl, | ||
EVT | MemVT, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
SDValue | Val, | ||
MachineMemOperand * | MMO | ||
) |
Gets a node for an atomic op, produces result (if relevant) and chain and takes 2 operands.
Definition at line8997 of fileSelectionDAG.cpp.
Referencesassert(),llvm::ISD::ATOMIC_LOAD_ADD,llvm::ISD::ATOMIC_LOAD_AND,llvm::ISD::ATOMIC_LOAD_CLR,llvm::ISD::ATOMIC_LOAD_FADD,llvm::ISD::ATOMIC_LOAD_FMAX,llvm::ISD::ATOMIC_LOAD_FMIN,llvm::ISD::ATOMIC_LOAD_FSUB,llvm::ISD::ATOMIC_LOAD_MAX,llvm::ISD::ATOMIC_LOAD_MIN,llvm::ISD::ATOMIC_LOAD_NAND,llvm::ISD::ATOMIC_LOAD_OR,llvm::ISD::ATOMIC_LOAD_SUB,llvm::ISD::ATOMIC_LOAD_UDEC_WRAP,llvm::ISD::ATOMIC_LOAD_UINC_WRAP,llvm::ISD::ATOMIC_LOAD_UMAX,llvm::ISD::ATOMIC_LOAD_UMIN,llvm::ISD::ATOMIC_LOAD_USUB_COND,llvm::ISD::ATOMIC_LOAD_USUB_SAT,llvm::ISD::ATOMIC_LOAD_XOR,llvm::ISD::ATOMIC_STORE,llvm::ISD::ATOMIC_SWAP,getAtomic(),llvm::SDValue::getValueType(),getVTList(), andPtr.
Referenced bycombineSetCCAtomicArith(),getAtomic(),getAtomicCmpSwap(),LowerATOMIC_STORE(),llvm::VETargetLowering::lowerATOMIC_SWAP(),lowerAtomicArith(), andtryToFoldExtOfAtomicLoad().
SDValue SelectionDAG::getAtomic | ( | unsigned | Opcode, |
constSDLoc & | dl, | ||
EVT | MemVT, | ||
SDVTList | VTList, | ||
ArrayRef<SDValue > | Ops, | ||
MachineMemOperand * | MMO | ||
) |
Gets a node for an atomic op, produces result and chain and takes N operands.
Definition at line8962 of fileSelectionDAG.cpp.
ReferencesAddNodeIDNode(),llvm::MachinePointerInfo::getAddrSpace(),llvm::SDLoc::getDebugLoc(),llvm::MachineMemOperand::getFlags(),llvm::SDLoc::getIROrder(),llvm::MachineMemOperand::getPointerInfo(),llvm::EVT::getRawBits(), andN.
SDValue SelectionDAG::getAtomicCmpSwap | ( | unsigned | Opcode, |
constSDLoc & | dl, | ||
EVT | MemVT, | ||
SDVTList | VTs, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
SDValue | Cmp, | ||
SDValue | Swp, | ||
MachineMemOperand * | MMO | ||
) |
Gets a node for an atomic cmpxchg op.
There are two valid Opcodes. ISD::ATOMIC_CMO_SWAP produces the value loaded and a chain result.ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS produces the value loaded, a success flag (initially i1), and a chain.
Definition at line8985 of fileSelectionDAG.cpp.
Referencesassert(),llvm::ISD::ATOMIC_CMP_SWAP,llvm::ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS,getAtomic(),llvm::SDValue::getValueType(), andPtr.
SDValue SelectionDAG::getAtomicMemcpy | ( | SDValue | Chain, |
constSDLoc & | dl, | ||
SDValue | Dst, | ||
SDValue | Src, | ||
SDValue | Size, | ||
Type * | SizeTy, | ||
unsigned | ElemSz, | ||
bool | isTailCall, | ||
MachinePointerInfo | DstPtrInfo, | ||
MachinePointerInfo | SrcPtrInfo | ||
) |
Definition at line8667 of fileSelectionDAG.cpp.
ReferencesgetContext(),getDataLayout(),getExternalSymbol(),llvm::DataLayout::getIntPtrType(),llvm::TargetLoweringBase::getLibcallCallingConv(),llvm::TargetLoweringBase::getLibcallName(),llvm::RTLIB::getMEMCPY_ELEMENT_UNORDERED_ATOMIC(),llvm::TargetLoweringBase::getPointerTy(),llvm::Type::getVoidTy(),llvm::TargetLowering::LowerCallTo(),llvm::report_fatal_error(),llvm::TargetLowering::CallLoweringInfo::setChain(),llvm::TargetLowering::CallLoweringInfo::setDebugLoc(),llvm::TargetLowering::CallLoweringInfo::setDiscardResult(),llvm::TargetLowering::CallLoweringInfo::setLibCallee(),llvm::TargetLowering::CallLoweringInfo::setTailCall(), andSize.
SDValue SelectionDAG::getAtomicMemmove | ( | SDValue | Chain, |
constSDLoc & | dl, | ||
SDValue | Dst, | ||
SDValue | Src, | ||
SDValue | Size, | ||
Type * | SizeTy, | ||
unsigned | ElemSz, | ||
bool | isTailCall, | ||
MachinePointerInfo | DstPtrInfo, | ||
MachinePointerInfo | SrcPtrInfo | ||
) |
Definition at line8784 of fileSelectionDAG.cpp.
ReferencesgetContext(),getDataLayout(),getExternalSymbol(),llvm::DataLayout::getIntPtrType(),llvm::TargetLoweringBase::getLibcallCallingConv(),llvm::TargetLoweringBase::getLibcallName(),llvm::RTLIB::getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(),llvm::TargetLoweringBase::getPointerTy(),llvm::Type::getVoidTy(),llvm::TargetLowering::LowerCallTo(),llvm::report_fatal_error(),llvm::TargetLowering::CallLoweringInfo::setChain(),llvm::TargetLowering::CallLoweringInfo::setDebugLoc(),llvm::TargetLowering::CallLoweringInfo::setDiscardResult(),llvm::TargetLowering::CallLoweringInfo::setLibCallee(),llvm::TargetLowering::CallLoweringInfo::setTailCall(), andSize.
SDValue SelectionDAG::getAtomicMemset | ( | SDValue | Chain, |
constSDLoc & | dl, | ||
SDValue | Dst, | ||
SDValue | Value, | ||
SDValue | Size, | ||
Type * | SizeTy, | ||
unsigned | ElemSz, | ||
bool | isTailCall, | ||
MachinePointerInfo | DstPtrInfo | ||
) |
Definition at line8922 of fileSelectionDAG.cpp.
ReferencesgetContext(),getDataLayout(),getExternalSymbol(),llvm::Type::getInt8Ty(),llvm::DataLayout::getIntPtrType(),llvm::TargetLoweringBase::getLibcallCallingConv(),llvm::TargetLoweringBase::getLibcallName(),llvm::RTLIB::getMEMSET_ELEMENT_UNORDERED_ATOMIC(),llvm::TargetLoweringBase::getPointerTy(),llvm::Type::getVoidTy(),llvm::TargetLowering::LowerCallTo(),llvm::report_fatal_error(),llvm::TargetLowering::CallLoweringInfo::setChain(),llvm::TargetLowering::CallLoweringInfo::setDebugLoc(),llvm::TargetLowering::CallLoweringInfo::setDiscardResult(),llvm::TargetLowering::CallLoweringInfo::setLibCallee(),llvm::TargetLowering::CallLoweringInfo::setTailCall(), andSize.
SDValue SelectionDAG::getBasicBlock | ( | MachineBasicBlock * | MBB | ) |
Definition at line2024 of fileSelectionDAG.cpp.
ReferencesAddNodeIDNode(),llvm::ISD::BasicBlock,getVTList(),MBB, andN.
Referenced byAddNodeIDCustom(),llvm::SelectionDAGBuilder::getValueImpl(),llvm::SelectionDAGBuilder::visitBitTestCase(),llvm::SelectionDAGBuilder::visitBitTestHeader(),llvm::SelectionDAGBuilder::visitJumpTableHeader(),llvm::SelectionDAGBuilder::visitSPDescriptorParent(), andllvm::SelectionDAGBuilder::visitSwitchCase().
| inline |
Definition at line513 of fileSelectionDAG.h.
Return a bitcast using theSDLoc of the value operand, and casting to the provided type.
Use getNode to set a customSDLoc.
Definition at line2433 of fileSelectionDAG.cpp.
Referencesllvm::ISD::BITCAST, andgetNode().
Referenced byaddShuffleForVecExtend(),adjustBitcastSrcVectorSSE1(),canonicalizeBitSelect(),canonicalizeLaneShuffleWithRepeatedOps(),canonicalizeShuffleMaskWithHorizOp(),canonicalizeShuffleVectorByLane(),canonicalizeShuffleWithOp(),combineAnd(),combineAndMaskToShift(),combineAndNotIntoANDNP(),combineAndnp(),combineAndShuffleNot(),combineArithReduction(),combineBasicSADPattern(),combineBitcast(),combineBitcastToBoolVector(),combineBitcastvxi1(),combineBitOpWithMOVMSK(),combineBitOpWithPACK(),combineBitOpWithShift(),combineBITREVERSE(),combineBlendOfPermutes(),combineBROADCAST_LOAD(),combineCastedMaskArithmetic(),combineCMP(),combineCompareEqual(),combineCONCAT_VECTORS(),combineConcatVectorOfExtracts(),combineConcatVectorOfScalars(),combineConcatVectorOps(),combineConstantPoolLoads(),combineCVTP2I_CVTTP2I(),combineCVTPH2PS(),combineEXTEND_VECTOR_INREG(),combineEXTRACT_SUBVECTOR(),combineExtractVectorElt(),combineExtractWithShuffle(),combineFaddCFmul(),combineFMulcFCMulc(),combineFneg(),combineFP_EXTEND(),combineFP_ROUND(),combineHorizOpWithShuffle(),combineLoad(),combineLogicBlendIntoConditionalNegate(),combineLogicBlendIntoPBLENDV(),combineMinMaxReduction(),combineMOVMSK(),combineMulToPMADDWD(),combineOr(),combinePMULDQ(),combinePMULH(),combinePredicateReduction(),combinePTESTCC(),combineRedundantDWordShuffle(),combineSCALAR_TO_VECTOR(),combineScalarAndWithMaskSetcc(),combineSelect(),combineSetCCMOVMSK(),combineShuffleOfBitcast(),combineShuffleToAnyExtendVectorInreg(),combineShuffleToZeroExtendVectorInReg(),combineSIntToFP(),combineStore(),combineTargetShuffle(),combineToExtendBoolVectorInReg(),combineToFPTruncExtElt(),combineTruncationShuffle(),combineVectorCompareAndMaskUnaryOp(),combineVectorHADDSUB(),combineVectorPack(),combineVectorShiftImm(),combineVectorSizedSetCCEquality(),combineVPDPBUSDPattern(),combineVSelectWithAllOnesOrZeros(),combineX86INT_TO_FP(),combineX86ShuffleChain(),combineX86ShuffleChainWithExtract(),combineX86ShufflesConstants(),combineX86ShufflesRecursively(),combineXor(),constructDup(),convertIntLogicToFPLogic(),convertShiftLeftToScale(),createMMXBuildVector(),EltsFromConsecutiveLoads(),expandBitCastF128ToI128(),expandBitCastI128ToF128(),llvm::TargetLowering::expandIS_FPCLASS(),llvm::TargetLowering::expandRoundInexactToOdd(),llvm::TargetLowering::expandUINT_TO_FP(),ExtractBitFromMaskVector(),FixupMMXIntrinsicTypes(),FoldConstantArithmetic(),FoldIntToFPToInt(),GeneratePerfectShuffle(),generateSToVPermutedForVecShuffle(),getAVX2GatherNode(),getBitcastedAnyExtOrTrunc(),getBitcastedSExtOrTrunc(),getBitcastedZExtOrTrunc(),getBuildDwordsVector(),getCanonicalConstSplat(),getConstVector(),getCopyFromPartsVector(),getCopyToPartsVector(),getDataClassTest(),getDeinterleaveShiftAndTrunc(),getFlagsOfCmpZeroFori1(),getMaskNode(),getMemsetValue(),llvm::X86TargetLowering::getNegatedExpression(),getOnesVector(),getPack(),getScalarMaskingNode(),getScalarValueForVectorElement(),getTargetVShiftByConstNode(),getTargetVShiftNode(),getv64i1Argument(),getVCIXISDNodeWCHAIN(),getVectorBitwiseReduce(),getVShift(),getWideningInterleave(),getWideningSpread(),getZeroVector(),llvm::TargetLowering::IncrementMemoryAddress(),isHorizontalBinOp(),IsNOT(),llvm::RISCVTargetLowering::joinRegisterPartsIntoValue(),llvm::SystemZTargetLowering::joinRegisterPartsIntoValue(),lower128BitShuffle(),lower256BitShuffle(),lower512BitShuffle(),LowerATOMIC_STORE(),LowerAVXExtend(),LowerBITCAST(),llvm::HexagonTargetLowering::LowerBITCAST(),LowerBITREVERSE(),LowerBITREVERSE_XOP(),lowerBitreverseShuffle(),lowerBUILD_VECTOR(),LowerBUILD_VECTORvXbf16(),LowerBUILD_VECTORvXi1(),lowerBuildVectorAsBroadcast(),LowerBuildVectorAsInsert(),lowerBuildVectorOfConstants(),LowerBuildVectorv16i8(),LowerBuildVectorv4x32(),llvm::HexagonTargetLowering::LowerCall(),LowerCTPOP(),LowerEXTEND_VECTOR_INREG(),llvm::VETargetLowering::lowerEXTRACT_VECTOR_ELT(),LowerEXTRACT_VECTOR_ELT_SSE4(),LowerFMINIMUM_FMAXIMUM(),llvm::SITargetLowering::LowerFormalArguments(),LowerFunnelShift(),LowerHorizontalByteSum(),llvm::VETargetLowering::lowerINSERT_VECTOR_ELT(),lowerLaneOp(),LowerLoad(),lowerMasksToReg(),LowerMUL(),LowerMULH(),llvm::RISCVTargetLowering::LowerOperation(),lowerRegToMasks(),llvm::HexagonTargetLowering::LowerReturn(),LowerRotate(),LowerSCALAR_TO_VECTOR(),LowerShift(),LowerShiftByScalarImmediate(),LowerShiftByScalarVariable(),lowerShuffleAsBitMask(),lowerShuffleAsBitRotate(),lowerShuffleAsBlend(),lowerShuffleAsBlendOfPSHUFBs(),lowerShuffleAsBroadcast(),lowerShuffleAsByteRotate(),lowerShuffleAsByteRotateAndPermute(),lowerShuffleAsByteShiftMask(),lowerShuffleAsElementInsertion(),lowerShuffleAsLanePermuteAndShuffle(),lowerShuffleAsPermuteAndUnpack(),lowerShuffleAsShift(),lowerShuffleAsSpecificZeroOrAnyExtend(),lowerShuffleAsVTRUNC(),lowerShuffleAsVTRUNCAndUnpack(),lowerShuffleAsZeroOrAnyExtend(),lowerShuffleWithPACK(),lowerShuffleWithPSHUFB(),lowerShuffleWithUNPCK256(),lowerShuffleWithVPMOV(),LowerStore(),LowerTruncateVecI1(),llvm::AMDGPUTargetLowering::LowerUDIVREM64(),LowerUINT_TO_FP_i32(),LowerUINT_TO_FP_i64(),lowerUINT_TO_FP_v2i32(),lowerUINT_TO_FP_vXi32(),lowerV16F32Shuffle(),lowerV16I32Shuffle(),lowerV16I8Shuffle(),lowerV2I64Shuffle(),lowerV4F32Shuffle(),lowerV4I32Shuffle(),lowerV4I64Shuffle(),lowerV8F16Shuffle(),lowerV8F32Shuffle(),lowerV8I16GeneralSingleInputShuffle(),lowerV8I16Shuffle(),lowerV8I32Shuffle(),lowerV8I64Shuffle(),llvm::HexagonTargetLowering::LowerVECTOR_SHUFFLE(),lowerVECTOR_SHUFFLE(),lowerVECTOR_SHUFFLEAsRotate(),lowerVECTOR_SHUFFLEAsVSlide1(),LowerVECTOR_SHUFFLEUsingMovs(),LowerVectorAllEqual(),LowerVectorCTLZInRegLUT(),LowerVectorCTPOP(),lowerVectorIntrinsicScalars(),LowerVectorMatch(),LowerVSETCC(),LowervXi8MulWithUNPCK(),lowerX86FPLogicOp(),matchPERM(),narrowExtractedVectorBinOp(),narrowExtractedVectorSelect(),packImage16bitOpsToDwords(),Passv64i1ArgInRegs(),performCONCAT_VECTORSCombine(),performConcatVectorsCombine(),llvm::RISCVTargetLowering::PerformDAGCombine(),performUzpCombine(),performVECTOR_SHUFFLECombine(),processVCIXOperands(),llvm::AArch64TargetLowering::ReconstructShuffle(),reduceBuildVecToShuffleWithZero(),reduceMaskedLoadToScalarLoad(),reduceMaskedStoreToScalarStore(),reduceVMULWidth(),llvm::RISCVTargetLowering::ReplaceNodeResults(),llvm::X86TargetLowering::ReplaceNodeResults(),scalarizeVectorStore(),llvm::TargetLowering::SimplifyDemandedBits(),llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(),llvm::TargetLowering::SimplifyDemandedVectorElts(),llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(),llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetShuffle(),llvm::TargetLowering::SimplifyMultipleUseDemandedBits(),llvm::X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode(),splitAndLowerShuffle(),llvm::RISCVTargetLowering::splitValueIntoRegisterParts(),llvm::SystemZTargetLowering::splitValueIntoRegisterParts(),takeInexpensiveLog2(),truncateVectorWithNARROW(),truncateVectorWithPACK(),tryWidenMaskForShuffle(),llvm::X86TargetLowering::visitMaskedLoad(), andllvm::X86TargetLowering::visitMaskedStore().
Convert Op, which must be of integer type, to the integer type VT, by first bitcasting (from potential vector) to corresponding scalar type then either any-extending or truncating it.
Definition at line1514 of fileSelectionDAG.cpp.
Referencesassert(),DL,getAnyExtOrTrunc(),getBitcast(),llvm::EVT::getIntegerVT(),llvm::SDValue::getValueType(),llvm::EVT::isVector(), andSize.
Referenced bygetDWordFromOffset(), andmatchPERM().
Convert Op, which must be of integer type, to the integer type VT, by first bitcasting (from potential vector) to corresponding scalar type then either sign-extending or truncating it.
Definition at line1529 of fileSelectionDAG.cpp.
Referencesassert(),DL,getBitcast(),llvm::MVT::getIntegerVT(),getSExtOrTrunc(),llvm::SDValue::getValueType(),llvm::EVT::isVector(), andSize.
Convert Op, which must be of integer type, to the integer type VT, by first bitcasting (from potential vector) to corresponding scalar type then either zero-extending or truncating it.
Definition at line1544 of fileSelectionDAG.cpp.
Referencesassert(),DL,getBitcast(),llvm::MVT::getIntegerVT(),llvm::SDValue::getValueType(),getZExtOrTrunc(),llvm::EVT::isVector(), andSize.
SDValue SelectionDAG::getBlockAddress | ( | constBlockAddress * | BA, |
EVT | VT, | ||
int64_t | Offset =0 , | ||
bool | isTarget =false , | ||
unsigned | TargetFlags =0 | ||
) |
Definition at line2382 of fileSelectionDAG.cpp.
ReferencesAddNodeIDNode(),llvm::ISD::BlockAddress,getVTList(),N,llvm::Offset, andllvm::ISD::TargetBlockAddress.
Referenced bygetTargetBlockAddress(),llvm::SelectionDAGBuilder::getValueImpl(), andllvm::LanaiTargetLowering::LowerBlockAddress().
Create a true or false constant of typeVT
using the target's BooleanContent for typeOpVT
.
Definition at line1651 of fileSelectionDAG.cpp.
ReferencesDL,getAllOnesConstant(),llvm::TargetLoweringBase::getBooleanContents(),getConstant(),llvm_unreachable,llvm::TargetLoweringBase::UndefinedBooleanContent,llvm::TargetLoweringBase::ZeroOrNegativeOneBooleanContent, andllvm::TargetLoweringBase::ZeroOrOneBooleanContent.
Referenced byllvm::TargetLowering::expandIS_FPCLASS(),expandMultipleResultFPLibCall(),FoldSetCC(),getDataClassTest(),getLogicalNOT(),getVPLogicalNOT(),performSETCCCombine(),llvm::TargetLowering::SimplifySetCC(), andUnrollVectorOverflowOp().
Convert Op, which must be of integer type, to the integer type VT, by using an extension appropriate for the target's BooleanContent for type OpVT or truncating it.
Definition at line1559 of fileSelectionDAG.cpp.
Referencesllvm::EVT::bitsLE(),llvm::TargetLoweringBase::getBooleanContents(),llvm::TargetLoweringBase::getExtendForContent(),getNode(), andllvm::ISD::TRUNCATE.
Referenced bycombineCarryDiamond(),combineSelectAsExtAnd(),llvm::TargetLowering::expandFP_TO_UINT(),llvm::TargetLowering::expandSADDSUBO(),llvm::TargetLowering::expandUADDSUBO(), andllvm::TargetLowering::SimplifySetCC().
Return anISD::BUILD_VECTOR node.
The number of elements in VT, which must be a vector type, must match the number of operands in Ops. The operands must have the same type as (or, for integers, a type wider than) VT's element type.
Definition at line866 of fileSelectionDAG.h.
Referencesllvm::ISD::BUILD_VECTOR,DL, andgetNode().
Return anISD::BUILD_VECTOR node.
The number of elements in VT, which must be a vector type, must match the number of operands in Ops. The operands must have the same type as (or, for integers, a type wider than) VT's element type.
Definition at line857 of fileSelectionDAG.h.
Referencesllvm::ISD::BUILD_VECTOR,DL, andgetNode().
Referenced byadjustLoadValueTypeImpl(),llvm::SparcTargetLowering::bitcastConstantFPToInt(),BuildExactSDIV(),BuildExactUDIV(),buildScalarToVector(),llvm::TargetLowering::BuildSDIV(),llvm::TargetLowering::BuildUDIV(),combineConcatVectorOfScalars(),combineEXTEND_VECTOR_INREG(),combineEXTRACT_SUBVECTOR(),combineShuffleOfScalars(),combineStore(),combineToExtendBoolVectorInReg(),combineX86ShuffleChain(),CompactSwizzlableVector(),convertLocVTToValVT(),convertShiftLeftToScale(),ExtendToType(),extractSubVector(),foldCONCAT_VECTORS(),FoldConstantArithmetic(),GenerateFixedLengthSVETBL(),GenerateTBL(),getBuildDwordsVector(),getBuildVectorSplat(),getConstant(),getConstVector(),getCopyFromPartsVector(),getDWordFromOffset(),getGeneralPermuteNode(),getGFNICtrlMask(),llvm::TargetLowering::getNegatedExpression(),getStepVector(),getTargetVShiftNode(),llvm::SelectionDAGBuilder::getValueImpl(),getVectorShuffle(),incDecVectorConstant(),LowerBITREVERSE(),LowerBITREVERSE_XOP(),lowerBUILD_VECTOR(),lowerBuildVectorOfConstants(),lowerBuildVectorToBitOp(),LowerBuildVectorv4x32(),lowerBuildVectorViaDominantValues(),lowerBuildVectorViaPacking(),llvm::AMDGPUTargetLowering::LowerCONCAT_VECTORS(),lowerDisjointIndicesShuffle(),llvm::AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(),llvm::SITargetLowering::LowerFormalArguments(),llvm::AMDGPUTargetLowering::LowerFP_TO_INT64(),llvm::AMDGPUTargetLowering::LowerFTRUNC(),lowerINT_TO_FP_vXi64(),lowerLaneOp(),lowerMSABinaryBitImmIntr(),lowerMSASplatZExt(),LowerMUL(),LowerShift(),lowerShuffleAsBitBlend(),lowerShuffleAsBitMask(),lowerShuffleAsBlend(),lowerShuffleAsBlendOfPSHUFBs(),lowerShuffleAsSpecificZeroOrAnyExtend(),lowerShuffleWithPSHUFB(),llvm::AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(),LowerTruncateVectorStore(),llvm::AMDGPUTargetLowering::LowerUDIVREM64(),lowerV16I8Shuffle(),lowerV8I16Shuffle(),lowerVECTOR_SHUFFLE(),lowerVECTOR_SHUFFLE_VSHF(),lowerVECTOR_SHUFFLE_VSHUF(),lowerVECTOR_SHUFFLE_XVSHUF(),LowerVECTOR_SHUFFLEv8i8(),LowerVectorCTLZInRegLUT(),LowerVectorCTPOPInRegLUT(),LowervXi8MulWithUNPCK(),NormalizeBuildVector(),packImage16bitOpsToDwords(),padEltsToUndef(),performBUILD_VECTORCombine(),PerformBUILD_VECTORCombine(),performConcatVectorsCombine(),llvm::AMDGPUTargetLowering::PerformDAGCombine(),llvm::R600TargetLowering::PerformDAGCombine(),llvm::RISCVTargetLowering::PerformDAGCombine(),llvm::ARMTargetLowering::PerformMVETruncCombine(),llvm::AMDGPUTargetLowering::performShlCombine(),llvm::AMDGPUTargetLowering::performSraCombine(),llvm::AMDGPUTargetLowering::performSrlCombine(),performVECTOR_SHUFFLECombine(),performVSelectCombine(),llvm::AArch64TargetLowering::ReconstructShuffle(),ReconstructShuffleWithRuntimeMask(),ReorganizeVector(),ReplaceINTRINSIC_W_CHAIN(),ReplaceLoadVector(),llvm::X86TargetLowering::ReplaceNodeResults(),scalarizeBinOpOfSplats(),llvm::TargetLowering::scalarizeVectorLoad(),llvm::TargetLowering::SimplifyDemandedVectorElts(),SkipExtensionForVMULL(),llvm::AMDGPUTargetLowering::splitBinaryBitConstantOpImpl(),takeInexpensiveLog2(),tryBuildVectorShuffle(),tryToConvertShuffleOfTbl2ToTbl4(),tryToFoldExtendOfConstant(),UnrollVectorOp(),UnrollVectorOverflowOp(),unrollVectorShift(), andwidenVectorToPartType().
| inline |
Return CalledGlobal associated withNode, or a nullopt if none exists.
Definition at line2387 of fileSelectionDAG.h.
Referencesllvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::end(),llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::find(), andI.
Referenced byllvm::ScheduleDAGSDNodes::EmitSchedule().
| inline |
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).
CALLSEQ_END does not have a usefulSDLoc.
Definition at line1106 of fileSelectionDAG.h.
Referencesllvm::ISD::CALLSEQ_END,DL,llvm::SDValue::getNode(),getNode(),getVTList(), andllvm::SmallVectorTemplateBase< T, bool >::push_back().
Referenced bygetCALLSEQ_END(),GetTLSADDR(),llvm::SITargetLowering::LowerCall(),llvm::NVPTXTargetLowering::LowerCall(),llvm::SystemZTargetLowering::LowerCall(),llvm::XtensaTargetLowering::LowerCall(),llvm::HexagonTargetLowering::LowerCall(),llvm::LoongArchTargetLowering::LowerCall(),llvm::RISCVTargetLowering::LowerCall(),llvm::VETargetLowering::LowerCall(),llvm::SparcTargetLowering::LowerCall_32(),llvm::SparcTargetLowering::LowerCall_64(),llvm::SITargetLowering::LowerDYNAMIC_STACKALLOC(),llvm::VETargetLowering::lowerDYNAMIC_STACKALLOC(),llvm::SparcTargetLowering::LowerGlobalTLSAddress(),llvm::VETargetLowering::lowerToTLSGeneralDynamicModel(), andPrepareTailCall().
| inline |
Definition at line1118 of fileSelectionDAG.h.
ReferencesDL,getCALLSEQ_END(), andgetIntPtrConstant().
| inline |
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside CALLSEQ_START..CALLSEQ_END sequence and OutSize specifies part of the frame set up prior to the sequence.
Definition at line1094 of fileSelectionDAG.h.
Referencesllvm::ISD::CALLSEQ_START,DL,getIntPtrConstant(),getNode(), andgetVTList().
Referenced byGetTLSADDR(),llvm::SITargetLowering::LowerCall(),llvm::NVPTXTargetLowering::LowerCall(),llvm::SystemZTargetLowering::LowerCall(),llvm::XtensaTargetLowering::LowerCall(),llvm::HexagonTargetLowering::LowerCall(),llvm::LoongArchTargetLowering::LowerCall(),llvm::RISCVTargetLowering::LowerCall(),llvm::VETargetLowering::LowerCall(),llvm::SparcTargetLowering::LowerCall_32(),llvm::SparcTargetLowering::LowerCall_64(),llvm::SITargetLowering::LowerDYNAMIC_STACKALLOC(),llvm::VETargetLowering::lowerDYNAMIC_STACKALLOC(),llvm::SparcTargetLowering::LowerGlobalTLSAddress(), andllvm::VETargetLowering::lowerToTLSGeneralDynamicModel().
| inline |
Return CallSiteInfo associated withNode, or a default if none exists.
Definition at line2349 of fileSelectionDAG.h.
Referencesllvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::end(),llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::find(), andI.
Referenced byllvm::ScheduleDAGSDNodes::EmitSchedule().
SDValue SelectionDAG::getCommutedVectorShuffle | ( | constShuffleVectorSDNode & | SV | ) |
Returns anISD::VECTOR_SHUFFLE node semantically equivalent to the shuffle node in input but with swapped operands.
Example: shuffle A, B, <0,5,2,7> -> shuffle B, A, <4,1,6,3>
Definition at line2318 of fileSelectionDAG.cpp.
Referencesllvm::ShuffleVectorSDNode::commuteMask(),llvm::ShuffleVectorSDNode::getMask(),llvm::SDNode::getOperand(),llvm::SDNode::getValueType(), andgetVectorShuffle().
Referenced bylowerVECTOR_SHUFFLE().
SDValue SelectionDAG::getCondCode | ( | ISD::CondCode | Cond | ) |
Definition at line2079 of fileSelectionDAG.cpp.
Referenced bycombine_CC(),llvm::TargetLowering::expandVPCTTZElements(),getSelectCC(),getSetCC(),getSetCCVP(),llvm::TargetLowering::LegalizeSetCCCondCode(),lowerBALLOTIntrinsic(),lowerFCMPIntrinsic(),lowerICMPIntrinsic(),LowerTruncatei1(),lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(),lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND(),LowerVSETCC(),performIntrinsicCombine(),performVSelectCombine(),splitVSETCC(), andtryConvertSVEWideCompare().
SDValue SelectionDAG::getConstant | ( | constAPInt & | Val, |
constSDLoc & | DL, | ||
EVT | VT, | ||
bool | isTarget =false , | ||
bool | isOpaque =false | ||
) |
Definition at line1672 of fileSelectionDAG.cpp.
ReferencesDL, andgetConstant().
SDValue SelectionDAG::getConstant | ( | constConstantInt & | Val, |
constSDLoc & | DL, | ||
EVT | VT, | ||
bool | isTarget =false , | ||
bool | isOpaque =false | ||
) |
Definition at line1677 of fileSelectionDAG.cpp.
ReferencesAddNodeIDNode(),llvm::append_range(),assert(),llvm::SmallVectorTemplateCommon< T, typename >::begin(),llvm::ISD::BITCAST,llvm::ISD::Constant,DL,llvm::SmallVectorTemplateCommon< T, typename >::end(),llvm::APInt::extractBits(),llvm::ConstantInt::getBitWidth(),getBuildVector(),getConstant(),getContext(),getDataLayout(),getNode(),llvm::EVT::getScalarType(),llvm::EVT::getSizeInBits(),getSplat(),llvm::Value::getType(),llvm::TargetLoweringBase::getTypeAction(),llvm::TargetLoweringBase::getTypeToTransformTo(),llvm::ConstantInt::getValue(),llvm::EVT::getVectorNumElements(),llvm::EVT::getVectorVT(),getVTList(),isBigEndian(),llvm::EVT::isInteger(),llvm::TargetLoweringBase::isOperationLegal(),llvm::EVT::isScalableVector(),llvm::TargetLoweringBase::isSExtCheaperThanZExt(),llvm::EVT::isVector(),N,NewNodesMustHaveLegalTypes,NewSDValueDbgMsg(),llvm::SmallVectorTemplateBase< T, bool >::push_back(),llvm::APInt::sextOrTrunc(),llvm::ISD::SPLAT_VECTOR,llvm::ISD::SPLAT_VECTOR_PARTS,llvm::ISD::TargetConstant,llvm::TargetLoweringBase::TypeExpandInteger,llvm::TargetLoweringBase::TypePromoteInteger, andllvm::APInt::zextOrTrunc().
SDValue SelectionDAG::getConstant | ( | uint64_t | Val, |
constSDLoc & | DL, | ||
EVT | VT, | ||
bool | isTarget =false , | ||
bool | isOpaque =false | ||
) |
Create aConstantSDNode wrapping a constant value.
If VT is a vector type, the constant is splatted into a BUILD_VECTOR.
If only legal types can be produced, this does the necessary transformations (e.g., if the vector element type is illegal).
Definition at line1666 of fileSelectionDAG.cpp.
ReferencesDL,getConstant(), andllvm::EVT::getScalarSizeInBits().
Referenced byAddCombineBUILD_VECTORToVPADDL(),AddCombineToVPADD(),AddCombineVUZPToVPADDL(),addIPMSequence(),adjustForSubtraction(),adjustForTestUnderMask(),adjustICmpTruncate(),adjustSubwordCmp(),adjustZeroCmp(),llvm::SparcTargetLowering::bitcastConstantFPToInt(),bitcastf32Toi32(),buildCallOperands(),BuildExactSDIV(),BuildExactUDIV(),BuildIntrinsicOp(),llvm::SITargetLowering::buildRSRC(),llvm::TargetLowering::BuildSDIV(),llvm::PPCTargetLowering::BuildSDIVPow2(),llvm::TargetLowering::buildSDIVPow2WithCMov(),llvm::TargetLowering::BuildUDIV(),canonicalizeShuffleVectorByLane(),carryFlagToValue(),checkSignTestSetCCCombine(),clampDynamicVectorIndex(),combine_CC(),combineAcrossLanesIntrinsic(),combineADC(),combineAddOfBooleanXor(),combineAddOrSubToADCOrSBB(),combineADDToADDZE(),combineAnd(),combineAndLoadToBZHI(),combineAndnp(),CombineANDShift(),combineArithReduction(),combineAVG(),CombineBaseUpdate(),combineBitcast(),combineBitcastToBoolVector(),combineCarryDiamond(),combineCarryThroughADD(),combineCMov(),combineCMP(),combineCompareEqual(),combineCONCAT_VECTORS(),combineConcatVectorOps(),combineDeMorganOfBoolean(),combineEXTEND_VECTOR_INREG(),combineEXTRACT_SUBVECTOR(),combineExtractVectorElt(),combineExtractWithShuffle(),combineFP_EXTEND(),combineGatherScatter(),combineI8TruncStore(),combineKSHIFT(),combineM68kBrCond(),combineMinMaxReduction(),combineMOVMSK(),combineMul(),combineMulSpecial(),combineMulToPMADDWD(),combineOr(),combinePMULDQ(),combinePredicateReduction(),combinePTESTCC(),combineSCALAR_TO_VECTOR(),combineScalarAndWithMaskSetcc(),llvm::VETargetLowering::combineSelect(),combineSelect(),llvm::VETargetLowering::combineSelectCC(),combineSelectOfTwoConstants(),combineSetCC(),combineSetCCAtomicArith(),combineSetCCMOVMSK(),combineShiftAnd1ToBitTest(),combineShiftLeft(),combineShiftOfShiftedLogic(),combineShiftRightArithmetic(),combineShiftRightLogical(),combineShiftToMULH(),combineStore(),combineSub(),combineSubOfBoolean(),combineSubSetcc(),combineSVEPrefetchVecBaseImmOff(),combineSVEReductionFP(),combineSVEReductionInt(),combineSVEReductionOrderedFP(),combineToExtendBoolVectorInReg(),combineTruncOfSraSext(),combineTruncSelectToSMaxUSat(),combineUADDO_CARRYDiamond(),combineV3I8LoadExt(),combineVectorCompare(),combineVectorMulToSraBitcast(),combineVectorShiftImm(),combineVectorShiftVar(),combineVectorSizedSetCCEquality(),CombineVMOVDRRCandidateWithVecOp(),combineVPMADD(),combineVSelectWithAllOnesOrZeros(),combinevXi1ConstantToInteger(),combineX86AddSub(),combineX86ShuffleChain(),constantFoldBFE(),constructDup(),constructRetValue(),ConvertBooleanCarryToCarryFlag(),ConvertCarryFlagToBooleanCarry(),convertFixedMaskToScalableVector(),convertFromScalableVector(),convertShiftLeftToScale(),convertToScalableVector(),convertValVTToLocVT(),CreateCopyOfByValArgument(),createFPCmp(),createLoadLR(),createPSADBW(),createSetFPEnvNodes(),createStoreLR(),createVariablePermute(),createVPDPBUSD(),llvm::TargetLowering::CTTZTableLookup(),customLegalizeToWOp(),EltsFromConsecutiveLoads(),EmitCMP(),emitConditionalComparison(),emitConstantSizeRepmov(),emitConstantSizeRepstos(),emitMemMemImm(),emitSETCC(),llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemchr(),llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(),llvm::BPFSelectionDAGInfo::EmitTargetCodeForMemcpy(),llvm::WebAssemblySelectionDAGInfo::EmitTargetCodeForMemcpy(),llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemset(),llvm::WebAssemblySelectionDAGInfo::EmitTargetCodeForMemset(),llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrcmp(),llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrcpy(),llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrlen(),EmitTest(),Expand64BitShift(),llvm::TargetLowering::expandABS(),llvm::TargetLowering::expandAddSubSat(),llvm::TargetLowering::expandAVG(),llvm::TargetLowering::expandBITREVERSE(),llvm::TargetLowering::expandBSWAP(),llvm::TargetLowering::expandCMP(),llvm::TargetLowering::expandCTLZ(),llvm::TargetLowering::expandCTPOP(),llvm::TargetLowering::expandCTTZ(),expandDivFix(),llvm::TargetLowering::expandDIVREMByConstant(),expandf64Toi32(),llvm::TargetLowering::expandFixedPointDiv(),llvm::TargetLowering::expandFixedPointMul(),llvm::TargetLowering::expandFP_ROUND(),llvm::TargetLowering::expandFP_TO_INT_SAT(),llvm::TargetLowering::expandFP_TO_SINT(),llvm::TargetLowering::expandFP_TO_UINT(),llvm::TargetLowering::expandFunnelShift(),llvm::TargetLowering::expandIntMINMAX(),expandIntrinsicWChainHelper(),llvm::TargetLowering::expandIS_FPCLASS(),expandMul(),llvm::TargetLowering::expandMUL_LOHI(),llvm::TargetLowering::expandMULO(),llvm::TargetLowering::expandROT(),llvm::TargetLowering::expandRoundInexactToOdd(),llvm::TargetLowering::expandSADDSUBO(),llvm::TargetLowering::expandShiftParts(),llvm::TargetLowering::expandShlSat(),llvm::TargetLowering::expandUADDSUBO(),llvm::TargetLowering::expandUINT_TO_FP(),llvm::TargetLowering::expandUnalignedLoad(),llvm::TargetLowering::expandUnalignedStore(),expandVAArg(),llvm::TargetLowering::expandVECTOR_COMPRESS(),llvm::TargetLowering::expandVectorFindLastActive(),llvm::TargetLowering::expandVectorSplice(),llvm::TargetLowering::expandVPBITREVERSE(),llvm::TargetLowering::expandVPBSWAP(),llvm::TargetLowering::expandVPCTLZ(),llvm::TargetLowering::expandVPCTPOP(),llvm::TargetLowering::expandVPCTTZ(),llvm::TargetLowering::expandVPCTTZElements(),expandVPFunnelShift(),ExtendToType(),extractF64Exponent(),extractShiftForRotate(),finalizeTS1AM(),foldADCToCINC(),foldAddSubBoolOfMaskedVal(),foldAndOrOfSETCC(),foldAndToUsubsat(),FoldConstantArithmetic(),foldCSELOfCSEL(),foldCSELofCTTZ(),foldExtendedSignBitTest(),foldMaskAndShiftToExtract(),foldMaskAndShiftToScale(),foldMaskedShiftToBEXTR(),foldSelectOfConstantsUsingSra(),foldSelectOfCTTZOrCTLZ(),FoldSetCC(),foldSetCCWithFunnelShift(),FoldSTEP_VECTOR(),llvm::TargetLowering::forceExpandMultiply(),llvm::TargetLowering::forceExpandWideMUL(),genConstMult(),generateEquivalentSub(),GenerateFixedLengthSVETBL(),GeneratePerfectShuffle(),GenerateTBL(),getAArch64Cmp(),getAArch64XALUOOp(),getAbsolute(),llvm::MipsTargetLowering::getAddrNonPICSym64(),getAllOnesConstant(),getARMIndexedAddressParts(),getAVX512Node(),getBitTestCondition(),getBoolConstant(),getBoundedStrlen(),getBuildVectorSplat(),getCanonicalConstSplat(),getCCResult(),getConstant(),llvm::VECustomDAG::getConstant(),getConstVector(),getCopyFromParts(),llvm::RegsForValue::getCopyFromRegs(),getCSAddressAndShifts(),getDataClassTest(),getDefaultVLOps(),getDeinterleaveShiftAndTrunc(),getDWordFromOffset(),getElementCount(),GetExponent(),getFlagsOfCmpZeroFori1(),getGeneralPermuteNode(),getGFNICtrlMask(),llvm::AMDGPUTargetLowering::getHiHalf64(),getIntPtrConstant(),getLimitedPrecisionExp2(),llvm::AMDGPUTargetLowering::getLoHalf64(),llvm::VECustomDAG::getMaskBroadcast(),getMaskNode(),getMemBasePlusOffset(),getMemsetStringVal(),getMemsetValue(),getMVEIndexedAddressParts(),getNegatedInteger(),getNegative(),getNeutralElement(),getNode(),getPack(),getPMOVMSKB(),llvm::AVRTargetLowering::getPostIndexedAddressParts(),getPTest(),getPTrue(),getReductionSDNode(),getScaledOffsetForBitWidth(),getSETCC(),getShiftAmountConstant(),getShuffleScalarElt(),getSignedConstant(),GetSignificand(),llvm::NVPTXTargetLowering::getSqrtEstimate(),getStepVector(),getSVEPredicateBitCast(),getT2IndexedAddressParts(),getTargetConstant(),getTargetVShiftByConstNode(),getTargetVShiftNode(),getTruncatedUSUBSAT(),getUniformBase(),llvm::SelectionDAGBuilder::getValueImpl(),getVectorBitwiseReduce(),getVectorIdxConstant(),llvm::TargetLowering::getVectorSubVecPointer(),getVPZeroExtendInReg(),getVScale(),getWideningInterleave(),getWideningSpread(),getZeroExtendInReg(),getZeroVector(),getzOSCalleeAndADA(),incDecVectorConstant(),llvm::TargetLowering::IncrementMemoryAddress(),insert1BitVector(),IntCondCCodeToICC(),isConditionalZeroOrAllOnes(),IsSingleInstrConstant(),legalizeIntrinsicImmArg(),llvm::AMDGPUTargetLowering::loadInputValue(),lower1BitShuffle(),LowerABS(),lowerAddrSpaceCast(),LowerADDSAT_SUBSAT(),LowerAndToBT(),LowerAndToBTST(),LowerAsSplatVectorLoad(),LowerATOMIC_FENCE(),LowerAVXExtend(),lowerBALLOTIntrinsic(),LowerBITREVERSE(),LowerBITREVERSE_XOP(),lowerBitreverseShuffle(),llvm::LanaiTargetLowering::LowerBR_CC(),LowerBR_CC(),LowerBRCOND(),llvm::HexagonTargetLowering::LowerBUILD_VECTOR(),lowerBUILD_VECTOR(),LowerBUILD_VECTOR_i1(),LowerBUILD_VECTORToVIDUP(),LowerBUILD_VECTORvXi1(),lowerBuildVectorOfConstants(),LowerBuildVectorOfFPExt(),LowerBuildVectorOfFPTrunc(),LowerBuildVectorv16i8(),lowerBuildVectorViaPacking(),llvm::SITargetLowering::LowerCall(),llvm::NVPTXTargetLowering::LowerCall(),llvm::XtensaTargetLowering::LowerCall(),llvm::HexagonTargetLowering::LowerCall(),llvm::LoongArchTargetLowering::LowerCall(),llvm::RISCVTargetLowering::LowerCall(),llvm::SparcTargetLowering::LowerCall_32(),llvm::SparcTargetLowering::LowerCall_64(),lowerCallResult(),LowerCallResult(),llvm::TargetLowering::LowerCallTo(),llvm::TargetLowering::lowerCmpEqZeroToCtlzSrl(),llvm::HexagonTargetLowering::LowerCONCAT_VECTORS(),LowerCONCAT_VECTORS_i1(),LowerCONCAT_VECTORSvXi1(),LowerCTLZ(),llvm::AMDGPUTargetLowering::LowerCTLZ_CTTZ(),llvm::AMDGPUTargetLowering::lowerCTLZResults(),LowerCTPOP(),LowerCTTZ(),lowerCttzElts(),lowerDisjointIndicesShuffle(),llvm::AMDGPUTargetLowering::LowerDIVREM24(),llvm::AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(),llvm::SITargetLowering::LowerDYNAMIC_STACKALLOC(),llvm::HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(),llvm::NVPTXTargetLowering::LowerDYNAMIC_STACKALLOC(),llvm::VETargetLowering::lowerDYNAMIC_STACKALLOC(),LowerDYNAMIC_STACKALLOC(),LowerEXTEND_VECTOR_INREG(),LowerEXTRACT_SUBVECTOR(),llvm::VETargetLowering::lowerEXTRACT_VECTOR_ELT(),LowerEXTRACT_VECTOR_ELT_i1(),llvm::SparcTargetLowering::LowerF128Compare(),LowerF128Load(),LowerF128Store(),lowerFABSorFNEG(),lowerFCOPYSIGN(),lowerFCOPYSIGN32(),lowerFCOPYSIGN64(),llvm::AMDGPUTargetLowering::lowerFEXP(),LowerFGETSIGN(),LowerFLDEXP(),llvm::AMDGPUTargetLowering::LowerFLOGCommon(),LowerFMINIMUM_FMAXIMUM(),llvm::R600TargetLowering::LowerFormalArguments(),llvm::SITargetLowering::LowerFormalArguments(),llvm::HexagonTargetLowering::LowerFormalArguments(),llvm::NVPTXTargetLowering::LowerFormalArguments(),llvm::SparcTargetLowering::LowerFormalArguments_64(),LowerFP16_TO_FP(),llvm::AMDGPUTargetLowering::LowerFP_TO_FP16(),llvm::AMDGPUTargetLowering::LowerFP_TO_INT64(),LowerFP_TO_INT_SAT(),lowerFP_TO_INT_SAT(),llvm::AMDGPUTargetLowering::LowerFTRUNC(),LowerFunnelShift(),llvm::SITargetLowering::lowerGET_ROUNDING(),llvm::AMDGPUTargetLowering::LowerGlobalAddress(),llvm::HexagonTargetLowering::LowerGLOBALADDRESS(),lowerGR128ToI128(),LowerHorizontalByteSum(),lowerI128ToGR128(),llvm::VETargetLowering::lowerINSERT_VECTOR_ELT(),LowerINSERT_VECTOR_ELT_i1(),llvm::AMDGPUTargetLowering::LowerINT_TO_FP32(),llvm::AMDGPUTargetLowering::LowerINT_TO_FP64(),lowerINT_TO_FP_vXi64(),LowerInterruptReturn(),llvm::HexagonTargetLowering::LowerINTRINSIC_VOID(),LowerINTRINSIC_W_CHAIN(),LowerLabelRef(),lowerLaneOp(),llvm::MipsTargetLowering::lowerLOAD(),lowerLoadF128(),lowerLoadI1(),LowerMemOpCallTo(),lowerMSABinaryBitImmIntr(),lowerMSABitClear(),lowerMSABitClearImm(),lowerMSASplatImm(),lowerMSASplatZExt(),LowerMUL(),llvm::LanaiTargetLowering::LowerMUL(),lowerMUL_LOHI32(),LowerMULH(),LowerMULO(),llvm::R600TargetLowering::LowerOperation(),llvm::RISCVTargetLowering::LowerOperation(),lowerOverflowArithmetic(),LowerPARITY(),LowerPredicateLoad(),LowerPredicateStore(),llvm::HexagonTargetLowering::LowerPREFETCH(),LowerPREFETCH(),lowerReductionSeq(),llvm::NVPTXTargetLowering::LowerReturn(),llvm::SparcTargetLowering::LowerReturn_32(),llvm::SparcTargetLowering::LowerReturn_64(),llvm::HexagonTargetLowering::LowerRETURNADDR(),llvm::MSP430TargetLowering::LowerRETURNADDR(),lowerRETURNADDR(),LowerRotate(),LowerSaturatingConditional(),lowerScalarInsert(),lowerScalarSplat(),LowerSDIV_v4i16(),LowerSDIV_v4i8(),llvm::AMDGPUTargetLowering::LowerSDIVREM(),llvm::LanaiTargetLowering::LowerSELECT_CC(),LowerSELECT_CC(),LowerSELECTWithCmpZero(),llvm::SITargetLowering::lowerSET_FPENV(),llvm::SITargetLowering::lowerSET_ROUNDING(),llvm::LanaiTargetLowering::LowerSETCC(),llvm::MSP430TargetLowering::LowerSETCC(),LowerSETCCCARRY(),LowerShift(),LowerShiftByScalarImmediate(),LowerShiftByScalarVariable(),llvm::LanaiTargetLowering::LowerSHL_PARTS(),lowerShuffleAsBitBlend(),lowerShuffleAsBitMask(),lowerShuffleAsBlend(),lowerShuffleAsBlendOfPSHUFBs(),lowerShuffleAsSpecificZeroOrAnyExtend(),lowerShuffleAsTruncBroadcast(),lowerShuffleAsVTRUNCAndUnpack(),lowerShuffleWithEXPAND(),lowerShuffleWithPSHUFB(),LowerSIGN_EXTEND_Mask(),LowerSMELdrStr(),llvm::LanaiTargetLowering::LowerSRL_PARTS(),llvm::NVPTXTargetLowering::LowerSTACKSAVE(),lowerStoreF128(),lowerStoreI1(),LowerSVEIntrinsicEXT(),LowerTruncatei1(),LowerTruncateVecI1(),LowerTruncateVectorStore(),llvm::HexagonTargetLowering::LowerUAddSubO(),LowerUADDSUBO_CARRY(),LowerUDIV(),llvm::AMDGPUTargetLowering::LowerUDIVREM(),llvm::AMDGPUTargetLowering::LowerUDIVREM64(),lowerUINT_TO_FP_v2i32(),lowerUINT_TO_FP_vXi32(),llvm::HexagonTargetLowering::LowerUnalignedLoad(),LowerUnalignedLoadRetParam(),LowerUnalignedStoreParam(),LowerUnalignedStoreRet(),lowerV16I8Shuffle(),lowerV8I16Shuffle(),llvm::VETargetLowering::lowerVAARG(),LowerVecReduce(),LowerVecReduceMinMax(),lowerVECTOR_COMPRESS(),LowerVECTOR_SHUFFLE(),lowerVECTOR_SHUFFLE(),LowerVECTOR_SHUFFLE_i1(),lowerVECTOR_SHUFFLE_VREPLVEI(),lowerVECTOR_SHUFFLE_VSHUF(),lowerVECTOR_SHUFFLE_VSHUF4I(),lowerVECTOR_SHUFFLE_XVREPLVEI(),lowerVECTOR_SHUFFLEAsRotate(),lowerVECTOR_SHUFFLEAsVSlidedown(),lowerVECTOR_SHUFFLEAsVSlideup(),LowerVECTOR_SHUFFLEUsingMovs(),LowerVectorAllEqual(),lowerVectorBitClear(),lowerVectorBitClearImm(),lowerVectorBitRevImm(),lowerVectorBitSetImm(),LowerVectorCTLZ_AVX512CDI(),LowerVectorCTLZInRegLUT(),LowerVectorCTPOPInRegLUT(),lowerVectorIntrinsicScalars(),LowerVectorMatch(),lowerVectorSplatImm(),LowerVSETCC(),LowerVSETCCWithSUBUS(),LowervXi8MulWithUNPCK(),lowerX86CmpEqZeroToCtlzSrl(),LowerXALUO(),LowerZERO_EXTEND_Mask(),llvm::SparcTargetLowering::makeAddress(),matchPERM(),MatchVectorAllEqualTest(),memsetStore(),narrowIndex(),NormalizeBuildVector(),optimizeIncrementingWhile(),optimizeLogicalImm(),overflowFlagToValue(),llvm::SITargetLowering::passSpecialInputs(),performAddCSelIntoCSinc(),PerformAddcSubcCombine(),PerformAddeSubeCombine(),performAddSubIntoVectorOp(),performAddUADDVCombine(),performANDCombine(),performANDORCSELCombine(),performANDSETCCCombine(),PerformARMBUILD_VECTORCombine(),PerformBFICombine(),PerformBUILD_VECTORCombine(),llvm::ARMTargetLowering::PerformCMOVCombine(),llvm::ARMTargetLowering::PerformCMOVToBFICombine(),performCONCAT_VECTORSCombine(),performConcatVectorsCombine(),performCSELCombine(),PerformCSETCombine(),llvm::AArch64TargetLowering::PerformDAGCombine(),llvm::AMDGPUTargetLowering::PerformDAGCombine(),llvm::R600TargetLowering::PerformDAGCombine(),llvm::HexagonTargetLowering::PerformDAGCombine(),llvm::PPCTargetLowering::PerformDAGCombine(),llvm::RISCVTargetLowering::PerformDAGCombine(),performDSPShiftCombine(),performDUPCombine(),performExtBinopLoadFold(),PerformEXTRACTCombine(),PerformExtractEltCombine(),PerformExtractEltToVMOVRRD(),performExtractVectorEltCombine(),llvm::AMDGPUTargetLowering::performFAbsCombine(),performFlagSettingCombine(),llvm::AMDGPUTargetLowering::performFNegCombine(),performFP_TO_INT_SATCombine(),performFpToIntCombine(),performGlobalAddressCombine(),performINTRINSIC_WO_CHAINCombine(),llvm::ARMTargetLowering::PerformIntrinsicCombine(),performLDNT1Combine(),PerformLongShiftCombine(),PerformMinMaxCombine(),PerformMinMaxToSatCombine(),performMulCombine(),PerformMULCombine(),llvm::ARMTargetLowering::PerformMVEExtCombine(),llvm::ARMTargetLowering::PerformMVETruncCombine(),performORCombine(),PerformORCombineToBFI(),PerformPREDICATE_CASTCombine(),performScalarToVectorCombine(),performSetccAddFolding(),performSETCCCombine(),PerformShiftCombine(),llvm::AMDGPUTargetLowering::performShlCombine(),performSHLCombine(),PerformSHLSimplify(),PerformShuffleVMOVNCombine(),PerformSplittingToNarrowingStores(),PerformSplittingToWideningLoad(),llvm::AMDGPUTargetLowering::performSraCombine(),performSRACombine(),llvm::AMDGPUTargetLowering::performSrlCombine(),performSRLCombine(),PerformSTORECombine(),performSUBCombine(),PerformSUBCombine(),performSubsToAndsCombine(),performSVEAndCombine(),performTBZCombine(),performTruncateCombine(),PerformTruncatingStoreCombine(),performUnpackCombine(),performUzpCombine(),PerformVCMPCombine(),PerformVCVTCombine(),PerformVDUPCombine(),performVecReduceAddCombine(),performVecReduceAddCombineWithUADDLP(),performVECTOR_SHUFFLECombine(),PerformVMOVrhCombine(),PerformVMOVRRDCombine(),PerformVMulVCTPCombine(),performVP_REVERSECombine(),performVP_STORECombine(),performVSelectCombine(),PerformVSELECTCombine(),PerformVSetCCToVCTPCombine(),performXORCombine(),PerformXORCombine(),performZExtDeinterleaveShuffleCombine(),performZExtUZPCombine(),prepareTS1AM(),promoteExtBeforeAdd(),reassociateCSELOperandsForCSE(),llvm::AArch64TargetLowering::ReconstructShuffle(),ReconstructShuffleWithRuntimeMask(),recoverFramePointer(),reduceBuildVecToShuffleWithZero(),refineUniformBase(),ReplaceATOMIC_LOAD_128Results(),ReplaceBITCAST(),llvm::SITargetLowering::ReplaceNodeResults(),llvm::AVRTargetLowering::ReplaceNodeResults(),llvm::LoongArchTargetLowering::ReplaceNodeResults(),llvm::RISCVTargetLowering::ReplaceNodeResults(),llvm::X86TargetLowering::ReplaceNodeResults(),ReplaceREADCYCLECOUNTER(),replaceVPICKVE2GRResults(),resolveSources(),SaturateWidenedDIVFIX(),llvm::TargetLowering::scalarizeVectorLoad(),llvm::TargetLowering::scalarizeVectorStore(),llvm::TargetLowering::ShrinkDemandedConstant(),llvm::TargetLowering::SimplifyDemandedBits(),llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(),llvm::ARMTargetLowering::SimplifyDemandedBitsForTargetNode(),llvm::TargetLowering::SimplifyDemandedVectorElts(),simplifyDivRem(),llvm::TargetLowering::SimplifySetCC(),simplifySetCCIntoEq(),simplifySetCCWithCTPOP(),simplifyShift(),SkipExtensionForVMULL(),llvm::TargetLowering::softenSetCCOperands(),llvm::AMDGPUTargetLowering::split64BitValue(),llvm::AMDGPUTargetLowering::splitBinaryBitConstantOpImpl(),SplitEVL(),splitStores(),splitStoreSplat(),llvm::RISCVTargetLowering::splitValueIntoRegisterParts(),llvm::AMDGPUTargetLowering::storeStackInputValue(),takeInexpensiveLog2(),llvm::ARMTargetLowering::targetShrinkDemandedConstant(),llvm::RISCVTargetLowering::targetShrinkDemandedConstant(),llvm::X86TargetLowering::targetShrinkDemandedConstant(),transformAddShlImm(),TranslateM68kCC(),translateSetCCForBranch(),TranslateX86CC(),truncateVecElts(),tryAdvSIMDModImm16(),tryAdvSIMDModImm32(),tryAdvSIMDModImm321s(),tryAdvSIMDModImm64(),tryAdvSIMDModImm8(),tryAdvSIMDModImmFP(),TryCombineBaseUpdate(),tryCombineMULLWithUZP1(),tryCombineShiftImm(),tryConvertSVEWideCompare(),tryDemorganOfBooleanCondition(),tryExtendDUPToExtractHigh(),tryFoldMADwithSRL(),tryFoldSelectIntoOp(),tryFoldToZero(),tryFormConcatFromShuffle(),tryLowerPartialReductionToDot(),tryMemPairCombine(),TryMULWIDECombine(),tryToConvertShuffleOfTbl2ToTbl4(),tryToFoldExtendOfConstant(),UnpackFromArgumentSlot(),UnrollVectorOverflowOp(),unrollVectorShift(),valueToCarryFlag(),vectorToScalarBitmask(),llvm::SelectionDAGBuilder::visitBitTestCase(),llvm::SelectionDAGBuilder::visitBitTestHeader(),llvm::SelectionDAGBuilder::visitJumpTableHeader(),llvm::X86TargetLowering::visitMaskedLoad(),llvm::SelectionDAGBuilder::visitSwitchCase(),WidenVector(), andwidenVectorOpsToi8().
SDDbgValue * SelectionDAG::getConstantDbgValue | ( | DIVariable * | Var, |
DIExpression * | Expr, | ||
constValue * | C, | ||
constDebugLoc & | DL, | ||
unsigned | O | ||
) |
Creates a constantSDDbgValue node.
Definition at line11338 of fileSelectionDAG.cpp.
Referencesassert(),llvm::CallingConv::C,DL,llvm::SDDbgOperand::fromConst(), andllvm::SDDbgInfo::getAlloc().
Referenced byllvm::SelectionDAGBuilder::resolveDanglingDebugInfo(), andllvm::SelectionDAGBuilder::salvageUnresolvedDbgValue().
SDValue SelectionDAG::getConstantFP | ( | constAPFloat & | Val, |
constSDLoc & | DL, | ||
EVT | VT, | ||
bool | isTarget =false | ||
) |
Definition at line1829 of fileSelectionDAG.cpp.
ReferencesDL,getConstantFP(), andgetContext().
SDValue SelectionDAG::getConstantFP | ( | constConstantFP & | V, |
constSDLoc & | DL, | ||
EVT | VT, | ||
bool | isTarget =false | ||
) |
Definition at line1834 of fileSelectionDAG.cpp.
ReferencesAddNodeIDNode(),assert(),llvm::ISD::ConstantFP,DL,getContext(),llvm::EVT::getScalarType(),getSplat(),llvm::Value::getType(),llvm::ConstantFP::getValue(),getVTList(),llvm::EVT::isFloatingPoint(),llvm::EVT::isVector(),N,NewSDValueDbgMsg(), andllvm::ISD::TargetConstantFP.
Create aConstantFPSDNode wrapping a constant value.
If VT is a vector type, the constant is splatted into a BUILD_VECTOR.
If only legal types can be produced, this does the necessary transformations (e.g., if the vector element type is illegal). The forms that take a double should only be used for simple constants that can be exactly represented in VT. No checks are made.
Definition at line1873 of fileSelectionDAG.cpp.
Referencesllvm::APFloat::convert(),DL,getConstantFP(),llvm::EVT::getFltSemantics(),llvm::EVT::getScalarType(),llvm_unreachable, andllvm::APFloatBase::rmNearestTiesToEven.
Referenced bycombineBitcast(),combineExtractWithShuffle(),combineFneg(),combineFP_ROUND(),combineVSelectWithAllOnesOrZeros(),EltsFromConsecutiveLoads(),expandExp(),llvm::TargetLowering::expandFMINIMUM_FMAXIMUM(),llvm::TargetLowering::expandFMINIMUMNUM_FMAXIMUMNUM(),llvm::TargetLowering::expandFP_TO_INT_SAT(),llvm::TargetLowering::expandFP_TO_UINT(),expandFP_TO_UINT_SSE(),llvm::TargetLowering::expandIS_FPCLASS(),expandLog(),ExpandPowI(),llvm::TargetLowering::expandUINT_TO_FP(),FoldConstantArithmetic(),foldConstantFPMath(),getConstantFP(),getConstVector(),getF32Constant(),getInvertedVectorForFMA(),llvm::AMDGPUTargetLowering::getIsFinite(),llvm::AMDGPUTargetLowering::getIsLtSmallestNormal(),getMemsetStringVal(),getMemsetValue(),llvm::TargetLowering::getNegatedExpression(),getNeutralElement(),getNode(),getRVVFPReductionOpAndOperands(),llvm::AMDGPUTargetLowering::getScaledLogInput(),getShuffleScalarElt(),llvm::TargetLowering::getSqrtInputTest(),llvm::TargetLowering::getSqrtResultForDenormInput(),getTargetConstantFP(),llvm::SelectionDAGBuilder::getValueImpl(),getZeroVector(),LowerFABSorFNEG(),LowerFCanonicalize(),llvm::AMDGPUTargetLowering::LowerFCEIL(),LowerFCOPYSIGN(),llvm::AMDGPUTargetLowering::lowerFEXP(),llvm::AMDGPUTargetLowering::lowerFEXP10Unsafe(),llvm::AMDGPUTargetLowering::lowerFEXP2(),llvm::AMDGPUTargetLowering::lowerFEXPUnsafe(),llvm::AMDGPUTargetLowering::LowerFFLOOR(),llvm::AMDGPUTargetLowering::LowerFLOG2(),llvm::AMDGPUTargetLowering::LowerFLOGCommon(),llvm::AMDGPUTargetLowering::LowerFLOGUnsafe(),LowerFMINIMUM_FMAXIMUM(),LowerFP_TO_FP16(),llvm::AMDGPUTargetLowering::LowerFP_TO_INT64(),LowerFROUND(),llvm::AMDGPUTargetLowering::LowerFROUND(),llvm::AMDGPUTargetLowering::LowerFROUNDEVEN(),lowerFTRUNC_FCEIL_FFLOOR_FROUND(),lowerShuffleAsBitMask(),llvm::AMDGPUTargetLowering::LowerUDIVREM64(),LowerUINT_TO_FP_i32(),lowerUINT_TO_FP_v2i32(),lowerUINT_TO_FP_vXi32(),lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(),lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND(),llvm::AMDGPUTargetLowering::PerformDAGCombine(),llvm::AMDGPUTargetLowering::performRcpCombine(),llvm::X86TargetLowering::ReplaceNodeResults(),llvm::TargetLowering::SimplifyDemandedBits(),simplifyFPBinop(), andstrictFPExtFromF16().
SDValue SelectionDAG::getConstantPool | ( | constConstant * | C, |
EVT | VT, | ||
MaybeAlign | Align =std::nullopt , | ||
int | Offs =0 , | ||
bool | isT =false , | ||
unsigned | TargetFlags =0 | ||
) |
Definition at line1968 of fileSelectionDAG.cpp.
ReferencesAddNodeIDNode(),assert(),llvm::CallingConv::C,llvm::ISD::ConstantPool,llvm::DataLayout::getABITypeAlign(),getDataLayout(),llvm::DataLayout::getPrefTypeAlign(),getVTList(),N,NewSDValueDbgMsg(),llvm::Offset,shouldOptForSize(), andllvm::ISD::TargetConstantPool.
Referenced bycombineConcatVectorOps(),combineTargetShuffle(),llvm::TargetLowering::CTTZTableLookup(),getAddressForMemoryInput(),getTargetConstantPool(),lowerBuildVectorAsBroadcast(),LowerUINT_TO_FP_i64(),lowerUINT_TO_FP_vXi32(), andllvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetShuffle().
SDValue SelectionDAG::getConstantPool | ( | MachineConstantPoolValue * | C, |
EVT | VT, | ||
MaybeAlign | Align =std::nullopt , | ||
int | Offs =0 , | ||
bool | isT =false , | ||
unsigned | TargetFlags =0 | ||
) |
Definition at line1998 of fileSelectionDAG.cpp.
ReferencesAddNodeIDNode(),assert(),llvm::CallingConv::C,llvm::ISD::ConstantPool,getDataLayout(),llvm::DataLayout::getPrefTypeAlign(),getVTList(),N,llvm::Offset, andllvm::ISD::TargetConstantPool.
| inline |
Definition at line510 of fileSelectionDAG.h.
Referenced byAddCombineVUZPToVPADDL(),llvm::RegsForValue::AddInlineAsmOperands(),addShuffleForVecExtend(),adjustLoadValueTypeImpl(),llvm::TargetLowering::BuildSDIV(),llvm::TargetLowering::buildSDIVPow2WithCMov(),llvm::TargetLowering::BuildUDIV(),BuildVectorFromScalar(),canCombineShuffleToExtendVectorInreg(),canFoldInAddressingMode(),checkIntrinsicImmArg(),CollectOpsToWiden(),combineAnd(),combineAndShuffleNot(),combineArithReduction(),combineBasicSADPattern(),combineBinOpOfExtractToReduceTree(),combineBinOpOfZExt(),combineBitcastToBoolVector(),combineBitcastvxi1(),combineBoolVectorAndTruncateStore(),combineCMP(),combineCONCAT_VECTORS(),combineConcatVectorOfCasts(),combineConcatVectorOfScalars(),combineConcatVectorOps(),combineExtractVectorElt(),combineExtractWithShuffle(),combineFMinNumFMaxNum(),combineFP_EXTEND(),combineFP_ROUND(),combineI8TruncStore(),combineLoad(),combineMinNumMaxNumImpl(),combineOr(),combinePMULH(),combinePredicateReduction(),combineScalarAndWithMaskSetcc(),combineSelect(),combineShiftAnd1ToBitTest(),combineShiftToAVG(),combineShiftToMULH(),combineShuffleToZeroExtendVectorInReg(),combineSIntToFP(),combineStore(),combineTargetShuffle(),combineToExtendBoolVectorInReg(),combineToFPTruncExtElt(),combineTruncateWithSat(),combineUIntToFP(),combineV3I8LoadExt(),combineVectorMulToSraBitcast(),CombineVMOVDRRCandidateWithVecOp(),combineVPDPBUSDPattern(),combineVSelectWithAllOnesOrZeros(),combinevXi1ConstantToInteger(),concatSubVectors(),constructRetValue(),convertIntLogicToFPLogic(),CreateStackTemporary(),llvm::TargetLowering::CTTZTableLookup(),detectPMADDUBSW(),earlyExpandDIVFIX(),EltsFromConsecutiveLoads(),llvm::SelectionDAGBuilder::EmitBranchForMergedCondition(),emitErrorAndReplaceIntrinsicResults(),emitIntrinsicErrorMessage(),emitIntrinsicWithChainErrorMessage(),emitNonHSAIntrinsicError(),emitRemovedIntrinsicError(),emitSMEStateSaveRestore(),llvm::ARMSelectionDAGInfo::EmitSpecializedLibcall(),llvm::AArch64SelectionDAGInfo::EmitStreamingCompatibleMemLibCall(),llvm::HexagonSelectionDAGInfo::EmitTargetCodeForMemcpy(),llvm::XCoreSelectionDAGInfo::EmitTargetCodeForMemcpy(),errorUnsupported(),llvm::TargetLowering::expandABD(),llvm::TargetLowering::expandAddSubSat(),llvm::TargetLowering::expandAVG(),llvm::TargetLowering::expandCMP(),llvm::TargetLowering::expandCTLZ(),llvm::TargetLowering::expandCTPOP(),llvm::TargetLowering::expandCTTZ(),expandDivFix(),llvm::TargetLowering::expandDIVREMByConstant(),llvm::TargetLowering::expandFixedPointDiv(),llvm::TargetLowering::expandFixedPointMul(),llvm::TargetLowering::expandFMINIMUM_FMAXIMUM(),llvm::TargetLowering::expandFMINIMUMNUM_FMAXIMUMNUM(),llvm::TargetLowering::expandFP_ROUND(),llvm::TargetLowering::expandFP_TO_INT_SAT(),llvm::TargetLowering::expandFP_TO_UINT(),llvm::TargetLowering::expandIntMINMAX(),llvm::TargetLowering::expandIS_FPCLASS(),llvm::TargetLowering::expandMUL_LOHI(),llvm::TargetLowering::expandMULO(),expandMultipleResultFPLibCall(),llvm::TargetLowering::expandRoundInexactToOdd(),llvm::TargetLowering::expandSADDSUBO(),llvm::TargetLowering::expandShiftParts(),llvm::TargetLowering::expandShlSat(),llvm::TargetLowering::expandUADDSUBO(),llvm::TargetLowering::expandUnalignedLoad(),llvm::TargetLowering::expandUnalignedStore(),expandVAArg(),llvm::TargetLowering::expandVecReduce(),llvm::TargetLowering::expandVectorFindLastActive(),llvm::TargetLowering::expandVectorSplice(),llvm::TargetLowering::expandVPCTPOP(),llvm::TargetLowering::expandVPCTTZElements(),extractSubVector(),fail(),findMemType(),FoldConstantArithmetic(),foldExtendVectorInregToExtendOfSubvector(),foldShuffleOfConcatUndefs(),foldXorTruncShiftIntoCmp(),llvm::TargetLowering::forceExpandWideMUL(),GenerateFixedLengthSVETBL(),getAtomicMemcpy(),getAtomicMemmove(),getAtomicMemset(),getConstant(),getConstantFP(),getCopyFromParts(),getCopyFromPartsVector(),llvm::SelectionDAGBuilder::getCopyFromRegs(),llvm::RegsForValue::getCopyFromRegs(),getCopyToParts(),getCopyToPartsVector(),llvm::RegsForValue::getCopyToRegs(),GetDependentSplitDestVTs(),getEVTAlign(),llvm::AMDGPUTargetLowering::getIsFinite(),llvm::AMDGPUTargetLowering::getIsLtSmallestNormal(),getLargeExternalSymbol(),getMemcpy(),getMemcpyLoadsAndStores(),getMemmove(),getMemmoveLoadsAndStores(),getMemset(),getMemsetStores(),getMemsetStringVal(),getMemsetValue(),getPrefTypeAlign(),getPTest(),getReducedAlign(),getRegistersForValue(),llvm::AMDGPUTargetLowering::getScaledLogInput(),getSplatValue(),GetSplitDestVTs(),llvm::AMDGPUTargetLowering::getSplitDestVTs(),llvm::TargetLowering::getSqrtInputTest(),GetTLSADDR(),getUniformBase(),llvm::SelectionDAGBuilder::getValueImpl(),getVectorBitwiseReduce(),llvm::TargetLowering::getVectorElementPointer(),llvm::VECustomDAG::getVectorVT(),llvm::TargetLowering::IncrementMemoryAddress(),llvm::SelectionDAGBuilder::init(),llvm::SITargetLowering::isEligibleForTailCallOptimization(),llvm::TargetLoweringBase::isLoadBitCastBeneficial(),llvm::AMDGPUTargetLowering::isLoadBitCastBeneficial(),isSaturatingMinMax(),isUpperSubvectorUndef(),llvm::RISCVTargetLowering::joinRegisterPartsIntoValue(),legalizeIntrinsicImmArg(),LowerADDSAT_SUBSAT(),llvm::X86TargetLowering::LowerAsmOperandForConstraint(),LowerAsSplatVectorLoad(),llvm::SelectionDAGBuilder::LowerAsSTATEPOINT(),lowerBitreverseShuffle(),lowerBuildVectorAsBroadcast(),llvm::SITargetLowering::LowerCall(),llvm::NVPTXTargetLowering::LowerCall(),llvm::SystemZTargetLowering::LowerCall(),llvm::XtensaTargetLowering::LowerCall(),llvm::HexagonTargetLowering::LowerCall(),llvm::LoongArchTargetLowering::LowerCall(),llvm::RISCVTargetLowering::LowerCall(),llvm::VETargetLowering::LowerCall(),llvm::SparcTargetLowering::LowerCall_32(),llvm::SparcTargetLowering::LowerCall_64(),llvm::SITargetLowering::LowerCallResult(),llvm::HexagonTargetLowering::LowerCallResult(),llvm::SelectionDAGBuilder::LowerCallSiteWithDeoptBundleImpl(),llvm::AMDGPUTargetLowering::LowerCONCAT_VECTORS(),LowerCONCAT_VECTORS_i1(),llvm::AMDGPUTargetLowering::LowerDIVREM24(),llvm::AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(),llvm::NVPTXTargetLowering::LowerDYNAMIC_STACKALLOC(),llvm::VETargetLowering::lowerDYNAMIC_STACKALLOC(),llvm::AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(),llvm::SparcTargetLowering::LowerF128_LibCallArg(),llvm::SparcTargetLowering::LowerF128Compare(),llvm::SparcTargetLowering::LowerF128Op(),llvm::AMDGPUTargetLowering::LowerFCEIL(),lowerFCMPIntrinsic(),llvm::AMDGPUTargetLowering::lowerFEXP(),llvm::AMDGPUTargetLowering::lowerFEXP10Unsafe(),llvm::AMDGPUTargetLowering::lowerFEXP2(),llvm::AMDGPUTargetLowering::lowerFEXPUnsafe(),llvm::AMDGPUTargetLowering::LowerFFLOOR(),LowerFMINIMUM_FMAXIMUM(),llvm::R600TargetLowering::LowerFormalArguments(),llvm::SITargetLowering::LowerFormalArguments(),llvm::HexagonTargetLowering::LowerFormalArguments(),llvm::LoongArchTargetLowering::LowerFormalArguments(),llvm::RISCVTargetLowering::LowerFormalArguments(),llvm::SystemZTargetLowering::LowerFormalArguments(),llvm::VETargetLowering::LowerFormalArguments(),llvm::XtensaTargetLowering::LowerFormalArguments(),llvm::SparcTargetLowering::LowerFormalArguments_32(),llvm::SparcTargetLowering::LowerFormalArguments_64(),llvm::AMDGPUTargetLowering::LowerFROUND(),llvm::AMDGPUTargetLowering::LowerFROUNDEVEN(),LowerFSINCOS(),llvm::AMDGPUTargetLowering::LowerFTRUNC(),llvm::AMDGPUTargetLowering::LowerGlobalAddress(),lowerICMPIntrinsic(),lowerLaneOp(),LowerMSCATTER(),LowerMULO(),llvm::RISCVTargetLowering::LowerOperation(),LowerPredicateLoad(),LowerPredicateStore(),llvm::SelectionDAGBuilder::lowerRangeToAssertZExt(),llvm::SITargetLowering::LowerReturn(),llvm::HexagonTargetLowering::LowerReturn(),llvm::LoongArchTargetLowering::LowerReturn(),llvm::RISCVTargetLowering::LowerReturn(),llvm::SystemZTargetLowering::LowerReturn(),llvm::VETargetLowering::LowerReturn(),llvm::XtensaTargetLowering::LowerReturn(),llvm::SparcTargetLowering::LowerReturn_32(),llvm::SparcTargetLowering::LowerReturn_64(),llvm::AMDGPUTargetLowering::LowerSDIVREM(),llvm::NVPTXTargetLowering::LowerSTACKRESTORE(),llvm::NVPTXTargetLowering::LowerSTACKSAVE(),llvm::SelectionDAGBuilder::LowerStatepoint(),LowerStore(),LowerSVEIntrinsicEXT(),llvm::TargetLowering::LowerToTLSEmulatedModel(),LowerToTLSExecModel(),llvm::VETargetLowering::lowerToVVP(),llvm::AMDGPUTargetLowering::LowerUDIVREM(),llvm::AMDGPUTargetLowering::LowerUDIVREM64(),LowerUINT_TO_FP_i64(),lowerUINT_TO_FP_vXi32(),llvm::HexagonTargetLowering::LowerUnalignedLoad(),llvm::AMDGPUTargetLowering::lowerUnhandledCall(),LowerVECTOR_SHUFFLE(),LowerVectorAllEqual(),lowerVectorBitClearImm(),lowerVectorBitRevImm(),lowerVectorBitSetImm(),LowerVectorExtend(),lowerVectorSplatImm(),LowerVSETCC(),llvm::VETargetLowering::lowerVVP_LOAD_STORE(),llvm::SystemZTargetLowering::makeExternalCall(),llvm::TargetLowering::makeLibCall(),makeStateFunctionCall(),matchBinOpReduction(),matchPMADDWD(),matchPMADDWD_2(),narrowExtractedVectorBinOp(),narrowIndex(),PerformARMBUILD_VECTORCombine(),PerformBUILD_VECTORCombine(),performConcatVectorsCombine(),llvm::AMDGPUTargetLowering::PerformDAGCombine(),llvm::PPCTargetLowering::PerformDAGCombine(),llvm::RISCVTargetLowering::PerformDAGCombine(),performDUPCombine(),performExtBinopLoadFold(),PerformExtractFpToIntStores(),PerformInsertEltCombine(),llvm::AMDGPUTargetLowering::performLoadCombine(),performLOADCombine(),PerformMinMaxFpToSatCombine(),performMSTORECombine(),performMulVectorCmpZeroCombine(),llvm::ARMTargetLowering::PerformMVEExtCombine(),llvm::ARMTargetLowering::PerformMVETruncCombine(),performSelectCombine(),performSignExtendInRegCombine(),PerformSplittingMVEEXTToWideningLoad(),PerformSplittingMVETruncToNarrowingStores(),PerformSplittingToNarrowingStores(),PerformSplittingToWideningLoad(),llvm::AMDGPUTargetLowering::performStoreCombine(),PerformSTORECombine(),performSunpkloCombine(),llvm::AMDGPUTargetLowering::performTruncateCombine(),PerformTruncatingStoreCombine(),performUADDVZextCombine(),PerformUMinFpToSatCombine(),performUzpCombine(),performVecReduceAddCombine(),performVECTOR_SHUFFLECombine(),performVectorExtCombine(),PromoteBinOpToF32(),llvm::TargetLoweringBase::promoteTargetBoolean(),promoteToConstantPool(),llvm::AArch64TargetLowering::ReconstructShuffle(),reduceVMULWidth(),ReplaceLoadVector(),llvm::SITargetLowering::ReplaceNodeResults(),llvm::LoongArchTargetLowering::ReplaceNodeResults(),llvm::PPCTargetLowering::ReplaceNodeResults(),llvm::RISCVTargetLowering::ReplaceNodeResults(),llvm::X86TargetLowering::ReplaceNodeResults(),scalarizeBinOpOfSplats(),llvm::TargetLowering::scalarizeVectorLoad(),llvm::TargetLowering::scalarizeVectorStore(),shouldTransformMulToShiftsAddsSubs(),llvm::TargetLowering::ShrinkDemandedOp(),ShrinkLoadReplaceStoreWithStore(),llvm::TargetLowering::SimplifyDemandedBits(),llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(),llvm::TargetLowering::SimplifySetCC(),skipExtensionForVectorMULL(),llvm::TargetLowering::softenSetCCOperands(),splitStores(),llvm::RISCVTargetLowering::splitValueIntoRegisterParts(),llvm::X86TargetLowering::targetShrinkDemandedConstant(),truncateVectorWithNARROW(),truncateVectorWithPACK(),tryCombineMULLWithUZP1(),tryFormConcatFromShuffle(),UnrollVectorOp(),UnrollVectorOverflowOp(),llvm::TargetLowering::verifyReturnAddressArgumentIsConstant(),llvm::SelectionDAGBuilder::visitBitTestCase(),llvm::SelectionDAGBuilder::visitBitTestHeader(),llvm::SelectionDAGBuilder::visitJumpTableHeader(),llvm::SelectionDAGBuilder::visitSPDescriptorParent(),llvm::SelectionDAGBuilder::visitSwitchCase(),widenAbs(),llvm::AMDGPUTargetLowering::WidenOrSplitVectorLoad(),widenVec(), andWidenVector().
| inline |
Definition at line828 of fileSelectionDAG.h.
Referencesllvm::ISD::CopyFromReg,getNode(),getRegister(),getVTList(), andReg.
Referenced byllvm::AMDGPUTargetLowering::CreateLiveInRegister(),emitSMEStateSaveRestore(),expandIntrinsicWChainHelper(),llvm::RegsForValue::getCopyFromRegs(),llvm::HexagonTargetLowering::GetDynamicTLSAddr(),getFRAMEADDR(),getReadTimeStampCounter(),GetTLSADDR(),getv64i1Argument(),getzOSCalleeAndADA(),llvm::X86TargetLowering::LowerAsmOutputForConstraint(),lowerBALLOTIntrinsic(),llvm::SITargetLowering::LowerCall(),llvm::NVPTXTargetLowering::LowerCall(),llvm::SystemZTargetLowering::LowerCall(),llvm::XtensaTargetLowering::LowerCall(),llvm::HexagonTargetLowering::LowerCall(),llvm::LoongArchTargetLowering::LowerCall(),llvm::RISCVTargetLowering::LowerCall(),llvm::VETargetLowering::LowerCall(),llvm::SparcTargetLowering::LowerCall_32(),llvm::SparcTargetLowering::LowerCall_64(),lowerCallResult(),llvm::SITargetLowering::LowerCallResult(),llvm::HexagonTargetLowering::LowerCallResult(),LowerCallResult(),LowerCMP_SWAP(),llvm::SITargetLowering::LowerDYNAMIC_STACKALLOC(),llvm::LanaiTargetLowering::LowerDYNAMIC_STACKALLOC(),LowerDYNAMIC_STACKALLOC(),llvm::R600TargetLowering::LowerFormalArguments(),llvm::SITargetLowering::LowerFormalArguments(),llvm::HexagonTargetLowering::LowerFormalArguments(),llvm::LoongArchTargetLowering::LowerFormalArguments(),llvm::RISCVTargetLowering::LowerFormalArguments(),llvm::SystemZTargetLowering::LowerFormalArguments(),llvm::VETargetLowering::LowerFormalArguments(),llvm::XtensaTargetLowering::LowerFormalArguments(),llvm::SparcTargetLowering::LowerFormalArguments_32(),llvm::SparcTargetLowering::LowerFormalArguments_64(),llvm::HexagonTargetLowering::LowerFRAMEADDR(),llvm::LanaiTargetLowering::LowerFRAMEADDR(),llvm::MSP430TargetLowering::LowerFRAMEADDR(),lowerFRAMEADDR(),llvm::SparcTargetLowering::LowerGlobalTLSAddress(),LowerINTRINSIC_W_CHAIN(),llvm::SparcTargetLowering::LowerReturn_32(),llvm::HexagonTargetLowering::LowerRETURNADDR(),llvm::LanaiTargetLowering::LowerRETURNADDR(),LowerRETURNADDR(),llvm::MSP430TargetLowering::LowerSETCC(),llvm::SITargetLowering::LowerSTACKSAVE(),llvm::VETargetLowering::lowerToTLSGeneralDynamicModel(),llvm::HexagonTargetLowering::LowerToTLSInitialExecModel(),llvm::HexagonTargetLowering::LowerToTLSLocalExecModel(),performDivRemCombine(),llvm::SparcTargetLowering::ReplaceNodeResults(),llvm::X86TargetLowering::ReplaceNodeResults(),replaceZeroVectorStore(),llvm::RISCVDAGToDAGISel::Select(),llvm::HexagonDAGToDAGISel::SelectFrameIndex(),llvm::LoongArchDAGToDAGISel::selectShiftMask(),llvm::AMDGPUTargetLowering::storeStackInputValue(),unpack64(),unpackF64OnRV32DSoftABI(),unpackFromRegLoc(),llvm::SelectionDAGBuilder::visitBitTestCase(), andllvm::SelectionDAGBuilder::visitJumpTable().
| inline |
Definition at line837 of fileSelectionDAG.h.
Referencesllvm::ISD::CopyFromReg,llvm::SDValue::getNode(),getNode(),getRegister(),getVTList(), andReg.
| inline |
Definition at line802 of fileSelectionDAG.h.
Referencesllvm::ISD::CopyToReg,getNode(),getRegister(),N, andReg.
Referenced byllvm::RISCVDAGToDAGISel::addVectorLoadStoreOperands(),emitRepmovs(),emitRepstos(),expandIntrinsicWChainHelper(),llvm::RegsForValue::getCopyToRegs(),llvm::MipsTargetLowering::getOpndList(),GetTLSADDR(),llvm::SITargetLowering::legalizeTargetIndependentNode(),llvm::SITargetLowering::LowerCall(),llvm::NVPTXTargetLowering::LowerCall(),llvm::SystemZTargetLowering::LowerCall(),llvm::XtensaTargetLowering::LowerCall(),llvm::HexagonTargetLowering::LowerCall(),llvm::LoongArchTargetLowering::LowerCall(),llvm::RISCVTargetLowering::LowerCall(),llvm::VETargetLowering::LowerCall(),llvm::SparcTargetLowering::LowerCall_32(),llvm::SparcTargetLowering::LowerCall_64(),llvm::HexagonTargetLowering::LowerCallResult(),llvm::SelectionDAGBuilder::LowerCallTo(),LowerCMP_SWAP(),llvm::SITargetLowering::LowerDYNAMIC_STACKALLOC(),llvm::LanaiTargetLowering::LowerDYNAMIC_STACKALLOC(),LowerDYNAMIC_STACKALLOC(),llvm::HexagonTargetLowering::LowerEH_RETURN(),llvm::SparcTargetLowering::LowerFormalArguments_32(),llvm::SparcTargetLowering::LowerGlobalTLSAddress(),llvm::SITargetLowering::LowerReturn(),llvm::HexagonTargetLowering::LowerReturn(),llvm::LoongArchTargetLowering::LowerReturn(),llvm::RISCVTargetLowering::LowerReturn(),llvm::SystemZTargetLowering::LowerReturn(),llvm::VETargetLowering::LowerReturn(),llvm::XtensaTargetLowering::LowerReturn(),llvm::SparcTargetLowering::LowerReturn_32(),llvm::SparcTargetLowering::LowerReturn_64(),llvm::HexagonTargetLowering::LowerToTLSGeneralDynamicModel(),llvm::SITargetLowering::PostISelFolding(),prepareDescriptorIndirectCall(),llvm::X86TargetLowering::ReplaceNodeResults(),llvm::RISCVDAGToDAGISel::Select(),llvm::SelectionDAGISel::SelectCodeCommon(),llvm::SelectionDAGBuilder::visitBitTestHeader(), andllvm::SelectionDAGBuilder::visitJumpTableHeader().
| inline |
Definition at line811 of fileSelectionDAG.h.
Referencesllvm::ISD::CopyToReg,llvm::SDValue::getNode(),getNode(),getRegister(),getVTList(),N, andReg.
| inline |
Definition at line820 of fileSelectionDAG.h.
Referencesllvm::ISD::CopyToReg,llvm::SDValue::getNode(),getNode(),getVTList(),N, andReg.
| inline |
Definition at line497 of fileSelectionDAG.h.
Referencesllvm::MachineFunction::getDataLayout().
Referenced byAddCombineBUILD_VECTORToVPADDL(),AddCombineToVPADD(),AddCombineVUZPToVPADDL(),addShuffleForVecExtend(),analyzeCallOperands(),llvm::SparcTargetLowering::bitcastConstantFPToInt(),BuildExactSDIV(),BuildExactUDIV(),llvm::TargetLowering::BuildSDIV(),llvm::TargetLowering::buildSDIVPow2WithCMov(),llvm::TargetLowering::BuildUDIV(),canCombineShuffleToExtendVectorInreg(),canFoldInAddressingMode(),combineBVOfVecSExt(),combineConcatVectorOps(),combineFMinNumFMaxNum(),combineGatherScatter(),combineLoad(),combinePredicateReduction(),combineShiftAnd1ToBitTest(),combineShuffleToAnyExtendVectorInreg(),combineShuffleToZeroExtendVectorInReg(),combineStore(),combineTargetShuffle(),combineTruncationShuffle(),combineVSelectWithAllOnesOrZeros(),computeKnownBits(),llvm::AMDGPUTargetLowering::computeKnownBitsForTargetNode(),ComputeNumSignBits(),llvm::SelectionDAGBuilder::CopyValueToVirtualRegister(),createGPRPairNode(),createGPRPairNodei64(),createMMXBuildVector(),createSetFPEnvNodes(),CreateStackTemporary(),llvm::TargetLowering::CTTZTableLookup(),EltsFromConsecutiveLoads(),emitSMEStateSaveRestore(),llvm::ARMSelectionDAGInfo::EmitSpecializedLibcall(),llvm::X86TargetLowering::emitStackGuardXorFP(),llvm::AArch64SelectionDAGInfo::EmitStreamingCompatibleMemLibCall(),llvm::HexagonSelectionDAGInfo::EmitTargetCodeForMemcpy(),llvm::XCoreSelectionDAGInfo::EmitTargetCodeForMemcpy(),llvm::TargetLowering::expandABD(),llvm::TargetLowering::expandAddSubSat(),llvm::TargetLowering::expandBITREVERSE(),llvm::TargetLowering::expandBSWAP(),llvm::TargetLowering::expandCMP(),llvm::TargetLowering::expandCTLZ(),llvm::TargetLowering::expandCTPOP(),llvm::TargetLowering::expandCTTZ(),expandDivFix(),llvm::TargetLowering::expandDIVREMByConstant(),llvm::TargetLowering::expandFixedPointDiv(),llvm::TargetLowering::expandFixedPointMul(),llvm::TargetLowering::expandFMINIMUM_FMAXIMUM(),llvm::TargetLowering::expandFMINIMUMNUM_FMAXIMUMNUM(),llvm::TargetLowering::expandFP_ROUND(),llvm::TargetLowering::expandFP_TO_INT_SAT(),llvm::TargetLowering::expandFP_TO_SINT(),llvm::TargetLowering::expandFP_TO_UINT(),llvm::TargetLowering::expandIntMINMAX(),llvm::TargetLowering::expandMUL_LOHI(),llvm::TargetLowering::expandMULO(),expandMultipleResultFPLibCall(),llvm::TargetLowering::expandRoundInexactToOdd(),llvm::TargetLowering::expandSADDSUBO(),llvm::TargetLowering::expandShiftParts(),llvm::TargetLowering::expandShlSat(),llvm::TargetLowering::expandUADDSUBO(),llvm::TargetLowering::expandUnalignedLoad(),llvm::TargetLowering::expandUnalignedStore(),expandVAArg(),expandVACopy(),llvm::TargetLowering::expandVECTOR_COMPRESS(),llvm::TargetLowering::expandVPBITREVERSE(),llvm::TargetLowering::expandVPBSWAP(),llvm::TargetLowering::expandVPCTLZ(),llvm::TargetLowering::expandVPCTPOP(),FoldConstantArithmetic(),foldXorTruncShiftIntoCmp(),llvm::TargetLowering::forceExpandWideMUL(),getADAEntry(),getAddressForMemoryInput(),getAtomicMemcpy(),getAtomicMemmove(),getAtomicMemset(),getAVX2GatherNode(),getConstant(),getConstantPool(),getCopyFromParts(),llvm::SelectionDAGBuilder::getCopyFromRegs(),getCopyToParts(),getEVTAlign(),GetExponent(),llvm::SelectionDAGBuilder::getFrameIndexTy(),getGatherNode(),getGlobalAddress(),llvm::MipsDAGToDAGISel::getGlobalBaseReg(),getIntPtrConstant(),llvm::AMDGPUTargetLowering::getIsFinite(),llvm::AMDGPUTargetLowering::getIsLtSmallestNormal(),getJumpTableDebugInfo(),getLifetimeNode(),getLimitedPrecisionExp2(),getLoadStackGuard(),getMemCmpLoad(),getMemcpy(),getMemcpyLoadsAndStores(),getMemmove(),getMemmoveLoadsAndStores(),getMemset(),getMemsetStores(),getMemsetStringVal(),getNode(),llvm::TargetLowering::getPICJumpTableRelocBase(),llvm::M68kTargetLowering::getPICJumpTableRelocBase(),llvm::PPCTargetLowering::getPICJumpTableRelocBase(),llvm::VETargetLowering::getPICJumpTableRelocBase(),llvm::X86TargetLowering::getPICJumpTableRelocBase(),getPPCf128HiElementSelector(),getPrefetchNode(),getPrefTypeAlign(),getReducedAlign(),llvm::X86TargetLowering::getReturnAddressFrameIndex(),llvm::AMDGPUTargetLowering::getScaledLogInput(),getScatterNode(),getShiftAmountConstant(),getShiftAmountOperand(),llvm::PPC::getSplatIdxForPPCMnemonics(),llvm::TargetLowering::getSqrtInputTest(),getSymbolFunctionGlobalAddress(),getTagSymNode(),getUniformBase(),llvm::SelectionDAGBuilder::getValueImpl(),getVectorIdxConstant(),getzOSCalleeAndADA(),llvm::SelectionDAGBuilder::handleDebugValue(),InferPtrAlign(),llvm::SelectionDAGBuilder::init(),isBLACompatibleAddress(),isExtendedBUILD_VECTOR(),llvm::TargetLoweringBase::isLoadBitCastBeneficial(),llvm::AMDGPUTargetLowering::isLoadBitCastBeneficial(),IsPredicateKnownToFail(),llvm::PPC::isVMRGEOShuffleMask(),llvm::PPC::isVMRGHShuffleMask(),llvm::PPC::isVMRGLShuffleMask(),llvm::PPC::isVPKUDUMShuffleMask(),llvm::PPC::isVPKUHUMShuffleMask(),llvm::PPC::isVPKUWUMShuffleMask(),llvm::PPC::isVSLDOIShuffleMask(),LowerADDSAT_SUBSAT(),llvm::SelectionDAGBuilder::LowerAsSTATEPOINT(),llvm::HexagonTargetLowering::LowerBlockAddress(),lowerBuildVectorAsBroadcast(),llvm::NVPTXTargetLowering::LowerCall(),llvm::XtensaTargetLowering::LowerCall(),llvm::LoongArchTargetLowering::LowerCall(),llvm::RISCVTargetLowering::LowerCall(),llvm::VETargetLowering::LowerCall(),llvm::SparcTargetLowering::LowerCall_32(),llvm::SparcTargetLowering::LowerCall_64(),llvm::SelectionDAGBuilder::LowerCallSiteWithPtrAuthBundle(),llvm::TargetLowering::LowerCallTo(),llvm::SelectionDAGBuilder::LowerCallTo(),llvm::LanaiTargetLowering::LowerConstantPool(),LowerCTPOP(),llvm::SelectionDAGBuilder::LowerDeoptimizeCall(),llvm::AMDGPUTargetLowering::LowerDIVREM24(),llvm::HexagonTargetLowering::LowerEH_RETURN(),llvm::SparcTargetLowering::LowerF128_LibCallArg(),llvm::SparcTargetLowering::LowerF128Compare(),llvm::SparcTargetLowering::LowerF128Op(),LowerF64Op(),llvm::AMDGPUTargetLowering::LowerFCEIL(),llvm::AMDGPUTargetLowering::lowerFEXP(),llvm::AMDGPUTargetLowering::lowerFEXP10Unsafe(),llvm::AMDGPUTargetLowering::lowerFEXP2(),llvm::AMDGPUTargetLowering::lowerFEXPUnsafe(),llvm::AMDGPUTargetLowering::LowerFFLOOR(),LowerFMINIMUM_FMAXIMUM(),LowerFNEGorFABS(),llvm::LoongArchTargetLowering::LowerFormalArguments(),llvm::NVPTXTargetLowering::LowerFormalArguments(),llvm::RISCVTargetLowering::LowerFormalArguments(),llvm::SystemZTargetLowering::LowerFormalArguments(),llvm::XtensaTargetLowering::LowerFormalArguments(),llvm::SparcTargetLowering::LowerFormalArguments_32(),llvm::AMDGPUTargetLowering::LowerFROUND(),llvm::AMDGPUTargetLowering::LowerFROUNDEVEN(),LowerFSINCOS(),llvm::AMDGPUTargetLowering::LowerFTRUNC(),llvm::HexagonTargetLowering::LowerGLOBAL_OFFSET_TABLE(),llvm::AMDGPUTargetLowering::LowerGlobalAddress(),llvm::HexagonTargetLowering::LowerGLOBALADDRESS(),llvm::LanaiTargetLowering::LowerGlobalAddress(),llvm::NVPTXTargetLowering::LowerGlobalAddress(),llvm::SparcTargetLowering::LowerGlobalTLSAddress(),llvm::SparcTargetLowering::LowerINTRINSIC_WO_CHAIN(),llvm::LanaiTargetLowering::LowerJumpTable(),LowerMemOpCallTo(),LowerMULO(),llvm::R600TargetLowering::LowerOperation(),llvm::RISCVTargetLowering::LowerOperation(),LowerPredicateLoad(),LowerPredicateStore(),llvm::NVPTXTargetLowering::LowerReturn(),llvm::SparcTargetLowering::LowerReturn_32(),LowerRETURNADDR(),llvm::NVPTXTargetLowering::LowerSTACKRESTORE(),llvm::NVPTXTargetLowering::LowerSTACKSAVE(),llvm::SelectionDAGBuilder::LowerStatepoint(),LowerSTORE(),llvm::TargetLowering::LowerToTLSEmulatedModel(),llvm::HexagonTargetLowering::LowerToTLSGeneralDynamicModel(),llvm::HexagonTargetLowering::LowerToTLSInitialExecModel(),llvm::HexagonTargetLowering::LowerToTLSLocalExecModel(),llvm::AMDGPUTargetLowering::LowerUDIVREM(),LowerUINT_TO_FP_i64(),lowerUINT_TO_FP_vXi32(),llvm::HexagonTargetLowering::LowerUnalignedLoad(),LowerVASTART(),llvm::HexagonTargetLowering::LowerVASTART(),llvm::LanaiTargetLowering::LowerVASTART(),llvm::VETargetLowering::lowerVASTART(),llvm::SparcTargetLowering::makeAddress(),llvm::SystemZTargetLowering::makeExternalCall(),llvm::TargetLowering::makeLibCall(),makeStateFunctionCall(),matchPERM(),narrowExtractedVectorLoad(),PerformBITCASTCombine(),llvm::PPCTargetLowering::PerformDAGCombine(),llvm::RISCVTargetLowering::PerformDAGCombine(),performMULCombine(),PerformSTORECombine(),llvm::AMDGPUTargetLowering::performTruncateCombine(),PerformTruncatingStoreCombine(),performUzpCombine(),PerformVMOVRRDCombine(),llvm::TargetLoweringBase::promoteTargetBoolean(),promoteToConstantPool(),llvm::AArch64TargetLowering::ReconstructShuffle(),recoverFramePointer(),reduceBuildVecToShuffleWithZero(),ReplaceATOMIC_LOAD_128Results(),ReplaceCMP_SWAP_128Results(),ReplaceCMP_SWAP_64Results(),ReplaceLoadVector(),llvm::SITargetLowering::ReplaceNodeResults(),llvm::PPCTargetLowering::ReplaceNodeResults(),llvm::TargetLowering::scalarizeVectorLoad(),llvm::TargetLowering::scalarizeVectorStore(),llvm::PPCTargetLowering::SelectAddressRegImm(),llvm::RISCVDAGToDAGISel::SelectAddrRegImm(),llvm::SelectionDAGISel::SelectCodeCommon(),llvm::PPCTargetLowering::SelectOptimalAddrMode(),ShrinkLoadReplaceStoreWithStore(),llvm::TargetLowering::SimplifyDemandedBits(),llvm::TargetLowering::SimplifyDemandedVectorElts(),llvm::TargetLowering::SimplifyMultipleUseDemandedBits(),llvm::TargetLowering::SimplifySetCC(),SkipExtensionForVMULL(),llvm::TargetLowering::softenSetCCOperands(),transformCallee(),unpackFromMemLoc(),UnrollVectorOverflowOp(),llvm::SelectionDAGBuilder::visitBitTestCase(),llvm::SelectionDAGBuilder::visitBitTestHeader(),llvm::SelectionDAGBuilder::visitJumpTable(),llvm::SelectionDAGBuilder::visitJumpTableHeader(),llvm::SelectionDAGBuilder::visitSPDescriptorParent(),llvm::SelectionDAGBuilder::visitSwitchCase(), andllvm::AMDGPUTargetLowering::WidenOrSplitVectorLoad().
SDDbgLabel * SelectionDAG::getDbgLabel | ( | DILabel * | Label, |
constDebugLoc & | DL, | ||
unsigned | O | ||
) |
Creates aSDDbgLabel node.
Definition at line11616 of fileSelectionDAG.cpp.
Referencesassert(),DL, andllvm::SDDbgInfo::getAlloc().
Referenced byllvm::SelectionDAGBuilder::visitDbgInfo().
SDDbgValue * SelectionDAG::getDbgValue | ( | DIVariable * | Var, |
DIExpression * | Expr, | ||
SDNode * | N, | ||
unsigned | R, | ||
bool | IsIndirect, | ||
constDebugLoc & | DL, | ||
unsigned | O | ||
) |
Creates aSDDbgValue node.
getDbgValue - Creates aSDDbgValue node.
Definition at line11326 of fileSelectionDAG.cpp.
Referencesassert(),DL,llvm::SDDbgOperand::fromNode(),llvm::SDDbgInfo::getAlloc(), andN.
Referenced byllvm::SelectionDAGBuilder::handleDebugDeclare().
SDDbgValue * SelectionDAG::getDbgValueList | ( | DIVariable * | Var, |
DIExpression * | Expr, | ||
ArrayRef<SDDbgOperand > | Locs, | ||
ArrayRef<SDNode * > | Dependencies, | ||
bool | IsIndirect, | ||
constDebugLoc & | DL, | ||
unsigned | O, | ||
bool | IsVariadic | ||
) |
Creates aSDDbgValue node from a list of locations.
Definition at line11388 of fileSelectionDAG.cpp.
Referencesassert(),DL, andllvm::SDDbgInfo::getAlloc().
Referenced byhandleDanglingVariadicDebugInfo(),llvm::SelectionDAGBuilder::handleDebugValue(),salvageDebugInfo(), andtransferDbgValues().
| inline |
Get the debug values which reference the givenSDNode.
Definition at line1865 of fileSelectionDAG.h.
Referencesllvm::SDDbgInfo::getSDDbgValues().
Referenced byProcessSDDbgValues(),salvageDebugInfo(), andtransferDbgValues().
| inline |
Return the current function's default denormal handling kind for the given floating point type.
Definition at line2409 of fileSelectionDAG.h.
Referencesllvm::MachineFunction::getDenormalMode(), andllvm::EVT::getFltSemantics().
std::pair<EVT,EVT > SelectionDAG::GetDependentSplitDestVTs | ( | constEVT & | VT, |
constEVT & | EnvVT, | ||
bool * | HiIsEmpty | ||
) | const |
Compute the VTs needed for the low/hi parts of a type, dependent on an enveloping VT that has been split into two identical pieces.
GetDependentSplitDestVTs - Compute the VTs needed for the low/hi parts of a type, dependent on an enveloping VT that has been split into two identical pieces.
Sets the HisIsEmpty flag when hi type has zero storage size.
Sets the HiIsEmpty flag when hi type has zero storage size.
Definition at line12976 of fileSelectionDAG.cpp.
Referencesassert(),getContext(),llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(),llvm::EVT::getVectorElementCount(),llvm::EVT::getVectorElementType(),llvm::EVT::getVectorVT(), andllvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isScalable().
Definition at line2358 of fileSelectionDAG.cpp.
Referencesllvm::ISD::EH_LABEL, andgetLabelNode().
SDValue SelectionDAG::getElementCount | ( | constSDLoc & | DL, |
EVT | VT, | ||
ElementCount | EC, | ||
bool | ConstantFold =true | ||
) |
Definition at line2111 of fileSelectionDAG.cpp.
ReferencesDL,getConstant(),llvm::EVT::getSizeInBits(), andgetVScale().
Referenced byllvm::RISCVTargetLowering::computeVLMax(),lowerCttzElts(), andllvm::RISCVTargetLowering::PerformDAGCombine().
| inline |
Return the token chain corresponding to the entry of the function.
Definition at line580 of fileSelectionDAG.h.
Referenced byllvm::AMDGPUTargetLowering::addTokenForArgument(),clear(),combineConcatVectorOps(),combineTargetShuffle(),copyExtraInfo(),llvm::SelectionDAGBuilder::CopyValueToVirtualRegister(),llvm::AMDGPUTargetLowering::CreateLiveInRegister(),llvm::AMDGPUTargetLowering::CreateLiveInRegisterRaw(),llvm::TargetLowering::CTTZTableLookup(),expandMultipleResultFPLibCall(),llvm::TargetLowering::expandVECTOR_COMPRESS(),llvm::TargetLowering::expandVectorSplice(),getADAEntry(),llvm::MipsTargetLowering::getAddrLocal(),llvm::SelectionDAGBuilder::getCopyFromRegs(),getFLUSHW(),getFRAMEADDR(),getLargeExternalSymbol(),getLargeGlobalAddress(),getMemCmpLoad(),getStackArgumentTokenFactor(),GetTLSADDR(),llvm::SelectionDAGBuilder::getValueImpl(),getzOSCalleeAndADA(),HandleMergeInputChains(),llvm::AMDGPUTargetLowering::loadStackInputValue(),lowerBALLOTIntrinsic(),lowerBuildVectorAsBroadcast(),llvm::NVPTXTargetLowering::LowerCall(),llvm::SparcTargetLowering::LowerF128Compare(),llvm::SparcTargetLowering::LowerF128Op(),LowerFCanonicalize(),llvm::SITargetLowering::LowerFormalArguments(),llvm::SparcTargetLowering::LowerFormalArguments_32(),llvm::HexagonTargetLowering::LowerFRAMEADDR(),llvm::LanaiTargetLowering::LowerFRAMEADDR(),llvm::MSP430TargetLowering::LowerFRAMEADDR(),lowerFRAMEADDR(),LowerFSINCOS(),llvm::AMDGPUTargetLowering::LowerGlobalAddress(),llvm::SparcTargetLowering::LowerGlobalTLSAddress(),llvm::HexagonTargetLowering::LowerRETURNADDR(),llvm::LanaiTargetLowering::LowerRETURNADDR(),llvm::MSP430TargetLowering::LowerRETURNADDR(),LowerRETURNADDR(),lowerRETURNADDR(),llvm::MSP430TargetLowering::LowerSETCC(),llvm::SelectionDAGBuilder::LowerStatepoint(),llvm::TargetLowering::LowerToTLSEmulatedModel(),LowerToTLSExecModel(),llvm::HexagonTargetLowering::LowerToTLSGeneralDynamicModel(),llvm::VETargetLowering::lowerToTLSGeneralDynamicModel(),llvm::HexagonTargetLowering::LowerToTLSInitialExecModel(),llvm::HexagonTargetLowering::LowerToTLSLocalExecModel(),LowerUINT_TO_FP_i64(),lowerUINT_TO_FP_vXi32(),llvm::AMDGPUTargetLowering::lowerUnhandledCall(),llvm::SparcTargetLowering::makeAddress(),llvm::VETargetLowering::makeAddress(),llvm::TargetLowering::makeLibCall(),performDivRemCombine(),llvm::ARMTargetLowering::PerformMVEExtCombine(),llvm::ARMTargetLowering::PerformMVETruncCombine(),llvm::SITargetLowering::PostISelFolding(),llvm::RISCVDAGToDAGISel::PreprocessISelDAG(),promoteXINT_TO_FP(),llvm::SITargetLowering::ReplaceNodeResults(),replaceZeroVectorStore(),llvm::RISCVDAGToDAGISel::Select(),llvm::SelectionDAGISel::SelectCodeCommon(),llvm::HexagonDAGToDAGISel::SelectFrameIndex(),llvm::LoongArchDAGToDAGISel::selectShiftMask(),llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetShuffle(), andllvm::SelectionDAGBuilder::visitSPDescriptorParent().
Compute the default alignment value for the given type.
Definition at line1358 of fileSelectionDAG.cpp.
Referencesllvm::PointerType::get(),llvm::DataLayout::getABITypeAlign(),getContext(),getDataLayout(), andllvm::EVT::getTypeForEVT().
Referenced bygetLoad(),getLoadStackGuard(),getLoadVP(),getMemIntrinsicNode(),getStore(), andgetTruncStore().
Definition at line2052 of fileSelectionDAG.cpp.
ReferencesgetVTList(),N, andSym.
Referenced byemitSMEStateSaveRestore(),llvm::ARMSelectionDAGInfo::EmitSpecializedLibcall(),llvm::AArch64SelectionDAGInfo::EmitStreamingCompatibleMemLibCall(),llvm::XCoreSelectionDAGInfo::EmitTargetCodeForMemcpy(),expandMultipleResultFPLibCall(),getAtomicMemcpy(),getAtomicMemmove(),getAtomicMemset(),getMemcpy(),getMemmove(),getMemset(),llvm::SelectionDAGBuilder::LowerDeoptimizeCall(),llvm::SparcTargetLowering::LowerF128Compare(),llvm::SparcTargetLowering::LowerF128Op(),LowerFSINCOS(),llvm::TargetLowering::LowerToTLSEmulatedModel(),llvm::SystemZTargetLowering::makeExternalCall(),llvm::TargetLowering::makeLibCall(), andmakeStateFunctionCall().
SDValue SelectionDAG::getExtLoad | ( | ISD::LoadExtType | ExtType, |
constSDLoc & | dl, | ||
EVT | VT, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
EVT | MemVT, | ||
MachineMemOperand * | MMO | ||
) |
Definition at line9298 of fileSelectionDAG.cpp.
ReferencesgetLoad(),getUNDEF(),Ptr, andllvm::ISD::UNINDEXED.
SDValue SelectionDAG::getExtLoad | ( | ISD::LoadExtType | ExtType, |
constSDLoc & | dl, | ||
EVT | VT, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
MachinePointerInfo | PtrInfo, | ||
EVT | MemVT, | ||
MaybeAlign | Alignment =MaybeAlign() , | ||
MachineMemOperand::Flags | MMOFlags =MachineMemOperand::MONone , | ||
constAAMDNodes & | AAInfo =AAMDNodes() | ||
) |
Definition at line9287 of fileSelectionDAG.cpp.
ReferencesgetLoad(),getUNDEF(),Ptr, andllvm::ISD::UNINDEXED.
Referenced byadjustSubwordCmp(),combineEXTEND_VECTOR_INREG(),combineLoad(),llvm::TargetLowering::CTTZTableLookup(),llvm::TargetLowering::expandUnalignedLoad(),llvm::TargetLowering::expandUnalignedStore(),getMemcpyLoadsAndStores(),LowerPredicateLoad(),lowerVECTOR_SHUFFLE(),llvm::RISCVTargetLowering::PerformDAGCombine(),performFPExtendCombine(),llvm::ARMTargetLowering::PerformMVEExtCombine(),PerformVMOVrhCombine(),llvm::RISCVTargetLowering::ReplaceNodeResults(),llvm::SparcTargetLowering::ReplaceNodeResults(),llvm::TargetLowering::scalarizeVectorLoad(),SkipLoadExtensionForVMULL(),llvm::AMDGPUTargetLowering::SplitVectorLoad(),tryToFoldExtOfExtload(),tryToFoldExtOfLoad(),unpackFromMemLoc(), andllvm::AMDGPUTargetLowering::WidenOrSplitVectorLoad().
SDValue SelectionDAG::getExtLoadVP | ( | ISD::LoadExtType | ExtType, |
constSDLoc & | dl, | ||
EVT | VT, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
SDValue | Mask, | ||
SDValue | EVL, | ||
EVT | MemVT, | ||
MachineMemOperand * | MMO, | ||
bool | IsExpanding =false | ||
) |
Definition at line9559 of fileSelectionDAG.cpp.
ReferencesgetLoadVP(),getUNDEF(),Ptr, andllvm::ISD::UNINDEXED.
SDValue SelectionDAG::getExtLoadVP | ( | ISD::LoadExtType | ExtType, |
constSDLoc & | dl, | ||
EVT | VT, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
SDValue | Mask, | ||
SDValue | EVL, | ||
MachinePointerInfo | PtrInfo, | ||
EVT | MemVT, | ||
MaybeAlign | Alignment, | ||
MachineMemOperand::Flags | MMOFlags, | ||
constAAMDNodes & | AAInfo, | ||
bool | IsExpanding =false | ||
) |
Definition at line9546 of fileSelectionDAG.cpp.
ReferencesgetLoadVP(),getUNDEF(),Ptr, andllvm::ISD::UNINDEXED.
Convert Op, which must be of integer type, to the integer type VT, by either sign/zero-extending (depending on IsSigned) or truncating it.
Definition at line999 of fileSelectionDAG.h.
ReferencesDL,getSExtOrTrunc(), andgetZExtOrTrunc().
Convert Op, which must be of integer type, to the integer type VT, by either any/sign/zero-extending (depending on IsAny / IsSigned) or truncating it.
Definition at line983 of fileSelectionDAG.h.
Referencesllvm::ISD::ANY_EXTEND,DL,getAnyExtOrTrunc(),getSExtOrTrunc(),getZExtOrTrunc(),llvm_unreachable,llvm::ISD::SIGN_EXTEND, andllvm::ISD::ZERO_EXTEND.
Referenced bycombineShiftToAVG(),combineShiftToMULH(),earlyExpandDIVFIX(),expandDivFix(),LowerShift(), andPerformMinMaxFpToSatCombine().
SDValue SelectionDAG::getExtStridedLoadVP | ( | ISD::LoadExtType | ExtType, |
constSDLoc & | DL, | ||
EVT | VT, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
SDValue | Stride, | ||
SDValue | Mask, | ||
SDValue | EVL, | ||
EVT | MemVT, | ||
MachineMemOperand * | MMO, | ||
bool | IsExpanding =false | ||
) |
Definition at line9764 of fileSelectionDAG.cpp.
ReferencesDL,getStridedLoadVP(),getUNDEF(),Ptr, andllvm::ISD::UNINDEXED.
| inline |
Definition at line516 of fileSelectionDAG.h.
Convert Op, which must be of float type, to the float type VT, by either extending or rounding (by truncation).
Definition at line1475 of fileSelectionDAG.cpp.
Referencesllvm::EVT::bitsGT(),DL,llvm::ISD::FP_EXTEND,llvm::ISD::FP_ROUND,getIntPtrConstant(), andgetNode().
Referenced byllvm::TargetLowering::expandRoundInexactToOdd(),getCopyFromPartsVector(),getNode(),llvm::RISCVTargetLowering::LowerOperation(),LowerUINT_TO_FP_i32(),llvm::RISCVTargetLowering::PerformDAGCombine(), andPromoteBinOpToF32().
Definition at line1925 of fileSelectionDAG.cpp.
ReferencesAddNodeIDNode(),llvm::ISD::FrameIndex,getVTList(),N, andllvm::ISD::TargetFrameIndex.
Referenced byllvm::StatepointLoweringState::allocateStackSlot(),llvm::X86TargetLowering::BuildFILD(),CalculateTailCallArgDest(),CreateStackTemporary(),EmitTailCallStoreFPAndRetAddr(),EmitTailCallStoreRetAddr(),getAddressForMemoryInput(),getLifetimeNode(),llvm::MSP430TargetLowering::getReturnAddressFrameIndex(),llvm::X86TargetLowering::getReturnAddressFrameIndex(),getTargetFrameIndex(),llvm::SelectionDAGBuilder::getValueImpl(),llvm::AMDGPUTargetLowering::loadStackInputValue(),llvm::SITargetLowering::LowerCall(),llvm::LoongArchTargetLowering::LowerCall(),llvm::RISCVTargetLowering::LowerCall(),llvm::SparcTargetLowering::LowerCall_32(),llvm::TargetLowering::LowerCallTo(),llvm::SparcTargetLowering::LowerF128_LibCallArg(),llvm::SparcTargetLowering::LowerF128Op(),llvm::HexagonTargetLowering::LowerFormalArguments(),llvm::LoongArchTargetLowering::LowerFormalArguments(),llvm::RISCVTargetLowering::LowerFormalArguments(),llvm::SystemZTargetLowering::LowerFormalArguments(),llvm::VETargetLowering::LowerFormalArguments(),llvm::XtensaTargetLowering::LowerFormalArguments(),llvm::SparcTargetLowering::LowerFormalArguments_32(),llvm::SparcTargetLowering::LowerFormalArguments_64(),LowerINTRINSIC_W_CHAIN(),lowerStatepointMetaArgs(),LowerVASTART(),llvm::HexagonTargetLowering::LowerVASTART(),llvm::LanaiTargetLowering::LowerVASTART(),llvm::MSP430TargetLowering::LowerVASTART(),unpack64(),unpackF64OnRV32DSoftABI(),unpackFromMemLoc(), andllvm::SelectionDAGBuilder::visitSPDescriptorParent().
SDDbgValue * SelectionDAG::getFrameIndexDbgValue | ( | DIVariable * | Var, |
DIExpression * | Expr, | ||
unsigned | FI, | ||
ArrayRef<SDNode * > | Dependencies, | ||
bool | IsIndirect, | ||
constDebugLoc & | DL, | ||
unsigned | O | ||
) |
Creates a FrameIndexSDDbgValue node.
FrameIndex with dependencies.
Definition at line11362 of fileSelectionDAG.cpp.
Referencesassert(),DL,llvm::SDDbgOperand::fromFrameIdx(), andllvm::SDDbgInfo::getAlloc().
SDDbgValue * SelectionDAG::getFrameIndexDbgValue | ( | DIVariable * | Var, |
DIExpression * | Expr, | ||
unsigned | FI, | ||
bool | IsIndirect, | ||
constDebugLoc & | DL, | ||
unsigned | O | ||
) |
Creates a FrameIndexSDDbgValue node.
FrameIndex.
Definition at line11351 of fileSelectionDAG.cpp.
Referencesassert(),DL, andgetFrameIndexDbgValue().
Referenced bygetFrameIndexDbgValue(), andllvm::SelectionDAGBuilder::handleDebugDeclare().
Return a freeze using theSDLoc of the value operand.
Definition at line2462 of fileSelectionDAG.cpp.
Referencesllvm::ISD::FREEZE, andgetNode().
Referenced bycombinePredicateReduction(),combineSelectToBinOp(),llvm::TargetLowering::expandABD(),llvm::TargetLowering::expandABS(),llvm::TargetLowering::expandAVG(),llvm::TargetLowering::expandIntMINMAX(),llvm::TargetLowering::expandVECTOR_COMPRESS(),foldBoolSelectToLogic(),foldSelectWithIdentityConstant(),foldVSelectToSignBitSplatMask(),getNode(),LowerABD(),LowerAVXCONCAT_VECTORS(),llvm::RISCVTargetLowering::LowerOperation(),LowerShiftByScalarImmediate(),lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(),lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND(),llvm::RISCVTargetLowering::PerformDAGCombine(),llvm::RISCVTargetLowering::ReplaceNodeResults(), andllvm::TargetLowering::SimplifyDemandedVectorElts().
| inline |
Returns the result of theAssignmentTrackingAnalysis pass if it's available, otherwise return nullptr.
Definition at line509 of fileSelectionDAG.h.
Referenced byllvm::SelectionDAGBuilder::visitDbgInfo().
SDValue SelectionDAG::getGatherVP | ( | SDVTList | VTs, |
EVT | VT, | ||
constSDLoc & | dl, | ||
ArrayRef<SDValue > | Ops, | ||
MachineMemOperand * | MMO, | ||
ISD::MemIndexType | IndexType | ||
) |
Definition at line9858 of fileSelectionDAG.cpp.
ReferencesAddNodeIDNode(),assert(),llvm::MachinePointerInfo::getAddrSpace(),llvm::SDLoc::getDebugLoc(),llvm::MachineMemOperand::getFlags(),llvm::SDLoc::getIROrder(),llvm::MachineMemOperand::getPointerInfo(),llvm::EVT::getRawBits(),llvm::details::FixedOrScalableQuantity< ElementCount, unsigned >::isKnownGE(),N,NewSDValueDbgMsg(), andllvm::ArrayRef< T >::size().
Referenced byllvm::RISCVTargetLowering::PerformDAGCombine().
SDValue SelectionDAG::getGetFPEnv | ( | SDValue | Chain, |
constSDLoc & | dl, | ||
SDValue | Ptr, | ||
EVT | MemVT, | ||
MachineMemOperand * | MMO | ||
) |
Definition at line10171 of fileSelectionDAG.cpp.
ReferencesAddNodeIDNode(),assert(),llvm::ISD::GET_FPENV_MEM,llvm::MachinePointerInfo::getAddrSpace(),llvm::SDLoc::getDebugLoc(),llvm::MachineMemOperand::getFlags(),llvm::SDLoc::getIROrder(),llvm::MachineMemOperand::getPointerInfo(),llvm::EVT::getRawBits(),llvm::SDValue::getValueType(),getVTList(),N,NewSDValueDbgMsg(), andPtr.
Return a GLOBAL_OFFSET_TABLE node. This does not have a usefulSDLoc.
Definition at line1141 of fileSelectionDAG.h.
ReferencesgetNode(), andllvm::ISD::GLOBAL_OFFSET_TABLE.
Referenced byllvm::TargetLowering::getPICJumpTableRelocBase(), andllvm::HexagonTargetLowering::LowerGLOBALADDRESS().
SDValue SelectionDAG::getGlobalAddress | ( | constGlobalValue * | GV, |
constSDLoc & | DL, | ||
EVT | VT, | ||
int64_t | offset =0 , | ||
bool | isTargetGA =false , | ||
unsigned | TargetFlags =0 | ||
) |
Definition at line1891 of fileSelectionDAG.cpp.
ReferencesAddNodeIDNode(),assert(),llvm::BitWidth,DL,getDataLayout(),llvm::DataLayout::getPointerTypeSizeInBits(),llvm::GlobalValue::getType(),getVTList(),llvm::ISD::GlobalAddress,llvm::ISD::GlobalTLSAddress,llvm::GlobalValue::isThreadLocal(),N,llvm::Offset,llvm::SignExtend64(),llvm::ISD::TargetGlobalAddress, andllvm::ISD::TargetGlobalTLSAddress.
Referenced byFoldSymbolOffset(),llvm::VETargetLowering::getPICJumpTableRelocBase(),getSymbolFunctionGlobalAddress(),getTargetGlobalAddress(),llvm::SelectionDAGBuilder::getValueImpl(),llvm::TargetLowering::LowerToTLSEmulatedModel(), andperformGlobalAddressCombine().
Get graph attributes for a node.
getGraphAttrs - Get graph attributes for a node.
(eg. "color=red".) Used from getNodeAttributes.
Definition at line203 of fileSelectionDAGPrinter.cpp.
Referencesllvm::errs(),I, andN.
Referenced byllvm::DOTGraphTraits< SelectionDAG * >::getNodeAttributes().
| static |
Definition at line123 of fileSelectionDAG.cpp.
ReferencesMaxSteps.
Referenced bycanFoldStoreIntoLibCallOutputPointers(),getPostIndexedLoadStoreOp(), andshouldCombineToPostInc().
Return HeapAllocSite associated withNode, or nullptr if none exists.
Definition at line2358 of fileSelectionDAG.h.
Referencesllvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::end(),llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::find(), andI.
Referenced byllvm::ScheduleDAGSDNodes::EmitSchedule().
SDValue SelectionDAG::getIndexedLoad | ( | SDValue | OrigLoad, |
constSDLoc & | dl, | ||
SDValue | Base, | ||
SDValue | Offset, | ||
ISD::MemIndexedMode | AM | ||
) |
Definition at line9306 of fileSelectionDAG.cpp.
Referencesassert(),llvm::sampleprof::Base,getLoad(),llvm::SDValue::getValueType(),llvm::MachineMemOperand::MODereferenceable,llvm::MachineMemOperand::MOInvariant, andllvm::Offset.
SDValue SelectionDAG::getIndexedLoadVP | ( | SDValue | OrigLoad, |
constSDLoc & | dl, | ||
SDValue | Base, | ||
SDValue | Offset, | ||
ISD::MemIndexedMode | AM | ||
) |
Definition at line9568 of fileSelectionDAG.cpp.
Referencesassert(),llvm::sampleprof::Base,getLoadVP(),llvm::SDValue::getValueType(),llvm::MachineMemOperand::MODereferenceable,llvm::MachineMemOperand::MOInvariant, andllvm::Offset.
SDValue SelectionDAG::getIndexedMaskedLoad | ( | SDValue | OrigLoad, |
constSDLoc & | dl, | ||
SDValue | Base, | ||
SDValue | Offset, | ||
ISD::MemIndexedMode | AM | ||
) |
Definition at line9980 of fileSelectionDAG.cpp.
Referencesassert(),llvm::sampleprof::Base,getMaskedLoad(),llvm::SDValue::getValueType(), andllvm::Offset.
SDValue SelectionDAG::getIndexedMaskedStore | ( | SDValue | OrigStore, |
constSDLoc & | dl, | ||
SDValue | Base, | ||
SDValue | Offset, | ||
ISD::MemIndexedMode | AM | ||
) |
Definition at line10029 of fileSelectionDAG.cpp.
Referencesassert(),llvm::sampleprof::Base,getMaskedStore(), andllvm::Offset.
SDValue SelectionDAG::getIndexedStore | ( | SDValue | OrigStore, |
constSDLoc & | dl, | ||
SDValue | Base, | ||
SDValue | Offset, | ||
ISD::MemIndexedMode | AM | ||
) |
Definition at line9438 of fileSelectionDAG.cpp.
ReferencesAddNodeIDNode(),assert(),llvm::sampleprof::Base,llvm::SDLoc::getDebugLoc(),llvm::SDLoc::getIROrder(),getVTList(),N,NewSDValueDbgMsg(),llvm::Offset, andllvm::ISD::STORE.
Referenced byllvm::HexagonTargetLowering::LowerStore().
SDValue SelectionDAG::getIndexedStoreVP | ( | SDValue | OrigStore, |
constSDLoc & | dl, | ||
SDValue | Base, | ||
SDValue | Offset, | ||
ISD::MemIndexedMode | AM | ||
) |
Definition at line9690 of fileSelectionDAG.cpp.
ReferencesAddNodeIDNode(),assert(),llvm::sampleprof::Base,llvm::SDLoc::getDebugLoc(),llvm::SDLoc::getIROrder(),getVTList(),N,NewSDValueDbgMsg(), andllvm::Offset.
Definition at line1806 of fileSelectionDAG.cpp.
ReferencesDL,getConstant(),getDataLayout(), andllvm::TargetLoweringBase::getPointerTy().
Referenced bybuildCallOperands(),combineBVZEXTLOAD(),CompactSwizzlableVector(),CreateCopyOfByValArgument(),emitConstantSizeRepmov(),emitConstantSizeRepstos(),emitRepmovsB(),emitRepstosB(),extractSubVector(),getCALLSEQ_END(),getCALLSEQ_START(),getCopyToParts(),getFPExtendOrRound(),getFRAMEADDR(),getParamsForOneTrueMaskedElt(),getStrictFPExtendOrRound(),GetTLSADDR(),llvm::SystemZTargetLowering::LowerCall(),llvm::XtensaTargetLowering::LowerCall(),llvm::LoongArchTargetLowering::LowerCall(),llvm::RISCVTargetLowering::LowerCall(),llvm::VETargetLowering::LowerCall(),llvm::SparcTargetLowering::LowerCall_32(),llvm::SparcTargetLowering::LowerCall_64(),LowerCONCAT_VECTORS(),LowerCONCAT_VECTORS_i1(),llvm::HexagonTargetLowering::LowerEH_RETURN(),LowerEXTRACT_SUBVECTOR(),LowerFCOPYSIGN(),LowerFLDEXP(),llvm::LoongArchTargetLowering::LowerFormalArguments(),llvm::NVPTXTargetLowering::LowerFormalArguments(),llvm::RISCVTargetLowering::LowerFormalArguments(),llvm::SystemZTargetLowering::LowerFormalArguments(),llvm::LanaiTargetLowering::LowerFRAMEADDR(),lowerINT_TO_FP(),lowerMasksToReg(),llvm::RISCVTargetLowering::LowerOperation(),llvm::LanaiTargetLowering::LowerRETURNADDR(),LowerRETURNADDR(),LowerSDIV(),llvm::AMDGPUTargetLowering::LowerSINT_TO_FP(),llvm::SelectionDAGBuilder::LowerStatepoint(),LowerToTLSExecModel(),LowerUDIV(),llvm::AMDGPUTargetLowering::LowerUINT_TO_FP(),LowerVAARG(),llvm::VETargetLowering::lowerVAARG(),LowerVACOPY(),llvm::HexagonTargetLowering::LowerVACOPY(),llvm::HexagonTargetLowering::LowerVASTART(),llvm::VETargetLowering::lowerVASTART(),LowerVASTART(),llvm::PPCTargetLowering::PerformDAGCombine(),performFPExtendCombine(),PerformTruncatingStoreCombine(),prepareDescriptorIndirectCall(),promoteXINT_TO_FP(),ReorganizeVector(),ReplaceLoadVector(), andSplitScalar().
Definition at line1941 of fileSelectionDAG.cpp.
ReferencesAddNodeIDNode(),assert(),getVTList(),llvm::ISD::JumpTable,N, andllvm::ISD::TargetJumpTable.
Referenced bygetTargetJumpTable(), andllvm::SelectionDAGBuilder::visitJumpTable().
Definition at line1961 of fileSelectionDAG.cpp.
ReferencesDL,getDataLayout(),getNode(),llvm::TargetLoweringBase::getPointerTy(),getTargetConstant(),getTargetLoweringInfo(), andllvm::ISD::JUMP_TABLE_DEBUG_INFO.
Referenced byllvm::TargetLowering::expandIndirectJTBranch(),llvm::RISCVTargetLowering::expandIndirectJTBranch(), andllvm::X86TargetLowering::expandIndirectJTBranch().
Definition at line2363 of fileSelectionDAG.cpp.
ReferencesAddNodeIDNode(),llvm::SDLoc::getDebugLoc(),llvm::SDLoc::getIROrder(),getVTList(), andN.
Referenced bygetEHLabel().
| inline |
Definition at line504 of fileSelectionDAG.h.
Referenced byexpandMultipleResultFPLibCall().
SDValue SelectionDAG::getLifetimeNode | ( | bool | IsStart, |
constSDLoc & | dl, | ||
SDValue | Chain, | ||
int | FrameIndex, | ||
int64_t | Size, | ||
int64_t | Offset =-1 | ||
) |
Creates aLifetimeSDNode that starts (IsStart==true
) or ends (IsStart==false
) the lifetime of the portion ofFrameIndex
between offsetsOffset
andOffset + Size
.
Definition at line9103 of fileSelectionDAG.cpp.
ReferencesAddNodeIDNode(),getDataLayout(),llvm::SDLoc::getDebugLoc(),getFrameIndex(),llvm::SDLoc::getIROrder(),getTargetLoweringInfo(),getVTList(),llvm::ISD::LIFETIME_END,llvm::ISD::LIFETIME_START,N,NewSDValueDbgMsg(),llvm::Offset, andSize.
SDValue SelectionDAG::getLoad | ( | EVT | VT, |
constSDLoc & | dl, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
MachineMemOperand * | MMO | ||
) |
Definition at line9280 of fileSelectionDAG.cpp.
ReferencesgetLoad(),getUNDEF(),llvm::ISD::NON_EXTLOAD,Ptr, andllvm::ISD::UNINDEXED.
SDValue SelectionDAG::getLoad | ( | EVT | VT, |
constSDLoc & | dl, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
MachinePointerInfo | PtrInfo, | ||
MaybeAlign | Alignment =MaybeAlign() , | ||
MachineMemOperand::Flags | MMOFlags =MachineMemOperand::MONone , | ||
constAAMDNodes & | AAInfo =AAMDNodes() , | ||
constMDNode * | Ranges =nullptr | ||
) |
Loads are not normal binary operators: their result type is not determined by their operands, and they produce a value AND a token chain.
This function will set the MOLoad flag on MMOFlags, but you can set it if you want. The MOStore flag must not be set.
Definition at line9270 of fileSelectionDAG.cpp.
ReferencesgetLoad(),getUNDEF(),llvm::ISD::NON_EXTLOAD,Ptr, andllvm::ISD::UNINDEXED.
Referenced bybitcastf32Toi32(),llvm::X86TargetLowering::BuildFILD(),combineBVOfConsecutiveLoads(),combineConcatVectorOps(),combineExtractFromVectorLoad(),combineExtractWithShuffle(),combineLoad(),combineMaskedLoadConstantMask(),combineMOVDQ2Q(),combineStore(),combineTargetShuffle(),combineV3I8LoadExt(),EltsFromConsecutiveLoads(),llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(),expandf64Toi32(),expandMultipleResultFPLibCall(),llvm::TargetLowering::expandUnalignedLoad(),llvm::TargetLowering::expandUnalignedStore(),expandVAArg(),expandVACopy(),llvm::TargetLowering::expandVECTOR_COMPRESS(),llvm::TargetLowering::expandVectorSplice(),getADAEntry(),llvm::MipsTargetLowering::getAddrGlobal(),llvm::MipsTargetLowering::getAddrGlobalLargeGOT(),llvm::MipsTargetLowering::getAddrLocal(),llvm::MipsTargetLowering::getDllimportVariable(),getExtLoad(),getFRAMEADDR(),getIndexedLoad(),getLargeExternalSymbol(),getLargeGlobalAddress(),getLoad(),getMemCmpLoad(),getMemmoveLoadsAndStores(),GetTLSADDR(),getzOSCalleeAndADA(),llvm::AMDGPUTargetLowering::loadStackInputValue(),LowerAsSplatVectorLoad(),llvm::NVPTXTargetLowering::LowerCall(),llvm::SparcTargetLowering::LowerCall_64(),lowerCallResult(),llvm::TargetLowering::LowerCallTo(),LowerF128Load(),llvm::SparcTargetLowering::LowerF128Op(),llvm::R600TargetLowering::LowerFormalArguments(),llvm::HexagonTargetLowering::LowerFormalArguments(),llvm::LoongArchTargetLowering::LowerFormalArguments(),llvm::NVPTXTargetLowering::LowerFormalArguments(),llvm::RISCVTargetLowering::LowerFormalArguments(),llvm::SystemZTargetLowering::LowerFormalArguments(),llvm::VETargetLowering::LowerFormalArguments(),llvm::XtensaTargetLowering::LowerFormalArguments(),llvm::SparcTargetLowering::LowerFormalArguments_32(),llvm::SparcTargetLowering::LowerFormalArguments_64(),llvm::HexagonTargetLowering::LowerFRAMEADDR(),llvm::LanaiTargetLowering::LowerFRAMEADDR(),llvm::MSP430TargetLowering::LowerFRAMEADDR(),lowerFRAMEADDR(),LowerLoad(),llvm::HexagonTargetLowering::LowerLoad(),lowerLoadF128(),lowerLoadI1(),lowerMSALoadIntr(),llvm::RISCVTargetLowering::LowerOperation(),llvm::HexagonTargetLowering::LowerRETURNADDR(),llvm::LanaiTargetLowering::LowerRETURNADDR(),llvm::MSP430TargetLowering::LowerRETURNADDR(),LowerRETURNADDR(),lowerRETURNADDR(),lowerShuffleAsBroadcast(),LowerToTLSExecModel(),llvm::HexagonTargetLowering::LowerToTLSInitialExecModel(),LowerUINT_TO_FP_i64(),llvm::HexagonTargetLowering::LowerUnalignedLoad(),LowerVAARG(),llvm::VETargetLowering::lowerVAARG(),lowerVECTOR_SHUFFLE(),llvm::SparcTargetLowering::makeAddress(),llvm::VETargetLowering::makeAddress(),narrowExtractedVectorLoad(),performConcatVectorsCombine(),llvm::PPCTargetLowering::PerformDAGCombine(),llvm::RISCVTargetLowering::PerformDAGCombine(),performExtBinopLoadFold(),performIntToFpCombine(),llvm::AMDGPUTargetLowering::performLoadCombine(),performLOADCombine(),llvm::ARMTargetLowering::PerformMVETruncCombine(),PerformSplittingMVEEXTToWideningLoad(),PerformSplittingToWideningLoad(),PerformVMOVhrCombine(),PerformVMOVRRDCombine(),prepareDescriptorIndirectCall(),reduceMaskedLoadToScalarLoad(),llvm::X86TargetLowering::ReplaceNodeResults(),llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(),llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetShuffle(),llvm::TargetLowering::SimplifySetCC(),SkipLoadExtensionForVMULL(),unpack64(),unpackF64OnRV32DSoftABI(), andllvm::SelectionDAGBuilder::visitSPDescriptorParent().
SDValue SelectionDAG::getLoad | ( | ISD::MemIndexedMode | AM, |
ISD::LoadExtType | ExtType, | ||
EVT | VT, | ||
constSDLoc & | dl, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
SDValue | Offset, | ||
EVT | MemVT, | ||
MachineMemOperand * | MMO | ||
) |
Definition at line9220 of fileSelectionDAG.cpp.
ReferencesAddNodeIDNode(),assert(),llvm::EVT::bitsLT(),llvm::MachinePointerInfo::getAddrSpace(),llvm::SDLoc::getDebugLoc(),llvm::MachineMemOperand::getFlags(),llvm::SDLoc::getIROrder(),llvm::MachineMemOperand::getPointerInfo(),llvm::EVT::getRawBits(),llvm::EVT::getScalarType(),llvm::EVT::getVectorElementCount(),getVTList(),Indexed,llvm::EVT::isInteger(),llvm::EVT::isVector(),llvm::ISD::LOAD,N,NewSDValueDbgMsg(),llvm::ISD::NON_EXTLOAD,llvm::Offset,Ptr, andllvm::ISD::UNINDEXED.
SDValue SelectionDAG::getLoad | ( | ISD::MemIndexedMode | AM, |
ISD::LoadExtType | ExtType, | ||
EVT | VT, | ||
constSDLoc & | dl, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
SDValue | Offset, | ||
MachinePointerInfo | PtrInfo, | ||
EVT | MemVT, | ||
Align | Alignment, | ||
MachineMemOperand::Flags | MMOFlags =MachineMemOperand::MONone , | ||
constAAMDNodes & | AAInfo =AAMDNodes() , | ||
constMDNode * | Ranges =nullptr | ||
) |
Definition at line9196 of fileSelectionDAG.cpp.
Referencesassert(),getLoad(),getMachineFunction(),llvm::MachineFunction::getMachineMemOperand(),llvm::EVT::getStoreSize(),llvm::SDValue::getValueType(),InferPointerInfo(),llvm::PointerUnion< PTs >::isNull(),llvm::MachineMemOperand::MOLoad,llvm::MachineMemOperand::MOStore,llvm::Offset,llvm::LocationSize::precise(),Ptr,Size, andllvm::MachinePointerInfo::V.
| inline |
Definition at line1409 of fileSelectionDAG.h.
ReferencesgetEVTAlign(),getLoad(),llvm::Offset, andPtr.
SDValue SelectionDAG::getLoadVP | ( | EVT | VT, |
constSDLoc & | dl, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
SDValue | Mask, | ||
SDValue | EVL, | ||
MachineMemOperand * | MMO, | ||
bool | IsExpanding =false | ||
) |
Definition at line9538 of fileSelectionDAG.cpp.
ReferencesgetLoadVP(),getUNDEF(),llvm::ISD::NON_EXTLOAD,Ptr, andllvm::ISD::UNINDEXED.
SDValue SelectionDAG::getLoadVP | ( | EVT | VT, |
constSDLoc & | dl, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
SDValue | Mask, | ||
SDValue | EVL, | ||
MachinePointerInfo | PtrInfo, | ||
MaybeAlign | Alignment, | ||
MachineMemOperand::Flags | MMOFlags, | ||
constAAMDNodes & | AAInfo, | ||
constMDNode * | Ranges =nullptr , | ||
bool | IsExpanding =false | ||
) |
Definition at line9525 of fileSelectionDAG.cpp.
ReferencesgetLoadVP(),getUNDEF(),llvm::ISD::NON_EXTLOAD,Ptr, andllvm::ISD::UNINDEXED.
SDValue SelectionDAG::getLoadVP | ( | ISD::MemIndexedMode | AM, |
ISD::LoadExtType | ExtType, | ||
EVT | VT, | ||
constSDLoc & | dl, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
SDValue | Offset, | ||
SDValue | Mask, | ||
SDValue | EVL, | ||
EVT | MemVT, | ||
MachineMemOperand * | MMO, | ||
bool | IsExpanding =false | ||
) |
Definition at line9490 of fileSelectionDAG.cpp.
ReferencesAddNodeIDNode(),assert(),llvm::MachinePointerInfo::getAddrSpace(),llvm::SDLoc::getDebugLoc(),llvm::MachineMemOperand::getFlags(),llvm::SDLoc::getIROrder(),llvm::MachineMemOperand::getPointerInfo(),llvm::EVT::getRawBits(),getVTList(),Indexed,N,NewSDValueDbgMsg(),llvm::Offset,Ptr, andllvm::ISD::UNINDEXED.
SDValue SelectionDAG::getLoadVP | ( | ISD::MemIndexedMode | AM, |
ISD::LoadExtType | ExtType, | ||
EVT | VT, | ||
constSDLoc & | dl, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
SDValue | Offset, | ||
SDValue | Mask, | ||
SDValue | EVL, | ||
MachinePointerInfo | PtrInfo, | ||
EVT | MemVT, | ||
Align | Alignment, | ||
MachineMemOperand::Flags | MMOFlags, | ||
constAAMDNodes & | AAInfo, | ||
constMDNode * | Ranges =nullptr , | ||
bool | IsExpanding =false | ||
) |
Definition at line9467 of fileSelectionDAG.cpp.
Referencesassert(),getLoadVP(),getMachineFunction(),llvm::MachineFunction::getMachineMemOperand(),llvm::EVT::getStoreSize(),llvm::SDValue::getValueType(),InferPointerInfo(),llvm::PointerUnion< PTs >::isNull(),llvm::MachineMemOperand::MOLoad,llvm::MachineMemOperand::MOStore,llvm::Offset,llvm::LocationSize::precise(),Ptr,Size, andllvm::MachinePointerInfo::V.
Referenced bygetExtLoadVP(),getIndexedLoadVP(), andgetLoadVP().
| inline |
Definition at line1472 of fileSelectionDAG.h.
ReferencesgetEVTAlign(),getLoadVP(),llvm::Offset, andPtr.
Create a logical NOT operation as (XOR Val, BooleanOne).
Definition at line1626 of fileSelectionDAG.cpp.
ReferencesDL,getBoolConstant(),getNode(), andllvm::ISD::XOR.
Referenced byextractBooleanFlip(),llvm::RISCVTargetLowering::LowerOperation(),llvm::HexagonTargetLowering::LowerUAddSubOCarry(),PerformORCombine_i1(),performVECTOR_SHUFFLECombine(), andperformVSELECTCombine().
| inline |
Definition at line492 of fileSelectionDAG.h.
Referenced byllvm::RegsForValue::AddInlineAsmOperands(),llvm::StatepointLoweringState::allocateStackSlot(),buildCallOperands(),llvm::X86TargetLowering::BuildFILD(),llvm::TargetLowering::BuildSDIVPow2(),llvm::TargetLowering::BuildSREMPow2(),CalculateTailCallSPDiff(),llvm::AArch64TargetLowering::changeStreamingMode(),combineConcatVectorOps(),combineFMA(),combineFMADDSUB(),combineFMinNumFMaxNum(),combineFneg(),combineI8TruncStore(),combineMul(),combineStore(),combineTargetShuffle(),combineV3I8LoadExt(),combineVectorSizedSetCCEquality(),llvm::BaseIndexOffset::computeAliasing(),computeKnownBits(),llvm::AMDGPUTargetLowering::computeKnownBitsForTargetNode(),llvm::SITargetLowering::computeKnownBitsForTargetNode(),llvm::AMDGPUTargetLowering::CreateLiveInRegister(),llvm::TargetLowering::CTTZTableLookup(),llvm::SITargetLowering::denormalsEnabledForType(),EmitCmp(),emitConstantSizeRepmov(),emitConstantSizeRepstos(),emitLockedStackOp(),llvm::AArch64SelectionDAGInfo::EmitMOPS(),emitNonHSAIntrinsicError(),emitRemovedIntrinsicError(),emitSMEStateSaveRestore(),llvm::ARMSelectionDAGInfo::EmitSpecializedLibcall(),llvm::AArch64SelectionDAGInfo::EmitStreamingCompatibleMemLibCall(),EmitTailCallStoreFPAndRetAddr(),EmitTailCallStoreRetAddr(),llvm::AArch64SelectionDAGInfo::EmitTargetCodeForMemcpy(),llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(),llvm::HexagonSelectionDAGInfo::EmitTargetCodeForMemcpy(),llvm::X86SelectionDAGInfo::EmitTargetCodeForMemcpy(),llvm::WebAssemblySelectionDAGInfo::EmitTargetCodeForMemcpy(),llvm::AArch64SelectionDAGInfo::EmitTargetCodeForMemmove(),llvm::AArch64SelectionDAGInfo::EmitTargetCodeForMemset(),llvm::X86SelectionDAGInfo::EmitTargetCodeForMemset(),llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemset(),llvm::WebAssemblySelectionDAGInfo::EmitTargetCodeForMemset(),llvm::AArch64SelectionDAGInfo::EmitTargetCodeForSetTag(),EmitUnrolledSetTag(),llvm::BaseIndexOffset::equalBaseIndex(),errorUnsupported(),llvm::X86TargetLowering::expandIndirectJTBranch(),llvm::TargetLowering::expandIS_FPCLASS(),expandMul(),expandMultipleResultFPLibCall(),llvm::TargetLowering::expandUnalignedLoad(),llvm::TargetLowering::expandUnalignedStore(),llvm::TargetLowering::expandVECTOR_COMPRESS(),llvm::TargetLowering::expandVectorFindLastActive(),llvm::TargetLowering::expandVectorSplice(),fail(),llvm::SelectionDAGBuilder::FindMergedConditions(),fixupFuncForFI(),getADAEntry(),getAddressForMemoryInput(),llvm::MipsTargetLowering::getAddrLocal(),getBROADCAST_LOAD(),getCopyFromParts(),llvm::HexagonTargetLowering::GetDynamicTLSAddr(),getFRAMEADDR(),llvm::MipsTargetLowering::getGlobalReg(),getLargeExternalSymbol(),getLargeGlobalAddress(),getLoad(),getLoadStackGuard(),getLoadVP(),getMemcpyLoadsAndStores(),getMemIntrinsicNode(),getMemmoveLoadsAndStores(),getMemsetStores(),llvm::MipsTargetLowering::getOpndList(),llvm::VETargetLowering::getPICJumpTableRelocBase(),getReducedAlign(),getRegistersForValue(),llvm::MSP430TargetLowering::getReturnAddressFrameIndex(),llvm::X86TargetLowering::getReturnAddressFrameIndex(),llvm::NVPTXTargetLowering::getSqrtEstimate(),getStore(),getTagSymNode(),GetTLSADDR(),getTruncStore(),getTruncStoreVP(),getv64i1Argument(),getVCIXISDNodeWCHAIN(),getVScale(),getzOSCalleeAndADA(),hasReturnsTwiceAttr(),InferPointerInfo(),InferPtrAlign(),llvm::SelectionDAGBuilder::init(),llvm::SITargetLowering::isCanonicalized(),isConsecutiveLSLoc(),llvm::HexagonTargetLowering::IsEligibleForTailCallOptimization(),llvm::SITargetLowering::isEligibleForTailCallOptimization(),isEligibleToFoldADDIForFasterLocalAccesses(),llvm::SITargetLowering::isFMADLegal(),llvm::SITargetLowering::isFPExtFoldable(),llvm::TargetLowering::isInTailCallPosition(),llvm::SITargetLowering::isKnownNeverNaNForTargetNode(),isKnownNeverZero(),isThreadPointerAcquisitionNode(),IsWebAssemblyLocal(),legalizeScatterGatherIndexType(),llvm::SITargetLowering::legalizeTargetIndependentNode(),llvm::AMDGPUTargetLowering::loadStackInputValue(),LowerAsSplatVectorLoad(),LowerATOMIC_STORE(),lowerBuildVectorAsBroadcast(),llvm::SITargetLowering::LowerCall(),llvm::NVPTXTargetLowering::LowerCall(),llvm::SystemZTargetLowering::LowerCall(),llvm::XtensaTargetLowering::LowerCall(),llvm::HexagonTargetLowering::LowerCall(),llvm::LoongArchTargetLowering::LowerCall(),llvm::RISCVTargetLowering::LowerCall(),llvm::VETargetLowering::LowerCall(),llvm::SparcTargetLowering::LowerCall_32(),llvm::SparcTargetLowering::LowerCall_64(),llvm::SITargetLowering::LowerCallResult(),llvm::HexagonTargetLowering::LowerCallResult(),llvm::TargetLowering::LowerCallTo(),llvm::AMDGPUTargetLowering::LowerDIVREM24(),llvm::AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(),llvm::SITargetLowering::LowerDYNAMIC_STACKALLOC(),llvm::NVPTXTargetLowering::LowerDYNAMIC_STACKALLOC(),llvm::HexagonTargetLowering::LowerEH_RETURN(),llvm::SparcTargetLowering::LowerF128_LibCallArg(),llvm::SparcTargetLowering::LowerF128Op(),llvm::HexagonTargetLowering::LowerFDIV(),llvm::R600TargetLowering::LowerFormalArguments(),llvm::SITargetLowering::LowerFormalArguments(),llvm::HexagonTargetLowering::LowerFormalArguments(),llvm::LoongArchTargetLowering::LowerFormalArguments(),llvm::NVPTXTargetLowering::LowerFormalArguments(),llvm::RISCVTargetLowering::LowerFormalArguments(),llvm::SystemZTargetLowering::LowerFormalArguments(),llvm::VETargetLowering::LowerFormalArguments(),llvm::XtensaTargetLowering::LowerFormalArguments(),llvm::SparcTargetLowering::LowerFormalArguments_32(),llvm::SparcTargetLowering::LowerFormalArguments_64(),llvm::HexagonTargetLowering::LowerFRAMEADDR(),llvm::LanaiTargetLowering::LowerFRAMEADDR(),llvm::MSP430TargetLowering::LowerFRAMEADDR(),lowerFRAMEADDR(),llvm::AMDGPUTargetLowering::LowerGlobalAddress(),llvm::SparcTargetLowering::LowerGlobalTLSAddress(),lowerIncomingStatepointValue(),llvm::HexagonTargetLowering::LowerINLINEASM(),LowerInterruptReturn(),LowerINTRINSIC_W_CHAIN(),llvm::VETargetLowering::lowerINTRINSIC_WO_CHAIN(),llvm::R600TargetLowering::LowerOperation(),llvm::SITargetLowering::LowerOperation(),llvm::SITargetLowering::LowerReturn(),llvm::HexagonTargetLowering::LowerReturn(),llvm::LoongArchTargetLowering::LowerReturn(),llvm::NVPTXTargetLowering::LowerReturn(),llvm::RISCVTargetLowering::LowerReturn(),llvm::SystemZTargetLowering::LowerReturn(),llvm::VETargetLowering::LowerReturn(),llvm::XtensaTargetLowering::LowerReturn(),llvm::SparcTargetLowering::LowerReturn_32(),llvm::SparcTargetLowering::LowerReturn_64(),llvm::HexagonTargetLowering::LowerRETURNADDR(),llvm::LanaiTargetLowering::LowerRETURNADDR(),llvm::MSP430TargetLowering::LowerRETURNADDR(),LowerRETURNADDR(),lowerRETURNADDR(),lowerShuffleAsBroadcast(),llvm::NVPTXTargetLowering::LowerSTACKRESTORE(),llvm::NVPTXTargetLowering::LowerSTACKSAVE(),lowerStatepointMetaArgs(),llvm::TargetLowering::LowerToTLSEmulatedModel(),LowerToTLSExecModel(),llvm::VETargetLowering::lowerToTLSGeneralDynamicModel(),LowerToTLSLocalDynamicModel(),llvm::AMDGPUTargetLowering::LowerUDIVREM64(),LowerUINT_TO_FP_i64(),lowerUINT_TO_FP_vXi32(),llvm::HexagonTargetLowering::LowerUnalignedLoad(),llvm::AMDGPUTargetLowering::lowerUnhandledCall(),LowerVACOPY(),LowerVASTART(),llvm::HexagonTargetLowering::LowerVASTART(),llvm::LanaiTargetLowering::LowerVASTART(),llvm::MSP430TargetLowering::LowerVASTART(),llvm::VETargetLowering::lowerVASTART(),lowerVECTOR_SHUFFLE(),llvm::SparcTargetLowering::makeAddress(),llvm::VETargetLowering::makeAddress(),MarkEHGuard(),MarkEHRegistrationNode(),narrowExtractedVectorLoad(),llvm::AMDGPUTargetLowering::needsDenormHandlingF32(),llvm::SITargetLowering::passSpecialInputs(),performBRCONDCombine(),performCONCAT_VECTORSCombine(),llvm::PPCTargetLowering::PerformDAGCombine(),PerformFADDCombineWithOperands(),performMemPairCombine(),llvm::ARMTargetLowering::PerformMVEExtCombine(),llvm::ARMTargetLowering::PerformMVETruncCombine(),performVP_REVERSECombine(),performVP_STORECombine(),llvm::SITargetLowering::PostISelFolding(),llvm::AArch64TargetLowering::preferredShiftLegalizationStrategy(),llvm::RISCVTargetLowering::preferredShiftLegalizationStrategy(),llvm::X86TargetLowering::preferredShiftLegalizationStrategy(),llvm::RISCVDAGToDAGISel::PreprocessISelDAG(),processVCIXOperands(),promoteToConstantPool(),promoteVCIXScalar(),recoverFramePointer(),reduceVMULWidth(),llvm::SITargetLowering::ReplaceNodeResults(),llvm::RISCVTargetLowering::ReplaceNodeResults(),llvm::X86TargetLowering::ReplaceNodeResults(),selectI64Imm(),setAlignFlagsForFI(),llvm::TargetLowering::CallLoweringInfo::setLibCallee(),setUsesTOCBasePtr(),shouldGenerateInlineTPLoop(),llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetShuffle(),llvm::TargetLowering::SimplifySetCC(),spillIncomingStatepointValue(),splitStores(),llvm::AMDGPUTargetLowering::storeStackInputValue(),StoreTailCallArgumentsToStackSlot(),transformCallee(),tryMemPairCombine(),llvm::X86InstrInfo::unfoldMemoryOperand(),unpack64(),unpackF64OnRV32DSoftABI(),unpackFromMemLoc(),unpackFromRegLoc(),updateForAIXShLibTLSModelOpt(),viewGraph(), andllvm::SelectionDAGBuilder::visitSPDescriptorParent().
MachineSDNode * SelectionDAG::getMachineNode | ( | unsigned | Opcode, |
constSDLoc & | dl, | ||
ArrayRef<EVT > | ResultTys, | ||
ArrayRef<SDValue > | Ops | ||
) |
Definition at line11230 of fileSelectionDAG.cpp.
ReferencesgetMachineNode(), andgetVTList().
MachineSDNode * SelectionDAG::getMachineNode | ( | unsigned | Opcode, |
constSDLoc & | dl, | ||
EVT | VT | ||
) |
These are used for target selectors to create a new node with specified return type(s),MachineInstr opcode, and operands.
getMachineNode - These are used for target selectors to create a new node with specified return type(s),MachineInstr opcode, and operands.
Note that getMachineNode returns the resultant node. If there is already a node of the specified opcode and operands, it returns that node instead of the current one.
Definition at line11149 of fileSelectionDAG.cpp.
ReferencesgetMachineNode(), andgetVTList().
Referenced bybuildRegSequence16(),buildRegSequence32(),llvm::SITargetLowering::buildRSRC(),buildSMovImm32(),llvm::VETargetLowering::combineTRUNCATE(),llvm::SITargetLowering::copyToM0(),createGPRPairNode(),createGPRPairNode2xi32(),llvm::HexagonDAGToDAGISel::DetectUseSxtw(),emitLockedStackOp(),llvm::AArch64SelectionDAGInfo::EmitMOPS(),llvm::X86TargetLowering::emitStackGuardXorFP(),llvm::AArch64SelectionDAGInfo::EmitTargetCodeForSetTag(),expandBitCastI128ToF128(),expandIntrinsicWChainHelper(),llvm::HexagonDAGToDAGISel::FastFDiv(),llvm::HexagonDAGToDAGISel::FDiv(),getDataClassTest(),getLeftShift(),getLoadStackGuard(),getMachineNode(),getPrefetchNode(),getTargetExtractSubreg(),getTargetInsertSubreg(),InvertCarryFlag(),isWorthFoldingIntoOrrWithShift(),llvm::SITargetLowering::legalizeTargetIndependentNode(),llvm::HexagonDAGToDAGISel::LoadInstrForLoadIntrinsic(),llvm::SelectionDAGBuilder::LowerAsSTATEPOINT(),llvm::VETargetLowering::lowerATOMIC_FENCE(),lowerBuildVectorViaPacking(),llvm::SITargetLowering::LowerCall(),llvm::VETargetLowering::LowerCall(),llvm::VETargetLowering::lowerEXTRACT_VECTOR_ELT(),LowerF128Load(),LowerF128Store(),LowerF64Op(),LowerFNEGorFABS(),llvm::VETargetLowering::LowerFormalArguments(),lowerI128ToGR128(),llvm::VETargetLowering::lowerINSERT_VECTOR_ELT(),LowerINTRINSIC_W_CHAIN(),lowerLoadF128(),lowerLoadI1(),llvm::SystemZTargetLowering::LowerOperationWrapper(),LowerPtrAuthGlobalAddressStatically(),llvm::VETargetLowering::LowerReturn(),lowerStoreF128(),lowerStoreI1(),optimizeLogicalImm(),llvm::packConstantV2I16(),llvm::SITargetLowering::PostISelFolding(),ReplaceATOMIC_LOAD_128Results(),ReplaceCMP_SWAP_128Results(),ReplaceCMP_SWAP_64Results(),replaceCMP_XCHG_128Results(),llvm::AMDGPUDAGToDAGISel::Select(),llvm::RISCVDAGToDAGISel::Select(),llvm::PPCTargetLowering::SelectAddressRegImm(),llvm::RISCVDAGToDAGISel::SelectAddrRegImm(),llvm::RISCVDAGToDAGISel::SelectAddrRegImmLsb00000(),llvm::RISCVDAGToDAGISel::SelectAddrRegRegScale(),llvm::HexagonDAGToDAGISel::SelectAddSubCarry(),llvm::HexagonDAGToDAGISel::SelectBrevLdIntrinsic(),llvm::AMDGPUDAGToDAGISel::SelectBuildVector(),llvm::SelectionDAGISel::SelectCodeCommon(),llvm::HexagonDAGToDAGISel::SelectConstant(),selectConstantAddr(),llvm::HexagonDAGToDAGISel::SelectConstantFP(),llvm::HexagonDAGToDAGISel::SelectD2P(),llvm::HexagonDAGToDAGISel::SelectFrameIndex(),llvm::HexagonDAGToDAGISel::SelectHVXDualOutput(),selectI64Imm(),selectI64ImmDirect(),selectI64ImmDirectPrefix(),selectImm(),selectImmSeq(),llvm::HexagonDAGToDAGISel::SelectIndexedStore(),llvm::HexagonDAGToDAGISel::SelectNewCircIntrinsic(),llvm::PPCTargetLowering::SelectOptimalAddrMode(),llvm::HexagonDAGToDAGISel::SelectP2D(),llvm::HexagonDAGToDAGISel::SelectQ2V(),llvm::HvxSelector::selectRor(),SelectSAddrFI(),llvm::RISCVDAGToDAGISel::selectSETCC(),llvm::RISCVDAGToDAGISel::selectSF_VC_X_SE(),llvm::LoongArchDAGToDAGISel::selectShiftMask(),llvm::RISCVDAGToDAGISel::selectShiftMask(),llvm::HexagonDAGToDAGISel::SelectSHL(),llvm::RISCVDAGToDAGISel::selectSHXADD_UWOp(),llvm::RISCVDAGToDAGISel::selectSHXADDOp(),llvm::HexagonDAGToDAGISel::SelectV2Q(),llvm::HexagonDAGToDAGISel::SelectV65Gather(),llvm::HexagonDAGToDAGISel::SelectV65GatherPred(),llvm::HexagonDAGToDAGISel::SelectVAlign(),llvm::HvxSelector::selectVAlign(),llvm::HexagonDAGToDAGISel::SelectVAlignAddr(),llvm::AMDGPUDAGToDAGISel::SelectVectorShuffle(),llvm::RISCVDAGToDAGISel::selectVLSEG(),llvm::RISCVDAGToDAGISel::selectVLSEGFF(),llvm::RISCVDAGToDAGISel::selectVLXSEG(),llvm::RISCVDAGToDAGISel::selectVSETVLI(),llvm::RISCVDAGToDAGISel::selectVSSEG(),llvm::RISCVDAGToDAGISel::selectVSXSEG(),tryBitfieldInsertOpFromOr(),tryBitfieldInsertOpFromOrAndImm(),llvm::RISCVDAGToDAGISel::tryIndexedLoad(),llvm::RISCVDAGToDAGISel::tryShrinkShlLogicImm(),llvm::RISCVDAGToDAGISel::trySignedBitfieldExtract(),llvm::X86InstrInfo::unfoldMemoryOperand(),Widen(), andllvm::SITargetLowering::wrapAddr64Rsrc().
MachineSDNode * SelectionDAG::getMachineNode | ( | unsigned | Opcode, |
constSDLoc & | dl, | ||
EVT | VT, | ||
ArrayRef<SDValue > | Ops | ||
) |
Definition at line11177 of fileSelectionDAG.cpp.
ReferencesgetMachineNode(), andgetVTList().
Definition at line11155 of fileSelectionDAG.cpp.
ReferencesgetMachineNode(), andgetVTList().
MachineSDNode * SelectionDAG::getMachineNode | ( | unsigned | Opcode, |
constSDLoc & | dl, | ||
EVT | VT, | ||
SDValue | Op1, | ||
SDValue | Op2 | ||
) |
Definition at line11162 of fileSelectionDAG.cpp.
ReferencesgetMachineNode(), andgetVTList().
MachineSDNode * SelectionDAG::getMachineNode | ( | unsigned | Opcode, |
constSDLoc & | dl, | ||
EVT | VT, | ||
SDValue | Op1, | ||
SDValue | Op2, | ||
SDValue | Op3 | ||
) |
Definition at line11169 of fileSelectionDAG.cpp.
ReferencesgetMachineNode(), andgetVTList().
MachineSDNode * SelectionDAG::getMachineNode | ( | unsigned | Opcode, |
constSDLoc & | dl, | ||
EVT | VT1, | ||
EVT | VT2, | ||
ArrayRef<SDValue > | Ops | ||
) |
Definition at line11199 of fileSelectionDAG.cpp.
ReferencesgetMachineNode(), andgetVTList().
MachineSDNode * SelectionDAG::getMachineNode | ( | unsigned | Opcode, |
constSDLoc & | dl, | ||
EVT | VT1, | ||
EVT | VT2, | ||
EVT | VT3, | ||
ArrayRef<SDValue > | Ops | ||
) |
Definition at line11223 of fileSelectionDAG.cpp.
ReferencesgetMachineNode(), andgetVTList().
MachineSDNode * SelectionDAG::getMachineNode | ( | unsigned | Opcode, |
constSDLoc & | dl, | ||
EVT | VT1, | ||
EVT | VT2, | ||
EVT | VT3, | ||
SDValue | Op1, | ||
SDValue | Op2 | ||
) |
Definition at line11206 of fileSelectionDAG.cpp.
ReferencesgetMachineNode(), andgetVTList().
MachineSDNode * SelectionDAG::getMachineNode | ( | unsigned | Opcode, |
constSDLoc & | dl, | ||
EVT | VT1, | ||
EVT | VT2, | ||
EVT | VT3, | ||
SDValue | Op1, | ||
SDValue | Op2, | ||
SDValue | Op3 | ||
) |
Definition at line11214 of fileSelectionDAG.cpp.
ReferencesgetMachineNode(), andgetVTList().
MachineSDNode * SelectionDAG::getMachineNode | ( | unsigned | Opcode, |
constSDLoc & | dl, | ||
EVT | VT1, | ||
EVT | VT2, | ||
SDValue | Op1, | ||
SDValue | Op2 | ||
) |
Definition at line11183 of fileSelectionDAG.cpp.
ReferencesgetMachineNode(), andgetVTList().
MachineSDNode * SelectionDAG::getMachineNode | ( | unsigned | Opcode, |
constSDLoc & | dl, | ||
EVT | VT1, | ||
EVT | VT2, | ||
SDValue | Op1, | ||
SDValue | Op2, | ||
SDValue | Op3 | ||
) |
Definition at line11191 of fileSelectionDAG.cpp.
ReferencesgetMachineNode(), andgetVTList().
MachineSDNode * SelectionDAG::getMachineNode | ( | unsigned | Opcode, |
constSDLoc & | dl, | ||
SDVTList | VTs, | ||
ArrayRef<SDValue > | Ops | ||
) |
Definition at line11237 of fileSelectionDAG.cpp.
ReferencesAddNodeIDNode(),DL,N,NewSDValueDbgMsg(),llvm::SDVTList::NumVTs, andllvm::SDVTList::VTs.
SDValue SelectionDAG::getMaskedGather | ( | SDVTList | VTs, |
EVT | MemVT, | ||
constSDLoc & | dl, | ||
ArrayRef<SDValue > | Ops, | ||
MachineMemOperand * | MMO, | ||
ISD::MemIndexType | IndexType, | ||
ISD::LoadExtType | ExtTy | ||
) |
Definition at line10040 of fileSelectionDAG.cpp.
ReferencesAddNodeIDNode(),assert(),llvm::MachinePointerInfo::getAddrSpace(),llvm::SDLoc::getDebugLoc(),llvm::MachineMemOperand::getFlags(),llvm::SDLoc::getIROrder(),llvm::MachineMemOperand::getPointerInfo(),llvm::EVT::getRawBits(),llvm::details::FixedOrScalableQuantity< ElementCount, unsigned >::isKnownGE(),llvm::ISD::MGATHER,N,NewSDValueDbgMsg(), andllvm::ArrayRef< T >::size().
Referenced byllvm::RISCVTargetLowering::PerformDAGCombine(),performMaskedGatherScatterCombine(), andrebuildGatherScatter().
SDValue SelectionDAG::getMaskedHistogram | ( | SDVTList | VTs, |
EVT | MemVT, | ||
constSDLoc & | dl, | ||
ArrayRef<SDValue > | Ops, | ||
MachineMemOperand * | MMO, | ||
ISD::MemIndexType | IndexType | ||
) |
Definition at line10133 of fileSelectionDAG.cpp.
ReferencesAddNodeIDNode(),assert(),llvm::ISD::EXPERIMENTAL_VECTOR_HISTOGRAM,llvm::MachinePointerInfo::getAddrSpace(),llvm::SDLoc::getDebugLoc(),llvm::MachineMemOperand::getFlags(),llvm::SDLoc::getIROrder(),llvm::MachineMemOperand::getPointerInfo(),llvm::EVT::getRawBits(),N,NewSDValueDbgMsg(), andllvm::ArrayRef< T >::size().
Referenced byperformMaskedGatherScatterCombine().
SDValue SelectionDAG::getMaskedLoad | ( | EVT | VT, |
constSDLoc & | dl, | ||
SDValue | Chain, | ||
SDValue | Base, | ||
SDValue | Offset, | ||
SDValue | Mask, | ||
SDValue | Src0, | ||
EVT | MemVT, | ||
MachineMemOperand * | MMO, | ||
ISD::MemIndexedMode | AM, | ||
ISD::LoadExtType | ExtTy, | ||
bool | IsExpanding =false | ||
) |
Definition at line9945 of fileSelectionDAG.cpp.
ReferencesAddNodeIDNode(),assert(),llvm::sampleprof::Base,llvm::MachinePointerInfo::getAddrSpace(),llvm::SDLoc::getDebugLoc(),llvm::MachineMemOperand::getFlags(),llvm::SDLoc::getIROrder(),llvm::MachineMemOperand::getPointerInfo(),llvm::EVT::getRawBits(),getVTList(),Indexed,llvm::ISD::MLOAD,N,NewSDValueDbgMsg(),llvm::Offset, andllvm::ISD::UNINDEXED.
Referenced bycombineMaskedLoad(),combineMaskedLoadConstantMask(),getIndexedMaskedLoad(),LowerMLOAD(),llvm::RISCVTargetLowering::PerformDAGCombine(),performLDNT1Combine(),performUnpackCombine(), andtryToFoldExtOfMaskedLoad().
SDValue SelectionDAG::getMaskedScatter | ( | SDVTList | VTs, |
EVT | MemVT, | ||
constSDLoc & | dl, | ||
ArrayRef<SDValue > | Ops, | ||
MachineMemOperand * | MMO, | ||
ISD::MemIndexType | IndexType, | ||
bool | IsTruncating =false | ||
) |
Definition at line10087 of fileSelectionDAG.cpp.
ReferencesAddNodeIDNode(),assert(),llvm::MachinePointerInfo::getAddrSpace(),llvm::SDLoc::getDebugLoc(),llvm::MachineMemOperand::getFlags(),llvm::SDLoc::getIROrder(),llvm::MachineMemOperand::getPointerInfo(),llvm::EVT::getRawBits(),llvm::details::FixedOrScalableQuantity< ElementCount, unsigned >::isKnownGE(),llvm::ISD::MSCATTER,N,NewSDValueDbgMsg(), andllvm::ArrayRef< T >::size().
Referenced byllvm::RISCVTargetLowering::PerformDAGCombine(),performMaskedGatherScatterCombine(), andrebuildGatherScatter().
SDValue SelectionDAG::getMaskedStore | ( | SDValue | Chain, |
constSDLoc & | dl, | ||
SDValue | Val, | ||
SDValue | Base, | ||
SDValue | Offset, | ||
SDValue | Mask, | ||
EVT | MemVT, | ||
MachineMemOperand * | MMO, | ||
ISD::MemIndexedMode | AM, | ||
bool | IsTruncating =false , | ||
bool | IsCompressing =false | ||
) |
Definition at line9991 of fileSelectionDAG.cpp.
ReferencesAddNodeIDNode(),assert(),llvm::sampleprof::Base,llvm::MachinePointerInfo::getAddrSpace(),llvm::SDLoc::getDebugLoc(),llvm::MachineMemOperand::getFlags(),llvm::SDLoc::getIROrder(),llvm::MachineMemOperand::getPointerInfo(),llvm::EVT::getRawBits(),llvm::SDValue::getValueType(),getVTList(),Indexed,llvm::ISD::MSTORE,N,NewSDValueDbgMsg(),llvm::Offset, andllvm::ISD::UNINDEXED.
Referenced bycombineMaskedStore(),getIndexedMaskedStore(),LowerINTRINSIC_W_CHAIN(),LowerMSTORE(),llvm::RISCVTargetLowering::PerformDAGCombine(),performMSTORECombine(), andperformSTNT1Combine().
Definition at line2060 of fileSelectionDAG.cpp.
ReferencesgetVTList(),N, andSym.
Referenced byrecoverFramePointer(), andtransformCallee().
Return anMDNodeSDNode which holds anMDNode.
Definition at line2418 of fileSelectionDAG.cpp.
ReferencesAddNodeIDNode(),getVTList(),llvm::ISD::MDNODE_SDNODE, andN.
Referenced byllvm::PPCTargetLowering::CollectTargetIntrinsicOperands(), andllvm::SelectionDAGBuilder::getValueImpl().
SDValue SelectionDAG::getMemBasePlusOffset | ( | SDValue | Base, |
SDValue | Offset, | ||
constSDLoc & | DL, | ||
constSDNodeFlags | Flags =SDNodeFlags() | ||
) |
Definition at line8068 of fileSelectionDAG.cpp.
Referencesllvm::ISD::ADD,assert(),DL,getNode(),llvm::Offset, andPtr.
SDValue SelectionDAG::getMemBasePlusOffset | ( | SDValue | Base, |
TypeSize | Offset, | ||
constSDLoc & | DL, | ||
constSDNodeFlags | Flags =SDNodeFlags() | ||
) |
Returns sum of the base pointer and offset.
Unlike getObjectPtrOffset this does not set NoUnsignedWrap by default.
Definition at line8052 of fileSelectionDAG.cpp.
Referencesllvm::sampleprof::Base,DL,getConstant(),getMemBasePlusOffset(),getVScale(), andllvm::Offset.
Referenced bycombineI8TruncStore(),combineLoad(),combineStore(),combineTargetShuffle(),combineV3I8LoadExt(),llvm::TargetLowering::CTTZTableLookup(),EmitUnrolledSetTag(),getBROADCAST_LOAD(),getMemBasePlusOffset(),getMemcpyLoadsAndStores(),getMemmoveLoadsAndStores(),getMemsetStores(),getObjectPtrOffset(),getParamsForOneTrueMaskedElt(),llvm::TargetLowering::getVectorSubVecPointer(),llvm::RISCVTargetLowering::LowerFormalArguments(),lowerShuffleAsBroadcast(),llvm::HexagonTargetLowering::LowerUnalignedLoad(),lowerVECTOR_SHUFFLE(),narrowExtractedVectorLoad(),performLOADCombine(),llvm::RISCVDAGToDAGISel::PreprocessISelDAG(),scalarizeVectorStore(),ShrinkLoadReplaceStoreWithStore(), andsplitVectorStore().
SDValue SelectionDAG::getMemcpy | ( | SDValue | Chain, |
constSDLoc & | dl, | ||
SDValue | Dst, | ||
SDValue | Src, | ||
SDValue | Size, | ||
Align | Alignment, | ||
bool | isVol, | ||
bool | AlwaysInline, | ||
constCallInst * | CI, | ||
std::optional<bool > | OverrideTailCall, | ||
MachinePointerInfo | DstPtrInfo, | ||
MachinePointerInfo | SrcPtrInfo, | ||
constAAMDNodes & | AAInfo =AAMDNodes() , | ||
BatchAAResults * | BatchAA =nullptr | ||
) |
Definition at line8581 of fileSelectionDAG.cpp.
Referencesassert(),checkAddrSpaceIsValidForLibcall(),llvm::SelectionDAGTargetInfo::EmitTargetCodeForMemcpy(),llvm::funcReturnsFirstArgOfCall(),llvm::MachinePointerInfo::getAddrSpace(),getContext(),getDataLayout(),getExternalSymbol(),llvm::DataLayout::getIntPtrType(),llvm::TargetLoweringBase::getLibcallCallingConv(),llvm::TargetLoweringBase::getLibcallName(),getMemcpyLoadsAndStores(),llvm::TargetLoweringBase::getPointerTy(),getTarget(),llvm::PointerType::getUnqual(),llvm::ConstantSDNode::getZExtValue(),llvm::isInTailCallPosition(),llvm::CallInst::isTailCall(),llvm::ConstantSDNode::isZero(),llvm::TargetLowering::LowerCallTo(),llvm::TargetLowering::CallLoweringInfo::setChain(),llvm::TargetLowering::CallLoweringInfo::setDebugLoc(),llvm::TargetLowering::CallLoweringInfo::setDiscardResult(),llvm::TargetLowering::CallLoweringInfo::setLibCallee(),llvm::TargetLowering::CallLoweringInfo::setTailCall(), andSize.
Referenced byCreateCopyOfByValArgument(),emitConstantSizeRepmov(),llvm::SITargetLowering::LowerCall(),llvm::XtensaTargetLowering::LowerCall(),llvm::LoongArchTargetLowering::LowerCall(),llvm::RISCVTargetLowering::LowerCall(),llvm::SparcTargetLowering::LowerCall_32(),LowerVACOPY(), andllvm::HexagonTargetLowering::LowerVACOPY().
SDValue SelectionDAG::getMemIntrinsicNode | ( | unsigned | Opcode, |
constSDLoc & | dl, | ||
SDVTList | VTList, | ||
ArrayRef<SDValue > | Ops, | ||
EVT | MemVT, | ||
MachineMemOperand * | MMO | ||
) |
Definition at line9060 of fileSelectionDAG.cpp.
ReferencesAddNodeIDNode(),assert(),llvm::ISD::BUILTIN_OP_END,llvm::MachinePointerInfo::getAddrSpace(),llvm::SDLoc::getDebugLoc(),llvm::MachineMemOperand::getFlags(),llvm::SDLoc::getIROrder(),llvm::MachineMemOperand::getPointerInfo(),llvm::EVT::getRawBits(),llvm::ISD::INTRINSIC_VOID,llvm::ISD::INTRINSIC_W_CHAIN,llvm::SelectionDAGTargetInfo::isTargetMemoryOpcode(),N,NewSDValueDbgMsg(),llvm::SDVTList::NumVTs,llvm::ISD::PREFETCH, andllvm::SDVTList::VTs.
SDValue SelectionDAG::getMemIntrinsicNode | ( | unsigned | Opcode, |
constSDLoc & | dl, | ||
SDVTList | VTList, | ||
ArrayRef<SDValue > | Ops, | ||
EVT | MemVT, | ||
MachinePointerInfo | PtrInfo, | ||
Align | Alignment, | ||
MachineMemOperand::Flags | Flags =MachineMemOperand::MOLoad | MachineMemOperand::MOStore , | ||
LocationSize | Size =0 , | ||
constAAMDNodes & | AAInfo =AAMDNodes() | ||
) |
Creates a MemIntrinsicNode that may produce a result and takes a list of operands.
Opcode may be INTRINSIC_VOID, INTRINSIC_W_CHAIN, or a target-specific memory-referencing opcode
Definition at line9045 of fileSelectionDAG.cpp.
ReferencesgetMachineFunction(),llvm::MachineFunction::getMachineMemOperand(),getMemIntrinsicNode(),llvm::EVT::getStoreSize(),llvm::LocationSize::precise(), andSize.
Referenced byllvm::X86TargetLowering::BuildFILD(),combineBitcast(),combineBVZEXTLOAD(),combineINSERT_SUBVECTOR(),combineStore(),combineTargetShuffle(),CombineVLDDUP(),combineX86CloadCstore(),createLoadLR(),createSetFPEnvNodes(),createStoreLR(),EltsFromConsecutiveLoads(),EmitMaskedTruncSStore(),EmitTruncSStore(),EmitUnrolledSetTag(),llvm::PPCTargetLowering::expandVSXLoadForLE(),llvm::PPCTargetLowering::expandVSXStoreForLE(),getAVX2GatherNode(),getBROADCAST_LOAD(),getGatherNode(),getMemIntrinsicNode(),getScatterNode(),LowerATOMIC_STORE(),lowerAtomicArithWithLOCK(),lowerBuildVectorAsBroadcast(),llvm::NVPTXTargetLowering::LowerCall(),LowerCMP_SWAP(),LowerINTRINSIC_W_CHAIN(),LowerMGATHER(),LowerMSCATTER(),llvm::SystemZTargetLowering::LowerOperationWrapper(),llvm::NVPTXTargetLowering::LowerReturn(),lowerShuffleAsBroadcast(),LowerStore(),LowerSTORE(),lowerUINT_TO_FP_vXi32(),LowerUnalignedLoadRetParam(),LowerUnalignedStoreParam(),LowerUnalignedStoreRet(),lowerVECTOR_SHUFFLE(),llvm::AMDGPUDAGToDAGISel::matchLoadD16FromBuildVector(),narrowLoadToVZLoad(),llvm::PPCTargetLowering::PerformDAGCombine(),PerformMVEVLDCombine(),performNEONPostLDSTCombine(),performPostLD1Combine(),PerformVDUPCombine(),llvm::RISCVDAGToDAGISel::PreprocessISelDAG(),ReplaceINTRINSIC_W_CHAIN(),ReplaceLoadVector(),llvm::SITargetLowering::ReplaceNodeResults(),llvm::X86TargetLowering::ReplaceNodeResults(),llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(),TryCombineBaseUpdate(),tryMemPairCombine(),llvm::X86TargetLowering::visitMaskedLoad(), andllvm::X86TargetLowering::visitMaskedStore().
| inline |
Definition at line1347 of fileSelectionDAG.h.
ReferencesgetEVTAlign(),getMemIntrinsicNode(), andSize.
SDValue SelectionDAG::getMemmove | ( | SDValue | Chain, |
constSDLoc & | dl, | ||
SDValue | Dst, | ||
SDValue | Src, | ||
SDValue | Size, | ||
Align | Alignment, | ||
bool | isVol, | ||
constCallInst * | CI, | ||
std::optional<bool > | OverrideTailCall, | ||
MachinePointerInfo | DstPtrInfo, | ||
MachinePointerInfo | SrcPtrInfo, | ||
constAAMDNodes & | AAInfo =AAMDNodes() , | ||
BatchAAResults * | BatchAA =nullptr | ||
) |
Definition at line8707 of fileSelectionDAG.cpp.
ReferencescheckAddrSpaceIsValidForLibcall(),llvm::SelectionDAGTargetInfo::EmitTargetCodeForMemmove(),llvm::funcReturnsFirstArgOfCall(),llvm::MachinePointerInfo::getAddrSpace(),getContext(),getDataLayout(),getExternalSymbol(),llvm::DataLayout::getIntPtrType(),llvm::TargetLoweringBase::getLibcallCallingConv(),llvm::TargetLoweringBase::getLibcallName(),getMemmoveLoadsAndStores(),llvm::TargetLoweringBase::getPointerTy(),getTarget(),llvm::PointerType::getUnqual(),llvm::ConstantSDNode::getZExtValue(),llvm::isInTailCallPosition(),llvm::CallInst::isTailCall(),llvm::ConstantSDNode::isZero(),llvm::TargetLowering::LowerCallTo(),llvm::TargetLowering::CallLoweringInfo::setChain(),llvm::TargetLowering::CallLoweringInfo::setDebugLoc(),llvm::TargetLowering::CallLoweringInfo::setDiscardResult(),llvm::TargetLowering::CallLoweringInfo::setLibCallee(),llvm::TargetLowering::CallLoweringInfo::setTailCall(), andSize.
SDValue SelectionDAG::getMemset | ( | SDValue | Chain, |
constSDLoc & | dl, | ||
SDValue | Dst, | ||
SDValue | Src, | ||
SDValue | Size, | ||
Align | Alignment, | ||
bool | isVol, | ||
bool | AlwaysInline, | ||
constCallInst * | CI, | ||
MachinePointerInfo | DstPtrInfo, | ||
constAAMDNodes & | AAInfo =AAMDNodes() | ||
) |
Definition at line8824 of fileSelectionDAG.cpp.
Referencesassert(),checkAddrSpaceIsValidForLibcall(),DL,llvm::SelectionDAGTargetInfo::EmitTargetCodeForMemset(),llvm::funcReturnsFirstArgOfCall(),llvm::MachinePointerInfo::getAddrSpace(),getContext(),getDataLayout(),getExternalSymbol(),llvm::TargetLoweringBase::getLibcallCallingConv(),llvm::TargetLoweringBase::getLibcallName(),getMemsetStores(),llvm::TargetLoweringBase::getPointerTy(),getTarget(),getTargetLoweringInfo(),llvm::PointerType::getUnqual(),llvm::Type::getVoidTy(),llvm::ConstantSDNode::getZExtValue(),llvm::isInTailCallPosition(),llvm::isNullConstant(),llvm::CallInst::isTailCall(),llvm::ConstantSDNode::isZero(),llvm::TargetLowering::LowerCallTo(),llvm::TargetLowering::CallLoweringInfo::setChain(),llvm::TargetLowering::CallLoweringInfo::setDebugLoc(),llvm::TargetLowering::CallLoweringInfo::setDiscardResult(),llvm::TargetLowering::CallLoweringInfo::setLibCallee(),llvm::TargetLowering::CallLoweringInfo::setTailCall(), andSize.
Referenced byemitConstantSizeRepstos().
Create a MERGE_VALUES node from the given operands.
getMergeValues - Create a MERGE_VALUES node from the given operands.
Definition at line9034 of fileSelectionDAG.cpp.
ReferencesgetNode(),getVTList(),llvm::ISD::MERGE_VALUES,llvm::SmallVectorTemplateBase< T, bool >::push_back(),llvm::SmallVectorImpl< T >::reserve(), andllvm::ArrayRef< T >::size().
Referenced bycombineFP_EXTEND(),combineFP_ROUND(),combineV3I8LoadExt(),combineVectorCompareAndMaskUnaryOp(),combineX86AddSub(),combineX86SubCmpForFlags(),constructRetValue(),emitIntrinsicWithChainErrorMessage(),expandMultipleResultFPLibCall(),FixupMMXIntrinsicTypes(),getAVX2GatherNode(),getGatherNode(),llvm::VECustomDAG::getMergeValues(),llvm::SelectionDAGBuilder::getValueImpl(),getVCIXISDNodeWCHAIN(),llvm::VETargetLowering::lowerATOMIC_SWAP(),llvm::AMDGPUTargetLowering::LowerDIVREM24(),lowerDSPIntr(),llvm::AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(),llvm::SITargetLowering::LowerDYNAMIC_STACKALLOC(),llvm::LanaiTargetLowering::LowerDYNAMIC_STACKALLOC(),llvm::NVPTXTargetLowering::LowerDYNAMIC_STACKALLOC(),llvm::VETargetLowering::lowerDYNAMIC_STACKALLOC(),LowerDYNAMIC_STACKALLOC(),LowerF128Load(),llvm::SITargetLowering::LowerFormalArguments(),LowerFP16_TO_FP(),LowerFP_TO_FP16(),llvm::SITargetLowering::lowerGET_FPENV(),llvm::SITargetLowering::lowerGET_ROUNDING(),LowerI64IntToFP16(),LowerI64IntToFP_AVX512DQ(),lowerINT_TO_FP_vXi64(),LowerINTRINSIC_W_CHAIN(),LowerLoad(),llvm::HexagonTargetLowering::LowerLoad(),llvm::MipsTargetLowering::lowerLOAD(),lowerLoadF128(),lowerLoadI1(),LowerMGATHER(),LowerMLOAD(),LowerMULO(),llvm::RISCVTargetLowering::LowerOperation(),LowerPredicateLoad(),llvm::SelectionDAGBuilder::lowerRangeToAssertZExt(),LowerREADCYCLECOUNTER(),llvm::AMDGPUTargetLowering::LowerSDIVREM(),LowerShiftParts(),llvm::LanaiTargetLowering::LowerSHL_PARTS(),llvm::LanaiTargetLowering::LowerSRL_PARTS(),llvm::SITargetLowering::LowerSTACKSAVE(),llvm::NVPTXTargetLowering::LowerSTACKSAVE(),llvm::HexagonTargetLowering::LowerUAddSubO(),llvm::HexagonTargetLowering::LowerUAddSubOCarry(),llvm::AMDGPUTargetLowering::LowerUDIVREM(),LowerUINT_TO_FP_i32(),lowerUINT_TO_FP_v2i32(),lowerUINT_TO_FP_vXi32(),llvm::HexagonTargetLowering::LowerUnalignedLoad(),lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND(),LowerVSETCC(),llvm::AArch64TargetLowering::PerformDAGCombine(),llvm::RISCVTargetLowering::PerformDAGCombine(),performFlagSettingCombine(),performGatherLoadCombine(),performLD1Combine(),performLD1ReplicateCombine(),performLDNT1Combine(),llvm::AMDGPUTargetLowering::performLoadCombine(),performLOADCombine(),PerformLongShiftCombine(),llvm::ARMTargetLowering::PerformMVEExtCombine(),PerformSplittingMVEEXTToWideningLoad(),PerformVMOVRRDCombine(),SplitStrictFPVectorOp(),llvm::AMDGPUTargetLowering::SplitVectorLoad(),tryMemPairCombine(),UnrollVectorOp(),llvm::AMDGPUTargetLowering::WidenOrSplitVectorLoad(), andwidenVectorOpsToi8().
| inline |
Definition at line494 of fileSelectionDAG.h.
| inline |
Definition at line514 of fileSelectionDAG.h.
Return the MMRAMDNode associated withNode, or nullptr if none exists.
Definition at line2377 of fileSelectionDAG.h.
Referencesllvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::end(), andllvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::find().
Referenced byllvm::ScheduleDAGSDNodes::EmitSchedule().
Create negative operation as (SUB 0, Val).
Definition at line1617 of fileSelectionDAG.cpp.
ReferencesDL,getConstant(),getNode(), andllvm::ISD::SUB.
Referenced bycombineAddOrSubToADCOrSBB(),combineAnd(),combineMul(),combinePredicateReduction(),combineSelectToBinOp(),combineSetCC(),combineX86AddSub(),LowerABS(),lowerAtomicArith(),LowerSELECTWithCmpZero(),LowerShift(),performCONCAT_VECTORSCombine(),llvm::RISCVTargetLowering::PerformDAGCombine(),performVECTOR_SHUFFLECombine(), andperformVSELECTCombine().
Get the (commutative) neutral element for the given opcode, if it exists.
Definition at line13545 of fileSelectionDAG.cpp.
Referencesllvm::ISD::ADD,llvm::ISD::AND,llvm::APFloat::changeSign(),DL,llvm::ISD::FADD,llvm::ISD::FMAXIMUM,llvm::ISD::FMAXNUM,llvm::ISD::FMINIMUM,llvm::ISD::FMINNUM,llvm::ISD::FMUL,getAllOnesConstant(),getConstant(),getConstantFP(),llvm::EVT::getFltSemantics(),llvm::APFloat::getInf(),llvm::APFloat::getLargest(),llvm::APFloat::getQNaN(),llvm::APInt::getSignedMaxValue(),llvm::APInt::getSignedMinValue(),llvm::EVT::getSizeInBits(),llvm::ISD::MUL,llvm::ISD::OR,llvm::ISD::SMAX,llvm::ISD::SMIN,llvm::ISD::UMAX,llvm::ISD::UMIN, andllvm::ISD::XOR.
Referenced bytryFoldSelectIntoOp().
SDValue SelectionDAG::getNode | ( | unsigned | Opcode, |
constSDLoc & | DL, | ||
ArrayRef<EVT > | ResultTys, | ||
ArrayRef<SDValue > | Ops | ||
) |
Definition at line10465 of fileSelectionDAG.cpp.
ReferencesDL,getNode(), andgetVTList().
Gets or creates the specified node.
Definition at line6181 of fileSelectionDAG.cpp.
ReferencesAddNodeIDNode(),DL,getVTList(),N, andNewSDValueDbgMsg().
Gets or creates the specified node.
Definition at line10327 of fileSelectionDAG.cpp.
ReferencesDL,getNode(), andllvm::ArrayRef< T >::size().
Referenced byAddCombineBUILD_VECTORToVPADDL(),AddCombineTo64bitMLAL(),AddCombineTo64BitSMLAL16(),AddCombineTo64bitUMAAL(),AddCombineToVPADD(),AddCombineVUZPToVPADDL(),addIPMSequence(),AddRequiredExtensionForVMULL(),addShuffleForVecExtend(),llvm::AMDGPUTargetLowering::addTokenForArgument(),adjustBitcastSrcVectorSSE1(),adjustForTestUnderMask(),adjustICmp128(),adjustLoadValueTypeImpl(),buildCallOperands(),BuildExactSDIV(),BuildExactUDIV(),buildFromShuffleMostly(),BuildIntrinsicOp(),buildMergeScalars(),buildPCRelGlobalAddress(),buildScalarToVector(),llvm::TargetLowering::BuildSDIV(),llvm::PPCTargetLowering::BuildSDIVPow2(),llvm::TargetLowering::buildSDIVPow2WithCMov(),llvm::TargetLowering::BuildUDIV(),BuildVectorFromScalar(),BuildVSLDOI(),canonicalizeBitSelect(),canonicalizeLaneShuffleWithRepeatedOps(),canonicalizeShuffleMaskWithHorizOp(),canonicalizeShuffleVectorByLane(),canonicalizeShuffleWithOp(),carryFlagToValue(),chainLoadsAndStoresForMemcpy(),llvm::AArch64TargetLowering::changeStreamingMode(),checkIntrinsicImmArg(),checkSignTestSetCCCombine(),clampDynamicVectorIndex(),CollectOpsToWiden(),combine_CC(),combineAcrossLanesIntrinsic(),combineADC(),combineAdd(),combineAddOfBooleanXor(),combineAddOfPMADDWD(),combineAddOrSubToADCOrSBB(),combineADDToADDZE(),combineADDToMAT_PCREL_ADDR(),combineADDX(),combineAnd(),combineAndLoadToBZHI(),combineAndMaskToShift(),combineAndNotIntoANDNP(),combineAndNotOrIntoAndNotAnd(),combineAndnp(),combineAndOrForCcmpCtest(),CombineANDShift(),combineAndShuffleNot(),combineArithReduction(),combineAVG(),combineBasicSADPattern(),combineBinOpOfExtractToReduceTree(),combineBinOpOfZExt(),combineBinOpToReduce(),combineBitcast(),combineBitcastToBoolVector(),combineBitcastvxi1(),combineBitOpWithMOVMSK(),combineBitOpWithPACK(),combineBitOpWithShift(),combineBoolVectorAndTruncateStore(),combineBrCond(),combineCarryDiamond(),combineCarryThroughADD(),combineCastedMaskArithmetic(),combineCMov(),combineCMP(),combineCommutableSHUFP(),combineCompareEqual(),combineConcatVectorOfCasts(),combineConcatVectorOfConcatVectors(),combineConcatVectorOfScalars(),combineConcatVectorOfShuffleAndItsOperands(),combineConcatVectorOps(),combineCVTP2I_CVTTP2I(),combineCVTPH2PS(),combineDeMorganOfBoolean(),combineEXTEND_VECTOR_INREG(),combineEXTRACT_SUBVECTOR(),combineExtractVectorElt(),combineExtractWithShuffle(),combineFaddCFmul(),combineFAndFNotToFAndn(),combineFMA(),combineFMADDSUB(),combineFMinFMax(),llvm::AMDGPUTargetLowering::combineFMinMaxLegacy(),llvm::AMDGPUTargetLowering::combineFMinMaxLegacyImpl(),combineFMinNumFMaxNum(),combineFMulcFCMulc(),combineFneg(),combineFP16_TO_FP(),combineFP_EXTEND(),combineFP_ROUND(),combineFP_TO_xINT_SAT(),combineGatherScatter(),combineHorizOpWithShuffle(),combineI8TruncStore(),combineINSERT_SUBVECTOR(),combineKSHIFT(),combineLoad(),combineLogicBlendIntoConditionalNegate(),combineLRINT_LLRINT(),combineM68kBrCond(),combineMADConstOne(),combineMinMaxReduction(),combineMinNumMaxNumImpl(),combineMOVMSK(),combineMul(),combineMulSelectConstOne(),combineMulSpecial(),combineMulToPMADDWD(),combineMulToPMULDQ(),combineOr(),combineOrCmpEqZeroToCtlzSrl(),combineOrOfCZERO(),combineOrXorWithSETCC(),combinePMULDQ(),combinePMULH(),combinePredicateReduction(),combinePTESTCC(),combineRedundantDWordShuffle(),combineSBB(),combineSCALAR_TO_VECTOR(),combineScalarAndWithMaskSetcc(),combineScalarCTPOPToVCPOP(),llvm::VETargetLowering::combineSelect(),combineSelect(),combineSelectAndUse(),combineSelectAsExtAnd(),llvm::VETargetLowering::combineSelectCC(),combineSelectOfTwoConstants(),combineSelectToBinOp(),combineSetCC(),combineSetCCMOVMSK(),combineSext(),combineSextInRegCmov(),combineShiftAnd1ToBitTest(),combineShiftLeft(),combineShiftOfShiftedLogic(),combineShiftRightArithmetic(),combineShiftRightLogical(),combineShiftToAVG(),combineShiftToMULH(),combineShiftToPMULH(),combineShuffleOfConcatUndef(),combineShuffleToAddSubOrFMAddSub(),combineShuffleToAnyExtendVectorInreg(),combineShuffleToFMAddSub(),combineShuffleToZeroExtendVectorInReg(),combineSignExtendInReg(),combineSIntToFP(),combineStore(),combineSub(),combineSubABS(),combineSubOfBoolean(),combineSubSetcc(),combineSubShiftToOrcB(),combineSUBX(),combineSVEPrefetchVecBaseImmOff(),combineSVEReductionFP(),combineSVEReductionInt(),combineSVEReductionOrderedFP(),combineTargetShuffle(),combineToExtendBoolVectorInReg(),combineToExtendCMOV(),combineToFPTruncExtElt(),combineToHorizontalAddSub(),combineToVWMACC(),combineTruncate(),combineTruncatedArithmetic(),combineTruncateWithSat(),combineTruncOfSraSext(),combineTruncSelectToSMaxUSat(),combineTruncToVnclip(),combineUADDO_CARRYDiamond(),combineUIntToFP(),combineV3I8LoadExt(),combineVectorCompareAndMaskUnaryOp(),combineVectorHADDSUB(),combineVectorInsert(),combineVectorMulToSraBitcast(),combineVectorPack(),combineVectorShiftImm(),combineVectorSizedSetCCEquality(),combineVFMADD_VLWithVFNEG_VL(),CombineVMOVDRRCandidateWithVecOp(),combineVPDPBUSDPattern(),combineVSelectToBLENDV(),combineVSelectWithAllOnesOrZeros(),combineVTRUNC(),combineVWADDSUBWSelect(),combineX86AddSub(),combineX86INT_TO_FP(),combineX86ShuffleChain(),combineX86SubCmpForFlags(),combineXor(),combineXorSubCTLZ(),combineZext(),CompactSwizzlableVector(),ConstantBuildVector(),constructDup(),constructRetValue(),ConvertBooleanCarryToCarryFlag(),ConvertCarryFlagToBooleanCarry(),convertFixedMaskToScalableVector(),convertFPToInt(),convertFromScalableVector(),convertIntLogicToFPLogic(),convertIntToFP(),convertLocVTToValVT(),convertMergedOpToPredOp(),ConvertSelectToConcatVector(),convertShiftLeftToScale(),convertToScalableVector(),convertValVTToLocVT(),createCMovFP(),createFPCmp(),createLoadLR(),createMemMemNode(),createMMXBuildVector(),createPSADBW(),createSetFPEnvNodes(),createStoreLR(),createVariablePermute(),createVPDPBUSD(),llvm::TargetLowering::CTTZTableLookup(),customLegalizeToWOp(),customLegalizeToWOpWithSExt(),CustomNonLegalBITCASTResults(),detectPMADDUBSW(),detectUSatPattern(),distributeOpThroughSelect(),dump(),EltsFromConsecutiveLoads(),EmitAVX512Test(),EmitCMP(),EmitCmp(),emitCmp(),emitComparison(),emitConditionalComparison(),emitConstantSizeRepmov(),emitConstantSizeRepstos(),emitIntrinsicWithCC(),emitIntrinsicWithCCAndChain(),emitMemMemReg(),llvm::AArch64SelectionDAGInfo::EmitMOPS(),emitOrXorXorTree(),emitRepmovs(),emitRepstos(),emitSETCC(),llvm::ARMSelectionDAGInfo::EmitSpecializedLibcall(),emitStrictFPComparison(),llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemchr(),llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(),llvm::BPFSelectionDAGInfo::EmitTargetCodeForMemcpy(),llvm::WebAssemblySelectionDAGInfo::EmitTargetCodeForMemcpy(),llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemset(),llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemset(),llvm::WebAssemblySelectionDAGInfo::EmitTargetCodeForMemset(),llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrcmp(),llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrcpy(),llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrnlen(),EmitTest(),EmitUnrolledSetTag(),EmitVectorComparison(),Expand64BitShift(),llvm::TargetLowering::expandABD(),llvm::TargetLowering::expandABS(),llvm::TargetLowering::expandAddSubSat(),llvm::TargetLowering::expandAVG(),expandBitCastF128ToI128(),llvm::TargetLowering::expandBITREVERSE(),llvm::TargetLowering::expandBSWAP(),ExpandBVWithShuffles(),llvm::TargetLowering::expandCMP(),llvm::TargetLowering::expandCTLZ(),llvm::TargetLowering::expandCTPOP(),llvm::TargetLowering::expandCTTZ(),expandDivFix(),llvm::TargetLowering::expandDIVREMByConstant(),expandExp(),expandExp2(),expandf64Toi32(),llvm::TargetLowering::expandFixedPointDiv(),llvm::TargetLowering::expandFixedPointMul(),llvm::TargetLowering::expandFMINIMUM_FMAXIMUM(),llvm::TargetLowering::expandFMINIMUMNUM_FMAXIMUMNUM(),llvm::TargetLowering::expandFMINNUM_FMAXNUM(),llvm::TargetLowering::expandFP_ROUND(),llvm::TargetLowering::expandFP_TO_INT_SAT(),llvm::TargetLowering::expandFP_TO_SINT(),llvm::TargetLowering::expandFP_TO_UINT(),expandFP_TO_UINT_SSE(),llvm::TargetLowering::expandFunnelShift(),ExpandHorizontalBinOp(),llvm::TargetLowering::expandIndirectJTBranch(),llvm::RISCVTargetLowering::expandIndirectJTBranch(),llvm::X86TargetLowering::expandIndirectJTBranch(),llvm::TargetLowering::expandIntMINMAX(),expandIntrinsicWChainHelper(),llvm::TargetLowering::expandIS_FPCLASS(),expandLog(),expandLog10(),expandLog2(),expandMul(),llvm::TargetLowering::expandMUL_LOHI(),llvm::TargetLowering::expandMULO(),expandMultipleResultFPLibCall(),expandPow(),ExpandPowI(),ExpandREAD_REGISTER(),llvm::TargetLowering::expandREM(),llvm::TargetLowering::expandROT(),llvm::TargetLowering::expandRoundInexactToOdd(),llvm::TargetLowering::expandSADDSUBO(),llvm::TargetLowering::expandShiftParts(),llvm::TargetLowering::expandShlSat(),llvm::TargetLowering::expandUADDSUBO(),llvm::TargetLowering::expandUINT_TO_FP(),llvm::TargetLowering::expandUnalignedLoad(),llvm::TargetLowering::expandUnalignedStore(),expandV4F32ToV2F64(),expandVAArg(),llvm::TargetLowering::expandVecReduce(),llvm::TargetLowering::expandVecReduceSeq(),llvm::TargetLowering::expandVECTOR_COMPRESS(),llvm::TargetLowering::expandVectorFindLastActive(),llvm::TargetLowering::expandVectorNaryOpBySplitting(),llvm::TargetLowering::expandVectorSplice(),llvm::TargetLowering::expandVPBITREVERSE(),llvm::TargetLowering::expandVPBSWAP(),llvm::TargetLowering::expandVPCTLZ(),llvm::TargetLowering::expandVPCTPOP(),llvm::TargetLowering::expandVPCTTZ(),llvm::TargetLowering::expandVPCTTZElements(),expandVPFunnelShift(),llvm::PPCTargetLowering::expandVSXLoadForLE(),llvm::PPCTargetLowering::expandVSXStoreForLE(),ExtendToType(),ExtractBitFromMaskVector(),extractF64Exponent(),extractLOHI(),extractShiftForRotate(),extractSubVector(),ExtractVectorElements(),finalizeTS1AM(),findMoreOptimalIndexType(),FixupMMXIntrinsicTypes(),foldADCToCINC(),foldAddSubBoolOfMaskedVal(),foldAddSubMasked1(),foldAddSubOfSignBit(),foldAndOrOfSETCC(),foldAndToUsubsat(),foldBinOpIntoSelectIfProfitable(),foldBitOrderCrossLogicOp(),FoldConstantArithmetic(),foldCSELOfCSEL(),foldCSELofCTTZ(),foldExtendedSignBitTest(),foldExtendVectorInregToExtendOfSubvector(),foldExtractSubvectorFromShuffleVector(),foldFPToIntToFP(),llvm::AMDGPUTargetLowering::foldFreeOpFromSelect(),foldIndexIntoBase(),FoldIntToFPToInt(),foldLogicOfShifts(),foldLogicTreeOfShifts(),foldMaskAndShiftToExtract(),foldMaskAndShiftToScale(),foldMaskedMergeImpl(),foldMaskedShiftToBEXTR(),foldMaskedShiftToScaledMask(),foldOverflowCheck(),foldSelectOfConstantsUsingSra(),foldSelectOfCTTZOrCTLZ(),foldSelectWithIdentityConstant(),foldSetCCWithFunnelShift(),foldSetCCWithRotate(),foldShuffleOfConcatUndefs(),foldSubCtlzNot(),foldToSaturated(),foldVectorXorShiftIntoCmp(),foldVSelectToSignBitSplatMask(),foldXorTruncShiftIntoCmp(),llvm::TargetLowering::forceExpandMultiply(),llvm::TargetLowering::forceExpandWideMUL(),fpExtendHelper(),genConstMult(),generateComparison(),generateEquivalentSub(),GenerateFixedLengthSVETBL(),GeneratePerfectShuffle(),GenerateTBL(),getAArch64Cmp(),getAArch64XALUOOp(),getAbsolute(),getADAEntry(),llvm::MipsTargetLowering::getAddrGlobal(),llvm::MipsTargetLowering::getAddrGlobalLargeGOT(),llvm::MipsTargetLowering::getAddrGPRel(),llvm::MipsTargetLowering::getAddrLocal(),llvm::MipsTargetLowering::getAddrNonPIC(),llvm::MipsTargetLowering::getAddrNonPICSym64(),getAllOnesMask(),getAnyExtOrTrunc(),getAVX512Node(),getAVX512TruncNode(),getBitcast(),getBitSelect(),getBitTestCondition(),getBMIMatchingOp(),getBoolExtOrTrunc(),getBoundedStrlen(),getBT(),getBuildVector(),getBuildVectorSplat(),getCALLSEQ_END(),getCALLSEQ_START(),getCCResult(),getConstant(),getCopyFromParts(),getCopyFromPartsVector(),getCopyFromReg(),llvm::RegsForValue::getCopyFromRegs(),getCopyToParts(),getCopyToPartsVector(),getCopyToReg(),llvm::RegsForValue::getCopyToRegs(),getCSAddressAndShifts(),getDataClassTest(),getDeinterleaveShiftAndTrunc(),llvm::MipsTargetLowering::getDllimportSymbol(),getDWordFromOffset(),llvm::HexagonTargetLowering::GetDynamicTLSAddr(),getEstimate(),GetExponent(),getEXTEND_VECTOR_INREG(),getFlagsOfCmpZeroFori1(),getFLUSHW(),getFPBinOp(),getFPExtendOrRound(),getFPTernOp(),getFRAMEADDR(),getFreeze(),getGeneralPermuteNode(),getGLOBAL_OFFSET_TABLE(),llvm::AMDGPUTargetLowering::getHiHalf64(),getHopForBuildVector(),getI128Select(),llvm::AMDGPUTargetLowering::getIsFinite(),getJumpTableDebugInfo(),getKnownUndefForVectorBinop(),getLargeExternalSymbol(),getLargeGlobalAddress(),getLimitedPrecisionExp2(),getLoadExtOrTrunc(),getLogicalNOT(),llvm::AMDGPUTargetLowering::getLoHalf64(),getMad(),getMad64_32(),llvm::VECustomDAG::getMaskBroadcast(),getMaskNode(),getMemBasePlusOffset(),getMemcpyLoadsAndStores(),getMemmoveLoadsAndStores(),getMemsetStores(),getMemsetStringVal(),getMemsetValue(),getMergeValues(),getMul24(),llvm::AMDGPUTargetLowering::getNegatedExpression(),llvm::X86TargetLowering::getNegatedExpression(),llvm::TargetLowering::getNegatedExpression(),llvm::PPCTargetLowering::getNegatedExpression(),getNegatedInteger(),getNegative(),llvm::EmptyMatchContext::getNode(),llvm::VECustomDAG::getNode(),getNode(),llvm::VPMatchContext::getNode(),getNOT(),llvm::VECustomDAG::getPack(),getPack(),getPartialReduceAdd(),getPermuteNode(),llvm::HexagonTargetLowering::getPICJumpTableRelocBase(),llvm::M68kTargetLowering::getPICJumpTableRelocBase(),llvm::PPCTargetLowering::getPICJumpTableRelocBase(),llvm::VETargetLowering::getPICJumpTableRelocBase(),llvm::X86TargetLowering::getPICJumpTableRelocBase(),getPMOVMSKB(),getPTest(),getPTrue(),llvm::AMDGPUTargetLowering::getRecipEstimate(),llvm::LoongArchTargetLowering::getRecipEstimate(),getReductionSDNode(),getRegistersForValue(),getRVVFPReductionOpAndOperands(),getScalarMaskingNode(),llvm::AMDGPUTargetLowering::getScaledLogInput(),getScaledOffsetForBitWidth(),getSelect(),getSelectCC(),getSETCC(),getSetCC(),getSetCCVP(),getSExtOrTrunc(),getShuffleHalfVectors(),GetSignificand(),getSplatBuildVector(),getSplatValue(),getSplatVector(),llvm::NVPTXTargetLowering::getSqrtEstimate(),llvm::AMDGPUTargetLowering::getSqrtEstimate(),llvm::LoongArchTargetLowering::getSqrtEstimate(),llvm::TargetLowering::getSqrtInputTest(),getStackArgumentTokenFactor(),getStepVector(),getSToVPermuted(),getStrictFPExtendOrRound(),getSVEPredicateBitCast(),getTargetVShiftByConstNode(),getTargetVShiftNode(),GetTLSADDR(),getTokenFactor(),getTruncatedUSUBSAT(),getUNDEF(),llvm::VECustomDAG::getUnpack(),getv64i1Argument(),getVAArg(),llvm::SelectionDAGBuilder::getValueImpl(),getVCIXISDNodeVOID(),getVCIXISDNodeWCHAIN(),getVectorBitwiseReduce(),getVectorMaskingNode(),getVectorShuffle(),llvm::TargetLowering::getVectorSubVecPointer(),getVPLogicalNOT(),getVPZeroExtendInReg(),getVPZExtOrTrunc(),getVScale(),getVShift(),getVSlidedown(),getVSlideup(),getWideningInterleave(),getWideningSpread(),getX86XALUOOp(),getZeroExtendInReg(),getZeroVector(),getZExtOrTrunc(),getzOSCalleeAndADA(),handleCMSEValue(),HandleMergeInputChains(),llvm::TargetLowering::IncrementMemoryAddress(),initAccumulator(),insert1BitVector(),InsertBitToMaskVector(),insertSubVector(),isFNEG(),isFusableLoadOpStorePattern(),IsNOT(),isUpperSubvectorUndef(),joinDwords(),llvm::RISCVTargetLowering::joinRegisterPartsIntoValue(),Legalize(),legalizeIntrinsicImmArg(),legalizeScatterGatherIndexType(),llvm::TargetLowering::LegalizeSetCCCondCode(),legalizeSVEGatherPrefetchOffsVec(),llvm::AMDGPUTargetLowering::loadInputValue(),lower1BitShuffle(),lower1BitShuffleAsKSHIFTR(),LowerABD(),LowerABS(),lowerAddrSpaceCast(),LowerADDRSPACECAST(),LowerADDSAT_SUBSAT(),LowerADDSUBO_CARRY(),lowerADDSUBO_CARRY(),LowerADDSUBSAT(),lowerAddSubToHorizontalOp(),llvm::X86TargetLowering::LowerAsmOutputForConstraint(),LowerAsSplatVectorLoad(),llvm::SelectionDAGBuilder::LowerAsSTATEPOINT(),llvm::HexagonTargetLowering::LowerATOMIC_FENCE(),llvm::VETargetLowering::lowerATOMIC_FENCE(),LowerATOMIC_FENCE(),LowerATOMIC_STORE(),llvm::VETargetLowering::lowerATOMIC_SWAP(),lowerAtomicArith(),LowerAVXCONCAT_VECTORS(),LowerAVXExtend(),lowerBALLOTIntrinsic(),LowerBITCAST(),LowerBITREVERSE(),LowerBITREVERSE_XOP(),lowerBitreverseShuffle(),llvm::HexagonTargetLowering::LowerBlockAddress(),llvm::LanaiTargetLowering::LowerBlockAddress(),llvm::MSP430TargetLowering::LowerBlockAddress(),llvm::LanaiTargetLowering::LowerBR_CC(),llvm::MSP430TargetLowering::LowerBR_CC(),LowerBR_CC(),LowerBRCOND(),llvm::HexagonTargetLowering::LowerBUILD_VECTOR(),lowerBUILD_VECTOR(),LowerBUILD_VECTOR_i1(),LowerBUILD_VECTORToVIDUP(),LowerBUILD_VECTORvXbf16(),LowerBUILD_VECTORvXi1(),lowerBuildVectorAsBroadcast(),LowerBuildVectorAsInsert(),lowerBuildVectorOfConstants(),LowerBuildVectorOfFPExt(),LowerBuildVectorOfFPTrunc(),lowerBuildVectorToBitOp(),LowerBuildVectorv16i8(),LowerBuildVectorv4x32(),lowerBuildVectorViaDominantValues(),lowerBuildVectorViaPacking(),llvm::SITargetLowering::LowerCall(),llvm::NVPTXTargetLowering::LowerCall(),llvm::SystemZTargetLowering::LowerCall(),llvm::XtensaTargetLowering::LowerCall(),llvm::HexagonTargetLowering::LowerCall(),llvm::LoongArchTargetLowering::LowerCall(),llvm::RISCVTargetLowering::LowerCall(),llvm::VETargetLowering::LowerCall(),llvm::SparcTargetLowering::LowerCall_32(),llvm::SparcTargetLowering::LowerCall_64(),lowerCallResult(),llvm::SITargetLowering::LowerCallResult(),LowerCallResult(),llvm::TargetLowering::LowerCallTo(),LowerCMP_SWAP(),llvm::TargetLowering::lowerCmpEqZeroToCtlzSrl(),llvm::AMDGPUTargetLowering::LowerCONCAT_VECTORS(),llvm::HexagonTargetLowering::LowerCONCAT_VECTORS(),LowerCONCAT_VECTORS(),LowerCONCAT_VECTORS_i1(),LowerCONCAT_VECTORSvXi1(),llvm::HexagonTargetLowering::LowerConstantPool(),llvm::LanaiTargetLowering::LowerConstantPool(),LowerConvertLow(),LowerCTLZ(),llvm::AMDGPUTargetLowering::LowerCTLZ_CTTZ(),llvm::AMDGPUTargetLowering::lowerCTLZResults(),LowerCTPOP(),LowerCTTZ(),lowerCttzElts(),LowerCVTPS2PH(),llvm::SelectionDAGBuilder::LowerDeoptimizingReturn(),lowerDisjointIndicesShuffle(),llvm::AMDGPUTargetLowering::LowerDIVREM24(),lowerDSPIntr(),llvm::SITargetLowering::LowerDYNAMIC_STACKALLOC(),llvm::HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(),llvm::LanaiTargetLowering::LowerDYNAMIC_STACKALLOC(),llvm::NVPTXTargetLowering::LowerDYNAMIC_STACKALLOC(),llvm::VETargetLowering::lowerDYNAMIC_STACKALLOC(),LowerDYNAMIC_STACKALLOC(),llvm::HexagonTargetLowering::LowerEH_RETURN(),llvm::VETargetLowering::lowerEH_SJLJ_LONGJMP(),llvm::VETargetLowering::lowerEH_SJLJ_SETJMP(),llvm::VETargetLowering::lowerEH_SJLJ_SETUP_DISPATCH(),LowerEXTEND_VECTOR_INREG(),llvm::MSP430TargetLowering::LowerExternalSymbol(),llvm::AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(),LowerEXTRACT_SUBVECTOR(),llvm::VETargetLowering::lowerEXTRACT_VECTOR_ELT(),LowerEXTRACT_VECTOR_ELT(),LowerEXTRACT_VECTOR_ELT_i1(),LowerEXTRACT_VECTOR_ELT_SSE4(),llvm::SparcTargetLowering::LowerF128Compare(),LowerF128Load(),LowerF128Store(),LowerF64Op(),LowerFABSorFNEG(),lowerFABSorFNEG(),LowerFCanonicalize(),llvm::AMDGPUTargetLowering::LowerFCEIL(),lowerFCMPIntrinsic(),LowerFCOPYSIGN(),lowerFCOPYSIGN(),lowerFCOPYSIGN32(),lowerFCOPYSIGN64(),llvm::AMDGPUTargetLowering::lowerFEXP(),llvm::AMDGPUTargetLowering::lowerFEXP10Unsafe(),llvm::AMDGPUTargetLowering::lowerFEXP2(),llvm::AMDGPUTargetLowering::lowerFEXPUnsafe(),llvm::AMDGPUTargetLowering::LowerFFLOOR(),LowerFGETSIGN(),LowerFLDEXP(),llvm::AMDGPUTargetLowering::LowerFLOG2(),llvm::AMDGPUTargetLowering::LowerFLOGCommon(),llvm::AMDGPUTargetLowering::LowerFLOGUnsafe(),lowerFMAXIMUM_FMINIMUM(),LowerFMINIMUM_FMAXIMUM(),llvm::AMDGPUTargetLowering::LowerFNEARBYINT(),LowerFNEGorFABS(),llvm::SITargetLowering::LowerFormalArguments(),llvm::HexagonTargetLowering::LowerFormalArguments(),llvm::LoongArchTargetLowering::LowerFormalArguments(),llvm::NVPTXTargetLowering::LowerFormalArguments(),llvm::RISCVTargetLowering::LowerFormalArguments(),llvm::SystemZTargetLowering::LowerFormalArguments(),llvm::VETargetLowering::LowerFormalArguments(),llvm::XtensaTargetLowering::LowerFormalArguments(),llvm::SparcTargetLowering::LowerFormalArguments_32(),llvm::SparcTargetLowering::LowerFormalArguments_64(),LowerFP16_TO_FP(),llvm::SITargetLowering::lowerFP_EXTEND(),LowerFP_TO_FP16(),llvm::AMDGPUTargetLowering::LowerFP_TO_FP16(),llvm::AMDGPUTargetLowering::LowerFP_TO_INT(),lowerFP_TO_INT(),llvm::AMDGPUTargetLowering::LowerFP_TO_INT64(),LowerFP_TO_INT_SAT(),lowerFP_TO_INT_SAT(),LowerFP_TO_SINT(),lowerFP_TO_SINT_STORE(),lowerFPToIntToFP(),llvm::LanaiTargetLowering::LowerFRAMEADDR(),llvm::AMDGPUTargetLowering::LowerFREM(),llvm::AMDGPUTargetLowering::LowerFRINT(),LowerFROUND(),llvm::AMDGPUTargetLowering::LowerFROUND(),llvm::AMDGPUTargetLowering::LowerFROUNDEVEN(),LowerFSINCOS(),llvm::AMDGPUTargetLowering::LowerFTRUNC(),lowerFTRUNC_FCEIL_FFLOOR_FROUND(),LowerFunnelShift(),llvm::SITargetLowering::lowerGET_FPENV(),llvm::SITargetLowering::lowerGET_ROUNDING(),lowerGetVectorLength(),llvm::HexagonTargetLowering::LowerGLOBAL_OFFSET_TABLE(),llvm::AMDGPUTargetLowering::LowerGlobalAddress(),llvm::HexagonTargetLowering::LowerGLOBALADDRESS(),llvm::LanaiTargetLowering::LowerGlobalAddress(),llvm::MSP430TargetLowering::LowerGlobalAddress(),llvm::NVPTXTargetLowering::LowerGlobalAddress(),llvm::SparcTargetLowering::LowerGlobalTLSAddress(),lowerGR128Binary(),lowerGR128ToI128(),LowerHorizontalByteSum(),lowerI128ToGR128(),LowerI64IntToFP16(),LowerI64IntToFP_AVX512DQ(),lowerICMPIntrinsic(),llvm::VETargetLowering::lowerINSERT_VECTOR_ELT(),LowerINSERT_VECTOR_ELT_i1(),lowerINT_TO_FP(),llvm::AMDGPUTargetLowering::LowerINT_TO_FP32(),llvm::AMDGPUTargetLowering::LowerINT_TO_FP64(),lowerINT_TO_FP_vXi64(),LowerInterruptReturn(),llvm::HexagonTargetLowering::LowerINTRINSIC_VOID(),LowerINTRINSIC_W_CHAIN(),llvm::VETargetLowering::lowerINTRINSIC_WO_CHAIN(),llvm::HexagonTargetLowering::LowerJumpTable(),llvm::LanaiTargetLowering::LowerJumpTable(),llvm::MSP430TargetLowering::LowerJumpTable(),LowerLabelRef(),lowerLaneOp(),LowerLoad(),llvm::MipsTargetLowering::lowerLOAD(),lowerLoadF128(),lowerLoadI1(),lowerMasksToReg(),LowerMemOpCallTo(),LowerMGATHER(),LowerMLOAD(),lowerMSABinaryBitImmIntr(),lowerMSABitClear(),lowerMSABitClearImm(),lowerMSACopyIntr(),lowerMSALoadIntr(),lowerMSASplatZExt(),lowerMSAStoreIntr(),LowerMSCATTER(),LowerMUL(),llvm::LanaiTargetLowering::LowerMUL(),lowerMUL_LOHI32(),LowerMULH(),LowerMULO(),llvm::AArch64TargetLowering::LowerOperation(),llvm::R600TargetLowering::LowerOperation(),llvm::RISCVTargetLowering::LowerOperation(),lowerOverflowArithmetic(),LowerPARITY(),LowerPredicateLoad(),LowerPredicateStore(),LowerPREFETCH(),llvm::HexagonTargetLowering::LowerPREFETCH(),llvm::SelectionDAGBuilder::lowerRangeToAssertZExt(),llvm::HexagonTargetLowering::LowerREADCYCLECOUNTER(),llvm::HexagonTargetLowering::LowerREADSTEADYCOUNTER(),lowerReductionSeq(),lowerRegToMasks(),llvm::AMDGPUTargetLowering::LowerReturn(),llvm::SITargetLowering::LowerReturn(),llvm::HexagonTargetLowering::LowerReturn(),llvm::LoongArchTargetLowering::LowerReturn(),llvm::NVPTXTargetLowering::LowerReturn(),llvm::RISCVTargetLowering::LowerReturn(),llvm::SystemZTargetLowering::LowerReturn(),llvm::VETargetLowering::LowerReturn(),llvm::XtensaTargetLowering::LowerReturn(),llvm::SparcTargetLowering::LowerReturn_32(),llvm::SparcTargetLowering::LowerReturn_64(),llvm::HexagonTargetLowering::LowerRETURNADDR(),llvm::LanaiTargetLowering::LowerRETURNADDR(),llvm::MSP430TargetLowering::LowerRETURNADDR(),LowerRETURNADDR(),lowerRETURNADDR(),LowerReverse_VECTOR_SHUFFLE(),LowerRotate(),LowerSaturatingConditional(),LowerSCALAR_TO_VECTOR(),lowerScalarInsert(),lowerScalarSplat(),LowerSDIV(),LowerSDIV_v4i16(),LowerSDIV_v4i8(),llvm::AMDGPUTargetLowering::LowerSDIVREM(),llvm::LanaiTargetLowering::LowerSELECT_CC(),llvm::MSP430TargetLowering::LowerSELECT_CC(),LowerSELECT_CC(),LowerSELECTWithCmpZero(),llvm::SITargetLowering::lowerSET_FPENV(),llvm::SITargetLowering::lowerSET_ROUNDING(),llvm::LanaiTargetLowering::LowerSETCC(),llvm::MSP430TargetLowering::LowerSETCC(),LowerSETCCCARRY(),LowerShift(),LowerShiftByScalarImmediate(),LowerShiftByScalarVariable(),llvm::MSP430TargetLowering::LowerShifts(),llvm::LanaiTargetLowering::LowerSHL_PARTS(),lowerShuffleAsBitMask(),lowerShuffleAsBitRotate(),lowerShuffleAsBlend(),lowerShuffleAsBlendOfPSHUFBs(),lowerShuffleAsBroadcast(),lowerShuffleAsByteRotate(),lowerShuffleAsByteRotateAndPermute(),lowerShuffleAsByteShiftMask(),lowerShuffleAsDecomposedShuffleMerge(),lowerShuffleAsElementInsertion(),lowerShuffleAsInsertPS(),lowerShuffleAsLanePermuteAndSHUFP(),lowerShuffleAsPermuteAndUnpack(),lowerShuffleAsShift(),lowerShuffleAsSpecificZeroOrAnyExtend(),lowerShuffleAsTruncBroadcast(),lowerShuffleAsUNPCKAndPermute(),lowerShuffleAsVALIGN(),lowerShuffleAsVTRUNC(),lowerShuffleAsVTRUNCAndUnpack(),lowerShuffleAsZeroOrAnyExtend(),lowerShuffleOfExtractsAsVperm(),lowerShufflePairAsUNPCKAndPermute(),lowerShuffleWithEXPAND(),lowerShuffleWithPACK(),lowerShuffleWithPERMV(),lowerShuffleWithPSHUFB(),lowerShuffleWithSHUFPD(),lowerShuffleWithSHUFPS(),lowerShuffleWithSSE4A(),lowerShuffleWithUndefHalf(),lowerShuffleWithUNPCK(),lowerShuffleWithUNPCK256(),LowerSIGN_EXTEND(),llvm::MSP430TargetLowering::LowerSIGN_EXTEND(),llvm::AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(),LowerSIGN_EXTEND_Mask(),llvm::AMDGPUTargetLowering::LowerSINT_TO_FP(),LowerSINT_TO_FP(),LowerSMELdrStr(),llvm::LanaiTargetLowering::LowerSRL_PARTS(),llvm::NVPTXTargetLowering::LowerSTACKRESTORE(),llvm::SITargetLowering::LowerSTACKSAVE(),llvm::NVPTXTargetLowering::LowerSTACKSAVE(),LowerStore(),LowerSTORE(),lowerStoreF128(),lowerStoreI1(),LowerSVEIntrinsicDUP(),LowerSVEIntrinsicEXT(),LowerSVEIntrinsicIndex(),lowerToAddSubOrFMAddSub(),LowerToTLSExecModel(),llvm::HexagonTargetLowering::LowerToTLSGeneralDynamicModel(),llvm::VETargetLowering::lowerToTLSGeneralDynamicModel(),llvm::HexagonTargetLowering::LowerToTLSInitialExecModel(),LowerToTLSLocalDynamicModel(),llvm::HexagonTargetLowering::LowerToTLSLocalExecModel(),LowerTruncate(),LowerTruncatei1(),LowerTruncateVecI1(),LowerTruncateVecPack(),LowerTruncateVectorStore(),llvm::HexagonTargetLowering::LowerUAddSubO(),LowerUADDSUBO_CARRY(),llvm::HexagonTargetLowering::LowerUAddSubOCarry(),LowerUDIV(),llvm::AMDGPUTargetLowering::LowerUDIVREM(),llvm::AMDGPUTargetLowering::LowerUDIVREM64(),llvm::AMDGPUTargetLowering::LowerUINT_TO_FP(),LowerUINT_TO_FP_i32(),LowerUINT_TO_FP_i64(),lowerUINT_TO_FP_v2i32(),lowerUINT_TO_FP_vXi32(),llvm::HexagonTargetLowering::LowerUnalignedLoad(),LowerUnalignedLoadRetParam(),LowerUnalignedStoreParam(),LowerUnalignedStoreRet(),lowerV16F32Shuffle(),lowerV16I32Shuffle(),lowerV16I8Shuffle(),lowerV2F64Shuffle(),lowerV2I64Shuffle(),lowerV2X128Shuffle(),lowerV4F32Shuffle(),lowerV4F64Shuffle(),lowerV4I32Shuffle(),lowerV4I64Shuffle(),lowerV4X128Shuffle(),lowerV8F32Shuffle(),lowerV8F64Shuffle(),lowerV8I16GeneralSingleInputShuffle(),lowerV8I16Shuffle(),lowerV8I32Shuffle(),lowerV8I64Shuffle(),LowerVAARG(),llvm::VETargetLowering::lowerVAARG(),llvm::HexagonTargetLowering::LowerVASTART(),llvm::VETargetLowering::lowerVASTART(),LowerVASTART(),LowerVecReduce(),LowerVecReduceMinMax(),lowerVECTOR_COMPRESS(),llvm::HexagonTargetLowering::LowerVECTOR_SHIFT(),llvm::HexagonTargetLowering::LowerVECTOR_SHUFFLE(),LowerVECTOR_SHUFFLE(),lowerVECTOR_SHUFFLE(),LowerVECTOR_SHUFFLE_i1(),lowerVECTOR_SHUFFLE_ILVEV(),lowerVECTOR_SHUFFLE_ILVL(),lowerVECTOR_SHUFFLE_ILVOD(),lowerVECTOR_SHUFFLE_ILVR(),lowerVECTOR_SHUFFLE_PCKEV(),lowerVECTOR_SHUFFLE_PCKOD(),lowerVECTOR_SHUFFLE_SHF(),lowerVECTOR_SHUFFLE_VILVH(),lowerVECTOR_SHUFFLE_VILVL(),lowerVECTOR_SHUFFLE_VPACKEV(),lowerVECTOR_SHUFFLE_VPACKOD(),lowerVECTOR_SHUFFLE_VPICKEV(),lowerVECTOR_SHUFFLE_VPICKOD(),lowerVECTOR_SHUFFLE_VREPLVEI(),lowerVECTOR_SHUFFLE_VSHF(),lowerVECTOR_SHUFFLE_VSHUF(),lowerVECTOR_SHUFFLE_VSHUF4I(),lowerVECTOR_SHUFFLE_XVILVH(),lowerVECTOR_SHUFFLE_XVILVL(),lowerVECTOR_SHUFFLE_XVPICKEV(),lowerVECTOR_SHUFFLE_XVPICKOD(),lowerVECTOR_SHUFFLE_XVREPLVEI(),lowerVECTOR_SHUFFLE_XVSHUF(),lowerVECTOR_SHUFFLEAsRotate(),lowerVECTOR_SHUFFLEAsVSlide1(),lowerVECTOR_SHUFFLEAsVSlidedown(),lowerVECTOR_SHUFFLEAsVSlideup(),LowerVECTOR_SHUFFLEUsingMovs(),LowerVECTOR_SHUFFLEUsingOneOff(),LowerVECTOR_SHUFFLEv8i8(),LowerVectorAllEqual(),LowerVectorArith(),lowerVectorBitClear(),lowerVectorBitClearImm(),lowerVectorBitRevImm(),lowerVectorBitSetImm(),LowerVectorCTLZ_AVX512CDI(),LowerVectorCTLZInRegLUT(),LowerVectorCTPOP(),LowerVectorCTPOPInRegLUT(),LowerVectorExtend(),LowerVectorFP_TO_INT(),lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(),LowerVectorINT_TO_FP(),lowerVectorIntrinsicScalars(),LowerVectorMatch(),lowerVectorSplatImm(),lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND(),lowerVectorXRINT(),LowerVSETCC(),LowerVSETCCWithSUBUS(),LowervXi8MulWithUNPCK(),LowerWRITE_REGISTER(),lowerX86CmpEqZeroToCtlzSrl(),lowerX86FPLogicOp(),LowerXALUO(),LowerZERO_EXTEND_Mask(),llvm::SparcTargetLowering::makeAddress(),llvm::VETargetLowering::makeAddress(),makeEquivalentMemoryOrdering(),llvm::SparcTargetLowering::makeHiLoPair(),llvm::VETargetLowering::makeHiLoPair(),matchBinOpReduction(),matchBSwapHWordOrAndAnd(),llvm::AMDGPUDAGToDAGISel::matchLoadD16FromBuildVector(),matchPERM(),matchPMADDWD(),matchPMADDWD_2(),matchSplatAsGather(),matchTruncateWithPACK(),MatchVectorAllEqualTest(),MaybeBitcast(),moveBelowOrigChain(),narrowExtractedVectorBinOp(),narrowIndex(),narrowInsertExtractVectorBinOp(),narrowVectorSelect(),optimizeLogicalImm(),overflowFlagToValue(),packImage16bitOpsToDwords(),partitionShuffleOfConcats(),llvm::SITargetLowering::passSpecialInputs(),performADDCombine(),performAddCombineForShiftedOperands(),performAddCombineSubShift(),PerformADDCombineWithOperands(),performAddCSelIntoCSinc(),PerformAddcSubcCombine(),performAddDotCombine(),PerformAddeSubeCombine(),performAddSubIntoVectorOp(),performAddSubLongCombine(),performAddUADDVCombine(),PerformADDVecReduce(),performANDCombine(),PerformANDCombine(),performANDORCSELCombine(),performANDSETCCCombine(),PerformARMBUILD_VECTORCombine(),llvm::AMDGPUTargetLowering::performAssertSZExtCombine(),PerformBFICombine(),performBitcastCombine(),PerformBITCASTCombine(),performBITREV_WCombine(),performBITREVERSECombine(),llvm::ARMTargetLowering::PerformBRCONDCombine(),performBRCONDCombine(),performBSPExpandForSVE(),performBUILD_VECTORCombine(),PerformBUILD_VECTORCombine(),performBuildShuffleExtendCombine(),performBuildVectorCombine(),llvm::ARMTargetLowering::PerformCMOVCombine(),performCMovFPCombine(),llvm::ARMTargetLowering::PerformCMOVToBFICombine(),performConcatVectorsCombine(),performCONDCombine(),performCSELCombine(),PerformCSETCombine(),performCTLZCombine(),llvm::AArch64TargetLowering::PerformDAGCombine(),llvm::AMDGPUTargetLowering::PerformDAGCombine(),llvm::R600TargetLowering::PerformDAGCombine(),llvm::SITargetLowering::PerformDAGCombine(),llvm::HexagonTargetLowering::PerformDAGCombine(),llvm::PPCTargetLowering::PerformDAGCombine(),llvm::RISCVTargetLowering::PerformDAGCombine(),performDivRemCombine(),performDSPShiftCombine(),performDUPCombine(),performDupLane128Combine(),performExtBinopLoadFold(),PerformExtendCombine(),performExtendCombine(),PerformEXTRACTCombine(),PerformExtractEltCombine(),PerformExtractEltToVMOVRRD(),performExtractSubvectorCombine(),performExtractVectorEltCombine(),llvm::AMDGPUTargetLowering::performFAbsCombine(),performFADDCombine(),PerformFADDCombineWithOperands(),PerformFADDVCMLACombine(),PerformFAddVSelectCombine(),performFlagSettingCombine(),llvm::AMDGPUTargetLowering::performFNegCombine(),performFP_TO_INT_SATCombine(),performFP_TO_INTCombine(),performFPExtendCombine(),performFpToIntCombine(),performGatherLoadCombine(),performGLD1Combine(),performGlobalAddressCombine(),PerformHWLoopCombine(),performINSERT_VECTOR_ELTCombine(),PerformInsertEltCombine(),PerformInsertSubvectorCombine(),performInsertSubvectorCombine(),performINTRINSIC_WO_CHAINCombine(),llvm::ARMTargetLowering::PerformIntrinsicCombine(),performIntrinsicCombine(),performIntToFpCombine(),performLD1Combine(),performLD1ReplicateCombine(),performLDNT1Combine(),llvm::AMDGPUTargetLowering::performLoadCombine(),performLOADCombine(),PerformLongShiftCombine(),performMADD_MSUBCombine(),PerformMinMaxCombine(),PerformMinMaxFpToSatCombine(),PerformMinMaxToSatCombine(),llvm::AMDGPUTargetLowering::performMulCombine(),performMulCombine(),performMULCombine(),PerformMULCombine(),llvm::AMDGPUTargetLowering::performMulhsCombine(),llvm::AMDGPUTargetLowering::performMulhuCombine(),llvm::AMDGPUTargetLowering::performMulLoHiCombine(),performMulVectorCmpZeroCombine(),performMulVectorExtendCombine(),llvm::ARMTargetLowering::PerformMVEExtCombine(),llvm::ARMTargetLowering::PerformMVETruncCombine(),PerformMVEVMULLCombine(),performNegCSelCombine(),performNVCASTCombine(),performORCombine(),PerformORCombine(),PerformORCombine_i1(),PerformORCombineToBFI(),PerformORCombineToSMULWBT(),performOrXorChainCombine(),PerformPREDICATE_CASTCombine(),PerformReduceShuffleCombine(),PerformREMCombine(),performScalarToVectorCombine(),performScatterStoreCombine(),llvm::AMDGPUTargetLowering::performSelectCombine(),performSELECTCombine(),performSelectCombine(),PerformSELECTCombine(),performSetccAddFolding(),performSETCCCombine(),PerformSETCCCombine(),performSetccMergeZeroCombine(),PerformShiftCombine(),llvm::AMDGPUTargetLowering::performShlCombine(),performSHLCombine(),PerformSHLSimplify(),PerformShuffleVMOVNCombine(),performSIGN_EXTEND_INREGCombine(),PerformSignExtendInregCombine(),performSignExtendInRegCombine(),performSignExtendSetCCCombine(),PerformSplittingMVEEXTToWideningLoad(),PerformSplittingMVETruncToNarrowingStores(),PerformSplittingToNarrowingStores(),PerformSplittingToWideningLoad(),llvm::AMDGPUTargetLowering::performSraCombine(),performSRACombine(),llvm::AMDGPUTargetLowering::performSrlCombine(),performSRLCombine(),performST1Combine(),performSTNT1Combine(),llvm::AMDGPUTargetLowering::performStoreCombine(),PerformSTORECombine(),performSubAddMULCombine(),performSUBCombine(),PerformSUBCombine(),PerformSubCSINCCombine(),performSubsToAndsCombine(),performSunpkloCombine(),performSVEAndCombine(),performSVEMulAddSubCombine(),performTBZCombine(),llvm::AMDGPUTargetLowering::performTruncateCombine(),performTRUNCATECombine(),performTruncateCombine(),PerformTruncatingStoreCombine(),performUADDVAddCombine(),performUADDVCombine(),performUADDVZextCombine(),PerformUMinFpToSatCombine(),PerformUMLALCombine(),performUzpCombine(),PerformVCMPCombine(),PerformVCVTCombine(),PerformVDUPCombine(),PerformVDUPLANECombine(),PerformVECREDUCE_ADDCombine(),performVecReduceAddCombine(),performVecReduceAddCombineWithUADDLP(),PerformVECTOR_REG_CASTCombine(),PerformVECTOR_SHUFFLECombine(),performVECTOR_SHUFFLECombine(),performVectorCompareAndMaskUnaryOpCombine(),performVectorExtCombine(),performVectorExtendCombine(),performVectorExtendToFPCombine(),performVectorTruncZeroCombine(),PerformVMOVDRRCombine(),PerformVMOVhrCombine(),PerformVMOVNCombine(),PerformVMOVrhCombine(),PerformVMOVRRDCombine(),PerformVMULCombine(),PerformVMulVCTPCombine(),performVP_REVERSECombine(),performVP_STORECombine(),PerformVQDMULHCombine(),performVSelectCombine(),performVSELECTCombine(),PerformVSELECTCombine(),PerformVSetCCToVCTPCombine(),performXORCombine(),PerformXORCombine(),performZExtDeinterleaveShuffleCombine(),performZExtUZPCombine(),prepareDescriptorIndirectCall(),prepareIndirectCall(),PrepareTailCall(),prepareTS1AM(),llvm::RISCVDAGToDAGISel::PreprocessISelDAG(),PromoteBinOpToF32(),promoteExtBeforeAdd(),PromoteMaskArithmetic(),PromoteMVEPredVector(),llvm::TargetLoweringBase::promoteTargetBoolean(),promoteToConstantPool(),promoteVCIXScalar(),promoteXINT_TO_FP(),pushAddIntoCmovOfConsts(),reassociateCSELOperandsForCSE(),llvm::AArch64TargetLowering::ReconstructShuffle(),ReconstructShuffleWithRuntimeMask(),ReconstructTruncateFromBuildVector(),recoverFramePointer(),reduceMaskedLoadToScalarLoad(),reduceMaskedStoreToScalarStore(),reduceVMULWidth(),refineUniformBase(),ReorganizeVector(),ReplaceAddWithADDP(),ReplaceAllUsesWith(),ReplaceATOMIC_LOAD_128Results(),ReplaceBITCAST(),ReplaceCMP_SWAP_128Results(),ReplaceCMP_SWAP_64Results(),replaceCMP_XCHG_128Results(),ReplaceCopyFromReg_128(),replaceInChain(),ReplaceINTRINSIC_W_CHAIN(),ReplaceLoadVector(),ReplaceLongIntrinsic(),llvm::SITargetLowering::ReplaceNodeResults(),llvm::AVRTargetLowering::ReplaceNodeResults(),llvm::LoongArchTargetLowering::ReplaceNodeResults(),llvm::PPCTargetLowering::ReplaceNodeResults(),llvm::RISCVTargetLowering::ReplaceNodeResults(),llvm::SparcTargetLowering::ReplaceNodeResults(),llvm::X86TargetLowering::ReplaceNodeResults(),ReplaceREADCYCLECOUNTER(),ReplaceReductionResults(),replaceShuffleOfInsert(),replaceVecCondBranchResults(),replaceVPICKVE2GRResults(),resolveSources(),SaturateWidenedDIVFIX(),scalarizeBinOpOfSplats(),scalarizeExtEltFP(),scalarizeExtractedBinOp(),llvm::TargetLowering::scalarizeVectorLoad(),llvm::TargetLowering::scalarizeVectorStore(),scalarizeVectorStore(),llvm::HexagonDAGToDAGISel::SelectIntrinsicWOChain(),llvm::TargetLowering::ShrinkDemandedConstant(),llvm::TargetLowering::ShrinkDemandedOp(),ShrinkLoadReplaceStoreWithStore(),signExtendBitcastSrcVector(),llvm::TargetLowering::SimplifyDemandedBits(),llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(),llvm::ARMTargetLowering::SimplifyDemandedBitsForTargetNode(),llvm::TargetLowering::SimplifyDemandedVectorElts(),llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(),simplifyMul24(),llvm::TargetLowering::SimplifySetCC(),simplifySetCCIntoEq(),simplifySetCCWithCTPOP(),skipExtensionForVectorMULL(),SkipExtensionForVMULL(),llvm::TargetLowering::softenSetCCOperands(),splatPartsI64WithVL(),llvm::AMDGPUTargetLowering::split64BitValue(),SplitAndExtendv16i1(),splitAndLowerShuffle(),llvm::AMDGPUTargetLowering::splitBinaryBitConstantOpImpl(),llvm::SITargetLowering::splitBinaryVectorOp(),SplitEVL(),SplitOpsAndApply(),SplitScalar(),splitStores(),splitStoreSplat(),SplitStrictFPVectorOp(),llvm::SITargetLowering::splitTernaryVectorOp(),llvm::SITargetLowering::splitUnaryVectorOp(),llvm::PPCTargetLowering::splitValueIntoRegisterParts(),llvm::RISCVTargetLowering::splitValueIntoRegisterParts(),llvm::AMDGPUTargetLowering::splitVector(),SplitVector(),llvm::AMDGPUTargetLowering::SplitVectorLoad(),SplitVectorOp(),splitVectorOp(),SplitVectorReductionOp(),llvm::AMDGPUTargetLowering::SplitVectorStore(),splitVectorStore(),SplitVPOp(),splitVSETCC(),llvm::AMDGPUTargetLowering::storeStackInputValue(),stripModuloOnShift(),takeInexpensiveLog2(),llvm::ARMTargetLowering::targetShrinkDemandedConstant(),llvm::RISCVTargetLowering::targetShrinkDemandedConstant(),llvm::X86TargetLowering::targetShrinkDemandedConstant(),transformAddImmMulImm(),transformAddShlImm(),translateSetCCForBranch(),truncateAVX512SetCCNoBWI(),truncateScalarIntegerArg(),truncateVecElts(),truncateVectorWithNARROW(),truncateVectorWithPACK(),truncateVectorWithPACKSS(),tryAdvSIMDModImm16(),tryAdvSIMDModImm32(),tryAdvSIMDModImm321s(),tryAdvSIMDModImm64(),tryAdvSIMDModImm8(),tryAdvSIMDModImmFP(),TryCombineBaseUpdate(),tryCombineCRC32(),tryCombineExtendRShTrunc(),tryCombineFixedPointConvert(),tryCombineLongOpWithDup(),tryCombineMULLWithUZP1(),tryCombineShiftImm(),tryCombineToBSL(),tryCombineWhileLo(),tryConvertSVEWideCompare(),tryDemorganOfBooleanCondition(),TryDistrubutionADDVecReduce(),tryExtendDUPToExtractHigh(),tryFoldMADwithSRL(),tryFoldSelectIntoOp(),tryFormConcatFromShuffle(),tryLowerPartialReductionToDot(),tryLowerPartialReductionToWideAdd(),tryLowerToSLI(),TryMULWIDECombine(),trySimplifySrlAddToRshrnb(),trySwapVSelectOperands(),tryToConvertShuffleOfTbl2ToTbl4(),tryToFoldExtendOfConstant(),tryToFoldExtendSelectLoad(),tryToFoldExtOfAtomicLoad(),tryToFoldExtOfLoad(),tryToFoldExtOfMaskedLoad(),tryToReplaceScalarFPConversionWithSVE(),tryToWidenSetCCOperands(),unpack64(),unpackF64OnRV32DSoftABI(),UnpackFromArgumentSlot(),UnrollVectorOp(),UnrollVectorOverflowOp(),unrollVectorShift(),valueToCarryFlag(),vectorizeExtractedCast(),vectorToScalarBitmask(),llvm::SelectionDAGBuilder::visitBitTestCase(),llvm::SelectionDAGBuilder::visitBitTestHeader(),llvm::SelectionDAGBuilder::visitJumpTable(),llvm::SelectionDAGBuilder::visitJumpTableHeader(),visitORCommutative(),llvm::SelectionDAGBuilder::visitSPDescriptorFailure(),llvm::SelectionDAGBuilder::visitSPDescriptorParent(),llvm::SelectionDAGBuilder::visitSwitchCase(),widenAbs(),widenCtPop(),llvm::AMDGPUTargetLowering::WidenOrSplitVectorLoad(),widenSubVector(),widenVec(),WidenVector(),WidenVector(),widenVectorOpsToi8(),widenVectorToPartType(), andWinDBZCheckDenominator().
Definition at line10343 of fileSelectionDAG.cpp.
ReferencesDL,llvm::SelectionDAG::FlagInserter::getFlags(), andgetNode().
SDValue SelectionDAG::getNode | ( | unsigned | Opcode, |
constSDLoc & | DL, | ||
EVT | VT, | ||
ArrayRef<SDValue > | Ops, | ||
constSDNodeFlags | Flags | ||
) |
Definition at line10351 of fileSelectionDAG.cpp.
ReferencesAddNodeIDNode(),assert(),llvm::ISD::BR_CC,llvm::ISD::BUILD_VECTOR,llvm::ISD::CONCAT_VECTORS,llvm::ISD::DELETED_NODE,DL,FoldBUILD_VECTOR(),foldCONCAT_VECTORS(),getNode(),getValueType(),llvm::EVT::getVectorElementCount(),llvm::EVT::getVectorElementType(),getVTList(),llvm::EVT::isVector(),N,NewSDValueDbgMsg(),llvm::ISD::SELECT_CC, andllvm::ArrayRef< T >::size().
Definition at line7209 of fileSelectionDAG.cpp.
ReferencesDL,llvm::SelectionDAG::FlagInserter::getFlags(), andgetNode().
SDValue SelectionDAG::getNode | ( | unsigned | Opcode, |
constSDLoc & | DL, | ||
EVT | VT, | ||
SDValue | N1, | ||
SDValue | N2, | ||
constSDNodeFlags | Flags | ||
) |
Definition at line7238 of fileSelectionDAG.cpp.
Referencesllvm::ISD::ABDS,llvm::ISD::ABDU,llvm::ISD::ADD,AddNodeIDNode(),llvm::ISD::AND,assert(),llvm::ISD::AssertSext,llvm::ISD::AssertZext,llvm::ISD::AVGCEILS,llvm::ISD::AVGCEILU,llvm::ISD::AVGFLOORS,llvm::ISD::AVGFLOORU,llvm::EVT::bitsLE(),llvm::ISD::BUILD_PAIR,llvm::ISD::BUILD_VECTOR,canonicalizeCommutativeBinop(),llvm::ISD::CONCAT_VECTORS,llvm::ISD::DELETED_NODE,DL,llvm::ISD::EntryToken,llvm::ISD::EXTRACT_ELEMENT,llvm::ISD::EXTRACT_SUBVECTOR,llvm::ISD::EXTRACT_VECTOR_ELT,llvm::APInt::extractBits(),llvm::ISD::FADD,llvm::ISD::FCOPYSIGN,llvm::ISD::FDIV,llvm::ISD::FMUL,FoldBUILD_VECTOR(),foldCONCAT_VECTORS(),FoldConstantArithmetic(),llvm::ISD::FP_ROUND,llvm::ISD::FP_TO_SINT_SAT,llvm::ISD::FP_TO_UINT_SAT,llvm::ISD::FREM,llvm::ISD::FSUB,getAllOnesConstant(),getAnyExtOrTrunc(),getConstant(),llvm::SDNode::getConstantOperandAPInt(),getDataLayout(),getFPExtendOrRound(),getNode(),getNOT(),llvm::SDValue::getOpcode(),llvm::SDValue::getOperand(),llvm::EVT::getScalarSizeInBits(),llvm::EVT::getScalarType(),getSExtOrTrunc(),llvm::EVT::getSizeInBits(),getUNDEF(),llvm::SDValue::getValueType(),llvm::EVT::getVectorElementCount(),llvm::EVT::getVectorElementType(),getVectorIdxConstant(),llvm::TargetLoweringBase::getVectorIdxTy(),llvm::EVT::getVectorMinNumElements(),llvm::EVT::getVectorNumElements(),getVScale(),getVTList(),llvm::ConstantSDNode::getZExtValue(),llvm::ISD::INSERT_SUBVECTOR,llvm::ISD::INSERT_VECTOR_ELT,llvm::ConstantSDNode::isAllOnes(),llvm::TargetLoweringBase::isCommutativeBinOp(),llvm::isConstOrConstSplat(),llvm::EVT::isFixedLengthVector(),llvm::EVT::isFloatingPoint(),llvm::EVT::isInteger(),llvm::EVT::isScalableVector(),llvm::SDValue::isUndef(),llvm::EVT::isVector(),llvm::ConstantSDNode::isZero(),llvm::Log2_32_Ceil(),llvm::ISD::MUL,llvm::ISD::MULHS,llvm::ISD::MULHU,N,NewSDValueDbgMsg(),llvm::ISD::OR,llvm::ISD::ROTL,llvm::ISD::ROTR,llvm::ISD::SADDSAT,llvm::ISD::SCMP,llvm::ISD::SDIV,llvm::ISD::SHL,llvm::ISD::SIGN_EXTEND_INREG,simplifyFPBinop(),simplifyShift(),llvm::ISD::SMAX,llvm::ISD::SMIN,llvm::ISD::SPLAT_VECTOR,llvm::ISD::SRA,llvm::ISD::SREM,llvm::ISD::SRL,llvm::ISD::SSUBSAT,llvm::ISD::SUB,std::swap(),llvm::ISD::TargetConstant,llvm::ISD::TokenFactor,llvm::ISD::UADDSAT,llvm::ISD::UCMP,llvm::ISD::UDIV,llvm::ISD::UMAX,llvm::ISD::UMIN,llvm::ISD::UREM,llvm::ISD::USUBSAT,llvm::ISD::VSCALE, andllvm::ISD::XOR.
SDValue SelectionDAG::getNode | ( | unsigned | Opcode, |
constSDLoc & | DL, | ||
EVT | VT, | ||
SDValue | N1, | ||
SDValue | N2, | ||
SDValue | N3 | ||
) |
Definition at line7717 of fileSelectionDAG.cpp.
ReferencesDL,llvm::SelectionDAG::FlagInserter::getFlags(), andgetNode().
SDValue SelectionDAG::getNode | ( | unsigned | Opcode, |
constSDLoc & | DL, | ||
EVT | VT, | ||
SDValue | N1, | ||
SDValue | N2, | ||
SDValue | N3, | ||
constSDNodeFlags | Flags | ||
) |
Definition at line7725 of fileSelectionDAG.cpp.
Referencesllvm::APFloat::add(),AddNodeIDNode(),assert(),llvm::ISD::BITCAST,llvm::ISD::BUILD_VECTOR,llvm::ISD::CONCAT_VECTORS,llvm::ISD::DELETED_NODE,DL,llvm::ISD::EXTRACT_SUBVECTOR,llvm::ISD::FMA,llvm::ISD::FMAD,FoldBUILD_VECTOR(),foldCONCAT_VECTORS(),FoldConstantArithmetic(),FoldSetCC(),llvm::APFloat::fusedMultiplyAdd(),llvm::get(),llvm::SDNode::getAsAPIntVal(),llvm::SDNode::getAsZExtVal(),llvm::APInt::getBitWidth(),getConstantFP(),getDataLayout(),llvm::SDValue::getOpcode(),llvm::SDValue::getOperand(),getUNDEF(),llvm::ConstantFPSDNode::getValueAPF(),llvm::SDValue::getValueType(),llvm::EVT::getVectorElementCount(),llvm::EVT::getVectorElementType(),llvm::TargetLoweringBase::getVectorIdxTy(),llvm::EVT::getVectorMinNumElements(),llvm::EVT::getVectorNumElements(),getVTList(),llvm::ConstantSDNode::getZExtValue(),llvm::ISD::INSERT_SUBVECTOR,llvm::ISD::INSERT_VECTOR_ELT,llvm::EVT::isFixedLengthVector(),llvm::EVT::isFloatingPoint(),llvm::EVT::isInteger(),llvm::EVT::isScalableVector(),llvm::SDValue::isUndef(),llvm::EVT::isVector(),isZero(),llvm_unreachable,llvm::APFloat::multiply(),N,NewSDValueDbgMsg(),llvm::APFloatBase::rmNearestTiesToEven,llvm::ISD::SELECT,llvm::ISD::SETCC,simplifySelect(),llvm::ISD::VECTOR_COMPRESS,llvm::ISD::VECTOR_SHUFFLE,llvm::ISD::VECTOR_SPLICE, andllvm::ISD::VSELECT.
SDValue SelectionDAG::getNode | ( | unsigned | Opcode, |
constSDLoc & | DL, | ||
EVT | VT, | ||
SDValue | N1, | ||
SDValue | N2, | ||
SDValue | N3, | ||
SDValue | N4 | ||
) |
Definition at line7922 of fileSelectionDAG.cpp.
ReferencesDL,llvm::SelectionDAG::FlagInserter::getFlags(), andgetNode().
SDValue SelectionDAG::getNode | ( | unsigned | Opcode, |
constSDLoc & | DL, | ||
EVT | VT, | ||
SDValue | N1, | ||
SDValue | N2, | ||
SDValue | N3, | ||
SDValue | N4, | ||
constSDNodeFlags | Flags | ||
) |
Definition at line7915 of fileSelectionDAG.cpp.
SDValue SelectionDAG::getNode | ( | unsigned | Opcode, |
constSDLoc & | DL, | ||
EVT | VT, | ||
SDValue | N1, | ||
SDValue | N2, | ||
SDValue | N3, | ||
SDValue | N4, | ||
SDValue | N5 | ||
) |
Definition at line7937 of fileSelectionDAG.cpp.
ReferencesDL,llvm::SelectionDAG::FlagInserter::getFlags(), andgetNode().
SDValue SelectionDAG::getNode | ( | unsigned | Opcode, |
constSDLoc & | DL, | ||
EVT | VT, | ||
SDValue | N1, | ||
SDValue | N2, | ||
SDValue | N3, | ||
SDValue | N4, | ||
SDValue | N5, | ||
constSDNodeFlags | Flags | ||
) |
Definition at line7930 of fileSelectionDAG.cpp.
Definition at line6198 of fileSelectionDAG.cpp.
ReferencesDL,llvm::SelectionDAG::FlagInserter::getFlags(), andgetNode().
SDValue SelectionDAG::getNode | ( | unsigned | Opcode, |
constSDLoc & | DL, | ||
EVT | VT, | ||
SDValue | Operand, | ||
constSDNodeFlags | Flags | ||
) |
Definition at line6206 of fileSelectionDAG.cpp.
Referencesllvm::ISD::ABS,AddNodeIDNode(),llvm::ISD::AND,llvm::ISD::ANY_EXTEND,llvm::ISD::ANY_EXTEND_VECTOR_INREG,assert(),llvm::ISD::BF16_TO_FP,llvm::ISD::BITCAST,llvm::ISD::BITREVERSE,llvm::EVT::bitsGT(),llvm::EVT::bitsLE(),llvm::EVT::bitsLT(),llvm::ISD::BSWAP,llvm::ISD::BUILD_VECTOR,llvm::ISD::CONCAT_VECTORS,llvm::ISD::CTLZ,llvm::ISD::CTLZ_ZERO_UNDEF,llvm::ISD::CTPOP,llvm::ISD::CTTZ,llvm::ISD::CTTZ_ZERO_UNDEF,llvm::ISD::DELETED_NODE,DL,llvm::ISD::EXTRACT_VECTOR_ELT,llvm::ISD::FABS,llvm::ISD::FCEIL,llvm::ISD::FFLOOR,llvm::ISD::FNEG,FoldBUILD_VECTOR(),FoldConstantArithmetic(),llvm::ISD::FP16_TO_FP,llvm::ISD::FP_EXTEND,llvm::ISD::FP_ROUND,llvm::ISD::FP_TO_BF16,llvm::ISD::FP_TO_FP16,llvm::ISD::FP_TO_SINT,llvm::ISD::FP_TO_UINT,llvm::ISD::FREEZE,llvm::ISD::FTRUNC,llvm::APInt::getBitsSetFrom(),getConstant(),getConstantFP(),llvm::SDValue::getConstantOperandAPInt(),llvm::SDValue::getConstantOperandVal(),llvm::SDNode::getFlags(),llvm::SDValue::getNode(),getNode(),getNOT(),llvm::SDValue::getOpcode(),llvm::SDNode::getOpcode(),llvm::SDValue::getOperand(),llvm::EVT::getScalarSizeInBits(),llvm::EVT::getScalarType(),llvm::SDValue::getScalarValueSizeInBits(),llvm::EVT::getSizeInBits(),getUNDEF(),llvm::SDValue::getValueSizeInBits(),llvm::SDValue::getValueType(),llvm::EVT::getVectorElementCount(),llvm::EVT::getVectorElementType(),llvm::EVT::getVectorMinNumElements(),getVScale(),getVTList(),llvm::SDNodeFlags::hasNonNeg(),llvm::EVT::isFloatingPoint(),isGuaranteedNotToBeUndefOrPoison(),llvm::EVT::isInteger(),llvm::EVT::isScalableVector(),llvm::SDValue::isUndef(),llvm::EVT::isVector(),llvm_unreachable,MaskedValueIsZero(),llvm::ISD::MERGE_VALUES,N,NewNodesMustHaveLegalTypes,NewSDValueDbgMsg(),llvm::ISD::SCALAR_TO_VECTOR,llvm::ISD::SIGN_EXTEND,llvm::ISD::SIGN_EXTEND_VECTOR_INREG,llvm::ISD::SINT_TO_FP,llvm::ISD::SPLAT_VECTOR,llvm::ISD::STEP_VECTOR,llvm::ISD::TargetConstant,llvm::ISD::TokenFactor,transferDbgValues(),llvm::APInt::trunc(),llvm::ISD::TRUNCATE,llvm::ISD::UINT_TO_FP,llvm::ISD::UNDEF,llvm::ISD::VECREDUCE_ADD,llvm::ISD::VECREDUCE_AND,llvm::ISD::VECREDUCE_OR,llvm::ISD::VECREDUCE_SMAX,llvm::ISD::VECREDUCE_SMIN,llvm::ISD::VECREDUCE_UMAX,llvm::ISD::VECREDUCE_UMIN,llvm::ISD::VECREDUCE_XOR,llvm::ISD::VSCALE,llvm::ISD::ZERO_EXTEND, andllvm::ISD::ZERO_EXTEND_VECTOR_INREG.
Definition at line10672 of fileSelectionDAG.cpp.
SDValue SelectionDAG::getNode | ( | unsigned | Opcode, |
constSDLoc & | DL, | ||
SDVTList | VTList, | ||
ArrayRef<SDValue > | Ops | ||
) |
Definition at line10470 of fileSelectionDAG.cpp.
ReferencesDL,llvm::SelectionDAG::FlagInserter::getFlags(), andgetNode().
SDValue SelectionDAG::getNode | ( | unsigned | Opcode, |
constSDLoc & | DL, | ||
SDVTList | VTList, | ||
ArrayRef<SDValue > | Ops, | ||
constSDNodeFlags | Flags | ||
) |
Definition at line10478 of fileSelectionDAG.cpp.
ReferencesAddNodeIDNode(),llvm::ISD::AND,assert(),llvm::EVT::bitsLT(),llvm::CallingConv::C,canonicalizeCommutativeBinop(),llvm::ISD::DELETED_NODE,DL,llvm::APInt::extractBits(),llvm::ISD::FFREXP,llvm::frexp(),getConstant(),getConstantFP(),getFreeze(),getNode(),getNOT(),llvm::EVT::getScalarSizeInBits(),getValueType(),llvm::EVT::getVectorElementCount(),llvm::EVT::getVectorElementType(),llvm::Hi,llvm::isConstOrConstSplat(),llvm::APFloat::isFinite(),llvm::EVT::isFloatingPoint(),llvm::EVT::isInteger(),llvm::EVT::isVector(),llvm::ConstantSDNode::isZero(),LHS,llvm::Lo,llvm::ISD::MERGE_VALUES,llvm::Mul,N,NewSDValueDbgMsg(),llvm::SDVTList::NumVTs,RHS,llvm::APFloatBase::rmNearestTiesToEven,llvm::ISD::SADDO,llvm::ISD::SADDO_CARRY,llvm::APInt::sext(),llvm::ISD::SHL_PARTS,llvm::ISD::SIGN_EXTEND_INREG,llvm::ArrayRef< T >::size(),llvm::ISD::SMUL_LOHI,llvm::ISD::SRA_PARTS,llvm::ISD::SRL_PARTS,llvm::ISD::SSUBO,llvm::ISD::SSUBO_CARRY,llvm::ISD::STRICT_FP_EXTEND,llvm::ISD::STRICT_FP_ROUND,llvm::ISD::TargetConstant,llvm::APInt::trunc(),llvm::ISD::UADDO,llvm::ISD::UADDO_CARRY,llvm::ISD::UMUL_LOHI,llvm::ISD::USUBO,llvm::ISD::USUBO_CARRY,llvm::SDVTList::VTs,llvm::ISD::XOR, andllvm::APInt::zext().
Definition at line10677 of fileSelectionDAG.cpp.
SDValue SelectionDAG::getNode | ( | unsigned | Opcode, |
constSDLoc & | DL, | ||
SDVTList | VTList, | ||
SDValue | N1, | ||
SDValue | N2 | ||
) |
Definition at line10683 of fileSelectionDAG.cpp.
SDValue SelectionDAG::getNode | ( | unsigned | Opcode, |
constSDLoc & | DL, | ||
SDVTList | VTList, | ||
SDValue | N1, | ||
SDValue | N2, | ||
SDValue | N3 | ||
) |
Definition at line10689 of fileSelectionDAG.cpp.
SDValue SelectionDAG::getNode | ( | unsigned | Opcode, |
constSDLoc & | DL, | ||
SDVTList | VTList, | ||
SDValue | N1, | ||
SDValue | N2, | ||
SDValue | N3, | ||
SDValue | N4 | ||
) |
Definition at line10695 of fileSelectionDAG.cpp.
SDValue SelectionDAG::getNode | ( | unsigned | Opcode, |
constSDLoc & | DL, | ||
SDVTList | VTList, | ||
SDValue | N1, | ||
SDValue | N2, | ||
SDValue | N3, | ||
SDValue | N4, | ||
SDValue | N5 | ||
) |
Definition at line10701 of fileSelectionDAG.cpp.
getNodeIfExists - Get the specified node if it's already available, or else return NULL.
Definition at line11287 of fileSelectionDAG.cpp.
Referencesllvm::SelectionDAG::FlagInserter::getFlags(), andgetNodeIfExists().
SDNode * SelectionDAG::getNodeIfExists | ( | unsigned | Opcode, |
SDVTList | VTList, | ||
ArrayRef<SDValue > | Ops, | ||
constSDNodeFlags | Flags | ||
) |
Get the specified node if it's already available, or else return NULL.
Definition at line11295 of fileSelectionDAG.cpp.
ReferencesAddNodeIDNode(),llvm::SDVTList::NumVTs, andllvm::SDVTList::VTs.
Referenced bycombineBitcastToBoolVector(),combineSetCC(),combineX86AddSub(),getInvertedVectorForFMA(),getNodeIfExists(),performDUPCombine(),PerformExtractFpToIntStores(),performFlagSettingCombine(), andtryToWidenSetCCOperands().
Return NoMerge info associated withNode.
Definition at line2399 of fileSelectionDAG.h.
Referencesllvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::end(),llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::find(), andI.
Referenced byllvm::ScheduleDAGSDNodes::EmitSchedule().
Create a bitwise NOT operation as (XOR Val, -1).
getNOT - Create a bitwise NOT operation as (XOR Val, -1).
Definition at line1622 of fileSelectionDAG.cpp.
ReferencesDL,getAllOnesConstant(),getNode(), andllvm::ISD::XOR.
Referenced bycombineAndNotOrIntoAndNotAnd(),combineAndnp(),combineMOVMSK(),combineSelect(),combineSelectOfTwoConstants(),combineSetCC(),combineSub(),combineVectorPack(),combineVSelectWithAllOnesOrZeros(),combineXor(),EmitVectorComparison(),llvm::TargetLowering::expandAddSubSat(),llvm::TargetLowering::expandCTLZ(),llvm::TargetLowering::expandCTTZ(),llvm::TargetLowering::expandFunnelShift(),foldAndOrOfSETCC(),foldExtendedSignBitTest(),foldVSelectToSignBitSplatMask(),llvm::VECustomDAG::getConstantMask(),getDataClassTest(),getI128Select(),getNode(),llvm::TargetLowering::LegalizeSetCCCondCode(),llvm::AMDGPUTargetLowering::LowerFTRUNC(),lowerMSABitClear(),LowerVectorAllEqual(),lowerVectorBitClear(),LowerVSETCC(),performBSPExpandForSVE(),performConcatVectorsCombine(),performINTRINSIC_WO_CHAINCombine(),performSETCCCombine(),performXORCombine(),llvm::TargetLowering::SimplifyDemandedBits(),llvm::TargetLowering::SimplifySetCC(), andvisitORCommutative().
Definition at line1085 of fileSelectionDAG.h.
ReferencesgetMemBasePlusOffset(),llvm::SDNodeFlags::NoUnsignedWrap,llvm::Offset, andPtr.
Create an add instruction with appropriate flags when used for addressing some offset of an object.
i.e. if a load is split into multiple components, create an add nuw from the base pointer to the offset.
Definition at line1081 of fileSelectionDAG.h.
ReferencesgetMemBasePlusOffset(),llvm::SDNodeFlags::NoUnsignedWrap,llvm::Offset, andPtr.
Referenced byllvm::TargetLowering::expandUnalignedLoad(),llvm::TargetLowering::expandUnalignedStore(),PerformSplittingMVEEXTToWideningLoad(),PerformSplittingMVETruncToNarrowingStores(),PerformSplittingToNarrowingStores(),PerformSplittingToWideningLoad(),llvm::TargetLowering::scalarizeVectorLoad(),llvm::TargetLowering::scalarizeVectorStore(),llvm::TargetLowering::SimplifySetCC(),llvm::AMDGPUTargetLowering::SplitVectorLoad(), andllvm::AMDGPUTargetLowering::SplitVectorStore().
Convert *_EXTEND_VECTOR_INREG to *_EXTEND opcode.
Definition at line937 of fileSelectionDAG.h.
Referencesllvm::ISD::ANY_EXTEND,llvm::ISD::ANY_EXTEND_VECTOR_INREG,llvm_unreachable,llvm::ISD::SIGN_EXTEND,llvm::ISD::SIGN_EXTEND_VECTOR_INREG,llvm::ISD::ZERO_EXTEND, andllvm::ISD::ZERO_EXTEND_VECTOR_INREG.
Referenced bycombineEXTEND_VECTOR_INREG(), andfoldExtendVectorInregToExtendOfSubvector().
Convert *_EXTEND to *_EXTEND_VECTOR_INREG opcode.
Definition at line953 of fileSelectionDAG.h.
Referencesllvm::ISD::ANY_EXTEND,llvm::ISD::ANY_EXTEND_VECTOR_INREG,llvm_unreachable,llvm::ISD::SIGN_EXTEND,llvm::ISD::SIGN_EXTEND_VECTOR_INREG,llvm::ISD::ZERO_EXTEND, andllvm::ISD::ZERO_EXTEND_VECTOR_INREG.
Referenced bycombineEXTRACT_SUBVECTOR(),getEXTEND_VECTOR_INREG(),LowerAVXExtend(), andmatchUnaryShuffle().
| inline |
Definition at line496 of fileSelectionDAG.h.
Referenced byllvm::FunctionLoweringInfo::set().
| inline |
Definition at line511 of fileSelectionDAG.h.
Create the DAG equivalent of vector_partial_reduce where Op1 and Op2 are its operands and ReducedTY is the intrinsic's return type.
Definition at line2476 of fileSelectionDAG.cpp.
Referencesllvm::ISD::ADD,assert(),DL,llvm::ISD::EXTRACT_SUBVECTOR,getNode(),llvm::SDValue::getValueType(),getVectorIdxConstant(),llvm::EVT::getVectorMinNumElements(), andI.
Referenced byperformIntrinsicCombine().
Definition at line493 of fileSelectionDAG.h.
Referenced byllvm::SITargetLowering::LowerFormalArguments(), andllvm::SITargetLowering::passSpecialInputs().
Return PCSections associated withNode, or nullptr if none exists.
Definition at line2371 of fileSelectionDAG.h.
Referencesllvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::end(), andllvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::find().
Referenced byllvm::ScheduleDAGSDNodes::EmitSchedule().
SDValue SelectionDAG::getPseudoProbeNode | ( | constSDLoc & | Dl, |
SDValue | Chain, | ||
uint64_t | Guid, | ||
uint64_t | Index, | ||
uint32_t | Attr | ||
) |
Creates aPseudoProbeSDNode with function GUIDGuid
and the index of the blockIndex
it is probing, as well as the attributesattr
of the probe.
Definition at line9133 of fileSelectionDAG.cpp.
ReferencesAddNodeIDNode(),llvm::SDLoc::getDebugLoc(),llvm::SDLoc::getIROrder(),getVTList(),llvm::Guid,N,NewSDValueDbgMsg(), andllvm::ISD::PSEUDO_PROBE.
| inline |
Definition at line512 of fileSelectionDAG.h.
Return the expression required to extend the Op as a pointer value assuming it was the smaller SrcTy value.
This may be either a zero extend or a sign extend.
Definition at line1611 of fileSelectionDAG.cpp.
ReferencesDL, andgetZeroExtendInReg().
Convert Op, which must be of integer type, to the integer type VT, by either truncating it or performing either zero or sign extension as appropriate extension for the pointer's semantics.
Definition at line1605 of fileSelectionDAG.cpp.
ReferencesDL, andgetZExtOrTrunc().
Referenced bygetLoadStackGuard(), andllvm::SelectionDAGBuilder::visitSwitchCase().
In most cases this function returns the ABI alignment for a given type, except for illegal vector types where the alignment exceeds that of the stack.
In such cases we attempt to break the vector down to a legal type and return the ABI alignment for that instead.
Definition at line2743 of fileSelectionDAG.cpp.
ReferencesDL,getContext(),getDataLayout(),llvm::TargetSubtargetInfo::getFrameLowering(),getMachineFunction(),llvm::TargetFrameLowering::getStackAlign(),llvm::MachineFunction::getSubtarget(),llvm::EVT::getTypeForEVT(),llvm::TargetLoweringBase::getVectorTypeBreakdown(),llvm::TargetLoweringBase::isTypeLegal(), andllvm::EVT::isVector().
Referenced byllvm::TargetLowering::expandVECTOR_COMPRESS(), andllvm::TargetLowering::expandVectorSplice().
Definition at line2328 of fileSelectionDAG.cpp.
ReferencesAddNodeIDNode(),getVTList(),llvm::TargetLowering::isSDNodeSourceOfDivergence(),N, andllvm::ISD::Register.
Referenced byllvm::RegsForValue::AddInlineAsmOperands(),llvm::RISCVDAGToDAGISel::addVectorLoadStoreOperands(),buildCallOperands(),createCMovFP(),llvm::AMDGPUTargetLowering::CreateLiveInRegister(),emitLockedStackOp(),EmitUnrolledSetTag(),extractPtrauthBlendDiscriminators(),getADAEntry(),llvm::MipsTargetLowering::getAddrGPRel(),getCopyFromReg(),getCopyToReg(),getDefaultScalableVLOps(),llvm::HexagonTargetLowering::GetDynamicTLSAddr(),llvm::MipsDAGToDAGISel::getGlobalBaseReg(),llvm::MipsTargetLowering::getGlobalReg(),llvm::MipsTargetLowering::getOpndList(),getPrefetchNode(),llvm::SITargetLowering::legalizeTargetIndependentNode(),llvm::SITargetLowering::LowerCall(),llvm::SystemZTargetLowering::LowerCall(),llvm::XtensaTargetLowering::LowerCall(),llvm::HexagonTargetLowering::LowerCall(),llvm::LoongArchTargetLowering::LowerCall(),llvm::RISCVTargetLowering::LowerCall(),llvm::VETargetLowering::LowerCall(),llvm::SparcTargetLowering::LowerCall_32(),llvm::SparcTargetLowering::LowerCall_64(),lowerCallResult(),llvm::SelectionDAGBuilder::LowerCallTo(),llvm::LanaiTargetLowering::LowerConstantPool(),llvm::HexagonTargetLowering::LowerEH_RETURN(),llvm::LanaiTargetLowering::LowerGlobalAddress(),llvm::SparcTargetLowering::LowerGlobalTLSAddress(),LowerINTRINSIC_W_CHAIN(),llvm::SparcTargetLowering::LowerINTRINSIC_WO_CHAIN(),llvm::LanaiTargetLowering::LowerJumpTable(),LowerMemOpCallTo(),llvm::SITargetLowering::LowerReturn(),llvm::HexagonTargetLowering::LowerReturn(),llvm::LoongArchTargetLowering::LowerReturn(),llvm::RISCVTargetLowering::LowerReturn(),llvm::SystemZTargetLowering::LowerReturn(),llvm::VETargetLowering::LowerReturn(),llvm::XtensaTargetLowering::LowerReturn(),llvm::SparcTargetLowering::LowerReturn_32(),llvm::SparcTargetLowering::LowerReturn_64(),llvm::VETargetLowering::lowerVASTART(),LowerVASTART(),lowerVECTOR_SHUFFLE(),lowerVectorIntrinsicScalars(),llvm::PPCTargetLowering::PerformDAGCombine(),llvm::RISCVTargetLowering::PerformDAGCombine(),performNEONPostLDSTCombine(),performPostLD1Combine(),llvm::SITargetLowering::PostISelFolding(),llvm::RISCVDAGToDAGISel::PreprocessISelDAG(),llvm::RISCVDAGToDAGISel::Select(),llvm::LoongArchDAGToDAGISel::SelectAddrConstant(),llvm::PPCTargetLowering::SelectAddressRegImm(),llvm::PPCTargetLowering::SelectAddressRegImm34(),llvm::PPCTargetLowering::SelectAddressRegRegOnly(),llvm::RISCVDAGToDAGISel::SelectAddrRegRegScale(),llvm::SelectionDAGISel::SelectCodeCommon(),selectConstantAddr(),llvm::PPCTargetLowering::SelectForceXFormMode(),selectImmSeq(),llvm::PPCTargetLowering::SelectOptimalAddrMode(),llvm::RISCVDAGToDAGISel::selectShiftMask(),selectSOffset(),llvm::RISCVDAGToDAGISel::selectVSETVLI(), andsplatPartsI64WithVL().
Definition at line2344 of fileSelectionDAG.cpp.
ReferencesAddNodeIDNode(),getVTList(),N, andllvm::ISD::RegisterMask.
Referenced bybuildCallOperands(),llvm::AArch64TargetLowering::changeStreamingMode(),llvm::HexagonTargetLowering::GetDynamicTLSAddr(),llvm::MipsTargetLowering::getOpndList(),llvm::SITargetLowering::LowerCall(),llvm::SystemZTargetLowering::LowerCall(),llvm::XtensaTargetLowering::LowerCall(),llvm::HexagonTargetLowering::LowerCall(),llvm::LoongArchTargetLowering::LowerCall(),llvm::RISCVTargetLowering::LowerCall(),llvm::VETargetLowering::LowerCall(),llvm::SparcTargetLowering::LowerCall_32(),llvm::SparcTargetLowering::LowerCall_64(),llvm::SparcTargetLowering::LowerGlobalTLSAddress(), andllvm::VETargetLowering::lowerToTLSGeneralDynamicModel().
Return the root tag of theSelectionDAG.
Definition at line577 of fileSelectionDAG.h.
Referenced byllvm::checkForCycles(),dump(),expandMultipleResultFPLibCall(),llvm::ScheduleDAGSDNodes::getCustomGraphFeatures(),getMemCmpLoad(),Legalize(),llvm::SelectionDAGBuilder::LowerAsSTATEPOINT(),llvm::SelectionDAGBuilder::LowerDeoptimizingReturn(),llvm::NVPTXTargetLowering::LowerFormalArguments(),llvm::SparcTargetLowering::LowerFormalArguments_32(),llvm::AMDGPUTargetLowering::LowerGlobalAddress(),llvm::RISCVDAGToDAGISel::PostprocessISelDAG(),RemoveDeadNode(),RemoveDeadNodes(),ReplaceAllUsesOfValueWith(),ReplaceAllUsesWith(), andllvm::DAGTypeLegalizer::run().
SDValue SelectionDAG::getScatterVP | ( | SDVTList | VTs, |
EVT | VT, | ||
constSDLoc & | dl, | ||
ArrayRef<SDValue > | Ops, | ||
MachineMemOperand * | MMO, | ||
ISD::MemIndexType | IndexType | ||
) |
Definition at line9901 of fileSelectionDAG.cpp.
ReferencesAddNodeIDNode(),assert(),llvm::MachinePointerInfo::getAddrSpace(),llvm::SDLoc::getDebugLoc(),llvm::MachineMemOperand::getFlags(),llvm::SDLoc::getIROrder(),llvm::MachineMemOperand::getPointerInfo(),llvm::EVT::getRawBits(),llvm::details::FixedOrScalableQuantity< ElementCount, unsigned >::isKnownGE(),N,NewSDValueDbgMsg(), andllvm::ArrayRef< T >::size().
Referenced byllvm::RISCVTargetLowering::PerformDAGCombine().
| inline |
Helper function to make it easier to build Select's if you just have operands and don't want to check for vector.
Definition at line1280 of fileSelectionDAG.h.
Referencesassert(),Cond,DL,getNode(),LHS,RHS,llvm::ISD::SELECT, andllvm::ISD::VSELECT.
Referenced byllvm::TargetLowering::BuildUDIV(),combineAndnp(),combineConcatVectorOps(),combineFMinNumFMaxNum(),combineLogicBlendIntoPBLENDV(),combineMaskedLoadConstantMask(),combineSelect(),commuteSelect(),llvm::TargetLowering::CTTZTableLookup(),llvm::TargetLowering::expandABD(),llvm::TargetLowering::expandAddSubSat(),llvm::TargetLowering::expandCMP(),llvm::TargetLowering::expandCTLZ(),llvm::TargetLowering::expandCTTZ(),llvm::TargetLowering::expandDIVREMByConstant(),llvm::TargetLowering::expandFixedPointDiv(),llvm::TargetLowering::expandFixedPointMul(),llvm::TargetLowering::expandFMINIMUM_FMAXIMUM(),llvm::TargetLowering::expandFMINIMUMNUM_FMAXIMUMNUM(),llvm::TargetLowering::expandFP_ROUND(),llvm::TargetLowering::expandFP_TO_INT_SAT(),llvm::TargetLowering::expandFP_TO_UINT(),llvm::TargetLowering::expandIntMINMAX(),llvm::TargetLowering::expandRoundInexactToOdd(),llvm::TargetLowering::expandShlSat(),llvm::TargetLowering::expandVECTOR_COMPRESS(),llvm::TargetLowering::expandVectorFindLastActive(),foldBinOpIntoSelectIfProfitable(),foldSelectWithIdentityConstant(),llvm::TargetLowering::getNegatedExpression(),LowerADDSAT_SUBSAT(),llvm::HexagonTargetLowering::LowerBUILD_VECTOR(),LowerBUILD_VECTORvXi1(),lowerCttzElts(),lowerFMAXIMUM_FMINIMUM(),LowerFMINIMUM_FMAXIMUM(),llvm::AMDGPUTargetLowering::LowerFROUNDEVEN(),lowerINT_TO_FP_vXi64(),llvm::RISCVTargetLowering::LowerOperation(),LowerRotate(),LowerShift(),llvm::LanaiTargetLowering::LowerSHL_PARTS(),lowerShuffleAsBlend(),LowerSIGN_EXTEND_Mask(),llvm::LanaiTargetLowering::LowerSRL_PARTS(),llvm::HexagonTargetLowering::LowerVSELECT(),LowerZERO_EXTEND_Mask(),narrowExtractedVectorSelect(),PerformADDCombineWithOperands(),performSelectCombine(),llvm::X86TargetLowering::ReplaceNodeResults(),signExtendBitcastSrcVector(),takeInexpensiveLog2(),tryFoldSelectIntoOp(),tryToFoldExtendOfConstant(),tryToFoldExtendSelectLoad(),UnrollVectorOverflowOp(), anduseInversedSetcc().
| inline |
Helper function to make it easier to build SelectCC's if you just have anISD::CondCode instead of anSDValue.
Definition at line1290 of fileSelectionDAG.h.
ReferencesCond,DL,getCondCode(),getNode(),llvm::SDValue::getValueType(),LHS,RHS, andllvm::ISD::SELECT_CC.
Referenced byllvm::TargetLowering::createSelectForFMINNUM_FMAXNUM(),createVariablePermute(),llvm::TargetLowering::expandFixedPointMul(),llvm::TargetLowering::expandFMINIMUMNUM_FMAXIMUMNUM(),llvm::TargetLowering::expandFP_TO_SINT(),llvm::TargetLowering::expandMUL_LOHI(),llvm::AMDGPUTargetLowering::LowerFP_TO_FP16(),lowerFP_TO_INT_SAT(),llvm::AMDGPUTargetLowering::LowerSDIVREM(),llvm::AMDGPUTargetLowering::LowerUDIVREM64(),llvm::R600TargetLowering::PerformDAGCombine(), andperformFP_TO_INT_SATCombine().
| inline |
Definition at line505 of fileSelectionDAG.h.
Referenced bycombineCVTP2I_CVTTP2I(),combineFMA(),combineVFMADD_VLWithVFNEG_VL(),llvm::SelectionDAGISel::mayRaiseFPException(), andperformVFMADD_VLCombine().
| inline |
Helper function to make it easier to build SetCC's if you just have anISD::CondCode instead of anSDValue.
Definition at line1251 of fileSelectionDAG.h.
Referencesassert(),Cond,DL,getCondCode(),getNode(),llvm::EVT::isVector(),LHS,RHS,llvm::ISD::SETCC,llvm::ISD::SETCC_INVALID,llvm::ISD::STRICT_FSETCC, andllvm::ISD::STRICT_FSETCCS.
Referenced byllvm::TargetLowering::buildSDIVPow2WithCMov(),llvm::TargetLowering::BuildUDIV(),combineAnd(),combineBitcast(),combineExtractVectorElt(),combineExtSetcc(),combineFMinNumFMaxNum(),combineOr(),combinePredicateReduction(),combineSelect(),combineSetCC(),combineShiftAnd1ToBitTest(),combineSubOfBoolean(),combineToExtendBoolVectorInReg(),combineVectorSizedSetCCEquality(),combineVSelectWithAllOnesOrZeros(),commuteSelect(),convertIntLogicToFPLogic(),llvm::TargetLowering::CTTZTableLookup(),emitOrXorXorTree(),llvm::TargetLowering::expandABD(),llvm::TargetLowering::expandCMP(),llvm::TargetLowering::expandCTLZ(),llvm::TargetLowering::expandCTTZ(),llvm::TargetLowering::expandDIVREMByConstant(),llvm::TargetLowering::expandFixedPointDiv(),llvm::TargetLowering::expandFixedPointMul(),llvm::TargetLowering::expandFMINIMUM_FMAXIMUM(),llvm::TargetLowering::expandFMINIMUMNUM_FMAXIMUMNUM(),llvm::TargetLowering::expandFP_ROUND(),llvm::TargetLowering::expandFP_TO_INT_SAT(),llvm::TargetLowering::expandFP_TO_UINT(),llvm::TargetLowering::expandIntMINMAX(),llvm::TargetLowering::expandIS_FPCLASS(),llvm::TargetLowering::expandMULO(),llvm::TargetLowering::expandRoundInexactToOdd(),llvm::TargetLowering::expandSADDSUBO(),llvm::TargetLowering::expandShiftParts(),llvm::TargetLowering::expandShlSat(),llvm::TargetLowering::expandUADDSUBO(),llvm::TargetLowering::expandVECTOR_COMPRESS(),foldAndOrOfSETCC(),FoldSetCC(),foldSetCCWithFunnelShift(),foldSetCCWithRotate(),foldVectorXorShiftIntoCmp(),foldXorTruncShiftIntoCmp(),getDataClassTest(),llvm::AMDGPUTargetLowering::getIsFinite(),llvm::AMDGPUTargetLowering::getIsLtSmallestNormal(),llvm::VECustomDAG::getMaskBroadcast(),llvm::AMDGPUTargetLowering::getScaledLogInput(),llvm::TargetLowering::getSqrtInputTest(),llvm::TargetLowering::LegalizeSetCCCondCode(),lower1BitShuffle(),LowerADDSAT_SUBSAT(),lowerBUILD_VECTOR(),lowerCttzElts(),llvm::AMDGPUTargetLowering::LowerDIVREM24(),LowerEXTEND_VECTOR_INREG(),llvm::AMDGPUTargetLowering::LowerFCEIL(),llvm::AMDGPUTargetLowering::lowerFEXP(),llvm::AMDGPUTargetLowering::lowerFEXP10Unsafe(),llvm::AMDGPUTargetLowering::lowerFEXP2(),llvm::AMDGPUTargetLowering::lowerFEXPUnsafe(),llvm::AMDGPUTargetLowering::LowerFFLOOR(),lowerFMAXIMUM_FMINIMUM(),LowerFMINIMUM_FMAXIMUM(),llvm::HexagonTargetLowering::LowerFormalArguments(),llvm::AMDGPUTargetLowering::LowerFROUND(),llvm::AMDGPUTargetLowering::LowerFROUNDEVEN(),llvm::AMDGPUTargetLowering::LowerFTRUNC(),llvm::SITargetLowering::lowerGET_ROUNDING(),lowerINT_TO_FP_vXi64(),LowerIntVSETCC_AVX512(),LowerMULH(),LowerMULO(),llvm::RISCVTargetLowering::LowerOperation(),llvm::HexagonTargetLowering::LowerSETCC(),LowerShift(),LowerShiftByScalarImmediate(),llvm::LanaiTargetLowering::LowerSHL_PARTS(),llvm::LanaiTargetLowering::LowerSRL_PARTS(),LowerTruncateVecI1(),llvm::HexagonTargetLowering::LowerUAddSubO(),llvm::AMDGPUTargetLowering::LowerUDIVREM(),lowerVECTOR_SHUFFLE(),LowerVectorAllEqual(),LowerVectorCTLZInRegLUT(),LowerVSETCC(),llvm::RISCVTargetLowering::PerformDAGCombine(),performOrXorChainCombine(),llvm::AMDGPUTargetLowering::performSelectCombine(),performSELECTCombine(),performSETCCCombine(),performSignExtendSetCCCombine(),performVSelectCombine(),performXORCombine(),llvm::RISCVTargetLowering::ReplaceNodeResults(),llvm::X86TargetLowering::ReplaceNodeResults(),scalarizeExtractedBinOp(),llvm::TargetLowering::SimplifySetCC(),simplifySetCCWithCTPOP(),llvm::TargetLowering::softenSetCCOperands(),truncateAVX512SetCCNoBWI(),tryDemorganOfBooleanCondition(),trySwapVSelectOperands(),useInversedSetcc(),llvm::SelectionDAGBuilder::visitBitTestCase(),llvm::SelectionDAGBuilder::visitBitTestHeader(),llvm::SelectionDAGBuilder::visitJumpTableHeader(),llvm::SelectionDAGBuilder::visitSPDescriptorParent(),llvm::SelectionDAGBuilder::visitSwitchCase(), andwidenVectorOpsToi8().
| inline |
Helper function to make it easier to build VP_SETCCs if you just have anISD::CondCode instead of anSDValue.
Definition at line1268 of fileSelectionDAG.h.
Referencesassert(),Cond,DL,getCondCode(),getNode(),LHS,RHS, andllvm::ISD::SETCC_INVALID.
Referenced byllvm::TargetLowering::LegalizeSetCCCondCode().
SDValue SelectionDAG::getSetFPEnv | ( | SDValue | Chain, |
constSDLoc & | dl, | ||
SDValue | Ptr, | ||
EVT | MemVT, | ||
MachineMemOperand * | MMO | ||
) |
Definition at line10198 of fileSelectionDAG.cpp.
ReferencesAddNodeIDNode(),assert(),llvm::MachinePointerInfo::getAddrSpace(),llvm::SDLoc::getDebugLoc(),llvm::MachineMemOperand::getFlags(),llvm::SDLoc::getIROrder(),llvm::MachineMemOperand::getPointerInfo(),llvm::EVT::getRawBits(),llvm::SDValue::getValueType(),getVTList(),N,NewSDValueDbgMsg(),Ptr, andllvm::ISD::SET_FPENV_MEM.
Convert Op, which must be of integer type, to the integer type VT, by either sign-extending or truncating it.
Definition at line1502 of fileSelectionDAG.cpp.
Referencesllvm::EVT::bitsGT(),DL,getNode(),llvm::ISD::SIGN_EXTEND, andllvm::ISD::TRUNCATE.
Referenced bycombineGatherScatter(),combineShuffleOfScalars(),combineToExtendBoolVectorInReg(),createVPDPBUSD(),llvm::TargetLowering::CTTZTableLookup(),llvm::TargetLowering::expandAddSubSat(),llvm::TargetLowering::expandCMP(),llvm::TargetLowering::expandFP_TO_SINT(),foldCONCAT_VECTORS(),getBitcastedSExtOrTrunc(),getExtOrTrunc(),llvm::VECustomDAG::getMaskBroadcast(),getNode(),LowerADDSUBSAT(),LowerBITCAST(),llvm::HexagonTargetLowering::LowerLoad(),LowerMULO(),llvm::HexagonTargetLowering::LowerSETCC(),llvm::HexagonTargetLowering::LowerVECTOR_SHIFT(),LowerVectorAllEqual(),llvm::HexagonTargetLowering::LowerVSELECT(),LowerVSETCC(),llvm::AMDGPUTargetLowering::performMulCombine(),llvm::AMDGPUTargetLowering::performMulhsCombine(),llvm::AMDGPUTargetLowering::performMulLoHiCombine(),tryLowerPartialReductionToDot(), andvectorToScalarBitmask().
Definition at line1818 of fileSelectionDAG.cpp.
Referencesassert(),DL,llvm::EVT::getScalarSizeInBits(),getShiftAmountConstant(),llvm::APInt::getZExtValue(), andllvm::APInt::ult().
Definition at line1811 of fileSelectionDAG.cpp.
Referencesassert(),DL,getConstant(),getDataLayout(),llvm::TargetLoweringBase::getShiftAmountTy(), andllvm::EVT::isInteger().
Referenced byllvm::TargetLowering::BuildSDIV(),llvm::TargetLowering::BuildUDIV(),combineExtractWithShuffle(),llvm::TargetLowering::expandABS(),llvm::TargetLowering::expandAVG(),llvm::TargetLowering::expandCTPOP(),llvm::TargetLowering::expandDIVREMByConstant(),llvm::TargetLowering::expandFixedPointDiv(),llvm::TargetLowering::expandFixedPointMul(),llvm::TargetLowering::expandFP_ROUND(),llvm::TargetLowering::expandMUL_LOHI(),llvm::TargetLowering::expandMULO(),llvm::TargetLowering::expandRoundInexactToOdd(),llvm::TargetLowering::expandUINT_TO_FP(),llvm::TargetLowering::expandUnalignedLoad(),llvm::TargetLowering::expandUnalignedStore(),llvm::TargetLowering::expandVPCTPOP(),extractShiftForRotate(),foldSubCtlzNot(),foldVSelectToSignBitSplatMask(),llvm::TargetLowering::forceExpandMultiply(),llvm::TargetLowering::forceExpandWideMUL(),getCopyToParts(),getShiftAmountConstant(),llvm::AMDGPUTargetLowering::loadInputValue(),LowerCTPOP(),LowerFunnelShift(),LowerINTRINSIC_W_CHAIN(),llvm::RISCVTargetLowering::LowerOperation(),LowerRotate(),matchBSwapHWordOrAndAnd(),llvm::SITargetLowering::passSpecialInputs(),llvm::X86TargetLowering::ReplaceNodeResults(),llvm::TargetLowering::scalarizeVectorLoad(),ShrinkLoadReplaceStoreWithStore(),llvm::TargetLowering::SimplifyDemandedBits(),llvm::TargetLowering::SimplifySetCC(), andvisitORCommutative().
Return the specified value casted to the target's desired shift amount type.
getShiftAmountOperand - Return the specified value casted to the target's desired shift amount type.
Definition at line2468 of fileSelectionDAG.cpp.
ReferencesgetDataLayout(),llvm::TargetLoweringBase::getShiftAmountTy(),getZExtOrTrunc(), andllvm::EVT::isVector().
Referenced byLowerCTPOP(), andUnrollVectorOp().
SDValue SelectionDAG::getSignedConstant | ( | int64_t | Val, |
constSDLoc & | DL, | ||
EVT | VT, | ||
bool | isTarget =false , | ||
bool | isOpaque =false | ||
) |
Definition at line1794 of fileSelectionDAG.cpp.
ReferencesDL,getConstant(),llvm::EVT::getScalarSizeInBits(), andSize.
Referenced byllvm::TargetLowering::BuildSDIV(),constantFoldBFE(),emitMemMemReg(),expandVAArg(),foldMaskedShiftToScaledMask(),getAArch64Cmp(),getCSAddressAndShifts(),llvm::AVRTargetLowering::getPreIndexedAddressParts(),getSignedTargetConstant(),isBLACompatibleAddress(),lowerBuildVectorOfConstants(),llvm::SITargetLowering::LowerDYNAMIC_STACKALLOC(),LowerDYNAMIC_STACKALLOC(),LowerFP_TO_INT_SAT(),llvm::RISCVTargetLowering::LowerOperation(),lowerShuffleAsBlend(),LowerVECTOR_SHUFFLEv8i8(),performCONCAT_VECTORSCombine(),llvm::RISCVTargetLowering::PerformDAGCombine(),performSETCCCombine(),llvm::SelectionDAGISel::SelectCodeCommon(),transformAddImmMulImm(), andtryConvertSVEWideCompare().
| inline |
Definition at line713 of fileSelectionDAG.h.
ReferencesDL, andgetSignedConstant().
Referenced byllvm::PPC::get_VSPLTI_elt(),llvm::HexagonDAGToDAGISel::LoadInstrForLoadIntrinsic(),llvm::ARMTargetLowering::LowerAsmOperandForConstraint(),llvm::M68kTargetLowering::LowerAsmOperandForConstraint(),llvm::RISCVTargetLowering::LowerAsmOperandForConstraint(),llvm::SparcTargetLowering::LowerAsmOperandForConstraint(),llvm::SystemZTargetLowering::LowerAsmOperandForConstraint(),llvm::PPCTargetLowering::SelectAddressRegImm(),llvm::PPCTargetLowering::SelectAddressRegImm34(),llvm::RISCVDAGToDAGISel::SelectAddrRegImm(),llvm::RISCVDAGToDAGISel::SelectAddrRegImmLsb00000(),selectConstantAddr(),selectImm(),selectImmSeq(),llvm::HexagonDAGToDAGISel::SelectIndexedStore(),llvm::PPCTargetLowering::SelectOptimalAddrMode(),llvm::HexagonDAGToDAGISel::SelectQ2V(),llvm::RISCVDAGToDAGISel::selectRVVSimm5(),llvm::RISCVDAGToDAGISel::selectSETCC(),llvm::RISCVDAGToDAGISel::selectSimm5Shl2(),llvm::HexagonDAGToDAGISel::SelectV2Q(),llvm::RISCVDAGToDAGISel::selectVLOp(),selectVSplatImmHelper(),llvm::RISCVDAGToDAGISel::tryIndexedLoad(), andllvm::RISCVDAGToDAGISel::tryShrinkShlLogicImm().
Returns a node representing a splat of one value into all lanes of the provided vector type.
This is a utility which returns either a BUILD_VECTOR or SPLAT_VECTOR depending on the scalability of the desired vector type.
Definition at line907 of fileSelectionDAG.h.
Referencesassert(),DL,getSplatBuildVector(),getSplatVector(),llvm::EVT::isScalableVector(), andllvm::EVT::isVector().
Referenced bycombineToExtendBoolVectorInReg(),llvm::TargetLowering::expandVPCTTZElements(),getConstant(),getConstantFP(),llvm::SelectionDAGBuilder::getValueImpl(),performCONCAT_VECTORSCombine(),llvm::RISCVTargetLowering::PerformDAGCombine(),refineUniformBase(),scalarizeBinOpOfSplats(), andtakeInexpensiveLog2().
Return a splatISD::BUILD_VECTOR node, consisting of Op splatted to all elements.
VT must be a vector type. Op's type must be the same as (or, for integers, a type wider than) VT's element type.
Definition at line874 of fileSelectionDAG.h.
Referencesassert(),llvm::EVT::bitsLE(),llvm::ISD::BUILD_VECTOR,DL,getNode(),llvm::EVT::getVectorElementType(),llvm::EVT::getVectorNumElements(),llvm::EVT::isInteger(), andllvm::ISD::UNDEF.
Referenced bycombineGatherScatter(),llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemset(),getMemsetValue(),getSplat(),getVectorShuffle(),lowerBUILD_VECTOR(), andlowerBuildVectorViaDominantValues().
If V is a splatted value, return the source vector and its splat index.
Definition at line3229 of fileSelectionDAG.cpp.
Referencesassert(),llvm::countr_one(),llvm::APInt::getAllOnes(),getUNDEF(),llvm::EVT::getVectorNumElements(),Idx,llvm::EVT::isScalableVector(),isSplatValue(),llvm::APInt::isSubsetOf(),llvm::peekThroughExtractSubvectors(),llvm::ISD::SPLAT_VECTOR, andllvm::ISD::VECTOR_SHUFFLE.
Referenced bygetSplatValue(),LowerFunnelShift(),LowerRotate(),LowerShiftByScalarVariable(), andscalarizeBinOpOfSplats().
If V is a splat vector, return its scalar source operand by extracting that element from the source vector.
If LegalTypes is true, this method may only return a legally-typed splat value. If it cannot legalize the splatted value it will return SDValue().
Definition at line3281 of fileSelectionDAG.cpp.
Referencesllvm::EVT::bitsLT(),llvm::ISD::EXTRACT_VECTOR_ELT,getContext(),getNode(),llvm::EVT::getScalarType(),getSplatSourceVector(),llvm::TargetLoweringBase::getTypeToTransformTo(),getVectorIdxConstant(),llvm::EVT::isInteger(), andllvm::TargetLoweringBase::isTypeLegal().
Referenced bycanLowerSRLToRoundingShiftForVT(),findMoreOptimalIndexType(),foldIndexIntoBase(),PerformVSetCCToVCTPCombine(), andrefineUniformBase().
Definition at line891 of fileSelectionDAG.h.
Referencesassert(),llvm::EVT::bitsLE(),DL,getNode(),llvm::EVT::getVectorElementType(),llvm::EVT::isInteger(),llvm::ISD::SPLAT_VECTOR, andllvm::ISD::UNDEF.
Referenced byBuildExactSDIV(),BuildExactUDIV(),llvm::TargetLowering::BuildSDIV(),llvm::TargetLowering::BuildUDIV(),FoldConstantArithmetic(),getSplat(),getWideningInterleave(),lowerBUILD_VECTOR(), andLowerVectorMatch().
Compute the VTs needed for the low/hi parts of a type which is split (or expanded) into two not necessarily identical pieces.
GetSplitDestVTs - Compute the VTs needed for the low/hi parts of a type which is split (or expanded) into two not necessarily identical pieces.
Definition at line12961 of fileSelectionDAG.cpp.
ReferencesgetContext(),llvm::EVT::getHalfNumVectorElementsVT(),llvm::TargetLoweringBase::getTypeToTransformTo(), andllvm::EVT::isVector().
Referenced byllvm::TargetLowering::expandVectorNaryOpBySplitting(),LowerCVTPS2PH(),LowerMULO(),llvm::X86TargetLowering::ReplaceNodeResults(),ReplaceReductionResults(),SplitStrictFPVectorOp(),llvm::SITargetLowering::splitTernaryVectorOp(),SplitVector(),SplitVectorOp(),splitVectorOp(),SplitVPOp(), andsplitVSETCC().
Construct a node to track a Value* through the backend.
Definition at line2403 of fileSelectionDAG.cpp.
ReferencesAddNodeIDNode(),getVTList(),N, andllvm::ISD::SRCVALUE.
Referenced byllvm::SelectionDAGBuilder::LowerAsSTATEPOINT().
Compute a TokenFactor to force all the incoming stack arguments to be loaded from the stack.
getStackArgumentTokenFactor - Compute a TokenFactor to force all the incoming stack arguments to be loaded from the stack.
This is used in tail call lowering to protect stack arguments from being clobbered.
Definition at line7948 of fileSelectionDAG.cpp.
ReferencesgetEntryNode(),getNode(),llvm::SmallVectorTemplateBase< T, bool >::push_back(),llvm::ISD::TokenFactor, andusers.
Returns a vector of type ResVT whose elements contain the linear sequence <0, 1, 2, 3, ...>
Definition at line2120 of fileSelectionDAG.cpp.
ReferencesDL,llvm::EVT::getScalarSizeInBits(), andgetStepVector().
Returns a vector of type ResVT whose elements contain the linear sequence <0, Step, Step * 2, Step * 3, ...>
Definition at line2125 of fileSelectionDAG.cpp.
Referencesassert(),DL,llvm::APInt::getBitWidth(),getBuildVector(),getConstant(),getNode(),llvm::EVT::getScalarSizeInBits(),getTargetConstant(),llvm::EVT::getVectorElementType(),llvm::EVT::getVectorNumElements(),llvm::EVT::isScalableVector(),llvm::SmallVectorTemplateBase< T, bool >::push_back(), andllvm::ISD::STEP_VECTOR.
Referenced byllvm::TargetLowering::expandVectorFindLastActive(),llvm::TargetLowering::expandVPCTTZElements(),findMoreOptimalIndexType(),FoldConstantArithmetic(),getStepVector(), andLowerSVEIntrinsicIndex().
SDValue SelectionDAG::getStore | ( | SDValue | Chain, |
constSDLoc & | dl, | ||
SDValue | Val, | ||
SDValue | Ptr, | ||
MachineMemOperand * | MMO | ||
) |
Definition at line9340 of fileSelectionDAG.cpp.
ReferencesAddNodeIDNode(),assert(),llvm::MachinePointerInfo::getAddrSpace(),llvm::SDLoc::getDebugLoc(),llvm::MachineMemOperand::getFlags(),llvm::SDLoc::getIROrder(),llvm::MachineMemOperand::getPointerInfo(),llvm::EVT::getRawBits(),getUNDEF(),llvm::SDValue::getValueType(),getVTList(),N,NewSDValueDbgMsg(),Ptr,llvm::ISD::STORE, andllvm::ISD::UNINDEXED.
SDValue SelectionDAG::getStore | ( | SDValue | Chain, |
constSDLoc & | dl, | ||
SDValue | Val, | ||
SDValue | Ptr, | ||
MachinePointerInfo | PtrInfo, | ||
Align | Alignment, | ||
MachineMemOperand::Flags | MMOFlags =MachineMemOperand::MONone , | ||
constAAMDNodes & | AAInfo =AAMDNodes() | ||
) |
Helper function to buildISD::STORE nodes.
This function will set the MOStore flag on MMOFlags, but you can set it if you want. The MOLoad and MOInvariant flags must not be set.
Definition at line9320 of fileSelectionDAG.cpp.
Referencesassert(),getMachineFunction(),llvm::MachineFunction::getMachineMemOperand(),getStore(),llvm::EVT::getStoreSize(),llvm::SDValue::getValueType(),InferPointerInfo(),llvm::PointerUnion< PTs >::isNull(),llvm::MachineMemOperand::MOLoad,llvm::MachineMemOperand::MOStore,llvm::LocationSize::precise(),Ptr,Size, andllvm::MachinePointerInfo::V.
Referenced bycombineBoolVectorAndTruncateStore(),combineI8TruncStore(),combineStore(),EmitTailCallStoreFPAndRetAddr(),EmitTailCallStoreRetAddr(),llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(),llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemset(),llvm::TargetLowering::expandUnalignedLoad(),llvm::TargetLowering::expandUnalignedStore(),expandVAArg(),expandVACopy(),llvm::TargetLowering::expandVECTOR_COMPRESS(),llvm::TargetLowering::expandVectorSplice(),foldTruncStoreOfExt(),getMemcpyLoadsAndStores(),getMemmoveLoadsAndStores(),getMemsetStores(),getStore(),getTruncStore(),LowerATOMIC_STORE(),llvm::SITargetLowering::LowerCall(),llvm::SystemZTargetLowering::LowerCall(),llvm::XtensaTargetLowering::LowerCall(),llvm::HexagonTargetLowering::LowerCall(),llvm::LoongArchTargetLowering::LowerCall(),llvm::RISCVTargetLowering::LowerCall(),llvm::VETargetLowering::LowerCall(),llvm::SparcTargetLowering::LowerCall_32(),llvm::SparcTargetLowering::LowerCall_64(),llvm::HexagonTargetLowering::LowerEH_RETURN(),llvm::SparcTargetLowering::LowerF128_LibCallArg(),LowerF128Store(),llvm::LoongArchTargetLowering::LowerFormalArguments(),llvm::RISCVTargetLowering::LowerFormalArguments(),llvm::SystemZTargetLowering::LowerFormalArguments(),llvm::XtensaTargetLowering::LowerFormalArguments(),llvm::SparcTargetLowering::LowerFormalArguments_32(),llvm::SparcTargetLowering::LowerFormalArguments_64(),lowerFP_TO_SINT_STORE(),LowerMemOpCallTo(),lowerMSAStoreIntr(),llvm::RISCVTargetLowering::LowerOperation(),LowerStore(),LowerSTORE(),lowerStoreF128(),lowerStoreI1(),LowerTruncateVectorStore(),LowerVAARG(),llvm::VETargetLowering::lowerVAARG(),LowerVASTART(),llvm::HexagonTargetLowering::LowerVASTART(),llvm::LanaiTargetLowering::LowerVASTART(),llvm::MSP430TargetLowering::LowerVASTART(),llvm::VETargetLowering::lowerVASTART(),memsetStore(),llvm::RISCVTargetLowering::PerformDAGCombine(),llvm::ARMTargetLowering::PerformMVEExtCombine(),llvm::AMDGPUTargetLowering::performStoreCombine(),PerformSTORECombine(),PerformTruncatingStoreCombine(),llvm::RISCVDAGToDAGISel::PreprocessISelDAG(),reduceMaskedStoreToScalarStore(),llvm::TargetLowering::scalarizeVectorStore(),scalarizeVectorStore(),ShrinkLoadReplaceStoreWithStore(),spillIncomingStatepointValue(),splitStores(),splitStoreSplat(),splitVectorStore(),llvm::HexagonDAGToDAGISel::StoreInstrForLoadIntrinsic(),llvm::AMDGPUTargetLowering::storeStackInputValue(), andStoreTailCallArgumentsToStackSlot().
| inline |
Definition at line1435 of fileSelectionDAG.h.
ReferencesgetEVTAlign(),getStore(),llvm::SDValue::getValueType(), andPtr.
SDValue SelectionDAG::getStoreVP | ( | SDValue | Chain, |
constSDLoc & | dl, | ||
SDValue | Val, | ||
SDValue | Ptr, | ||
SDValue | Offset, | ||
SDValue | Mask, | ||
SDValue | EVL, | ||
EVT | MemVT, | ||
MachineMemOperand * | MMO, | ||
ISD::MemIndexedMode | AM, | ||
bool | IsTruncating =false , | ||
bool | IsCompressing =false | ||
) |
Definition at line9584 of fileSelectionDAG.cpp.
ReferencesAddNodeIDNode(),assert(),llvm::MachinePointerInfo::getAddrSpace(),llvm::SDLoc::getDebugLoc(),llvm::MachineMemOperand::getFlags(),llvm::SDLoc::getIROrder(),llvm::MachineMemOperand::getPointerInfo(),llvm::EVT::getRawBits(),llvm::SDValue::getValueType(),getVTList(),Indexed,N,NewSDValueDbgMsg(),llvm::Offset,Ptr, andllvm::ISD::UNINDEXED.
Referenced bygetTruncStoreVP(), andllvm::RISCVTargetLowering::PerformDAGCombine().
std::pair<SDValue,SDValue > SelectionDAG::getStrictFPExtendOrRound | ( | SDValue | Op, |
SDValue | Chain, | ||
constSDLoc & | DL, | ||
EVT | VT | ||
) |
Convert Op, which must be a STRICT operation of float type, to the float type VT, by either extending or rounding (by truncation).
Definition at line1483 of fileSelectionDAG.cpp.
Referencesassert(),llvm::EVT::bitsEq(),llvm::EVT::bitsGT(),DL,getIntPtrConstant(),llvm::SDValue::getNode(),getNode(),llvm::ISD::STRICT_FP_EXTEND, andllvm::ISD::STRICT_FP_ROUND.
Referenced byllvm::RISCVTargetLowering::LowerOperation(), andLowerUINT_TO_FP_i32().
SDValue SelectionDAG::getStridedLoadVP | ( | EVT | VT, |
constSDLoc & | DL, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
SDValue | Stride, | ||
SDValue | Mask, | ||
SDValue | EVL, | ||
MachineMemOperand * | MMO, | ||
bool | IsExpanding =false | ||
) |
Definition at line9754 of fileSelectionDAG.cpp.
ReferencesDL,getStridedLoadVP(),getUNDEF(),llvm::ISD::NON_EXTLOAD,Ptr, andllvm::ISD::UNINDEXED.
SDValue SelectionDAG::getStridedLoadVP | ( | ISD::MemIndexedMode | AM, |
ISD::LoadExtType | ExtType, | ||
EVT | VT, | ||
constSDLoc & | DL, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
SDValue | Offset, | ||
SDValue | Stride, | ||
SDValue | Mask, | ||
SDValue | EVL, | ||
EVT | MemVT, | ||
MachineMemOperand * | MMO, | ||
bool | IsExpanding =false | ||
) |
Definition at line9720 of fileSelectionDAG.cpp.
ReferencesAddNodeIDNode(),assert(),DL,llvm::MachinePointerInfo::getAddrSpace(),llvm::MachineMemOperand::getPointerInfo(),llvm::EVT::getRawBits(),getVTList(),Indexed,N,NewSDValueDbgMsg(),llvm::Offset,Ptr, andllvm::ISD::UNINDEXED.
Referenced bygetExtStridedLoadVP(),getStridedLoadVP(),performCONCAT_VECTORSCombine(),llvm::RISCVTargetLowering::PerformDAGCombine(), andperformVP_REVERSECombine().
SDValue SelectionDAG::getStridedStoreVP | ( | SDValue | Chain, |
constSDLoc & | DL, | ||
SDValue | Val, | ||
SDValue | Ptr, | ||
SDValue | Offset, | ||
SDValue | Stride, | ||
SDValue | Mask, | ||
SDValue | EVL, | ||
EVT | MemVT, | ||
MachineMemOperand * | MMO, | ||
ISD::MemIndexedMode | AM, | ||
bool | IsTruncating =false , | ||
bool | IsCompressing =false | ||
) |
Definition at line9773 of fileSelectionDAG.cpp.
ReferencesAddNodeIDNode(),assert(),DL,llvm::MachinePointerInfo::getAddrSpace(),llvm::MachineMemOperand::getPointerInfo(),llvm::EVT::getRawBits(),llvm::SDValue::getValueType(),getVTList(),Indexed,N,NewSDValueDbgMsg(),llvm::Offset,Ptr, andllvm::ISD::UNINDEXED.
Referenced bygetTruncStridedStoreVP(), andperformVP_STORECombine().
| inline |
Definition at line499 of fileSelectionDAG.h.
Referencesllvm::MachineFunction::getSubtarget().
Referenced byadjustICmp128(),combineCommutableSHUFP(),emitComparison(),emitConditionalComparison(),emitStrictFPComparison(),llvm::HexagonSelectionDAGInfo::EmitTargetCodeForMemcpy(),llvm::XCoreSelectionDAGInfo::EmitTargetCodeForMemcpy(),findMoreOptimalIndexType(),GenerateFixedLengthSVETBL(),getPredicateForFixedLengthVector(),GetTLSADDR(),init(),isAllActivePredicate(),llvm::PPC::isVPKUDUMShuffleMask(),lowerMSASplatZExt(),llvm::HexagonTargetLowering::LowerToTLSGeneralDynamicModel(),LowerVectorFP_TO_INT(),LowerVectorINT_TO_FP(),optimizeIncrementingWhile(),patchMatchingInput(),performBuildVectorCombine(),performExtractVectorEltCombine(),performSVEMulAddSubCombine(),recoverFramePointer(),llvm::AMDGPUDAGToDAGISel::SelectBuildVector(),truncateVecElts(),tryAdvSIMDModImm16(),tryAdvSIMDModImm32(),tryCombineToBSL(), andvectorToScalarBitmask().
| inline |
Definition at line500 of fileSelectionDAG.h.
Referencesllvm::MachineFunction::getSubtarget().
SDValue SelectionDAG::getSymbolFunctionGlobalAddress | ( | SDValue | Op, |
Function ** | TargetFunction =nullptr | ||
) |
Return a GlobalAddress of the function from the current module with name matching the given ExternalSymbol.
Additionally can provide the matched function. Panic if the function doesn't exist.
Definition at line12178 of fileSelectionDAG.cpp.
Referencesassert(),llvm::GlobalValue::getAddressSpace(),getDataLayout(),llvm::MachineFunction::getFunction(),llvm::Module::getFunction(),getGlobalAddress(),llvm::GlobalValue::getParent(),llvm::TargetLoweringBase::getPointerTy(), andllvm::report_fatal_error().
Referenced byllvm::NVPTXTargetLowering::LowerCall().
| inline |
Definition at line498 of fileSelectionDAG.h.
Referenced byllvm::AMDGPUTargetLowering::allowApproxFunc(),canCreateUndefOrPoison(),canOptimizeTLSDFormToXForm(),combineFaddCFmul(),combineFMinFMax(),combineFMinNumFMaxNum(),combineSelect(),llvm::ScheduleDAGSDNodes::EmitSchedule(),llvm::TargetLowering::expandFMINIMUMNUM_FMAXIMUMNUM(),llvm::TargetLowering::expandIndirectJTBranch(),llvm::RISCVTargetLowering::expandIndirectJTBranch(),llvm::X86TargetLowering::expandIndirectJTBranch(),foldFPToIntToFP(),getMemcpy(),getMemmove(),getMemset(),llvm::TargetLowering::getNegatedExpression(),GetTLSADDR(),llvm::SITargetLowering::isEligibleForTailCallOptimization(),isEligibleToFoldADDIForFasterLocalAccesses(),isFMAddSubOrFMSubAdd(),isKnownNeverNaN(),isLegalToCombineMinNumMaxNum(),llvm::LoongArchTargetLowering::LowerCall(),llvm::VETargetLowering::LowerCall(),llvm::SelectionDAGBuilder::LowerCallTo(),llvm::SelectionDAGBuilder::LowerDeoptimizingReturn(),LowerFMINIMUM_FMAXIMUM(),llvm::SparcTargetLowering::LowerGlobalTLSAddress(),llvm::VETargetLowering::lowerINTRINSIC_WO_CHAIN(),transformCallee(), andllvm::SelectionDAGBuilder::visitSPDescriptorFailure().
| inline |
Definition at line797 of fileSelectionDAG.h.
ReferencesgetBlockAddress(), andllvm::Offset.
Referenced bygetTargetNode(),llvm::TargetLowering::LowerAsmOperandForConstraint(),llvm::X86TargetLowering::LowerAsmOperandForConstraint(),llvm::HexagonTargetLowering::LowerBlockAddress(),llvm::MSP430TargetLowering::LowerBlockAddress(),llvm::SparcTargetLowering::withTargetFlags(), andllvm::VETargetLowering::withTargetFlags().
| inline |
Definition at line705 of fileSelectionDAG.h.
ReferencesDL, andgetConstant().
| inline |
Definition at line709 of fileSelectionDAG.h.
ReferencesDL, andgetConstant().
| inline |
Definition at line701 of fileSelectionDAG.h.
ReferencesDL, andgetConstant().
Referenced byllvm::RegsForValue::AddInlineAsmOperands(),llvm::RISCVDAGToDAGISel::addVectorLoadStoreOperands(),buildPCRelGlobalAddress(),buildRegSequence16(),buildRegSequence32(),llvm::SITargetLowering::buildRSRC(),buildSMovImm32(),canonicalizeBitSelect(),llvm::AArch64TargetLowering::changeStreamingMode(),checkCVTFixedPointOperandWithFBits(),llvm::SITargetLowering::CollectTargetIntrinsicOperands(),combineADC(),combineAddOrSubToADCOrSBB(),combineAndMaskToShift(),combineAndOrForCcmpCtest(),combineBitcastToBoolVector(),combineBrCond(),combineCMov(),combineCommutableSHUFP(),combineCompareEqual(),combineConcatVectorOps(),combineEXTRACT_SUBVECTOR(),combineExtractWithShuffle(),combineFP16_TO_FP(),combineFP_ROUND(),combineKSHIFT(),combineStore(),combineTargetShuffle(),llvm::VETargetLowering::combineTRUNCATE(),combineVectorShiftImm(),combineX86ShuffleChain(),combineX86SubCmpForFlags(),createGPRPairNode(),createGPRPairNode2xi32(),createMMXBuildVector(),createSetFPEnvNodes(),llvm::HexagonDAGToDAGISel::DetectUseSxtw(),EmitAVX512Test(),emitCmp(),emitLockedStackOp(),emitSETCC(),llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemchr(),llvm::AArch64SelectionDAGInfo::EmitTargetCodeForSetTag(),expandBitCastI128ToF128(),llvm::TargetLowering::expandFMINIMUM_FMAXIMUM(),llvm::TargetLowering::expandFMINIMUMNUM_FMAXIMUMNUM(),expandFP_TO_UINT_SSE(),ExtractBitFromMaskVector(),extractPtrauthBlendDiscriminators(),llvm::HexagonDAGToDAGISel::FastFDiv(),llvm::HexagonDAGToDAGISel::FDiv(),llvm::PPC::get_VSPLTI_elt(),getADAEntry(),getAL(),getAVX2GatherNode(),getCopyFromParts(),getDataClassTest(),getGatherNode(),getGeneralPermuteNode(),getIntOperandsFromRegisterString(),getJumpTableDebugInfo(),getLeftShift(),getPack(),getPermuteNode(),getPrefetchNode(),getPTrue(),getScatterNode(),getSETCC(),getSHUFPDImmForMask(),getSPDenormModeValue(),getStepVector(),getTargetExtractSubreg(),getTargetInsertSubreg(),getTargetVShiftByConstNode(),getTargetVShiftNode(),getUniformBase(),getV4X86ShuffleImm8ForMask(),getVAArg(),getVShift(),getVSlidedown(),getVSlideup(),getZeroVector(),insert1BitVector(),InvertCarryFlag(),isVMOVModifiedImm(),isWorthFoldingIntoOrrWithShift(),lower1BitShuffle(),lower1BitShuffleAsKSHIFTR(),LowerABD(),LowerABS(),llvm::TargetLowering::LowerAsmOperandForConstraint(),llvm::SITargetLowering::LowerAsmOperandForConstraint(),llvm::AVRTargetLowering::LowerAsmOperandForConstraint(),llvm::LanaiTargetLowering::LowerAsmOperandForConstraint(),llvm::PPCTargetLowering::LowerAsmOperandForConstraint(),llvm::RISCVTargetLowering::LowerAsmOperandForConstraint(),llvm::SystemZTargetLowering::LowerAsmOperandForConstraint(),llvm::X86TargetLowering::LowerAsmOperandForConstraint(),llvm::SelectionDAGBuilder::LowerAsSTATEPOINT(),llvm::VETargetLowering::lowerATOMIC_FENCE(),LowerBITREVERSE(),LowerBuildVectorv4x32(),llvm::SITargetLowering::LowerCall(),llvm::VETargetLowering::LowerCall(),llvm::SparcTargetLowering::LowerCall_32(),LowerCMP_SWAP(),LowerCONCAT_VECTORSvXi1(),LowerCTLZ(),LowerCTTZ(),llvm::SITargetLowering::LowerDYNAMIC_STACKALLOC(),llvm::NVPTXTargetLowering::LowerDYNAMIC_STACKALLOC(),LowerEXTEND_VECTOR_INREG(),LowerEXTRACT_SUBVECTOR(),llvm::VETargetLowering::lowerEXTRACT_VECTOR_ELT(),LowerEXTRACT_VECTOR_ELT_SSE4(),LowerF128Load(),LowerF128Store(),llvm::AMDGPUTargetLowering::lowerFEXP(),llvm::AMDGPUTargetLowering::lowerFEXP2(),llvm::AMDGPUTargetLowering::LowerFLOG2(),llvm::AMDGPUTargetLowering::LowerFLOGCommon(),LowerFMINIMUM_FMAXIMUM(),llvm::VETargetLowering::LowerFormalArguments(),LowerFP_TO_FP16(),lowerFP_TO_INT_SAT(),lowerFTRUNC_FCEIL_FFLOOR_FROUND(),LowerFunnelShift(),llvm::SITargetLowering::lowerGET_FPENV(),llvm::SITargetLowering::lowerGET_ROUNDING(),lowerGetVectorLength(),LowerINTRINSIC_W_CHAIN(),lowerLaneOp(),lowerLoadF128(),lowerLoadI1(),LowerMLOAD(),LowerMUL(),LowerPREFETCH(),LowerPtrAuthGlobalAddressStatically(),lowerReductionSeq(),llvm::VETargetLowering::LowerReturn(),LowerRotate(),LowerSELECTWithCmpZero(),llvm::SITargetLowering::lowerSET_FPENV(),llvm::SITargetLowering::lowerSET_ROUNDING(),LowerShift(),LowerShiftByScalarImmediate(),lowerShuffleAsBitRotate(),lowerShuffleAsBlend(),lowerShuffleAsByteRotate(),lowerShuffleAsByteRotateAndPermute(),lowerShuffleAsByteShiftMask(),lowerShuffleAsElementInsertion(),lowerShuffleAsInsertPS(),lowerShuffleAsShift(),lowerShuffleAsSpecificZeroOrAnyExtend(),lowerShuffleAsVALIGN(),lowerShuffleAsVTRUNC(),lowerShufflePairAsUNPCKAndPermute(),lowerShuffleWithSHUFPD(),lowerShuffleWithSSE4A(),LowerSMELdrStr(),lowerStatepointMetaArgs(),LowerSTORE(),lowerStoreF128(),lowerStoreI1(),lowerUINT_TO_FP_vXi32(),lowerV16I8Shuffle(),lowerV2F64Shuffle(),lowerV2X128Shuffle(),lowerV4F64Shuffle(),lowerV8F64Shuffle(),lowerV8I16Shuffle(),lowerVECTOR_SHUFFLE(),lowerVECTOR_SHUFFLE_SHF(),lowerVECTOR_SHUFFLE_VSHF(),lowerVECTOR_SHUFFLE_XVSHUF(),lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(),lowerVectorIntrinsicScalars(),LowerVectorMatch(),lowerVectorXRINT(),LowerVSETCC(),optimizeLogicalImm(),llvm::packConstantV2I16(),parseTexFail(),llvm::PPCTargetLowering::PerformDAGCombine(),performFP_TO_INT_SATCombine(),performFP_TO_INTCombine(),PerformHWLoopCombine(),pickOpcodeForVectorStParam(),llvm::RISCVDAGToDAGISel::PreprocessISelDAG(),PromoteMVEPredVector(),pushStackMapConstant(),llvm::SITargetLowering::ReplaceNodeResults(),llvm::RISCVTargetLowering::ReplaceNodeResults(),ReplaceREADCYCLECOUNTER(),llvm::AMDGPUDAGToDAGISel::Select(),llvm::RISCVDAGToDAGISel::Select(),llvm::LoongArchDAGToDAGISel::SelectAddrConstant(),llvm::PPCTargetLowering::SelectAddressRegImm(),llvm::RISCVDAGToDAGISel::SelectAddrFrameIndex(),llvm::RISCVDAGToDAGISel::SelectAddrRegImm(),llvm::LoongArchDAGToDAGISel::SelectAddrRegImm12(),llvm::RISCVDAGToDAGISel::SelectAddrRegImmLsb00000(),llvm::RISCVDAGToDAGISel::SelectAddrRegRegScale(),llvm::HexagonDAGToDAGISel::SelectAnyImmediate(),llvm::HexagonDAGToDAGISel::SelectAnyInt(),llvm::AMDGPUDAGToDAGISel::SelectBuildVector(),llvm::SelectionDAGISel::SelectCodeCommon(),selectConstantAddr(),llvm::HexagonDAGToDAGISel::SelectConstantFP(),llvm::HexagonDAGToDAGISel::SelectD2P(),llvm::HexagonDAGToDAGISel::SelectFrameIndex(),selectI64Imm(),selectI64ImmDirect(),selectI64ImmDirectPrefix(),selectImm(),llvm::HexagonDAGToDAGISel::SelectIndexedStore(),llvm::HexagonDAGToDAGISel::SelectInlineAsmMemoryOperand(),llvm::LoongArchDAGToDAGISel::SelectInlineAsmMemoryOperand(),llvm::NVPTXDAGToDAGISel::SelectInlineAsmMemoryOperand(),llvm::RISCVDAGToDAGISel::SelectInlineAsmMemoryOperand(),llvm::SelectionDAGISel::SelectInlineAsmMemoryOperands(),llvm::HexagonDAGToDAGISel::SelectNewCircIntrinsic(),llvm::PPCTargetLowering::SelectOptimalAddrMode(),llvm::RISCVDAGToDAGISel::selectSETCC(),llvm::RISCVDAGToDAGISel::selectSF_VC_X_SE(),llvm::HexagonDAGToDAGISel::SelectSHL(),llvm::RISCVDAGToDAGISel::selectSHXADD_UWOp(),llvm::RISCVDAGToDAGISel::selectSHXADDOp(),llvm::RISCVDAGToDAGISel::selectSimm5Shl2(),llvm::HexagonDAGToDAGISel::SelectV65Gather(),llvm::HexagonDAGToDAGISel::SelectV65GatherPred(),llvm::HexagonDAGToDAGISel::SelectVAlign(),llvm::HexagonDAGToDAGISel::SelectVAlignAddr(),llvm::AMDGPUDAGToDAGISel::SelectVectorShuffle(),llvm::RISCVDAGToDAGISel::selectVLOp(),llvm::RISCVDAGToDAGISel::selectVSETVLI(),llvm::LoongArchDAGToDAGISel::selectVSplatImm(),llvm::LoongArchDAGToDAGISel::selectVSplatUimmInvPow2(),llvm::LoongArchDAGToDAGISel::selectVSplatUimmPow2(),llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(),llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(),llvm::TargetLowering::SimplifySetCC(),tryBitfieldInsertOpFromOr(),tryBitfieldInsertOpFromOrAndImm(),tryCombineWhileLo(),llvm::RISCVDAGToDAGISel::tryIndexedLoad(),tryLowerToSLI(),tryOrrWithShift(),llvm::RISCVDAGToDAGISel::tryShrinkShlLogicImm(),llvm::RISCVDAGToDAGISel::trySignedBitfieldExtract(),trySimplifySrlAddToRshrnb(),tryToConvertShuffleOfTbl2ToTbl4(),llvm::X86TargetLowering::visitMaskedLoad(),llvm::X86TargetLowering::visitMaskedStore(), andllvm::SITargetLowering::wrapAddr64Rsrc().
Definition at line740 of fileSelectionDAG.h.
ReferencesDL, andgetConstantFP().
| inline |
Definition at line743 of fileSelectionDAG.h.
ReferencesDL, andgetConstantFP().
Definition at line737 of fileSelectionDAG.h.
ReferencesDL, andgetConstantFP().
Referenced bypickOpcodeForVectorStParam(), andllvm::SelectionDAGISel::SelectCodeCommon().
| inline |
Definition at line768 of fileSelectionDAG.h.
Referencesllvm::CallingConv::C,getConstantPool(), andllvm::Offset.
Referenced bygetLargeExternalSymbol(),getLargeGlobalAddress(),getTargetNode(),llvm::XtensaTargetLowering::LowerCall(),llvm::HexagonTargetLowering::LowerConstantPool(),llvm::LanaiTargetLowering::LowerConstantPool(),promoteToConstantPool(),llvm::SparcTargetLowering::withTargetFlags(), andllvm::VETargetLowering::withTargetFlags().
| inline |
Definition at line776 of fileSelectionDAG.h.
Referencesllvm::CallingConv::C,getConstantPool(), andllvm::Offset.
Definition at line2069 of fileSelectionDAG.cpp.
ReferencesgetVTList(),N, andSym.
Referenced byllvm::HexagonSelectionDAGInfo::EmitTargetCodeForMemcpy(),getTagSymNode(),GetTLSADDR(),getzOSCalleeAndADA(),llvm::NVPTXTargetLowering::LowerCall(),llvm::SystemZTargetLowering::LowerCall(),llvm::XtensaTargetLowering::LowerCall(),llvm::HexagonTargetLowering::LowerCall(),llvm::LoongArchTargetLowering::LowerCall(),llvm::RISCVTargetLowering::LowerCall(),llvm::VETargetLowering::LowerCall(),llvm::SparcTargetLowering::LowerCall_32(),llvm::SparcTargetLowering::LowerCall_64(),llvm::VETargetLowering::lowerDYNAMIC_STACKALLOC(),llvm::MSP430TargetLowering::LowerExternalSymbol(),llvm::HexagonTargetLowering::LowerGLOBAL_OFFSET_TABLE(),llvm::SparcTargetLowering::LowerGlobalTLSAddress(),llvm::VETargetLowering::lowerINTRINSIC_WO_CHAIN(),transformCallee(),llvm::SparcTargetLowering::withTargetFlags(), andllvm::VETargetLowering::withTargetFlags().
A convenience function for creating TargetInstrInfo::EXTRACT_SUBREG nodes.
getTargetExtractSubreg - A convenience function for creating TargetOpcode::EXTRACT_SUBREG nodes.
Definition at line11267 of fileSelectionDAG.cpp.
ReferencesDL,getMachineNode(), andgetTargetConstant().
Referenced byllvm::SITargetLowering::buildRSRC(),expandBitCastF128ToI128(),LowerF64Op(),LowerFNEGorFABS(),lowerGR128Binary(),lowerGR128ToI128(),LowerINTRINSIC_W_CHAIN(),narrowIfNeeded(),NarrowVector(),ReplaceCMP_SWAP_128Results(),ReplaceCMP_SWAP_64Results(),llvm::RISCVDAGToDAGISel::Select(),llvm::HexagonDAGToDAGISel::SelectExtractSubvector(),llvm::HvxSelector::selectExtractSubvector(),llvm::HexagonDAGToDAGISel::SelectIndexedStore(),llvm::HexagonDAGToDAGISel::SelectVAlign(), andllvm::AMDGPUDAGToDAGISel::SelectVectorShuffle().
Definition at line756 of fileSelectionDAG.h.
ReferencesgetFrameIndex().
Referenced byaddStackMapLiveVars(),llvm::AArch64SelectionDAGInfo::EmitTargetCodeForSetTag(),EmitUnrolledSetTag(),lowerIncomingStatepointValue(),lowerStatepointMetaArgs(),reservePreviousStackSlotForValue(),llvm::PPCTargetLowering::SelectAddressRegImm(),llvm::PPCTargetLowering::SelectAddressRegImm34(),llvm::HexagonDAGToDAGISel::SelectAddrFI(),llvm::RISCVDAGToDAGISel::SelectAddrFrameIndex(),llvm::RISCVDAGToDAGISel::SelectAddrRegImm(),llvm::RISCVDAGToDAGISel::SelectAddrRegImmLsb00000(),llvm::LoongArchDAGToDAGISel::SelectBaseAddr(),llvm::HexagonDAGToDAGISel::SelectFrameIndex(),llvm::PPCTargetLowering::SelectOptimalAddrMode(),SelectSAddrFI(), andspillIncomingStatepointValue().
| inline |
Definition at line751 of fileSelectionDAG.h.
ReferencesDL, andgetGlobalAddress().
Referenced bybuildPCRelGlobalAddress(),combineADDToMAT_PCREL_ADDR(),foldADDIForFasterLocalAccesses(),getADAEntry(),llvm::HexagonTargetLowering::GetDynamicTLSAddr(),getTargetNode(),GetTLSADDR(),getzOSCalleeAndADA(),llvm::TargetLowering::LowerAsmOperandForConstraint(),llvm::X86TargetLowering::LowerAsmOperandForConstraint(),llvm::SITargetLowering::LowerCall(),llvm::SystemZTargetLowering::LowerCall(),llvm::HexagonTargetLowering::LowerCall(),llvm::LoongArchTargetLowering::LowerCall(),llvm::RISCVTargetLowering::LowerCall(),llvm::VETargetLowering::LowerCall(),llvm::SparcTargetLowering::LowerCall_32(),llvm::SparcTargetLowering::LowerCall_64(),llvm::HexagonTargetLowering::LowerGLOBALADDRESS(),llvm::LanaiTargetLowering::LowerGlobalAddress(),llvm::MSP430TargetLowering::LowerGlobalAddress(),llvm::NVPTXTargetLowering::LowerGlobalAddress(),LowerToTLSExecModel(),llvm::HexagonTargetLowering::LowerToTLSGeneralDynamicModel(),llvm::HexagonTargetLowering::LowerToTLSInitialExecModel(),LowerToTLSLocalDynamicModel(),llvm::HexagonTargetLowering::LowerToTLSLocalExecModel(),llvm::RISCVDAGToDAGISel::SelectAddrRegImm(),llvm::HexagonDAGToDAGISel::SelectGlobalAddress(),transformCallee(),llvm::SparcTargetLowering::withTargetFlags(), andllvm::VETargetLowering::withTargetFlags().
SDValue SelectionDAG::getTargetInsertSubreg | ( | int | SRIdx, |
constSDLoc & | DL, | ||
EVT | VT, | ||
SDValue | Operand, | ||
SDValue | Subreg | ||
) |
A convenience function for creating TargetInstrInfo::INSERT_SUBREG nodes.
getTargetInsertSubreg - A convenience function for creating TargetOpcode::INSERT_SUBREG nodes.
Definition at line11277 of fileSelectionDAG.cpp.
ReferencesDL,getMachineNode(), andgetTargetConstant().
Referenced byLowerF64Op(),LowerFNEGorFABS(),llvm::RISCVDAGToDAGISel::Select(), andWiden().
Definition at line761 of fileSelectionDAG.h.
ReferencesgetJumpTable().
Referenced byllvm::HexagonTargetLowering::getPICJumpTableRelocBase(),getTargetNode(),llvm::HexagonTargetLowering::LowerJumpTable(),llvm::LanaiTargetLowering::LowerJumpTable(),llvm::MSP430TargetLowering::LowerJumpTable(), andllvm::VETargetLowering::withTargetFlags().
| inline |
Definition at line503 of fileSelectionDAG.h.
Referenced byAddCombineBUILD_VECTORToVPADDL(),AddCombineToVPADD(),AddCombineVUZPToVPADDL(),llvm::RegsForValue::AddInlineAsmOperands(),buildFromShuffleMostly(),canonicalizeShuffleWithOp(),combineAdd(),combineAddOrSubToADCOrSBB(),combineAnd(),combineAndNotOrIntoAndNotAnd(),combineAndnp(),combineAndShuffleNot(),combineBEXTR(),combineBinOpOfZExt(),combineBitcast(),combineBitcastToBoolVector(),combineBITREVERSE(),combineBT(),combineCMP(),combineCONCAT_VECTORS(),combineConcatVectorOfCasts(),combineConcatVectorOfConcatVectors(),combineConcatVectorOfExtracts(),combineConcatVectorOfScalars(),combineConcatVectorOps(),combineCVTPH2PS(),combineEXTEND_VECTOR_INREG(),combineEXTRACT_SUBVECTOR(),combineExtractFromVectorLoad(),combineExtractVectorElt(),combineFMA(),combineFMADDSUB(),combineFMinNumFMaxNum(),combineFneg(),combineGatherScatter(),combineKSHIFT(),combineLoad(),combineLogicBlendIntoConditionalNegate(),combineMaskedLoad(),combineMaskedStore(),combineMOVMSK(),combineOr(),combinePDEP(),combinePMULDQ(),combinePredicateReduction(),combinePTESTCC(),combineScalarAndWithMaskSetcc(),combineSelect(),combineSelectAsExtAnd(),combineSelectOfTwoConstants(),combineSetCC(),combineShiftAnd1ToBitTest(),combineShuffle(),combineShuffleToFMAddSub(),combineStore(),combineTargetShuffle(),combineTESTP(),combineTruncatedArithmetic(),combineTruncateWithSat(),combineTruncSelectToSMaxUSat(),combineVectorInsert(),combineVectorMulToSraBitcast(),combineVectorShiftImm(),combineVectorShiftVar(),combineVEXTRACT_STORE(),combineVPMADD(),combineVSelectToBLENDV(),combineVSelectWithAllOnesOrZeros(),combineVTRUNC(),combineX86GatherScatter(),combineX86INT_TO_FP(),combineX86ShuffleChain(),combineX86ShuffleChainWithExtract(),combineX86ShufflesConstants(),combineX86ShufflesRecursively(),combineXor(),llvm::SelectionDAGBuilder::CopyValueToVirtualRegister(),createMMXBuildVector(),createSetFPEnvNodes(),EltsFromConsecutiveLoads(),expandBitCastF128ToI128(),expandBitCastI128ToF128(),ExpandPowI(),expandVAArg(),expandVACopy(),llvm::TargetLowering::expandVectorFindLastActive(),foldAndOrOfSETCC(),foldBoolSelectToLogic(),foldCONCAT_VECTORS(),foldExtendedSignBitTest(),foldShuffleOfConcatUndefs(),foldSubCtlzNot(),foldVSelectToSignBitSplatMask(),foldXorTruncShiftIntoCmp(),formSplatFromShuffles(),getADAEntry(),getAddressForMemoryInput(),getAVX2GatherNode(),getAVX512Node(),getAVX512TruncNode(),getBT(),getConstVector(),getContainerForFixedLengthVector(),getCopyFromParts(),getCopyFromPartsVector(),llvm::SelectionDAGBuilder::getCopyFromRegs(),llvm::RegsForValue::getCopyFromRegs(),getCopyToParts(),getCopyToPartsVector(),llvm::RegsForValue::getCopyToRegs(),llvm::SelectionDAGBuilder::getFrameIndexTy(),getGatherNode(),getJumpTableDebugInfo(),getKnownUndefForVectorBinop(),getLifetimeNode(),getLimitedPrecisionExp2(),getLoadStackGuard(),getMemcpyLoadsAndStores(),getMemmoveLoadsAndStores(),getMemset(),getMemsetStores(),getMemsetValue(),getPredicateForFixedLengthVector(),getPredicateForScalableVector(),getPrefetchNode(),getPTest(),getRegistersForValue(),getScatterNode(),getSVEPredicateBitCast(),getTagSymNode(),getUniformBase(),llvm::SelectionDAGBuilder::getValueImpl(),getVCIXISDNodeWCHAIN(),getZeroVector(),getzOSCalleeAndADA(),llvm::SelectionDAGBuilder::handleDebugValue(),llvm::SelectionDAGBuilder::init(),isAddSubOrSubAdd(),isBLACompatibleAddress(),isConsecutiveLSLoc(),isKnownToBeAPowerOfTwo(),IsNOT(),isPackedVectorType(),LowerABD(),LowerADDSAT_SUBSAT(),LowerADDSUBO_CARRY(),llvm::SelectionDAGBuilder::LowerAsSTATEPOINT(),LowerATOMIC_STORE(),lowerBuildVectorAsBroadcast(),lowerBuildVectorToBitOp(),llvm::NVPTXTargetLowering::LowerCall(),llvm::SelectionDAGBuilder::LowerCallTo(),LowerCTPOP(),llvm::SelectionDAGBuilder::LowerDeoptimizeCall(),LowerFABSorFNEG(),LowerFCOPYSIGN(),LowerFMINIMUM_FMAXIMUM(),LowerFSINCOS(),lowerGR128ToI128(),lowerI128ToGR128(),llvm::SelectionDAGBuilder::lowerInvokable(),LowerMemOpCallTo(),LowerMSCATTER(),LowerMULO(),LowerRotate(),LowerShiftParts(),lowerShuffleAsElementInsertion(),lowerShuffleAsShift(),llvm::SelectionDAGBuilder::LowerStatepoint(),lowerStatepointMetaArgs(),LowerStore(),LowerUINT_TO_FP_i64(),lowerUINT_TO_FP_vXi32(),LowerVASTART(),lowerVECTOR_SHUFFLE(),LowerVectorAllEqual(),LowerVSETCC(),LowerXALUO(),matchLSNode(),matchRotateSub(),narrowExtractedVectorBinOp(),narrowExtractedVectorLoad(),narrowInsertExtractVectorBinOp(),narrowShuffle(),llvm::ScheduleDAGSDNodes::newSUnit(),patchMatchingInput(),performAddCSelIntoCSinc(),performAddSubIntoVectorOp(),performANDCombine(),PerformANDCombine(),PerformARMBUILD_VECTORCombine(),performBuildVectorCombine(),performConcatVectorsCombine(),llvm::AArch64TargetLowering::PerformDAGCombine(),llvm::AMDGPUTargetLowering::PerformDAGCombine(),performExtBinopLoadFold(),PerformExtendCombine(),PerformExtractEltToVMOVRRD(),PerformFADDCombineWithOperands(),performFP_TO_INT_SATCombine(),performFP_TO_INTCombine(),performFpToIntCombine(),performGatherLoadCombine(),PerformInsertSubvectorCombine(),performInsertSubvectorCombine(),PerformLOADCombine(),PerformMinMaxFpToSatCombine(),performORCombine(),PerformORCombine(),PerformPREDICATE_CASTCombine(),performScatterStoreCombine(),performSelectCombine(),PerformShiftCombine(),PerformSTORECombine(),performTBISimplification(),PerformTruncatingStoreCombine(),PerformUMinFpToSatCombine(),PerformVDUPLANECombine(),PerformVECTOR_SHUFFLECombine(),PerformVMOVhrCombine(),PerformVMOVNCombine(),PerformVQMOVNCombine(),PerformVSetCCToVCTPCombine(),performXORCombine(),PerformXORCombine(),PromoteMaskArithmetic(),recoverFramePointer(),reduceBuildVecToShuffleWithZero(),refineIndexType(),llvm::LoongArchTargetLowering::ReplaceNodeResults(),scalarizeBinOpOfSplats(),scalarizeExtractedBinOp(),llvm::TargetLowering::CallLoweringInfo::setLibCallee(),llvm::SelectionDAGBuilder::shouldKeepJumpConditionsTogether(),shouldTransformMulToShiftsAddsSubs(),ShrinkLoadReplaceStoreWithStore(),simplifyMul24(),transformCallee(),tryWidenMaskForShuffle(),vectorToScalarBitmask(),llvm::SelectionDAGBuilder::visitBitTestCase(),llvm::SelectionDAGBuilder::visitBitTestHeader(),llvm::SelectionDAGBuilder::visitJumpTable(),llvm::SelectionDAGBuilder::visitJumpTableHeader(),llvm::SelectionDAGBuilder::visitSPDescriptorFailure(),llvm::SelectionDAGBuilder::visitSPDescriptorParent(),llvm::SelectionDAGBuilder::visitSwitchCase(),widenAbs(),widenCtPop(), andwidenVectorToPartType().
SDValue SelectionDAG::getTokenFactor | ( | constSDLoc & | DL, |
SmallVectorImpl<SDValue > & | Vals | ||
) |
Creates a new TokenFactor containingVals
.
IfVals
contains 64k values or more, move values into new TokenFactors in 64k-1 blocks, until the final TokenFactor has less than 64k operands.
Definition at line13532 of fileSelectionDAG.cpp.
Referencesllvm::SmallVectorTemplateCommon< T, typename >::begin(),DL,llvm::SmallVectorImpl< T >::emplace_back(),llvm::SmallVectorTemplateCommon< T, typename >::end(),llvm::SmallVectorImpl< T >::erase(),llvm::SDNode::getMaxNumOperands(),getNode(),llvm::SmallVectorBase< Size_T >::size(),llvm::ArrayRef< T >::slice(), andllvm::ISD::TokenFactor.
Referenced byllvm::SITargetLowering::LowerCall().
SDValue SelectionDAG::getTruncStore | ( | SDValue | Chain, |
constSDLoc & | dl, | ||
SDValue | Val, | ||
SDValue | Ptr, | ||
EVT | SVT, | ||
MachineMemOperand * | MMO | ||
) |
Definition at line9392 of fileSelectionDAG.cpp.
ReferencesAddNodeIDNode(),assert(),llvm::EVT::bitsLT(),llvm::MachinePointerInfo::getAddrSpace(),llvm::SDLoc::getDebugLoc(),llvm::MachineMemOperand::getFlags(),llvm::SDLoc::getIROrder(),llvm::MachineMemOperand::getPointerInfo(),llvm::EVT::getRawBits(),llvm::EVT::getScalarType(),getStore(),getUNDEF(),llvm::SDValue::getValueType(),llvm::EVT::getVectorElementCount(),getVTList(),llvm::EVT::isInteger(),llvm::EVT::isVector(),N,NewSDValueDbgMsg(),Ptr,llvm::ISD::STORE, andllvm::ISD::UNINDEXED.
SDValue SelectionDAG::getTruncStore | ( | SDValue | Chain, |
constSDLoc & | dl, | ||
SDValue | Val, | ||
SDValue | Ptr, | ||
MachinePointerInfo | PtrInfo, | ||
EVT | SVT, | ||
Align | Alignment, | ||
MachineMemOperand::Flags | MMOFlags =MachineMemOperand::MONone , | ||
constAAMDNodes & | AAInfo =AAMDNodes() | ||
) |
Definition at line9371 of fileSelectionDAG.cpp.
Referencesassert(),getMachineFunction(),llvm::MachineFunction::getMachineMemOperand(),llvm::EVT::getStoreSize(),getTruncStore(),llvm::SDValue::getValueType(),InferPointerInfo(),llvm::PointerUnion< PTs >::isNull(),llvm::MachineMemOperand::MOLoad,llvm::MachineMemOperand::MOStore,llvm::LocationSize::precise(),Ptr, andllvm::MachinePointerInfo::V.
Referenced bychainLoadsAndStoresForMemcpy(),combineStore(),llvm::TargetLowering::expandUnalignedLoad(),llvm::TargetLowering::expandUnalignedStore(),getAddressForMemoryInput(),getMemcpyLoadsAndStores(),getTruncStore(),LowerINTRINSIC_W_CHAIN(),LowerPredicateStore(),llvm::HexagonTargetLowering::LowerStore(),PerformExtractFpToIntStores(),llvm::ARMTargetLowering::PerformMVETruncCombine(),PerformSplittingMVETruncToNarrowingStores(),PerformSplittingToNarrowingStores(),performSTORECombine(),llvm::TargetLowering::scalarizeVectorStore(),ShrinkLoadReplaceStoreWithStore(),llvm::AMDGPUTargetLowering::SplitVectorStore(), andllvm::HexagonDAGToDAGISel::StoreInstrForLoadIntrinsic().
| inline |
Definition at line1451 of fileSelectionDAG.h.
ReferencesgetEVTAlign(),getTruncStore(), andPtr.
SDValue SelectionDAG::getTruncStoreVP | ( | SDValue | Chain, |
constSDLoc & | dl, | ||
SDValue | Val, | ||
SDValue | Ptr, | ||
SDValue | Mask, | ||
SDValue | EVL, | ||
EVT | SVT, | ||
MachineMemOperand * | MMO, | ||
bool | IsCompressing =false | ||
) |
Definition at line9641 of fileSelectionDAG.cpp.
ReferencesAddNodeIDNode(),assert(),llvm::EVT::bitsLT(),llvm::MachinePointerInfo::getAddrSpace(),llvm::SDLoc::getDebugLoc(),llvm::MachineMemOperand::getFlags(),llvm::SDLoc::getIROrder(),llvm::MachineMemOperand::getPointerInfo(),llvm::EVT::getRawBits(),llvm::EVT::getScalarType(),getStoreVP(),getUNDEF(),llvm::SDValue::getValueType(),llvm::EVT::getVectorElementCount(),getVTList(),llvm::EVT::isInteger(),llvm::EVT::isVector(),N,NewSDValueDbgMsg(),Ptr, andllvm::ISD::UNINDEXED.
SDValue SelectionDAG::getTruncStoreVP | ( | SDValue | Chain, |
constSDLoc & | dl, | ||
SDValue | Val, | ||
SDValue | Ptr, | ||
SDValue | Mask, | ||
SDValue | EVL, | ||
MachinePointerInfo | PtrInfo, | ||
EVT | SVT, | ||
Align | Alignment, | ||
MachineMemOperand::Flags | MMOFlags, | ||
constAAMDNodes & | AAInfo, | ||
bool | IsCompressing =false | ||
) |
Definition at line9618 of fileSelectionDAG.cpp.
Referencesassert(),getMachineFunction(),llvm::MachineFunction::getMachineMemOperand(),llvm::EVT::getStoreSize(),getTruncStoreVP(),llvm::SDValue::getValueType(),InferPointerInfo(),llvm::PointerUnion< PTs >::isNull(),llvm::MachineMemOperand::MOLoad,llvm::MachineMemOperand::MOStore,llvm::LocationSize::precise(),Ptr, andllvm::MachinePointerInfo::V.
Referenced bygetTruncStoreVP().
SDValue SelectionDAG::getTruncStridedStoreVP | ( | SDValue | Chain, |
constSDLoc & | DL, | ||
SDValue | Val, | ||
SDValue | Ptr, | ||
SDValue | Stride, | ||
SDValue | Mask, | ||
SDValue | EVL, | ||
EVT | SVT, | ||
MachineMemOperand * | MMO, | ||
bool | IsCompressing =false | ||
) |
Definition at line9809 of fileSelectionDAG.cpp.
ReferencesAddNodeIDNode(),assert(),llvm::EVT::bitsLT(),DL,llvm::MachinePointerInfo::getAddrSpace(),llvm::MachineMemOperand::getPointerInfo(),llvm::EVT::getRawBits(),llvm::EVT::getScalarType(),getStridedStoreVP(),getUNDEF(),llvm::SDValue::getValueType(),llvm::EVT::getVectorElementCount(),getVTList(),llvm::EVT::isInteger(),llvm::EVT::isVector(),N,NewSDValueDbgMsg(),Ptr, andllvm::ISD::UNINDEXED.
Return an UNDEF node. UNDEF does not have a usefulSDLoc.
Definition at line1129 of fileSelectionDAG.h.
ReferencesgetNode(), andllvm::ISD::UNDEF.
Referenced byaddShuffleForVecExtend(),adjustLoadValueTypeImpl(),buildFromShuffleMostly(),buildMergeScalars(),buildScalarToVector(),llvm::TargetLowering::BuildUDIV(),canonicalizeShuffleMaskWithHorizOp(),collectConcatOps(),CollectOpsToWiden(),combineArithReduction(),combineBasicSADPattern(),combineBinOpToReduce(),combineBitcast(),combineBitcastToBoolVector(),combineBlendOfPermutes(),combineBVOfConsecutiveLoads(),combineConcatVectorOfConcatVectors(),combineConcatVectorOfExtracts(),combineConcatVectorOfShuffleAndItsOperands(),combineConcatVectorOps(),combineEXTRACT_SUBVECTOR(),combineExtractVectorElt(),combineExtractWithShuffle(),combineFP_EXTEND(),combineFP_TO_xINT_SAT(),combineI8TruncStore(),combineINSERT_SUBVECTOR(),combineLRINT_LLRINT(),combineMaskedLoadConstantMask(),combineSelect(),combineSetCCAtomicArith(),combineShuffleOfBitcast(),combineShuffleOfConcatUndef(),combineShuffleOfScalars(),combineShuffleOfSplatVal(),combineSVEReductionOrderedFP(),combineTargetShuffle(),combineToHorizontalAddSub(),combineTruncateWithSat(),combineTruncToVnclip(),combineVectorPack(),combineVPDPBUSDPattern(),combineX86ShuffleChain(),combineX86ShufflesRecursively(),combineXorSubCTLZ(),CompactSwizzlableVector(),concatSubVectors(),convertLocVTToValVT(),convertShiftLeftToScale(),convertToScalableVector(),createMMXBuildVector(),EltsFromConsecutiveLoads(),emitErrorAndReplaceIntrinsicResults(),emitIntrinsicWithChainErrorMessage(),emitNonHSAIntrinsicError(),emitRemovedIntrinsicError(),EmitTruncSStore(),ExpandBVWithShuffles(),ExpandHorizontalBinOp(),expandV4F32ToV2F64(),ExtendToType(),extractSubVector(),FoldBUILD_VECTOR(),foldCONCAT_VECTORS(),FoldConstantArithmetic(),foldConstantFPMath(),foldExtractSubvectorFromShuffleVector(),FoldSetCC(),getBuildDwordsVector(),getConstVector(),getCopyFromPartsVector(),getDeinterleaveShiftAndTrunc(),getExtLoad(),getExtLoadVP(),getExtStridedLoadVP(),getGeneralPermuteNode(),getHopForBuildVector(),getInvertedVectorForFMA(),getKnownUndefForVectorBinop(),getLoad(),getLoadVP(),getNode(),getShuffleHalfVectors(),getShuffleScalarElt(),getShuffleVectorZeroOrUndef(),getSplatSourceVector(),getStore(),getStridedLoadVP(),getTargetVShiftNode(),getTruncStore(),getTruncStoreVP(),getTruncStridedStoreVP(),llvm::VECustomDAG::getUNDEF(),llvm::SelectionDAGBuilder::getValueImpl(),getVectorShuffle(),getVectorShuffle(),getWideningInterleave(),insert1BitVector(),isAddSubOrSubAdd(),isFNEG(),isHopBuildVector(),isHorizontalBinOpPart(),joinDwords(),lower1BitShuffle(),LowerAsSplatVectorLoad(),lowerAtomicArith(),LowerAVXCONCAT_VECTORS(),LowerAVXExtend(),LowerBITCAST(),LowerBITREVERSE_XOP(),lowerBitreverseShuffle(),lowerBUILD_VECTOR(),LowerBUILD_VECTORvXi1(),lowerBuildVectorOfConstants(),LowerBuildVectorOfFPTrunc(),LowerBuildVectorv4x32(),lowerBuildVectorViaDominantValues(),llvm::SITargetLowering::LowerCall(),llvm::HexagonTargetLowering::LowerCONCAT_VECTORS(),LowerCONCAT_VECTORS(),LowerCONCAT_VECTORSvXi1(),LowerCTLZ(),LowerCTTZ(),lowerDisjointIndicesShuffle(),LowerEXTEND_VECTOR_INREG(),lowerFCMPIntrinsic(),LowerFLDEXP(),lowerFMAXIMUM_FMINIMUM(),llvm::R600TargetLowering::LowerFormalArguments(),llvm::SITargetLowering::LowerFormalArguments(),lowerFP_TO_INT_SAT(),llvm::AMDGPUTargetLowering::LowerGlobalAddress(),lowerICMPIntrinsic(),lowerINT_TO_FP_vXi64(),LowerINTRINSIC_W_CHAIN(),llvm::MipsTargetLowering::lowerLOAD(),LowerMSCATTER(),LowerMUL(),llvm::RISCVTargetLowering::LowerOperation(),LowerPredicateStore(),lowerReductionSeq(),LowerSCALAR_TO_VECTOR(),lowerScalarInsert(),lowerScalarSplat(),LowerShift(),LowerShiftByScalarImmediate(),lowerShuffleAsBlend(),lowerShuffleAsBlendAndPermute(),lowerShuffleAsBlendOfPSHUFBs(),lowerShuffleAsByteRotateAndPermute(),lowerShuffleAsDecomposedShuffleMerge(),lowerShuffleAsElementInsertion(),lowerShuffleAsLanePermuteAndPermute(),lowerShuffleAsLanePermuteAndShuffle(),lowerShuffleAsPermuteAndUnpack(),lowerShuffleAsRepeatedMaskAndLanePermute(),lowerShuffleAsSpecificZeroOrAnyExtend(),lowerShuffleAsUNPCKAndPermute(),lowerShuffleOfExtractsAsVperm(),lowerShuffleWithPSHUFB(),lowerShuffleWithSSE4A(),lowerShuffleWithUndefHalf(),lowerShuffleWithUNPCK256(),LowerSIGN_EXTEND_Mask(),llvm::SelectionDAGBuilder::LowerStatepoint(),LowerStore(),LowerTruncateVectorStore(),lowerUINT_TO_FP_v2i32(),lowerUINT_TO_FP_vXi32(),llvm::AMDGPUTargetLowering::lowerUnhandledCall(),lowerV16I8Shuffle(),lowerV2F64Shuffle(),lowerV2X128Shuffle(),lowerV4X128Shuffle(),lowerVECTOR_COMPRESS(),llvm::HexagonTargetLowering::LowerVECTOR_SHUFFLE(),LowerVECTOR_SHUFFLE(),lowerVECTOR_SHUFFLE(),LowerVECTOR_SHUFFLE_i1(),lowerVECTOR_SHUFFLE_VREPLVEI(),lowerVECTOR_SHUFFLE_XVREPLVEI(),lowerVECTOR_SHUFFLEAsVSlide1(),lowerVECTOR_SHUFFLEAsVSlidedown(),lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(),lowerVectorIntrinsicScalars(),lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND(),LowerZERO_EXTEND_Mask(),matchBinaryPermuteShuffle(),matchBinaryShuffle(),matchShuffleAsInsertPS(),matchShuffleWithUNPCK(),matchSplatAsGather(),NormalizeBuildVector(),padEltsToUndef(),partitionShuffleOfConcats(),llvm::SITargetLowering::passSpecialInputs(),PerformARMBUILD_VECTORCombine(),performBuildShuffleExtendCombine(),performBuildVectorCombine(),performConcatVectorsCombine(),llvm::R600TargetLowering::PerformDAGCombine(),llvm::RISCVTargetLowering::PerformDAGCombine(),performDupLane128Combine(),performLDNT1Combine(),performLOADCombine(),PerformMinMaxCombine(),llvm::ARMTargetLowering::PerformMVETruncCombine(),PerformSplittingMVEEXTToWideningLoad(),PerformSplittingToNarrowingStores(),PerformSplittingToWideningLoad(),performSTNT1Combine(),PerformTruncatingStoreCombine(),performUnpackCombine(),performUzpCombine(),PerformVECTOR_REG_CASTCombine(),PerformVECTOR_SHUFFLECombine(),performVECTOR_SHUFFLECombine(),llvm::RISCVDAGToDAGISel::PreprocessISelDAG(),llvm::AArch64TargetLowering::ReconstructShuffle(),ReconstructShuffleWithRuntimeMask(),ReplaceAddWithADDP(),ReplaceCMP_SWAP_64Results(),llvm::LoongArchTargetLowering::ReplaceNodeResults(),llvm::RISCVTargetLowering::ReplaceNodeResults(),llvm::X86TargetLowering::ReplaceNodeResults(),llvm::TargetLowering::SimplifyDemandedBits(),llvm::TargetLowering::SimplifyDemandedVectorElts(),llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(),simplifyDivRem(),simplifyFPBinop(),llvm::TargetLowering::SimplifyMultipleUseDemandedBits(),llvm::X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode(),simplifyShift(),splatPartsI64WithVL(),splitAndLowerShuffle(),llvm::RISCVTargetLowering::splitValueIntoRegisterParts(),llvm::AMDGPUTargetLowering::SplitVectorLoad(),truncateVectorWithPACK(),tryBuildVectorShuffle(),tryCombineMULLWithUZP1(),tryToFoldExtendOfConstant(),tryToReplaceScalarFPConversionWithSVE(),UnrollVectorOp(),UnrollVectorOverflowOp(),vectorizeExtractedCast(),widenSubVector(),widenVec(),WidenVector(),WidenVector(), andwidenVectorToPartType().
| inline |
Definition at line506 of fileSelectionDAG.h.
Referenced byllvm::FunctionLoweringInfo::set().
SDValue SelectionDAG::getVAArg | ( | EVT | VT, |
constSDLoc & | dl, | ||
SDValue | Chain, | ||
SDValue | Ptr, | ||
SDValue | SV, | ||
unsigned | Align | ||
) |
VAArg produces a result and token chain, and takes a pointer and a source value as input.
Definition at line10321 of fileSelectionDAG.cpp.
ReferencesgetNode(),getTargetConstant(),getVTList(),Ptr, andllvm::ISD::VAARG.
std::optional<uint64_t > SelectionDAG::getValidMaximumShiftAmount | ( | SDValue | V, |
constAPInt & | DemandedElts, | ||
unsigned | Depth =0 | ||
) | const |
If a SHL/SRA/SRL nodeV
has shift amounts that are all less than the element bit-width of the shift node, return the maximum possible value.
Definition at line3392 of fileSelectionDAG.cpp.
Referencesassert(),llvm::Depth,getValidShiftAmountRange(),llvm::ISD::SHL,llvm::ISD::SRA, andllvm::ISD::SRL.
Referenced bycanCreateUndefOrPoison(),getValidMaximumShiftAmount(),llvm::TargetLowering::SimplifyDemandedBits(), andllvm::TargetLowering::SimplifyMultipleUseDemandedBits().
std::optional<uint64_t > SelectionDAG::getValidMaximumShiftAmount | ( | SDValue | V, |
unsigned | Depth =0 | ||
) | const |
If a SHL/SRA/SRL nodeV
has shift amounts that are all less than the element bit-width of the shift node, return the maximum possible value.
Definition at line3404 of fileSelectionDAG.cpp.
Referencesllvm::Depth,llvm::APInt::getAllOnes(),getValidMaximumShiftAmount(),llvm::EVT::getVectorNumElements(), andllvm::EVT::isFixedLengthVector().
std::optional<uint64_t > SelectionDAG::getValidMinimumShiftAmount | ( | SDValue | V, |
constAPInt & | DemandedElts, | ||
unsigned | Depth =0 | ||
) | const |
If a SHL/SRA/SRL nodeV
has shift amounts that are all less than the element bit-width of the shift node, return the minimum possible value.
Definition at line3371 of fileSelectionDAG.cpp.
Referencesassert(),llvm::Depth,getValidShiftAmountRange(),llvm::ISD::SHL,llvm::ISD::SRA, andllvm::ISD::SRL.
Referenced bycomputeKnownBits(),ComputeNumSignBits(), andgetValidMinimumShiftAmount().
std::optional<uint64_t > SelectionDAG::getValidMinimumShiftAmount | ( | SDValue | V, |
unsigned | Depth =0 | ||
) | const |
If a SHL/SRA/SRL nodeV
has shift amounts that are all less than the element bit-width of the shift node, return the minimum possible value.
Definition at line3383 of fileSelectionDAG.cpp.
Referencesllvm::Depth,llvm::APInt::getAllOnes(),getValidMinimumShiftAmount(),llvm::EVT::getVectorNumElements(), andllvm::EVT::isFixedLengthVector().
std::optional<uint64_t > SelectionDAG::getValidShiftAmount | ( | SDValue | V, |
constAPInt & | DemandedElts, | ||
unsigned | Depth =0 | ||
) | const |
If a SHL/SRA/SRL nodeV
has a uniform shift amount that is less than the element bit-width of the shift node, return it.
Definition at line3349 of fileSelectionDAG.cpp.
Referencesassert(),llvm::Depth,getValidShiftAmountRange(),llvm::ISD::SHL,llvm::ISD::SRA, andllvm::ISD::SRL.
Referenced bycheckSignTestSetCCCombine(),getFauxShuffleMask(),getValidShiftAmount(),matchTruncateWithPACK(), andllvm::TargetLowering::SimplifyDemandedBits().
If a SHL/SRA/SRL nodeV
has a uniform shift amount that is less than the element bit-width of the shift node, return it.
Definition at line3362 of fileSelectionDAG.cpp.
Referencesllvm::Depth,llvm::APInt::getAllOnes(),getValidShiftAmount(),llvm::EVT::getVectorNumElements(), andllvm::EVT::isFixedLengthVector().
std::optional<ConstantRange > SelectionDAG::getValidShiftAmountRange | ( | SDValue | V, |
constAPInt & | DemandedElts, | ||
unsigned | Depth | ||
) | const |
If a SHL/SRA/SRL nodeV
has shift amounts that are all less than the element bit-width of the shift node, return the valid constant range.
Definition at line3300 of fileSelectionDAG.cpp.
Referencesassert(),llvm::BitWidth,computeKnownBits(),llvm::Depth,llvm::ConstantRange::fromKnownBits(),llvm::KnownBits::getMaxValue(),llvm::ISD::SHL,llvm::ISD::SRA,llvm::ISD::SRL,llvm::APInt::uge(),llvm::APInt::ugt(), andllvm::APInt::ult().
Referenced byComputeNumSignBits(),getValidMaximumShiftAmount(),getValidMinimumShiftAmount(), andgetValidShiftAmount().
Definition at line2038 of fileSelectionDAG.cpp.
Referencesllvm::EVT::getSimpleVT(),llvm::EVT::isExtended(),llvm::EVT::isSimple(),N, andllvm::MVT::SimpleTy.
Referenced byaddShuffleForVecExtend(),combineShiftRightArithmetic(),convertLocVTToValVT(),customLegalizeToWOpWithSExt(),emitRepmovs(),emitRepstos(),FoldConstantArithmetic(),getAArch64Cmp(),getCopyFromParts(),llvm::RegsForValue::getCopyFromRegs(),getNode(),LowerBUILD_VECTOR_i1(),llvm::VETargetLowering::LowerCall(),llvm::SparcTargetLowering::LowerCall_64(),llvm::SITargetLowering::LowerCallResult(),llvm::AMDGPUTargetLowering::LowerDIVREM24(),llvm::SITargetLowering::LowerFormalArguments(),llvm::VETargetLowering::LowerFormalArguments(),llvm::XtensaTargetLowering::LowerFormalArguments(),llvm::SparcTargetLowering::LowerFormalArguments_32(),llvm::SparcTargetLowering::LowerFormalArguments_64(),LowerFP_TO_INT_SAT(),LowerINSERT_VECTOR_ELT_i1(),lowerMSACopyIntr(),llvm::SelectionDAGBuilder::lowerRangeToAssertZExt(),llvm::MSP430TargetLowering::LowerShifts(),llvm::MSP430TargetLowering::LowerSIGN_EXTEND(),llvm::AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(),llvm::ARMTargetLowering::PerformCMOVCombine(),llvm::AMDGPUTargetLowering::PerformDAGCombine(),llvm::PPCTargetLowering::PerformDAGCombine(),performGatherLoadCombine(),performLD1Combine(),PerformMinMaxCombine(),PerformMinMaxFpToSatCombine(),llvm::ARMTargetLowering::PerformMVEExtCombine(),performScatterStoreCombine(),performSETCCCombine(),performSignExtendInRegCombine(),performSRACombine(),performST1Combine(),PerformUMinFpToSatCombine(),PromoteMaskArithmetic(),llvm::RISCVTargetLowering::ReplaceNodeResults(),llvm::X86TargetLowering::ReplaceNodeResults(),replaceVPICKVE2GRResults(),scalarizeExtractedBinOp(),llvm::TargetLowering::SimplifyDemandedBits(),llvm::X86TargetLowering::targetShrinkDemandedConstant(),truncateScalarIntegerArg(),truncateVectorWithPACKSS(),UnpackFromArgumentSlot(),UnrollVectorOp(), andunrollVectorShift().
Definition at line1824 of fileSelectionDAG.cpp.
ReferencesDL,getConstant(),getDataLayout(), andllvm::TargetLoweringBase::getVectorIdxTy().
Referenced bybuildFromShuffleMostly(),BuildVectorFromScalar(),CollectOpsToWiden(),combineArithReduction(),combineBinOpOfExtractToReduceTree(),combineBinOpToReduce(),combineBitcast(),combineBitcastToBoolVector(),combineCompareEqual(),combineConcatVectorOps(),combineEXTRACT_SUBVECTOR(),combineExtractFromVectorLoad(),combineExtractVectorElt(),combineExtractWithShuffle(),combineFP16_TO_FP(),combineFP_EXTEND(),combineFP_ROUND(),combineI8TruncStore(),combineINSERT_SUBVECTOR(),combineKSHIFT(),combineMinMaxReduction(),combineSelect(),combineTargetShuffle(),combineTruncateWithSat(),combineVectorSizedSetCCEquality(),convertIntLogicToFPLogic(),convertToScalableVector(),CustomNonLegalBITCASTResults(),detectPMADDUBSW(),EltsFromConsecutiveLoads(),llvm::TargetLowering::expandVECTOR_COMPRESS(),ExtendToType(),ExtractBitFromMaskVector(),extractSubVector(),ExtractVectorElements(),foldExtractSubvectorFromShuffleVector(),GeneratePerfectShuffle(),getCopyFromPartsVector(),getCopyToPartsVector(),getDataClassTest(),getDeinterleaveShiftAndTrunc(),getMaskNode(),getMemsetStores(),getNode(),getPartialReduceAdd(),getRVVFPReductionOpAndOperands(),getScalarMaskingNode(),getShuffleHalfVectors(),getSplatValue(),insert1BitVector(),insertSubVector(),llvm::RISCVTargetLowering::joinRegisterPartsIntoValue(),lower1BitShuffle(),lower1BitShuffleAsKSHIFTR(),lowerAddSubToHorizontalOp(),LowerAVXCONCAT_VECTORS(),LowerBITCAST(),LowerBITREVERSE(),LowerBITREVERSE_XOP(),lowerBitreverseShuffle(),lowerBUILD_VECTOR(),LowerBUILD_VECTORvXi1(),LowerBuildVectorAsInsert(),lowerBuildVectorOfConstants(),LowerBuildVectorv16i8(),lowerBuildVectorViaDominantValues(),LowerCONCAT_VECTORSvXi1(),LowerEXTRACT_SUBVECTOR(),LowerFABSorFNEG(),LowerFCOPYSIGN(),LowerFMINIMUM_FMAXIMUM(),LowerFP16_TO_FP(),LowerFP_TO_FP16(),lowerFPToIntToFP(),LowerFSINCOS(),LowerI64IntToFP16(),LowerI64IntToFP_AVX512DQ(),lowerINT_TO_FP_vXi64(),lowerLaneOp(),LowerLoad(),LowerMGATHER(),LowerMLOAD(),llvm::RISCVTargetLowering::LowerOperation(),lowerReductionSeq(),lowerScalarInsert(),lowerShuffleAsVTRUNCAndUnpack(),lowerShuffleOfExtractsAsVperm(),lowerShuffleWithUndefHalf(),LowerSIGN_EXTEND_Mask(),LowerStore(),LowerUINT_TO_FP_i32(),LowerUINT_TO_FP_i64(),lowerUINT_TO_FP_v2i32(),lowerUINT_TO_FP_vXi32(),lowerV2X128Shuffle(),lowerV4X128Shuffle(),lowerVECTOR_SHUFFLE(),LowerVECTOR_SHUFFLEUsingOneOff(),LowerZERO_EXTEND_Mask(),matchBinOpReduction(),matchPMADDWD_2(),matchSplatAsGather(),narrowExtractedVectorBinOp(),performBuildVectorCombine(),llvm::RISCVTargetLowering::PerformDAGCombine(),performINSERT_VECTOR_ELTCombine(),PerformInsertSubvectorCombine(),performInsertSubvectorCombine(),performLOADCombine(),performSunpkloCombine(),performTruncateCombine(),PerformVQDMULHCombine(),llvm::RISCVTargetLowering::ReplaceNodeResults(),llvm::X86TargetLowering::ReplaceNodeResults(),replaceShuffleOfInsert(),scalarizeBinOpOfSplats(),llvm::TargetLowering::scalarizeVectorStore(),scalarizeVectorStore(),SplitAndExtendv16i1(),llvm::RISCVTargetLowering::splitValueIntoRegisterParts(),llvm::AMDGPUTargetLowering::splitVector(),SplitVector(),llvm::AMDGPUTargetLowering::SplitVectorLoad(),tryToReplaceScalarFPConversionWithSVE(),UnrollVectorOp(),vectorizeExtractedCast(),llvm::AMDGPUTargetLowering::WidenOrSplitVectorLoad(),widenSubVector(),WidenVector(), andwidenVectorToPartType().
SDValue SelectionDAG::getVectorShuffle | ( | EVT | VT, |
constSDLoc & | dl, | ||
SDValue | N1, | ||
SDValue | N2, | ||
ArrayRef< int > | Mask | ||
) |
Return anISD::VECTOR_SHUFFLE node.
The number of elements in VT, which must be a vector type, must match the number of mask elements NumElts. An integer mask element equal to -1 is treated as undefined.
Definition at line2147 of fileSelectionDAG.cpp.
ReferencesAddNodeIDNode(),llvm::all_of(),llvm::BumpPtrAllocatorImpl< AllocatorT, SlabSize, SizeThreshold, GrowthDelay >::Allocate(),assert(),llvm::ISD::BITCAST,commuteShuffle(),llvm::copy(),llvm::SDLoc::getDebugLoc(),llvm::SDLoc::getIROrder(),getNode(),llvm::SDNode::getOperand(),getSplatBuildVector(),llvm::BuildVectorSDNode::getSplatValue(),getUNDEF(),llvm::SDValue::getValueType(),llvm::EVT::getVectorNumElements(),getVTList(),llvm::TargetLoweringBase::hasVectorBlend(),llvm::isNullConstant(),llvm::SDValue::isUndef(),N,NewSDValueDbgMsg(),llvm::BitVector::none(),llvm::Offset,llvm::Splat, andllvm::ISD::VECTOR_SHUFFLE.
Referenced byaddShuffleForVecExtend(),buildFromShuffleMostly(),llvm::TargetLowering::buildLegalVectorShuffle(),BuildVSLDOI(),combineAddOfPMADDWD(),combineAndShuffleNot(),combineArithReduction(),combineBasicSADPattern(),combineBITREVERSE(),combineBlendOfPermutes(),combineBVOfConsecutiveLoads(),combineConcatVectorOfShuffleAndItsOperands(),combineConcatVectorOps(),combineFP_ROUND(),combineHorizOpWithShuffle(),combineINSERT_SUBVECTOR(),combineMinMaxReduction(),combinePMULDQ(),combineSelect(),combineShuffleOfBitcast(),combineShuffleOfConcatUndef(),combineShuffleOfSplatVal(),combineSIntToFP(),combineToExtendBoolVectorInReg(),combineToHorizontalAddSub(),combineVPDPBUSDPattern(),createVariablePermute(),EltsFromConsecutiveLoads(),ExpandBVWithShuffles(),expandV4F32ToV2F64(),foldExtractSubvectorFromShuffleVector(),foldShuffleOfConcatUndefs(),formSplatFromShuffles(),GeneratePerfectShuffle(),getCommutedVectorShuffle(),getPack(),getShuffleHalfVectors(),getShuffleVectorZeroOrUndef(),getSToVPermuted(),getTargetVShiftNode(),getVectorShuffle(),isFNEG(),lower128BitShuffle(),lower1BitShuffle(),lower256BitShuffle(),lower512BitShuffle(),LowerAsSplatVectorLoad(),LowerBuildVectorv4x32(),LowerConvertLow(),lowerDisjointIndicesShuffle(),LowerEXTEND_VECTOR_INREG(),LowerMUL(),LowerMULH(),LowerReverse_VECTOR_SHUFFLE(),LowerRotate(),LowerShift(),LowerShiftByScalarImmediate(),LowerShiftByScalarVariable(),lowerShuffleAsBlend(),lowerShuffleAsBlendAndPermute(),lowerShuffleAsBroadcast(),lowerShuffleAsByteRotateAndPermute(),lowerShuffleAsDecomposedShuffleMerge(),lowerShuffleAsElementInsertion(),lowerShuffleAsLanePermuteAndPermute(),lowerShuffleAsLanePermuteAndRepeatedMask(),lowerShuffleAsLanePermuteAndShuffle(),lowerShuffleAsLanePermuteAndSHUFP(),lowerShuffleAsPermuteAndUnpack(),lowerShuffleAsRepeatedMaskAndLanePermute(),lowerShuffleAsSpecificZeroOrAnyExtend(),lowerShuffleAsUNPCKAndPermute(),lowerShuffleAsVTRUNCAndUnpack(),lowerShuffleOfExtractsAsVperm(),lowerShuffleWithUNPCK256(),LowerSIGN_EXTEND(),lowerToAddSubOrFMAddSub(),LowerTruncateVecI1(),LowerUINT_TO_FP_i64(),lowerV16I8Shuffle(),lowerV2I64Shuffle(),lowerV4I32Shuffle(),lowerV8F16Shuffle(),lowerVECTOR_SHUFFLE(),LowerVECTOR_SHUFFLE_i1(),LowerVECTOR_SHUFFLEUsingMovs(),lowerVSELECTtoVectorShuffle(),LowerVSETCC(),partitionShuffleOfConcats(),performBuildShuffleExtendCombine(),performConcatVectorsCombine(),llvm::RISCVTargetLowering::PerformDAGCombine(),performExtBinopLoadFold(),performSelectCombine(),PerformTruncatingStoreCombine(),PerformVECTOR_SHUFFLECombine(),performVECTOR_SHUFFLECombine(),PerformVQDMULHCombine(),llvm::AArch64TargetLowering::ReconstructShuffle(),reduceVMULWidth(),ReplaceAddWithADDP(),llvm::X86TargetLowering::ReplaceNodeResults(),llvm::TargetLowering::SimplifyDemandedBits(),splitAndLowerShuffle(),truncateVectorWithPACK(),tryWidenMaskForShuffle(), andvectorizeExtractedCast().
Create a vector-predicated logical NOT operation as (VP_XOR Val, BooleanOne, Mask, EVL).
Definition at line1631 of fileSelectionDAG.cpp.
ReferencesDL,getBoolConstant(), andgetNode().
SDValue SelectionDAG::getVPPtrExtOrTrunc | ( | constSDLoc & | DL, |
EVT | VT, | ||
SDValue | Op, | ||
SDValue | Mask, | ||
SDValue | EVL | ||
) |
Convert a vector-predicated Op, which must be of integer type, to the vector-type integer type VT, by either truncating it or performing either vector-predicated zero or sign extension as appropriate extension for the pointer's semantics.
This function just redirects to getVPZExtOrTrunc right now.
Definition at line1637 of fileSelectionDAG.cpp.
ReferencesDL, andgetVPZExtOrTrunc().
SDValue SelectionDAG::getVPZeroExtendInReg | ( | SDValue | Op, |
SDValue | Mask, | ||
SDValue | EVL, | ||
constSDLoc & | DL, | ||
EVT | VT | ||
) |
Return the expression required to zero extend the Op value assuming it was the smaller SrcTy value.
Definition at line1586 of fileSelectionDAG.cpp.
Referencesassert(),llvm::EVT::bitsLE(),DL,getConstant(),llvm::APInt::getLowBitsSet(),getNode(),llvm::EVT::getScalarSizeInBits(),llvm::EVT::getVectorElementCount(),llvm::EVT::isInteger(), andllvm::EVT::isVector().
Convert a vector-predicated Op, which must be an integer vector, to the vector-type VT, by performing either vector-predicated zext or truncating it.
The Op will be returned as-is if Op and VT are vectors containing integer with same width.
Definition at line1642 of fileSelectionDAG.cpp.
Referencesllvm::EVT::bitsGT(),llvm::EVT::bitsLT(),DL, andgetNode().
Referenced bygetVPPtrExtOrTrunc().
SDDbgValue * SelectionDAG::getVRegDbgValue | ( | DIVariable * | Var, |
DIExpression * | Expr, | ||
unsigned | VReg, | ||
bool | IsIndirect, | ||
constDebugLoc & | DL, | ||
unsigned | O | ||
) |
Creates a VRegSDDbgValue node.
VReg.
Definition at line11377 of fileSelectionDAG.cpp.
Referencesassert(),DL,llvm::SDDbgOperand::fromVReg(), andllvm::SDDbgInfo::getAlloc().
Referenced byllvm::SelectionDAGBuilder::handleDebugValue().
Return a node that represents the runtime scaling 'MulImm * RuntimeVL'.
Definition at line2092 of fileSelectionDAG.cpp.
Referencesassert(),llvm::CallingConv::C,DL,F,llvm::APInt::getBitWidth(),getConstant(),llvm::MachineFunction::getFunction(),getMachineFunction(),getNode(),llvm::ConstantRange::getSingleElement(),llvm::EVT::getSizeInBits(),llvm::getVScaleRange(), andllvm::ISD::VSCALE.
Referenced byclampDynamicVectorIndex(),llvm::TargetLowering::expandVectorSplice(),GenerateFixedLengthSVETBL(),getElementCount(),getMemBasePlusOffset(),getNode(),llvm::SelectionDAGBuilder::getValueImpl(),llvm::TargetLowering::getVectorSubVecPointer(),llvm::TargetLowering::IncrementMemoryAddress(), andSplitEVL().
Definition at line10775 of fileSelectionDAG.cpp.
Referencesllvm::BumpPtrAllocatorImpl< AllocatorT, SlabSize, SizeThreshold, GrowthDelay >::Allocate(),llvm::copy(), andllvm::ArrayRef< T >::size().
Return anSDVTList that represents the list of values specified.
Definition at line10708 of fileSelectionDAG.cpp.
Referencesllvm::EVT::getSimpleVT(),llvm::EVT::isExtended(), andmakeVTList().
Referenced byAddCombineTo64bitMLAL(),AddCombineTo64BitSMLAL16(),AddCombineTo64bitUMAAL(),llvm::X86TargetLowering::BuildFILD(),llvm::TargetLowering::BuildSDIV(),llvm::TargetLowering::BuildUDIV(),llvm::AArch64TargetLowering::changeStreamingMode(),CloneNodeWithValues(),combineADC(),combineAddOrSubToADCOrSBB(),combineADDToADDZE(),combineADDX(),combineBitcast(),combineBitcastToBoolVector(),combineBVZEXTLOAD(),combineCMov(),combineCMP(),combineINSERT_SUBVECTOR(),combineSBB(),combineSetCC(),combineStore(),combineSubSetcc(),combineSUBX(),combineSVEPrefetchVecBaseImmOff(),combineTargetShuffle(),CombineVLDDUP(),combineX86AddSub(),combineXorSubCTLZ(),ConvertBooleanCarryToCarryFlag(),ConvertCarryFlagToBooleanCarry(),convertFPToInt(),convertIntToFP(),createLoadLR(),createMemMemNode(),createSetFPEnvNodes(),createStoreLR(),EltsFromConsecutiveLoads(),EmitCmp(),emitCmp(),emitComparison(),emitIntrinsicWithCCAndChain(),EmitMaskedTruncSStore(),emitRepmovs(),emitRepstos(),llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemchr(),llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(),llvm::BPFSelectionDAGInfo::EmitTargetCodeForMemcpy(),llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrcmp(),llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrcpy(),EmitTest(),EmitTruncSStore(),EmitUnrolledSetTag(),Expand64BitShift(),llvm::TargetLowering::expandABD(),llvm::TargetLowering::expandAddSubSat(),llvm::TargetLowering::expandAVG(),llvm::TargetLowering::expandDIVREMByConstant(),llvm::TargetLowering::expandFixedPointDiv(),llvm::TargetLowering::expandFixedPointMul(),llvm::TargetLowering::expandIntMINMAX(),expandIntrinsicWChainHelper(),llvm::TargetLowering::expandMUL_LOHI(),llvm::TargetLowering::expandMULO(),ExpandREAD_REGISTER(),llvm::TargetLowering::expandREM(),expandV4F32ToV2F64(),llvm::PPCTargetLowering::expandVSXLoadForLE(),llvm::PPCTargetLowering::expandVSXStoreForLE(),llvm::HexagonDAGToDAGISel::FastFDiv(),llvm::HexagonDAGToDAGISel::FDiv(),FixupMMXIntrinsicTypes(),foldAndOrOfSETCC(),GeneratePerfectShuffle(),getAArch64XALUOOp(),llvm::MipsTargetLowering::getAddrGPRel(),getAddrSpaceCast(),getAssertAlign(),getAtomic(),getAVX2GatherNode(),getBasicBlock(),getBlockAddress(),getBoundedStrlen(),getBROADCAST_LOAD(),getCALLSEQ_END(),getCALLSEQ_START(),getConstant(),getConstantFP(),getConstantPool(),getCopyFromParts(),getCopyFromReg(),llvm::RegsForValue::getCopyFromRegs(),getCopyToReg(),llvm::HexagonTargetLowering::GetDynamicTLSAddr(),getExternalSymbol(),getFlagsOfCmpZeroFori1(),getFPBinOp(),getFPTernOp(),getFrameIndex(),getGatherNode(),getGetFPEnv(),getGlobalAddress(),getIndexedStore(),getIndexedStoreVP(),getInvertedVectorForFMA(),getJumpTable(),getLabelNode(),getLifetimeNode(),getLoad(),getLoadVP(),getMachineNode(),getMad64_32(),getMaskedLoad(),getMaskedStore(),getMCSymbol(),getMDNode(),getMergeValues(),getNode(),getPseudoProbeNode(),getRegister(),getRegisterMask(),getScatterNode(),getSetFPEnv(),getSrcValue(),getStore(),getStoreVP(),getStridedLoadVP(),getStridedStoreVP(),getTargetExternalSymbol(),GetTLSADDR(),getTruncStore(),getTruncStoreVP(),getTruncStridedStoreVP(),getVAArg(),getVCIXISDNodeWCHAIN(),getVectorShuffle(),getX86XALUOOp(),llvm::RISCVTargetLowering::joinRegisterPartsIntoValue(),legalizeSVEGatherPrefetchOffsVec(),LowerABD(),LowerABS(),LowerADDSAT_SUBSAT(),LowerADDSUBO_CARRY(),lowerADDSUBO_CARRY(),llvm::SelectionDAGBuilder::LowerAsSTATEPOINT(),LowerATOMIC_STORE(),llvm::VETargetLowering::lowerATOMIC_SWAP(),lowerAtomicArithWithLOCK(),LowerBUILD_VECTORToVIDUP(),lowerBuildVectorAsBroadcast(),llvm::NVPTXTargetLowering::LowerCall(),llvm::SystemZTargetLowering::LowerCall(),llvm::XtensaTargetLowering::LowerCall(),llvm::LoongArchTargetLowering::LowerCall(),llvm::RISCVTargetLowering::LowerCall(),llvm::VETargetLowering::LowerCall(),llvm::SparcTargetLowering::LowerCall_32(),llvm::SparcTargetLowering::LowerCall_64(),LowerCallResult(),llvm::TargetLowering::LowerCallTo(),LowerCMP_SWAP(),LowerCTLZ(),LowerCTTZ(),llvm::HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(),llvm::VETargetLowering::lowerEH_SJLJ_SETJMP(),LowerFSINCOS(),llvm::SITargetLowering::lowerGET_FPENV(),llvm::SparcTargetLowering::LowerGlobalTLSAddress(),LowerINTRINSIC_W_CHAIN(),LowerMGATHER(),LowerMSCATTER(),LowerMULO(),llvm::RISCVTargetLowering::LowerOperation(),llvm::SystemZTargetLowering::LowerOperationWrapper(),lowerOverflowArithmetic(),LowerPARITY(),llvm::HexagonTargetLowering::LowerREADCYCLECOUNTER(),llvm::HexagonTargetLowering::LowerREADSTEADYCOUNTER(),llvm::NVPTXTargetLowering::LowerReturn(),llvm::RISCVTargetLowering::LowerReturn(),llvm::AMDGPUTargetLowering::LowerSDIVREM(),LowerSELECTWithCmpZero(),LowerSETCCCARRY(),lowerShuffleAsBroadcast(),LowerStore(),LowerSTORE(),llvm::VETargetLowering::lowerToTLSGeneralDynamicModel(),LowerUADDSUBO_CARRY(),llvm::AMDGPUTargetLowering::LowerUDIVREM64(),lowerUINT_TO_FP_vXi32(),LowerUnalignedLoadRetParam(),LowerUnalignedStoreParam(),LowerUnalignedStoreRet(),LowerVECTOR_SHUFFLE(),lowerVECTOR_SHUFFLE(),LowerVectorExtend(),lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND(),LowerXALUO(),llvm::AMDGPUDAGToDAGISel::matchLoadD16FromBuildVector(),mutateStrictFPToFP(),narrowLoadToVZLoad(),PerformADDVecReduce(),llvm::ARMTargetLowering::PerformCMOVCombine(),performCONDCombine(),llvm::AArch64TargetLowering::PerformDAGCombine(),llvm::PPCTargetLowering::PerformDAGCombine(),llvm::RISCVTargetLowering::PerformDAGCombine(),performDUPCombine(),PerformExtractFpToIntStores(),performFlagSettingCombine(),performGatherLoadCombine(),PerformHWLoopCombine(),performLD1Combine(),performMaskedGatherScatterCombine(),PerformMVEVLDCombine(),performNEONPostLDSTCombine(),performPostLD1Combine(),performScatterStoreCombine(),PerformSETCCCombine(),performSignExtendInRegCombine(),PerformUMLALCombine(),PerformVDUPCombine(),PerformVECREDUCE_ADDCombine(),PerformVMOVhrCombine(),llvm::RISCVDAGToDAGISel::PreprocessISelDAG(),reassociateCSELOperandsForCSE(),ReplaceATOMIC_LOAD_128Results(),ReplaceCMP_SWAP_128Results(),ReplaceCMP_SWAP_64Results(),replaceCMP_XCHG_128Results(),ReplaceINTRINSIC_W_CHAIN(),ReplaceLoadVector(),ReplaceLongIntrinsic(),llvm::SITargetLowering::ReplaceNodeResults(),llvm::PPCTargetLowering::ReplaceNodeResults(),llvm::RISCVTargetLowering::ReplaceNodeResults(),llvm::X86TargetLowering::ReplaceNodeResults(),ReplaceREADCYCLECOUNTER(),llvm::AMDGPUDAGToDAGISel::Select(),llvm::SelectionDAGISel::SelectCodeCommon(),llvm::HexagonDAGToDAGISel::SelectHVXDualOutput(),SelectNodeTo(),llvm::HexagonDAGToDAGISel::SelectTypecast(),llvm::HexagonDAGToDAGISel::SelectV65Gather(),llvm::HexagonDAGToDAGISel::SelectV65GatherPred(),llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(),llvm::TargetLowering::SimplifySetCC(),SplitStrictFPVectorOp(),TryCombineBaseUpdate(),tryMemPairCombine(),tryToWidenSetCCOperands(),UnrollVectorOverflowOp(),valueToCarryFlag(),llvm::X86TargetLowering::visitMaskedLoad(),llvm::X86TargetLowering::visitMaskedStore(), andwidenVectorOpsToi8().
Definition at line10715 of fileSelectionDAG.cpp.
Referencesllvm::BumpPtrAllocatorImpl< AllocatorT, SlabSize, SizeThreshold, GrowthDelay >::Allocate(), andllvm::EVT::getRawBits().
Definition at line10733 of fileSelectionDAG.cpp.
Referencesllvm::BumpPtrAllocatorImpl< AllocatorT, SlabSize, SizeThreshold, GrowthDelay >::Allocate(), andllvm::EVT::getRawBits().
Definition at line10753 of fileSelectionDAG.cpp.
Referencesllvm::BumpPtrAllocatorImpl< AllocatorT, SlabSize, SizeThreshold, GrowthDelay >::Allocate(), andllvm::EVT::getRawBits().
Return the expression required to zero extend the Op value assuming it was the smaller SrcTy value.
Definition at line1568 of fileSelectionDAG.cpp.
Referencesllvm::ISD::AND,assert(),llvm::EVT::bitsLE(),DL,getConstant(),llvm::APInt::getLowBitsSet(),getNode(),llvm::EVT::getScalarSizeInBits(),llvm::EVT::getVectorElementCount(),llvm::EVT::isInteger(), andllvm::EVT::isVector().
Referenced bycombineExtSetcc(),combineStore(),getPtrExtendInReg(),lowerFP_TO_INT_SAT(),llvm::MSP430TargetLowering::LowerShifts(),LowerStore(),llvm::AMDGPUTargetLowering::PerformDAGCombine(),performFP_TO_INT_SATCombine(),llvm::ARMTargetLowering::PerformMVEExtCombine(),PromoteMaskArithmetic(),scalarizeExtractedBinOp(),llvm::TargetLowering::SimplifyDemandedBits(),truncateVectorWithPACKUS(), andtryFoldMADwithSRL().
Convert Op, which must be of integer type, to the integer type VT, by either zero-extending or truncating it.
Definition at line1508 of fileSelectionDAG.cpp.
Referencesllvm::EVT::bitsGT(),DL,getNode(),llvm::ISD::TRUNCATE, andllvm::ISD::ZERO_EXTEND.
Referenced bycombineAnd(),combineAndLoadToBZHI(),combineBitcast(),combineBitcastvxi1(),combineBoolVectorAndTruncateStore(),combineCompareEqual(),combineExtractVectorElt(),combineExtractWithShuffle(),combineOr(),combinePredicateReduction(),combineSCALAR_TO_VECTOR(),combineScalarAndWithMaskSetcc(),combineScalarCTPOPToVCPOP(),combineSelect(),combineSetCC(),combineSetCCMOVMSK(),combineShiftAnd1ToBitTest(),combineShuffleOfScalars(),combineXor(),createVariablePermute(),createVPDPBUSD(),earlyExpandDIVFIX(),emitMemMemReg(),llvm::AArch64SelectionDAGInfo::EmitStreamingCompatibleMemLibCall(),llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemchr(),llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(),llvm::WebAssemblySelectionDAGInfo::EmitTargetCodeForMemcpy(),llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemset(),llvm::WebAssemblySelectionDAGInfo::EmitTargetCodeForMemset(),llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrnlen(),Expand64BitShift(),expandDivFix(),llvm::TargetLowering::expandDIVREMByConstant(),llvm::TargetLowering::expandFP_TO_SINT(),llvm::TargetLowering::expandVectorFindLastActive(),llvm::TargetLowering::expandVPCTTZElements(),foldAddSubBoolOfMaskedVal(),foldCONCAT_VECTORS(),foldMaskAndShiftToExtract(),foldMaskAndShiftToScale(),foldMaskedShiftToBEXTR(),foldSelectOfCTTZOrCTLZ(),getBitcastedZExtOrTrunc(),getExtOrTrunc(),getFlagsOfCmpZeroFori1(),getPTest(),getPtrExtOrTrunc(),getShiftAmountOperand(),getTargetVShiftNode(),llvm::TargetLowering::getVectorSubVecPointer(),llvm::TargetLowering::IncrementMemoryAddress(),llvm::TargetLowering::LegalizeSetCCCondCode(),lowerBALLOTIntrinsic(),LowerBITCAST(),llvm::HexagonTargetLowering::LowerBITCAST(),lowerBuildVectorToBitOp(),LowerBuildVectorv16i8(),LowerCTPOP(),llvm::NVPTXTargetLowering::LowerDYNAMIC_STACKALLOC(),lowerFCMPIntrinsic(),LowerFGETSIGN(),llvm::AMDGPUTargetLowering::LowerFP_TO_FP16(),LowerFunnelShift(),lowerICMPIntrinsic(),LowerINTRINSIC_W_CHAIN(),llvm::HexagonTargetLowering::LowerLoad(),llvm::SystemZTargetLowering::LowerOperationWrapper(),LowerShift(),llvm::HexagonTargetLowering::LowerVECTOR_SHIFT(),LowervXi8MulWithUNPCK(),lowerX86CmpEqZeroToCtlzSrl(),performBitcastCombine(),llvm::AArch64TargetLowering::PerformDAGCombine(),llvm::HexagonTargetLowering::PerformDAGCombine(),llvm::PPCTargetLowering::PerformDAGCombine(),performExtractVectorEltCombine(),llvm::AMDGPUTargetLowering::performMulCombine(),llvm::AMDGPUTargetLowering::performMulhuCombine(),llvm::AMDGPUTargetLowering::performMulLoHiCombine(),performSETCCCombine(),llvm::AMDGPUTargetLowering::performShlCombine(),llvm::AMDGPUTargetLowering::performTruncateCombine(),PerformUMinFpToSatCombine(),PerformVSetCCToVCTPCombine(),replaceBoolVectorBitcast(),llvm::X86TargetLowering::ReplaceNodeResults(),takeInexpensiveLog2(),tryCombineWhileLo(),llvm::SelectionDAGBuilder::visitBitTestHeader(),llvm::SelectionDAGBuilder::visitJumpTableHeader(),visitORCommutative(),widenAbs(), andwidenCtPop().
| inline |
Return true if there are anySDDbgValue nodes associated with thisSelectionDAG.
Definition at line1872 of fileSelectionDAG.h.
Referencesllvm::SDDbgInfo::empty().
Referenced byllvm::ScheduleDAGSDNodes::EmitSchedule().
Return true if A and B have no common bits set.
As an example, this can allow an 'add' to be transformed into an 'or'.
Definition at line6041 of fileSelectionDAG.cpp.
ReferencesA,assert(),B,computeKnownBits(),llvm::KnownBits::haveNoCommonBitsSet(), andhaveNoCommonBitsSetCommutative().
Referenced bygetPointerConstIncrement(), andisADDLike().
MaybeAlign SelectionDAG::InferPtrAlign | ( | SDValue | Ptr | ) | const |
Infer alignment of a load / store address.
InferPtrAlignment - Infer alignment of a load / store address.
Return std::nullopt if it cannot be inferred.
Definition at line12910 of fileSelectionDAG.cpp.
Referencesllvm::commonAlignment(),llvm::computeKnownBits(),llvm::KnownBits::countMinTrailingZeros(),getDataLayout(),llvm::MachineFunction::getFrameInfo(),getMachineFunction(),llvm::MachineFrameInfo::getObjectAlign(),llvm::DataLayout::getPointerTypeSizeInBits(),llvm::GlobalValue::getType(),isBaseWithConstantOffset(),llvm::TargetLowering::isGAPlusOffset(), andPtr.
Referenced bygetMemcpyLoadsAndStores(),getMemmoveLoadsAndStores(), andLowerAsSplatVectorLoad().
| inline |
Definition at line475 of fileSelectionDAG.h.
Referencesinit().
void SelectionDAG::init | ( | MachineFunction & | NewMF, |
OptimizationRemarkEmitter & | NewORE, | ||
Pass * | PassPtr, | ||
constTargetLibraryInfo * | LibraryInfo, | ||
UniformityInfo * | UA, | ||
ProfileSummaryInfo * | PSIin, | ||
BlockFrequencyInfo * | BFIin, | ||
MachineModuleInfo & | MMI, | ||
FunctionVarLocsconst * | FnVarLocs | ||
) |
Prepare thisSelectionDAG to process code in the givenMachineFunction.
Definition at line1374 of fileSelectionDAG.cpp.
Referencesllvm::Function::getContext(),llvm::MachineFunction::getFunction(),llvm::TargetSubtargetInfo::getSelectionDAGInfo(),getSubtarget(), andllvm::TargetSubtargetInfo::getTargetLowering().
Referenced byinit(), andllvm::SelectionDAGISel::initializeAnalysisResults().
Return true if the specified operand is anISD::OR orISD::XOR node that can be treated as anISD::ADD node.
or(x,y) == add(x,y) iff haveNoCommonBitsSet(x,y) xor(x,y) == add(x,y) iff isMinSignedConstant(y) && !NoWrap IfNoWrap
is true, this will not matchISD::XOR.
Definition at line5657 of fileSelectionDAG.cpp.
ReferenceshaveNoCommonBitsSet(),llvm::isMinSignedConstant(),llvm::ISD::OR, andllvm::ISD::XOR.
Referenced byisBaseWithConstantOffset().
Return true if the specified operand is anISD::ADD with aConstantSDNode on the right-hand side, or if it is anISD::OR with aConstantSDNode that is guaranteed to have the same semantics as an ADD.
This handles the equivalence: X|Cst == X+Cst iff X&Cst = 0.
Definition at line5667 of fileSelectionDAG.cpp.
Referencesllvm::ISD::ADD,llvm::DWARFExpression::Operation::getNumOperands(), andisADDLike().
Referenced bygetBaseWithConstantOffset(),getBaseWithOffsetUsingSplitOR(),InferPtrAlign(),llvm::SITargetLowering::isReassocProfitable(),LowerAsSplatVectorLoad(),replaceZeroVectorStore(),llvm::RISCVDAGToDAGISel::SelectAddrRegImm(),llvm::LoongArchDAGToDAGISel::SelectAddrRegImm12(),llvm::RISCVDAGToDAGISel::SelectAddrRegImmLsb00000(), andllvm::LoongArchDAGToDAGISel::SelectInlineAsmMemoryOperand().
Check if a value \op N is a constant using the target's BooleanContent for its type.
Definition at line13477 of fileSelectionDAG.cpp.
Referencesllvm::TargetLoweringBase::getBooleanContents(),llvm::APInt::isAllOnes(),llvm::isConstOrConstSplat(),llvm::APInt::isOne(),llvm::APInt::isZero(),llvm_unreachable,N,llvm::TargetLoweringBase::UndefinedBooleanContent,llvm::TargetLoweringBase::ZeroOrNegativeOneBooleanContent, andllvm::TargetLoweringBase::ZeroOrOneBooleanContent.
Referenced byextractBooleanFlip(), andsimplifySelect().
Test whether the given value is a constant FP or similar node.
Definition at line13463 of fileSelectionDAG.cpp.
Referencesllvm::ISD::isBuildVectorOfConstantFPSDNodes(),N, andllvm::ISD::SPLAT_VECTOR.
Referenced bycanonicalizeCommutativeBinop(), andisConstantValueOfAnyType().
Test whether the given value is a constant int or similar node.
Definition at line13439 of fileSelectionDAG.cpp.
Referencesllvm::CallingConv::C,llvm::ISD::GlobalAddress,llvm::ISD::isBuildVectorOfConstantSDNodes(),llvm::TargetLowering::isOffsetFoldingLegal(),N,llvm::peekThroughBitcasts(), andllvm::ISD::SPLAT_VECTOR.
Referenced bycanonicalizeCommutativeBinop(),combineAndNotOrIntoAndNotAnd(),combinePMULDQ(),combineSetCC(),combineSub(),foldAddSubOfSignBit(),isConstantValueOfAnyType(),performSubAddMULCombine(),llvm::TargetLowering::SimplifySetCC(), andstripConstantMask().
N
is any kind of constant or build_vector of constants, int or float. If a vector, it may not necessarily be a splat.Definition at line2334 of fileSelectionDAG.h.
ReferencesisConstantFPBuildVectorOrConstantFP(),isConstantIntBuildVectorOrConstantInt(), andN.
Referenced byllvm::AMDGPUTargetLowering::performSelectCombine(), andsimplifySelect().
Test whether two SDValues are known to compare equal.
This is true if they are the same value, or if one is negative zero and the other positive zero.
Definition at line5975 of fileSelectionDAG.cpp.
Referenced bycombineSelect().
| inline |
Return true if this function can prove thatOp
is never poison.
The DemandedElts argument limits the check to the requested vector elements.
Definition at line2101 of fileSelectionDAG.h.
Referencesllvm::Depth, andisGuaranteedNotToBeUndefOrPoison().
Return true if this function can prove thatOp
is never poison.
Definition at line2095 of fileSelectionDAG.h.
Referencesllvm::Depth, andisGuaranteedNotToBeUndefOrPoison().
bool SelectionDAG::isGuaranteedNotToBeUndefOrPoison | ( | SDValue | Op, |
bool | PoisonOnly =false , | ||
unsigned | Depth =0 | ||
) | const |
Return true if this function can prove thatOp
is never poison and, ifPoisonOnly
is false, does not have undef bits.
Definition at line5430 of fileSelectionDAG.cpp.
Referencesllvm::Depth,llvm::ISD::FREEZE,llvm::APInt::getAllOnes(),llvm::EVT::getVectorNumElements(),llvm::EVT::isFixedLengthVector(),isGuaranteedNotToBeUndefOrPoison(), andPoisonOnly.
Referenced bycanCreateUndefOrPoison(),computeKnownBits(),getNode(),isGuaranteedNotToBePoison(),isGuaranteedNotToBeUndefOrPoison(),llvm::X86TargetLowering::isGuaranteedNotToBeUndefOrPoisonForTargetNode(),llvm::TargetLowering::SimplifyDemandedVectorElts(), andllvm::TargetLowering::SimplifyMultipleUseDemandedBits().
bool SelectionDAG::isGuaranteedNotToBeUndefOrPoison | ( | SDValue | Op, |
constAPInt & | DemandedElts, | ||
bool | PoisonOnly =false , | ||
unsigned | Depth =0 | ||
) | const |
Return true if this function can prove thatOp
is never poison and, ifPoisonOnly
is false, does not have undef bits.
The DemandedElts argument limits the check to the requested vector elements.
Definition at line5443 of fileSelectionDAG.cpp.
Referencesllvm::all_of(),llvm::ISD::BUILD_VECTOR,llvm::ISD::BUILTIN_OP_END,canCreateUndefOrPoison(),llvm::ISD::CONDCODE,llvm::ISD::CopyFromReg,llvm::Depth,llvm::ISD::FrameIndex,llvm::ISD::FREEZE,llvm::APInt::getBitWidth(),llvm::DWARFExpression::Operation::getNumOperands(),llvm::getShuffleDemandedElts(),llvm::ISD::INTRINSIC_VOID,llvm::ISD::INTRINSIC_W_CHAIN,llvm::ISD::INTRINSIC_WO_CHAIN,isGuaranteedNotToBeUndefOrPoison(),llvm::TargetLowering::isGuaranteedNotToBeUndefOrPoisonForTargetNode(),llvm::isIntOrFPConstant(),llvm::APInt::isZero(),MaxRecursionDepth,PoisonOnly,llvm::ISD::SPLAT_VECTOR,llvm::ISD::TargetFrameIndex,llvm::ISD::UNDEF,llvm::ISD::VALUETYPE, andllvm::ISD::VECTOR_SHUFFLE.
Test whether the givenSDValue (or all elements of it, if it is a vector) is known to never be NaN.
IfSNaN
is true, returns ifOp
is known to never be a signaling NaN (it may still be a qNaN).
Definition at line5672 of fileSelectionDAG.cpp.
Referencesllvm::ISD::BUILD_VECTOR,llvm::ISD::BUILTIN_OP_END,llvm::CallingConv::C,llvm::Depth,llvm::ISD::EXTRACT_VECTOR_ELT,llvm::ISD::FABS,llvm::ISD::FACOS,llvm::ISD::FADD,llvm::ISD::FASIN,llvm::ISD::FATAN,llvm::ISD::FATAN2,llvm::ISD::FCANONICALIZE,llvm::ISD::FCEIL,llvm::ISD::FCOPYSIGN,llvm::ISD::FCOS,llvm::ISD::FCOSH,llvm::ISD::FDIV,llvm::ISD::FEXP,llvm::ISD::FEXP10,llvm::ISD::FEXP2,llvm::ISD::FFLOOR,llvm::ISD::FLDEXP,llvm::ISD::FLOG,llvm::ISD::FLOG10,llvm::ISD::FLOG2,llvm::ISD::FMA,llvm::ISD::FMAD,llvm::ISD::FMAXIMUM,llvm::ISD::FMAXIMUMNUM,llvm::ISD::FMAXNUM,llvm::ISD::FMAXNUM_IEEE,llvm::ISD::FMINIMUM,llvm::ISD::FMINIMUMNUM,llvm::ISD::FMINNUM,llvm::ISD::FMINNUM_IEEE,llvm::ISD::FMUL,llvm::ISD::FNEARBYINT,llvm::ISD::FNEG,llvm::ISD::FP_EXTEND,llvm::ISD::FP_ROUND,llvm::ISD::FPOW,llvm::ISD::FPOWI,llvm::ISD::FREM,llvm::ISD::FRINT,llvm::ISD::FROUND,llvm::ISD::FROUNDEVEN,llvm::ISD::FSIN,llvm::ISD::FSINH,llvm::ISD::FSQRT,llvm::ISD::FSUB,llvm::ISD::FTAN,llvm::ISD::FTANH,llvm::ISD::FTRUNC,getTarget(),llvm::ISD::INTRINSIC_VOID,llvm::ISD::INTRINSIC_W_CHAIN,llvm::ISD::INTRINSIC_WO_CHAIN,isKnownNeverNaN(),llvm::TargetLowering::isKnownNeverNaNForTargetNode(),isKnownNeverSNaN(),llvm::ISD::LLRINT,llvm::ISD::LLROUND,llvm::ISD::LRINT,llvm::ISD::LROUND,MaxRecursionDepth,Options,llvm::ISD::SELECT,llvm::ISD::SINT_TO_FP, andllvm::ISD::UINT_TO_FP.
Referenced byarebothOperandsNotNan(),combineFMinNumFMaxNum(),combineSelect(),llvm::TargetLowering::expandFMINIMUM_FMAXIMUM(),llvm::TargetLowering::expandFMINIMUMNUM_FMAXIMUMNUM(),llvm::TargetLowering::expandFMINNUM_FMAXNUM(),isKnownNeverNaN(),llvm::AMDGPUTargetLowering::isKnownNeverNaNForTargetNode(),llvm::SITargetLowering::isKnownNeverNaNForTargetNode(),isKnownNeverSNaN(),isLegalToCombineMinNumMaxNum(),lowerFMAXIMUM_FMINIMUM(), andLowerFMINIMUM_FMAXIMUM().
Op
is known to never be a signaling NaN.Definition at line2153 of fileSelectionDAG.h.
Referencesllvm::Depth, andisKnownNeverNaN().
Referenced byarebothOperandsNotSNan(),llvm::TargetLowering::expandFMINIMUMNUM_FMAXIMUMNUM(),llvm::TargetLowering::expandFMINNUM_FMAXNUM(),llvm::SITargetLowering::isCanonicalized(), andisKnownNeverNaN().
Test whether the givenSDValue is known to contain non-zerovalue(s).
Definition at line5814 of fileSelectionDAG.cpp.
Referencesllvm::ISD::ABS,llvm::ISD::ADD,assert(),llvm::ISD::BITREVERSE,llvm::ISD::BSWAP,llvm::CallingConv::C,computeKnownBits(),llvm::ConstantRange::contains(),llvm::ISD::CTPOP,llvm::Depth,F,llvm::ConstantRange::getBitWidth(),llvm::KnownBits::getBitWidth(),llvm::MachineFunction::getFunction(),getMachineFunction(),llvm::KnownBits::getMaxValue(),llvm::getVScaleRange(),isKnownNeverZero(),llvm::KnownBits::isNegative(),llvm::KnownBits::isNonZero(),llvm::isNullConstant(),llvm::KnownBits::isStrictlyPositive(),llvm::APInt::isZero(),llvm::APInt::lshr(),llvm::ISD::matchUnaryPredicate(),MaxRecursionDepth,llvm::ISD::MUL,llvm::ConstantRange::multiply(),llvm::KnownBits::ne(),llvm::KnownBits::One,llvm::ISD::OR,llvm::ISD::ROTL,llvm::ISD::ROTR,llvm::ISD::SDIV,llvm::ISD::SELECT,llvm::APInt::shl(),llvm::ISD::SHL,llvm::ISD::SIGN_EXTEND,llvm::ISD::SMAX,llvm::ISD::SMIN,llvm::ISD::SRA,llvm::ISD::SRL,llvm::ISD::SUB,llvm::ISD::UADDSAT,llvm::ISD::UDIV,llvm::APInt::ult(),llvm::ISD::UMAX,llvm::ISD::UMIN,llvm::ISD::VSCALE,llvm::ISD::VSELECT, andllvm::ISD::ZERO_EXTEND.
Referenced byllvm::X86TargetLowering::computeKnownBitsForTargetNode(),isCMN(),isKnownNeverZero(),isKnownToBeAPowerOfTwo(),isSafeToSpeculativelyExecuteNode(),LowerCTLZ(),LowerCTTZ(),LowerShift(), andsimplifySetCCWithCTPOP().
Test whether the given floating pointSDValue is known to never be positive or negative zero.
Definition at line5805 of fileSelectionDAG.cpp.
Referencesassert(),llvm::CallingConv::C, andllvm::ISD::matchUnaryFpPredicate().
Referenced bycombineSelect(),llvm::TargetLowering::expandFMINIMUM_FMAXIMUM(),llvm::TargetLowering::expandFMINIMUMNUM_FMAXIMUMNUM(),llvm::TargetLowering::expandFMINNUM_FMAXNUM(), andLowerFMINIMUM_FMAXIMUM().
Test if the given value is known to have exactly one bit set.
This differs from computeKnownBits in that it doesn't necessarily determine which bit is set.
Definition at line4645 of fileSelectionDAG.cpp.
Referencesllvm::all_of(),llvm::BitWidth,llvm::ISD::BUILD_VECTOR,llvm::CallingConv::C,llvm::Depth,llvm::SDValue::getOpcode(),llvm::SDValue::getOperand(),llvm::SDNode::getOperand(),llvm::EVT::getScalarSizeInBits(),getTargetLoweringInfo(),llvm::SDValue::getValueType(),llvm::isConstOrConstSplat(),isKnownNeverZero(),isKnownToBeAPowerOfTwo(),llvm::PatternMatch::m_And(),llvm::PatternMatch::m_Deferred(),llvm::PatternMatch::m_Neg(),llvm::PatternMatch::m_Value(),llvm::ISD::matchUnaryPredicate(),MaxRecursionDepth,llvm::SDNode::ops(),llvm::ISD::ROTL,llvm::ISD::ROTR,llvm::SDPatternMatch::sd_match(),llvm::ISD::SELECT,llvm::ISD::SHL,llvm::ISD::SMAX,llvm::ISD::SMIN,llvm::ISD::SPLAT_VECTOR,llvm::ISD::SRL,llvm::ISD::UMAX,llvm::ISD::UMIN,llvm::ISD::VSCALE,llvm::ISD::VSELECT,X, andllvm::ISD::ZERO_EXTEND.
Referenced byisKnownToBeAPowerOfTwo(), andisKnownToBeAPowerOfTwoFP().
Test if the givenfp value is known to be an integer power-of-2, either positive or negative.
Definition at line4729 of fileSelectionDAG.cpp.
Referencesllvm::Depth,llvm::SDValue::getOpcode(),llvm::SDValue::getOperand(),llvm::isConstOrConstSplatFP(),isKnownToBeAPowerOfTwo(),llvm::ISD::SINT_TO_FP, andllvm::ISD::UINT_TO_FP.
Some opcodes may create immediate undefined behavior when used with some values (integer division-by-zero for example).
Therefore, these operations are not generally safe to move around or change.
Definition at line2422 of fileSelectionDAG.h.
Referencesllvm::ISD::SDIV,llvm::ISD::SDIVREM,llvm::ISD::SREM,llvm::ISD::UDIV,llvm::ISD::UDIVREM, andllvm::ISD::UREM.
Referenced byisSafeToSpeculativelyExecuteNode(), andperformBUILD_VECTORCombine().
Check if the provided node is save to speculatively executed given its current arguments.
So, whileudiv
the opcode is not safe to speculatively execute, a givenudiv
node may be if the denominator is known nonzero.
Definition at line2440 of fileSelectionDAG.h.
ReferencesisKnownNeverZero(),isSafeToSpeculativelyExecute(),N, andllvm::ISD::UDIV.
Referenced byfoldSelectWithIdentityConstant().
Test whetherV
has a splatted value.
Helper wrapper to main isSplatValue function.
Definition at line3215 of fileSelectionDAG.cpp.
Referencesassert(),llvm::APInt::getAllOnes(),llvm::EVT::getVectorNumElements(),llvm::EVT::isScalableVector(),isSplatValue(), andllvm::EVT::isVector().
bool SelectionDAG::isSplatValue | ( | SDValue | V, |
constAPInt & | DemandedElts, | ||
APInt & | UndefElts, | ||
unsigned | Depth =0 | ||
) | const |
Test whetherV
has a splatted value for all the demanded elements.
isSplatValue - Return true if the vector V has the same value across all DemandedElts.
On successUndefElts
will indicate the elements that have UNDEF values instead of the splat value, this is only guaranteed to be correct forDemandedElts
.
NOTE: The function will return true for a demanded splat of UNDEF values.
For scalable vectors, we don't know the number of lanes at compile time. Instead, we use a 1 bitAPInt to represent a conservative value for all lanes; that is, that one bit value is implicitly splatted across all lanes.
Definition at line3029 of fileSelectionDAG.cpp.
Referencesllvm::ISD::ABS,llvm::ISD::ADD,llvm::ISD::AND,llvm::ISD::ANY_EXTEND_VECTOR_INREG,assert(),llvm::ISD::BITCAST,llvm::BitWidth,llvm::ISD::BUILD_VECTOR,llvm::ISD::BUILTIN_OP_END,llvm::Depth,llvm::ISD::EXTRACT_SUBVECTOR,llvm::APInt::extractBits(),llvm::APInt::getAllOnes(),llvm::APInt::getBitWidth(),llvm::APInt::getOneBitSet(),llvm::EVT::getScalarSizeInBits(),llvm::APInt::getSplat(),llvm::EVT::getVectorNumElements(),llvm::APInt::getZero(),I,Idx,llvm::ISD::INTRINSIC_VOID,llvm::ISD::INTRINSIC_W_CHAIN,llvm::ISD::INTRINSIC_WO_CHAIN,llvm::EVT::isInteger(),llvm::EVT::isScalableVector(),isSplatValue(),llvm::TargetLowering::isSplatValueForTargetNode(),llvm::EVT::isVector(),llvm::APInt::isZero(),isZero(),LHS,MaxRecursionDepth,llvm::ISD::OR,RHS,llvm::APIntOps::ScaleBitMask(),llvm::APInt::setBit(),llvm::APInt::shl(),llvm::ISD::SIGN_EXTEND,llvm::ISD::SIGN_EXTEND_VECTOR_INREG,llvm::ISD::SPLAT_VECTOR,llvm::ISD::SUB,llvm::APInt::trunc(),llvm::ISD::TRUNCATE,llvm::ISD::VECTOR_SHUFFLE,llvm::ISD::XOR,llvm::ISD::ZERO_EXTEND,llvm::ISD::ZERO_EXTEND_VECTOR_INREG, andllvm::APInt::zext().
Referenced bycanonicalizeShuffleWithOp(),combineEXTRACT_SUBVECTOR(),combineShuffleOfSplatVal(),combineX86ShuffleChain(),getSplatSourceVector(),isOnlyUsedByStores(),isSplatValue(),LowerRotate(),lowerVECTOR_SHUFFLE(),llvm::X86TargetLowering::shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(),llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(),llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(),splitVector(), andtryCombineMULLWithUZP1().
Return true if the result of this operation is always undefined.
Definition at line6647 of fileSelectionDAG.cpp.
Referencesllvm::any_of(),assert(),llvm::SDValue::getNode(),llvm::ISD::isBuildVectorOfConstantSDNodes(),llvm::isNullConstant(),llvm::SDValue::isUndef(),llvm::SDNode::op_values(),llvm::ISD::SDIV,llvm::ArrayRef< T >::size(),llvm::ISD::SREM,llvm::ISD::UDIV, andllvm::ISD::UREM.
Referenced byFoldConstantArithmetic(), andsimplifyDivRem().
void SelectionDAG::Legalize | ( | ) |
This transforms theSelectionDAG into aSelectionDAG that is compatible with the target instruction selector, as indicated by theTargetLowering object.
This is the entry point for the file.
Note that this is an involved process that may invalidate pointers into the graph.
Definition at line5808 of fileLegalizeDAG.cpp.
Referencesallnodes_begin(),allnodes_end(),AssignTopologicalOrder(),DeleteNode(),llvm::SmallPtrSetImpl< PtrType >::erase(),llvm::SDValue::getNode(),getNode(),getRoot(),llvm::SmallPtrSetImpl< PtrType >::insert(),N, andRemoveDeadNodes().
bool SelectionDAG::LegalizeOp | ( | SDNode * | N, |
SmallSetVector<SDNode *, 16 > & | UpdatedNodes | ||
) |
Transforms aSelectionDAG node and any operands to it into a node that is compatible with the target instruction selector, as indicated by theTargetLowering object.
N
is a valid, legal node after calling this.This essentially runs a single recursive walk of theLegalize
process over the given node (and its operands). This can be used to incrementally legalize the DAG. All of the nodes which are directly replaced, potentially including N, are added to the output parameterUpdatedNodes
so that the delta to the DAG can be understood by the caller.
When this returns false, N has been legalized in a way that make the pointer passed in no longer valid. It may have even been deleted from the DAG, and so it shouldn't be used further. When this returns true, the N passed in is a legal node, and can be immediately processed as such. This may still have done some work on the DAG, and will still populate UpdatedNodes with any new nodes replacing those originally in the DAG.
Definition at line5857 of fileLegalizeDAG.cpp.
Referencesllvm::SmallPtrSetImpl< PtrType >::count(),llvm::SmallPtrSetImpl< PtrType >::insert(), andN.
bool SelectionDAG::LegalizeTypes | ( | ) |
This transforms theSelectionDAG into aSelectionDAG that only uses types natively supported by the target.
Returns "true" if it made any changes.
Note that this is an involved process that may invalidate pointers into the graph.
Definition at line1055 of fileLegalizeTypes.cpp.
Referencesllvm::DAGTypeLegalizer::run().
bool SelectionDAG::LegalizeVectors | ( | ) |
This transforms theSelectionDAG into aSelectionDAG that only uses vector math operations supported by the target.
This is necessary as a separate step from Legalize because unrolling a vector operation can introduce illegal types, which requires running LegalizeTypes again.
This returns true if it made any changes; in that case, LegalizeTypes is called again before Legalize.
Note that this is an involved process that may invalidate pointers into the graph.
Definition at line2309 of fileLegalizeVectorOps.cpp.
SDValue SelectionDAG::makeEquivalentMemoryOrdering | ( | LoadSDNode * | OldLoad, |
SDValue | NewMemOp | ||
) |
If an existing load has uses of its chain, create a token factor node with that chain and the new memory node's chain and update users of the old chain to the token factor.
This ensures that the new memory node will have the same relative memory dependency position as the old load. Returns the new merged load chain.
Definition at line12170 of fileSelectionDAG.cpp.
Referencesassert(),llvm::SDValue::getNode(),llvm::SDValue::getValue(), andmakeEquivalentMemoryOrdering().
If an existing load has uses of its chain, create a token factor node with that chain and the new memory node's chain and update users of the old chain to the token factor.
This ensures that the new memory node will have the same relative memory dependency position as the old load. Returns the new merged load chain.
Definition at line12152 of fileSelectionDAG.cpp.
Referencesassert(),getNode(),llvm::SDValue::getValueType(),ReplaceAllUsesOfValueWith(),llvm::ISD::TokenFactor,UpdateNodeOperands(), andllvm::SDValue::use_empty().
Referenced bycombineBVOfConsecutiveLoads(),combineExtractFromVectorLoad(),combineStore(),EltsFromConsecutiveLoads(),getBROADCAST_LOAD(),lowerShuffleAsBroadcast(),lowerVECTOR_SHUFFLE(),makeEquivalentMemoryOrdering(),narrowExtractedVectorLoad(),performCONCAT_VECTORSCombine(),performExtBinopLoadFold(), andllvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode().
SDValue SelectionDAG::makeStateFunctionCall | ( | unsigned | LibFunc, |
SDValue | Ptr, | ||
SDValue | InChain, | ||
constSDLoc & | DLoc | ||
) |
Helper used to make a call to a library function that has one argument of pointer type.
Such functions include 'fegetmode', 'fesetenv' and some others, which are used to get or set floating-point state. They have one argument of pointer type, which points to the memory region containing bits of the floating-point state. The value returned by such function is ignored in the created call.
LibFunc | Reference to library function (value ofRTLIB::Libcall). |
Ptr | Pointer used to save/load state. |
InChain | Ingoing token chain. |
Definition at line13610 of fileSelectionDAG.cpp.
Referencesassert(),getContext(),getDataLayout(),getExternalSymbol(),llvm::TargetLoweringBase::getLibcallCallingConv(),llvm::TargetLoweringBase::getLibcallName(),llvm::TargetLoweringBase::getPointerTy(),llvm::SDValue::getValueType(),llvm::Type::getVoidTy(),llvm::TargetLowering::LowerCallTo(),Ptr,llvm::TargetLowering::CallLoweringInfo::setChain(),llvm::TargetLowering::CallLoweringInfo::setDebugLoc(), andllvm::TargetLowering::CallLoweringInfo::setLibCallee().
Return true if '(Op & Mask) == Mask'.
MaskedValueIsAllOnes - Return true if '(Op & Mask) == Mask'.
Op and Mask are known to be the same type.
Definition at line2999 of fileSelectionDAG.cpp.
ReferencescomputeKnownBits(), andllvm::Depth.
bool SelectionDAG::MaskedValueIsZero | ( | SDValue | V, |
constAPInt & | Mask, | ||
constAPInt & | DemandedElts, | ||
unsigned | Depth =0 | ||
) | const |
Return true if 'Op & Mask' is known to be zero in DemandedElts.
MaskedValueIsZero - Return true if 'V & Mask' is known to be zero in DemandedElts.
We use this predicate to simplify operations downstream. Op and Mask are known to be the same type.
We use this predicate to simplify operations downstream. Mask is known to be zero for bits that V cannot have.
Definition at line2985 of fileSelectionDAG.cpp.
ReferencescomputeKnownBits(), andllvm::Depth.
Return true if 'Op & Mask' is known to be zero.
MaskedValueIsZero - Return true if 'V & Mask' is known to be zero.
We use this predicate to simplify operations downstream. Op and Mask are known to be the same type.
We use this predicate to simplify operations downstream. Mask is known to be zero for bits that V cannot have.
Definition at line2977 of fileSelectionDAG.cpp.
ReferencescomputeKnownBits(), andllvm::Depth.
Referenced byllvm::SelectionDAGISel::CheckAndMask(),combine_CC(),combineAddOfBooleanXor(),combineAddOfPMADDWD(),combineAnd(),combineCMP(),combineDeMorganOfBoolean(),combineMulToPMADDWD(),combineMulToPMULDQ(),combineSetCC(),combineSubShiftToOrcB(),combineTargetShuffle(),combineVectorPack(),combineZext(),EmitCmp(),llvm::XCoreSelectionDAGInfo::EmitTargetCodeForMemcpy(),llvm::TargetLowering::expandMUL_LOHI(),foldMaskAndShiftToScale(),getBT(),getFauxShuffleMask(),getNode(),getTruncatedUSUBSAT(),isTruncWithZeroHighBitsInput(),LowerPARITY(),llvm::AMDGPUTargetLowering::LowerUDIVREM64(),matchLSNode(),matchShuffleWithPACK(),llvm::PPCTargetLowering::PerformDAGCombine(),llvm::RISCVTargetLowering::PerformDAGCombine(),PerformORCombineToBFI(),performSETCCCombine(),llvm::RISCVTargetLowering::ReplaceNodeResults(),selectUmullSmull(),llvm::RISCVDAGToDAGISel::selectZExtBits(),llvm::LoongArchDAGToDAGISel::selectZExti32(),ShrinkLoadReplaceStoreWithStore(),SignBitIsZero(),llvm::TargetLowering::SimplifyDemandedBits(),llvm::TargetLowering::SimplifySetCC(), andtryDemorganOfBooleanCondition().
Return true if 'Op' is known to be zero in DemandedElts.
MaskedVectorIsZero - Return true if 'Op' is known to be zero in DemandedElts.
We use this predicate to simplify operations downstream.
Definition at line2993 of fileSelectionDAG.cpp.
ReferencescomputeKnownBits(),llvm::Depth, andllvm::KnownBits::isZero().
Referenced bycombineOr(),computeVectorKnownZeroElements(),isTargetShuffleEquivalent(),matchBinaryShuffle(), andllvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode().
SDValue SelectionDAG::matchBinOpReduction | ( | SDNode * | Extract, |
ISD::NodeType & | BinOp, | ||
ArrayRef<ISD::NodeType > | CandidateBinOps, | ||
bool | AllowPartials =false | ||
) |
Match a binop + shuffle pyramid that represents a horizontal reduction over the elements of a vector starting from the EXTRACT_VECTOR_ELT node /p Extract.
The reduction must use one of the opcodes listed in /p CandidateBinOps and on success /p BinOp will contain the matching opcode. Returns the vector that is being reduced on, or SDValue() if a reduction was not matched. IfAllowPartials
is set then in the case of a reduction pattern that only matches the first few stages, the extracted subvector of the start of the reduction is returned.
Definition at line12604 of fileSelectionDAG.cpp.
Referencesllvm::ISD::EXTRACT_SUBVECTOR,llvm::ISD::EXTRACT_VECTOR_ELT,llvm::ISD::FADD,llvm::SDValue::getConstantOperandAPInt(),getContext(),llvm::ShuffleVectorSDNode::getMaskElt(),getNode(),llvm::SDValue::getOpcode(),llvm::SDNode::getOpcode(),llvm::SDValue::getOperand(),llvm::SDNode::getOperand(),llvm::EVT::getScalarType(),getVectorIdxConstant(),llvm::EVT::getVectorVT(),llvm::TargetLoweringBase::isExtractSubvectorCheap(),llvm::isNullConstant(),llvm_unreachable,llvm::Log2_32(), andllvm::none_of().
Referenced bycombineArithReduction(),combineBasicSADPattern(),combineMinMaxReduction(),combinePredicateReduction(),combineVPDPBUSDPattern(), andMatchVectorAllEqualTest().
Thismutates the specified node to have the specified return type, opcode, and operands.
MorphNodeTo - Thismutates the specified node to have the specified return type, opcode, and operands.
Note that MorphNodeTo returns the resultant node. If there is already a node of the specified opcode and operands, it returns that node instead of the current one. Note that theSDLoc need not be the same.
Using MorphNodeTo is faster than creating a new node and swapping it in with ReplaceAllUsesWith both because it often avoids allocating a new node, and because it doesn't require CSE recalculation for any of the node's users.
However, note that MorphNodeTo recursively deletes dead nodes from the DAG. As a consequence it isn't appropriate to use from within the DAG combiner or the legalizer which maintain worklists that would need to be updated when deleting things.
Definition at line11048 of fileSelectionDAG.cpp.
ReferencesAddNodeIDNode(),llvm::SmallPtrSetImplBase::empty(),I,llvm::SmallPtrSetImpl< PtrType >::insert(),N,llvm::SDVTList::NumVTs,llvm::SmallVectorTemplateBase< T, bool >::push_back(),RemoveDeadNodes(),llvm::Use::set(), andllvm::SDVTList::VTs.
Referenced byCloneNodeWithValues(),llvm::NVPTXTargetLowering::LowerCall(),mutateStrictFPToFP(),llvm::AMDGPUDAGToDAGISel::Select(),SelectNodeTo(), andllvm::HexagonDAGToDAGISel::SelectTypecast().
Mutate the specified strict FP node to its non-strict equivalent, unlinking the node from its chain and dropping the metadata arguments.
The node must be a strict FP node.
Definition at line11101 of fileSelectionDAG.cpp.
Referencesassert(),getVTList(),llvm_unreachable,MorphNodeTo(),llvm::SmallVectorTemplateBase< T, bool >::push_back(),RemoveDeadNode(),ReplaceAllUsesOfValueWith(),ReplaceAllUsesWith(), andllvm::SDNode::setNodeId().
| delete |
void SelectionDAG::RemoveDeadNode | ( | SDNode * | N | ) |
Remove the specified node from the system.
If any of its operands then becomes dead, remove them as well. Inform UpdateListener for each node deleted.
Definition at line1084 of fileSelectionDAG.cpp.
ReferencesgetRoot(),N, andRemoveDeadNodes().
Referenced byfoldADDIForFasterLocalAccesses(),foldMaskAndShiftToExtract(),foldMaskAndShiftToScale(),foldMaskedShiftToBEXTR(),foldMaskedShiftToScaledMask(),llvm::TargetLowering::getCheaperOrNeutralNegatedExpression(),llvm::TargetLowering::getNegatedExpression(),llvm::SITargetLowering::legalizeTargetIndependentNode(),llvm::NVPTXTargetLowering::LowerCall(),mutateStrictFPToFP(),llvm::SelectionDAGISel::ReplaceNode(),llvm::RISCVDAGToDAGISel::Select(),llvm::HexagonDAGToDAGISel::SelectBrevLdIntrinsic(),llvm::SelectionDAGISel::SelectCodeCommon(),llvm::HexagonDAGToDAGISel::SelectHVXDualOutput(),llvm::HexagonDAGToDAGISel::SelectIndexedStore(),llvm::HexagonDAGToDAGISel::SelectIntrinsicWChain(),llvm::HexagonDAGToDAGISel::SelectNewCircIntrinsic(),SelectNodeTo(),llvm::HvxSelector::selectVAlign(),llvm::RISCVDAGToDAGISel::selectVLSEG(),llvm::RISCVDAGToDAGISel::selectVLSEGFF(),llvm::RISCVDAGToDAGISel::selectVLXSEG(), andllvm::HexagonDAGToDAGISel::tryLoadOfLoadIntrinsic().
void SelectionDAG::RemoveDeadNodes | ( | ) |
This method deletes all unreachable nodes in theSelectionDAG.
RemoveDeadNodes - This method deletes all unreachable nodes in theSelectionDAG.
Definition at line1030 of fileSelectionDAG.cpp.
Referencesallnodes(),getRoot(),llvm::SmallVectorTemplateBase< T, bool >::push_back(),RemoveDeadNodes(), andsetRoot().
Referenced byLegalize(),MorphNodeTo(),llvm::AMDGPUDAGToDAGISel::PostprocessISelDAG(),llvm::RISCVDAGToDAGISel::PostprocessISelDAG(),llvm::AMDGPUDAGToDAGISel::PreprocessISelDAG(),llvm::RISCVDAGToDAGISel::PreprocessISelDAG(),RemoveDeadNode(),RemoveDeadNodes(), andllvm::DAGTypeLegalizer::run().
void SelectionDAG::RemoveDeadNodes | ( | SmallVectorImpl<SDNode * > & | DeadNodes | ) |
This method deletes the unreachable nodes in the given list, and any nodes that become unreachable as a result.
RemoveDeadNodes - This method deletes the unreachable nodes in the given list, and any nodes that become unreachable as a result.
Definition at line1050 of fileSelectionDAG.cpp.
Referencesllvm::ISD::DELETED_NODE,llvm::SmallVectorBase< Size_T >::empty(),I,N,llvm::SelectionDAG::DAGUpdateListener::Next,llvm::SmallVectorImpl< T >::pop_back_val(),llvm::SmallVectorTemplateBase< T, bool >::push_back(),llvm::Use::set(), andllvm::SDNode::use_empty().
Like ReplaceAllUsesOfValueWith, but for multiple values at once.
ReplaceAllUsesOfValuesWith - Replace any uses of From with To, leaving uses of other values produced by From.getNode() alone.
This correctly handles the case where there is an overlap between the From values and the To values.
The same value may appear in both the From and To list. The Deleted vector is handled the same way as for ReplaceAllUsesWith.
Definition at line11989 of fileSelectionDAG.cpp.
ReferencescopyExtraInfo(),From,llvm::Use::getUser(),ReplaceAllUsesOfValueWith(),llvm::Use::set(),llvm::sort(),transferDbgValues(),llvm::SDNode::uses(), andUses.
Referenced byllvm::SelectionDAGISel::ReplaceUses().
Replace any uses of From with To, leaving uses of other values produced by From.getNode() alone.
ReplaceAllUsesOfValueWith - Replace any uses of From with To, leaving uses of other values produced by From.getNode() alone.
The Deleted vector is handled the same way as for ReplaceAllUsesWith.
Definition at line11814 of fileSelectionDAG.cpp.
ReferencescopyExtraInfo(),From,llvm::SDValue::getNode(),getRoot(),llvm::SDUse::getUser(),llvm::SDNode::isDivergent(),ReplaceAllUsesWith(),llvm::Use::set(),setRoot(),transferDbgValues(), andupdateDivergence().
Referenced byAddCombineTo64bitMLAL(),AddCombineTo64BitSMLAL16(),AddCombineTo64bitUMAAL(),adjustSubwordCmp(),combineBitcast(),combineCarryDiamond(),combineConcatVectorOps(),combineCVTP2I_CVTTP2I(),combineCVTPH2PS(),combineEXTEND_VECTOR_INREG(),combineExtractWithShuffle(),combineINSERT_SUBVECTOR(),combineMOVDQ2Q(),combineOp_VLToVWOp_VL(),combineSelect(),combineSetCCAtomicArith(),combineSIntToFP(),combineTargetShuffle(),combineVSelectToBLENDV(),combineX86INT_TO_FP(),emitIntrinsicWithCCAndChain(),EmitTest(),expandMultipleResultFPLibCall(),lowerBuildVectorAsBroadcast(),llvm::HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(),makeEquivalentMemoryOrdering(),llvm::AMDGPUDAGToDAGISel::matchLoadD16FromBuildVector(),mutateStrictFPToFP(),performConcatVectorsCombine(),llvm::PPCTargetLowering::PerformDAGCombine(),llvm::RISCVTargetLowering::PerformDAGCombine(),performDivRemCombine(),performExtractVectorEltCombine(),PerformHWLoopCombine(),performIntToFpCombine(),PerformORCombineToSMULWBT(),PerformSplittingMVEEXTToWideningLoad(),PerformSplittingToWideningLoad(),llvm::AMDGPUTargetLowering::performStoreCombine(),performUnpackCombine(),PerformVDUPCombine(),PerformVMOVhrCombine(),PerformVMOVrhCombine(),PerformVMOVRRDCombine(),performVP_REVERSECombine(),llvm::RISCVDAGToDAGISel::PreprocessISelDAG(),reduceVSXSwap(),ReplaceAllUsesOfValuesWith(),llvm::SelectionDAGISel::ReplaceUses(),SkipExtensionForVMULL(),tryToFoldExtOfAtomicLoad(),tryToFoldExtOfExtload(),tryToFoldExtOfLoad(), andtryToFoldExtOfMaskedLoad().
ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead.
This can cause recursive merging of nodes in the DAG.
This version can replace From with any result values. To must match the number and types of values returned by From.
Definition at line11764 of fileSelectionDAG.cpp.
ReferencescopyExtraInfo(),From,getNode(),getRoot(),llvm::SDUse::getUser(),llvm::SDNode::isDivergent(),ReplaceAllUsesWith(),llvm::Use::set(),setRoot(),transferDbgValues(), andupdateDivergence().
ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead.
This can cause recursive merging of nodes in the DAG.
This version assumes that for each value of From, there is a corresponding value in To in the same position with the same type.
Definition at line11706 of fileSelectionDAG.cpp.
Referencesassert(),copyExtraInfo(),From,getNode(),getRoot(),llvm::SDUse::getUser(),llvm::SDNode::getValueType(),llvm::SDNode::isDivergent(),setRoot(),transferDbgValues(), andupdateDivergence().
Modify anything using 'From' to use 'To' instead.
ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead.
This can cause recursive merging of nodes in the DAG.Use the first version if 'From' is known to have a single result, use the second if you have two nodes with identical results (or if 'To' has a superset of the results of 'From'), use the third otherwise.
These methods all take an optional UpdateListener, which (if not null) is informed about nodes that are deleted and modified due to recursive changes in the dag.
These functions only replace all existing uses. It's possible that as these replacements are being performed, CSE may cause the From node to be given new uses. These new uses of From are left in place, and not automatically transferred to To.
This can cause recursive merging of nodes in the DAG.
This version assumes From has a single result value.
Definition at line11653 of fileSelectionDAG.cpp.
Referencesassert(),copyExtraInfo(),From,llvm::SDValue::getNode(),llvm::SDValue::getResNo(),getRoot(),llvm::SDUse::getUser(),llvm::SDNode::isDivergent(),llvm::Use::set(),setRoot(),transferDbgValues(), andupdateDivergence().
Referenced byemitComparison(),foldMaskAndShiftToExtract(),foldMaskAndShiftToScale(),foldMaskedShiftToBEXTR(),foldMaskedShiftToScaledMask(),llvm::SITargetLowering::legalizeTargetIndependentNode(),llvm::SelectionDAGBuilder::LowerAsSTATEPOINT(),llvm::NVPTXTargetLowering::LowerCall(),lowerShufflePairAsUNPCKAndPermute(),mutateStrictFPToFP(),performCONDCombine(),llvm::AMDGPUTargetLowering::performFNegCombine(),PerformHWLoopCombine(),PerformLongShiftCombine(),performSETCCCombine(),reassociateCSELOperandsForCSE(),ReplaceAllUsesOfValueWith(),ReplaceAllUsesWith(),llvm::SelectionDAGISel::ReplaceNode(),llvm::SelectionDAGISel::ReplaceUses(),SelectNodeTo(),tryCombineMULLWithUZP1(), andtryMemPairCombine().
| inline |
Move node N in the AllNodes list to be immediately before the given iterator Position.
This may be used to update the topological ordering when the list of nodes is modified.
Definition at line1853 of fileSelectionDAG.h.
Referencesllvm::iplist_impl< IntrusiveListT, TraitsT >::insert(),N, andllvm::iplist_impl< IntrusiveListT, TraitsT >::remove().
Referenced byinsertDAGNode().
void SelectionDAG::salvageDebugInfo | ( | SDNode & | N | ) |
To be invoked on anSDNode that is slated to be erased.
This function mirrorsllvm::salvageDebugInfo
.
Definition at line11482 of fileSelectionDAG.cpp.
Referencesllvm::ISD::ADD,AddDbgValue(),llvm::any_of(),llvm::DIExpression::appendOffset(),llvm::DIExpression::appendOpsToArg(),assert(),llvm::DIExpression::convertToVariadicExpression(),llvm::dbgs(),llvm::dwarf::DW_OP_LLVM_arg,llvm::SDDbgOperand::fromFrameIdx(),llvm::SDDbgOperand::fromNode(),getDbgValueList(),GetDbgValues(),llvm::DIExpression::getExtOps(),llvm::SDValue::getNode(),llvm::SDValue::getResNo(),llvm::SDValue::getValueSizeInBits(),LLVM_DEBUG,N,llvm::Offset,llvm::SmallVectorTemplateBase< T, bool >::push_back(),RHS,llvm::SDDbgOperand::SDNODE, andllvm::ISD::TRUNCATE.
Referenced byllvm::SelectionDAGISel::SelectCodeCommon().
These are used for target selectors tomutate the specified node to have the specified return type,Target opcode, and operands.
SelectNodeTo - These are wrappers around MorphNodeTo that accept a machine opcode.
Note that target opcodes are stored as ~TargetOpcode in the node opcode field. The resultant node is returned.
Definition at line10941 of fileSelectionDAG.cpp.
ReferencesgetVTList(),N, andSelectNodeTo().
Referenced byllvm::AMDGPUDAGToDAGISel::SelectBuildVector(),SelectNodeTo(),llvm::AMDGPUDAGToDAGISel::SelectVectorShuffle(),tryBitfieldInsertOpFromOr(),tryBitfieldInsertOpFromOrAndImm(), andtryOrrWithShift().
Definition at line10970 of fileSelectionDAG.cpp.
ReferencesgetVTList(),N, andSelectNodeTo().
Definition at line10947 of fileSelectionDAG.cpp.
ReferencesgetVTList(),N, andSelectNodeTo().
Definition at line10954 of fileSelectionDAG.cpp.
ReferencesgetVTList(),N, andSelectNodeTo().
SDNode * SelectionDAG::SelectNodeTo | ( | SDNode * | N, |
unsigned | MachineOpc, | ||
EVT | VT, | ||
SDValue | Op1, | ||
SDValue | Op2, | ||
SDValue | Op3 | ||
) |
Definition at line10962 of fileSelectionDAG.cpp.
ReferencesgetVTList(),N, andSelectNodeTo().
Definition at line10982 of fileSelectionDAG.cpp.
ReferencesgetVTList(),N, andSelectNodeTo().
SDNode * SelectionDAG::SelectNodeTo | ( | SDNode * | N, |
unsigned | MachineOpc, | ||
EVT | VT1, | ||
EVT | VT2, | ||
ArrayRef<SDValue > | Ops | ||
) |
Definition at line10976 of fileSelectionDAG.cpp.
ReferencesgetVTList(),N, andSelectNodeTo().
SDNode * SelectionDAG::SelectNodeTo | ( | SDNode * | N, |
unsigned | MachineOpc, | ||
EVT | VT1, | ||
EVT | VT2, | ||
EVT | VT3, | ||
ArrayRef<SDValue > | Ops | ||
) |
Definition at line10988 of fileSelectionDAG.cpp.
ReferencesgetVTList(),N, andSelectNodeTo().
SDNode * SelectionDAG::SelectNodeTo | ( | SDNode * | N, |
unsigned | MachineOpc, | ||
EVT | VT1, | ||
EVT | VT2, | ||
SDValue | Op1, | ||
SDValue | Op2 | ||
) |
Definition at line10995 of fileSelectionDAG.cpp.
ReferencesgetVTList(),N, andSelectNodeTo().
SDNode * SelectionDAG::SelectNodeTo | ( | SDNode * | N, |
unsigned | MachineOpc, | ||
SDVTList | VTs, | ||
ArrayRef<SDValue > | Ops | ||
) |
Definition at line11003 of fileSelectionDAG.cpp.
ReferencesMorphNodeTo(),N,RemoveDeadNode(), andReplaceAllUsesWith().
| inline |
Definition at line517 of fileSelectionDAG.h.
Referenced byllvm::SelectionDAG::FlagInserter::FlagInserter(), andllvm::SelectionDAG::FlagInserter::~FlagInserter().
| inline |
Definition at line484 of fileSelectionDAG.h.
Set graph attributes for a node. (eg. "color=red".)
setGraphAttrs - Set graph attributes for a node.
(eg. "color=red".)
Definition at line191 of fileSelectionDAGPrinter.cpp.
Referencesllvm::errs(), andN.
Convenience for setting node color attribute.
setGraphColor - Convenience for setting node color attribute.
Definition at line221 of fileSelectionDAGPrinter.cpp.
Referencesllvm::errs(), andN.
void SelectionDAG::setNodeMemRefs | ( | MachineSDNode * | N, |
ArrayRef<MachineMemOperand * > | NewMemRefs | ||
) |
Mutate the specified machine node's memory references to the provided list.
Definition at line10917 of fileSelectionDAG.cpp.
Referencesllvm::copy(),llvm::ArrayRef< T >::empty(),N, andllvm::ArrayRef< T >::size().
Referenced byCloneNodeWithValues(),llvm::AArch64SelectionDAGInfo::EmitMOPS(),llvm::AArch64SelectionDAGInfo::EmitTargetCodeForSetTag(),getLoadStackGuard(),llvm::SelectionDAGBuilder::LowerAsSTATEPOINT(),ReplaceATOMIC_LOAD_128Results(),ReplaceCMP_SWAP_128Results(),ReplaceCMP_SWAP_64Results(),replaceCMP_XCHG_128Results(),llvm::RISCVDAGToDAGISel::Select(),llvm::HexagonDAGToDAGISel::SelectBrevLdIntrinsic(),llvm::SelectionDAGISel::SelectCodeCommon(),llvm::HexagonDAGToDAGISel::SelectIndexedStore(),llvm::HexagonDAGToDAGISel::SelectV65Gather(),llvm::HexagonDAGToDAGISel::SelectV65GatherPred(),llvm::RISCVDAGToDAGISel::selectVLSEG(),llvm::RISCVDAGToDAGISel::selectVLSEGFF(),llvm::RISCVDAGToDAGISel::selectVLXSEG(),llvm::RISCVDAGToDAGISel::selectVSSEG(),llvm::RISCVDAGToDAGISel::selectVSXSEG(),llvm::RISCVDAGToDAGISel::tryIndexedLoad(), andllvm::X86InstrInfo::unfoldMemoryOperand().
Set the current root tag of theSelectionDAG.
Definition at line586 of fileSelectionDAG.h.
Referencesassert(),llvm::checkForCycles(), andN.
Referenced byexpandMultipleResultFPLibCall(),llvm::TargetLowering::LowerCallTo(),llvm::SelectionDAGBuilder::LowerCallTo(),llvm::SelectionDAGBuilder::LowerDeoptimizingReturn(),llvm::NVPTXTargetLowering::LowerFormalArguments(),llvm::AMDGPUTargetLowering::LowerGlobalAddress(),lowerIncomingStatepointValue(),llvm::SelectionDAGBuilder::lowerInvokable(),llvm::RISCVDAGToDAGISel::PostprocessISelDAG(),RemoveDeadNodes(),ReplaceAllUsesOfValueWith(),ReplaceAllUsesWith(),llvm::DAGTypeLegalizer::run(),llvm::SelectionDAGBuilder::visitBitTestCase(),llvm::SelectionDAGBuilder::visitBitTestHeader(),llvm::SelectionDAGBuilder::visitJumpTable(),llvm::SelectionDAGBuilder::visitJumpTableHeader(),llvm::SelectionDAGBuilder::visitSPDescriptorFailure(),llvm::SelectionDAGBuilder::visitSPDescriptorParent(), andllvm::SelectionDAGBuilder::visitSwitchCase().
Convenience for setting subgraph color attribute.
setSubgraphColor - Convenience for setting subgraph color attribute.
Definition at line265 of fileSelectionDAGPrinter.cpp.
Referencesllvm::errs(), andN.
bool SelectionDAG::shouldOptForSize | ( | ) | const |
Definition at line1401 of fileSelectionDAG.cpp.
Referencesllvm::MachineBasicBlock::getBasicBlock(),llvm::FunctionLoweringInfo::MBB, andllvm::shouldOptimizeForSize().
Referenced bycombineX86ShuffleChain(),combineX86ShufflesConstants(),llvm::TargetLowering::expandDIVREMByConstant(),ExpandPowI(),getConstantPool(),LowerAndToBT(),lowerBuildVectorAsBroadcast(),lowerBuildVectorOfConstants(),lowerBuildVectorViaDominantValues(),lowerConstant(),lowerFTRUNC_FCEIL_FFLOOR_FROUND(),LowerFunnelShift(),lowerShuffleAsBlend(),shouldLowerMemFuncForSize(),llvm::SelectionDAGISel::shouldOptForSize(), andshouldUseHorizontalOp().
Return true if the sign bit of Op is known to be zero.
SignBitIsZero - Return true if the sign bit of Op is known to be zero.
We use this predicate to simplify operations downstream.
Definition at line2969 of fileSelectionDAG.cpp.
Referencesllvm::BitWidth,llvm::Depth,llvm::APInt::getSignMask(), andMaskedValueIsZero().
Referenced bycanReduceVMulWidth(),checkSignTestSetCCCombine(),combineUIntToFP(),llvm::TargetLowering::expandABD(),getCmp(), andLowerVSETCC().
SDValue SelectionDAG::simplifyFPBinop | ( | unsigned | Opcode, |
SDValue | X, | ||
SDValue | Y, | ||
SDNodeFlags | Flags | ||
) |
Try to simplify a floating-point binary operation into 1 of its operands or a constant.
Definition at line10276 of fileSelectionDAG.cpp.
Referencesllvm::ISD::FADD,llvm::ISD::FDIV,llvm::ISD::FMUL,llvm::ISD::FSUB,getConstantFP(),getUNDEF(),llvm::ConstantFPSDNode::getValueAPF(),llvm::isConstOrConstSplatFP(),llvm::APFloat::isExactlyValue(),llvm::APFloat::isInfinity(),llvm::APFloat::isNaN(),llvm::APFloat::isNegZero(),llvm::APFloat::isPosZero(),llvm::APFloat::isZero(),X, andY.
Referenced bygetNode().
Try to simplify a select/vselect into 1 of its operands or a constant.
Definition at line10225 of fileSelectionDAG.cpp.
Referencesllvm::CallingConv::C,Cond,F,isBoolConstant(), andisConstantValueOfAnyType().
Referenced bycombineSelect(), andgetNode().
Try to simplify a shift into 1 of its operands or a constant.
Definition at line10248 of fileSelectionDAG.cpp.
ReferencesgetConstant(),getUNDEF(),llvm::isNullOrNullSplat(),llvm::ISD::matchUnaryPredicate(),X, andY.
Referenced bygetNode().
Split the explicit vector length parameter of a VP operation.
Definition at line13027 of fileSelectionDAG.cpp.
Referencesassert(),DL,getConstant(),getNode(),llvm::EVT::getScalarSizeInBits(),llvm::EVT::getVectorElementCount(),llvm::EVT::getVectorMinNumElements(),getVScale(),llvm::Hi,llvm::EVT::isFixedLengthVector(),llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isKnownEven(),llvm::Lo,N,llvm::ISD::UMIN, andllvm::ISD::USUBSAT.
Referenced bySplitVectorReductionOp(), andSplitVPOp().
std::pair<SDValue,SDValue > SelectionDAG::SplitScalar | ( | constSDValue & | N, |
constSDLoc & | DL, | ||
constEVT & | LoVT, | ||
constEVT & | HiVT | ||
) |
Split the scalar node with EXTRACT_ELEMENT using the provided VTs and return the low/high part.
Definition at line12946 of fileSelectionDAG.cpp.
Referencesassert(),DL,llvm::ISD::EXTRACT_ELEMENT,getIntPtrConstant(),getNode(),llvm::Hi,llvm::EVT::isVector(),llvm::Lo, andN.
Referenced bycreateGPRPairNode(),createGPRPairNodei64(),Expand64BitShift(),expandBitCastI128ToF128(),llvm::TargetLowering::expandDIVREMByConstant(),getMaskNode(),initAccumulator(),LowerBITCAST(),lowerI128ToGR128(),llvm::AArch64TargetLowering::LowerOperation(),llvm::RISCVTargetLowering::LowerOperation(),llvm::AMDGPUTargetLowering::LowerUDIVREM64(),LowerVectorAllEqual(),lowerVectorIntrinsicScalars(),LowerWRITE_REGISTER(),Passv64i1ArgInRegs(),PerformADDVecReduce(),performMADD_MSUBCombine(),ReplaceATOMIC_LOAD_128Results(),ReplaceCMP_SWAP_128Results(),replaceCMP_XCHG_128Results(),ReplaceLongIntrinsic(),llvm::X86TargetLowering::ReplaceNodeResults(),splatSplitI64WithVL(),llvm::RISCVTargetLowering::splitValueIntoRegisterParts(), andWinDBZCheckDenominator().
| inline |
Split the vector with EXTRACT_SUBVECTOR and return the low/high part.
Definition at line2295 of fileSelectionDAG.h.
ReferencesDL,GetSplitDestVTs(),N, andSplitVector().
std::pair<SDValue,SDValue > SelectionDAG::SplitVector | ( | constSDValue & | N, |
constSDLoc & | DL, | ||
constEVT & | LoVT, | ||
constEVT & | HiVT | ||
) |
Split the vector with EXTRACT_SUBVECTOR using the provided VTs and return the low/high part.
SplitVector - Split the vector with EXTRACT_SUBVECTOR and return the low/high part.
Definition at line13006 of fileSelectionDAG.cpp.
Referencesassert(),DL,llvm::ISD::EXTRACT_SUBVECTOR,getNode(),getVectorIdxConstant(),llvm::EVT::getVectorMinNumElements(),llvm::Hi,llvm::EVT::isScalableVector(),llvm::Lo, andN.
Referenced bycombineHorizOpWithShuffle(),combinePredicateReduction(),llvm::TargetLowering::expandVecReduce(),llvm::TargetLowering::expandVectorNaryOpBySplitting(),getPMOVMSKB(),getVectorBitwiseReduce(),isHorizontalBinOp(),LowerVecReduceMinMax(),LowerVectorAllEqual(),ReplaceAddWithADDP(),llvm::X86TargetLowering::ReplaceNodeResults(),SplitStrictFPVectorOp(),SplitVector(),SplitVectorOp(),SplitVectorOperand(),SplitVectorReductionOp(), andSplitVPOp().
| inline |
Split the node's operand with EXTRACT_SUBVECTOR and return the low/high part.
Definition at line2306 of fileSelectionDAG.h.
ReferencesN, andSplitVector().
Referenced byLowerCVTPS2PH(),LowerTruncate(),llvm::X86TargetLowering::ReplaceNodeResults(),ReplaceReductionResults(),llvm::SITargetLowering::splitBinaryVectorOp(),llvm::SITargetLowering::splitTernaryVectorOp(), andllvm::SITargetLowering::splitUnaryVectorOp().
void SelectionDAG::transferDbgValues | ( | SDValue | From, |
SDValue | To, | ||
unsigned | OffsetInBits =0 , | ||
unsigned | SizeInBits =0 , | ||
bool | InvalidateDbg =true | ||
) |
Transfer debug values from one node to another, while optionally generating fragment expressions for split-up values.
IfInvalidateDbg
is set, debug values are invalidated after they are transferred.
Definition at line11400 of fileSelectionDAG.cpp.
ReferencesAddDbgValue(),assert(),llvm::DIExpression::createFragmentExpression(),From,llvm::SDDbgOperand::fromNode(),getDbgValueList(),GetDbgValues(),llvm::SDNode::getHasDebugValue(),llvm::SDNode::getIROrder(),llvm::SDValue::getNode(),llvm::SDValue::getResNo(),llvm::is_contained(), andllvm::SmallVectorTemplateBase< T, bool >::push_back().
Referenced bygetNode(),ReplaceAllUsesOfValuesWith(),ReplaceAllUsesOfValueWith(), andReplaceAllUsesWith().
Utility function used by legalize and lowering to "unroll" a vector operation by splitting out the scalars and operating on each element individually.
If the ResNE is 0, fully unroll the vector op. If ResNE is less than the width of the vector op, unroll up to ResNE. If the ResNE is greater than the width of the vector op, unroll the vector op and fill the end of the resulting vector with UNDEFS.
Definition at line12720 of fileSelectionDAG.cpp.
Referencesllvm::ISD::ADDRSPACECAST,assert(),llvm::ISD::EXTRACT_VECTOR_ELT,getAddrSpaceCast(),getBuildVector(),getContext(),getMergeValues(),getNode(),getShiftAmountOperand(),getUNDEF(),llvm::SDValue::getValue(),llvm::SDValue::getValueType(),getValueType(),llvm::EVT::getVectorElementType(),getVectorIdxConstant(),llvm::EVT::getVectorNumElements(),llvm::EVT::getVectorVT(),llvm::EVT::isVector(),N,Operands,llvm::SmallVectorTemplateBase< T, bool >::push_back(),llvm::ISD::ROTL,llvm::ISD::ROTR,llvm::ISD::SELECT,llvm::ISD::SHL,llvm::ISD::SIGN_EXTEND_INREG,llvm::ISD::SRA,llvm::ISD::SRL, andllvm::ISD::VSELECT.
Referenced byllvm::TargetLowering::expandABD(),llvm::TargetLowering::expandAddSubSat(),llvm::TargetLowering::expandFMINIMUM_FMAXIMUM(),llvm::TargetLowering::expandFMINIMUMNUM_FMAXIMUMNUM(),llvm::TargetLowering::expandIntMINMAX(),llvm::TargetLowering::expandShlSat(),LowerVectorFP_TO_INT(),LowerVectorINT_TO_FP(), andunrollVectorShift().
LikeUnrollVectorOp(), but for the [US](ADD|SUB|MUL)O family of opcodes.
This is a separate function because those opcodes have two results.
Definition at line12832 of fileSelectionDAG.cpp.
Referencesllvm::SmallVectorImpl< T >::append(),assert(),ExtractVectorElements(),getBoolConstant(),getBuildVector(),getConstant(),getContext(),getDataLayout(),getNode(),getSelect(),llvm::TargetLoweringBase::getSetCCResultType(),getUNDEF(),llvm::SDValue::getValue(),llvm::EVT::getVectorElementType(),llvm::EVT::getVectorNumElements(),llvm::EVT::getVectorVT(),getVTList(),N,llvm::SmallVectorTemplateBase< T, bool >::push_back(),llvm::ISD::SADDO,llvm::ISD::SMULO,llvm::ISD::SSUBO,llvm::ISD::UADDO,llvm::ISD::UMULO, andllvm::ISD::USUBO.
void SelectionDAG::updateDivergence | ( | SDNode * | N | ) |
Definition at line11943 of fileSelectionDAG.cpp.
Referencesllvm::append_range(),calculateDivergence(),llvm::SmallVectorBase< Size_T >::empty(),N, andllvm::SmallVectorImpl< T >::pop_back_val().
Referenced byReplaceAllUsesOfValueWith(),ReplaceAllUsesWith(), andUpdateNodeOperands().
Definition at line10875 of fileSelectionDAG.cpp.
Referencesassert(),llvm::ArrayRef< T >::begin(),llvm::ArrayRef< T >::end(),N,llvm::ArrayRef< T >::size(), andupdateDivergence().
Mutate the specified node in-place to have the specified operands.
UpdateNodeOperands -Mutate the specified node in-place to have the specified operands.
If the resultant node already exists in the DAG, this does not modify the specified node, instead it returns the node that already exists. If the resultant node does not exist in the DAG, the input node is returned. As a degenerate case, if you specify the same input operands as the node already has, the input node is returned.
Definition at line10801 of fileSelectionDAG.cpp.
Referencesassert(),N, andupdateDivergence().
Referenced byfoldADDIForFasterLocalAccesses(),llvm::SITargetLowering::legalizeTargetIndependentNode(),makeEquivalentMemoryOrdering(),moveBelowOrigChain(),llvm::PPCTargetLowering::PerformDAGCombine(),llvm::AMDGPUTargetLowering::performIntrinsicWOChainCombine(), andUpdateNodeOperands().
Definition at line10826 of fileSelectionDAG.cpp.
Referencesassert(),N, andupdateDivergence().
Definition at line10855 of fileSelectionDAG.cpp.
ReferencesN, andUpdateNodeOperands().
SDNode * SelectionDAG::UpdateNodeOperands | ( | SDNode * | N, |
SDValue | Op1, | ||
SDValue | Op2, | ||
SDValue | Op3, | ||
SDValue | Op4 | ||
) |
Definition at line10861 of fileSelectionDAG.cpp.
ReferencesN, andUpdateNodeOperands().
SDNode * SelectionDAG::UpdateNodeOperands | ( | SDNode * | N, |
SDValue | Op1, | ||
SDValue | Op2, | ||
SDValue | Op3, | ||
SDValue | Op4, | ||
SDValue | Op5 | ||
) |
Definition at line10868 of fileSelectionDAG.cpp.
ReferencesN, andUpdateNodeOperands().
void SelectionDAG::viewGraph | ( | ) |
Definition at line159 of fileSelectionDAGPrinter.cpp.
ReferencesviewGraph().
Referenced byviewGraph().
void SelectionDAG::viewGraph | ( | const std::string & | Title | ) |
Pop up a GraphViz/gv window with the DAG rendered using 'dot'.
viewGraph - Pop up a ghostview window with the reachable parts of the DAG rendered using 'dot'.
Definition at line146 of fileSelectionDAGPrinter.cpp.
Referencesllvm::errs(),getMachineFunction(),getName(), andllvm::ViewGraph().
Widen the vector up to the next power of two using INSERT_SUBVECTOR.
Definition at line13045 of fileSelectionDAG.cpp.
ReferencesDL,getContext(),getNode(),getUNDEF(),llvm::EVT::getVectorElementType(),getVectorIdxConstant(),llvm::EVT::getVectorNumElements(),llvm::EVT::getVectorVT(),llvm::ISD::INSERT_SUBVECTOR,N, andllvm::NextPowerOf2().
Determine if the result of the addition of 2 nodes can never overflow.
Definition at line2000 of fileSelectionDAG.h.
ReferencescomputeOverflowForAdd(), andOFK_Never.
Referenced bycombineAdd(),combineShiftToAVG(), andpromoteExtBeforeAdd().
Determine if the result of the mul of 2 nodes can never overflow.
Definition at line2036 of fileSelectionDAG.h.
ReferencescomputeOverflowForMul(), andOFK_Never.
Determine if the result of the sub of 2 nodes can never overflow.
Definition at line2018 of fileSelectionDAG.h.
ReferencescomputeOverflowForSub(), andOFK_Never.
Referenced byllvm::TargetLowering::expandABD().
| friend |
DAGUpdateListener is a friend so it can manipulate the listener stack.
Definition at line401 of fileSelectionDAG.h.
| staticconstexpr |
Definition at line458 of fileSelectionDAG.h.
Referenced bycollectInstructionDeps(),combineBitcastToBoolVector(),computeKnownBits(),ComputeNumSignBits(),llvm::TargetLowering::getNegatedExpression(),llvm::PPCTargetLowering::getNegatedExpression(),getShuffleScalarElt(),getTargetShuffleInputs(),getUsefulBits(),llvm::RISCVDAGToDAGISel::hasAllNBitUsers(),isFNEG(),isGuaranteedNotToBeUndefOrPoison(),isKnownNeverNaN(),isKnownNeverZero(),isKnownToBeAPowerOfTwo(),isSplatValue(),PromoteMaskArithmetic(),llvm::SelectionDAGBuilder::shouldKeepJumpConditionsTogether(),llvm::TargetLowering::SimplifyDemandedBits(),llvm::TargetLowering::SimplifyDemandedVectorElts(),llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), andtakeInexpensiveLog2().
bool llvm::SelectionDAG::NewNodesMustHaveLegalTypes = false |
When true, additional steps are taken to ensure thatgetConstant() and similar functions return DAG nodes that have legal types.
This is important after type legalization since any illegally typed nodes generated after this point will not experience type legalization.
Definition at line397 of fileSelectionDAG.h.
Referenced bycombineBinOpOfExtractToReduceTree(),FoldConstantArithmetic(),getConstant(), andgetNode().