Movatterモバイル変換

Convenient type to represent the alternatives for mapping an instruction.

Todo:

When we move toTableGen this should be an array ref.

Definition at line277 of fileRegisterBankInfo.h.

Create aRegisterBankInfo that can accommodate up toNumRegBanksRegisterBank instances.

Definition at line56 of fileRegisterBankInfo.cpp.

Referencesassert(),End,getNumRegBanks(),Idx, andRegBanks.

This constructor is meaningless.

It just provides a default constructor that can be used at link time when GlobalISel is not built. That way, targets can still inherit from this class without doing crazy gymnastic to avoid link time failures.

Note

That works because the constructor is inlined.

Definition at line435 of fileRegisterBankInfo.h.

Referencesllvm_unreachable.

Helper method to apply something that is like the default mapping.

Basically, that means thatOpdMapper.getMI() is left untouched aside from the reassignment of the register operand that have been remapped.

The type of all the new registers that have been created by the mapper are properly remapped to the type of the original registers they replace. In other words, the semantic of the instruction does not change, only the register banks.

If the mapping of one of the operand spans several registers, this method will abort as this is not like a default mapping anymore.

Precondition

For OpIdx in {0..OpdMapper.getMI().getNumOperands()) the range OpdMapper.getVRegs(OpIdx) is empty or of size 1.

Definition at line439 of fileRegisterBankInfo.cpp.

Referencesassert(),llvm::iterator_range< IteratorT >::begin(),llvm::dbgs(),llvm::iterator_range< IteratorT >::empty(),llvm::RegisterBankInfo::OperandsMapper::getInstrMapping(),llvm::RegisterBankInfo::OperandsMapper::getMI(),llvm::RegisterBankInfo::OperandsMapper::getMRI(),llvm::RegisterBankInfo::InstructionMapping::getNumOperands(),llvm::MachineOperand::getReg(),llvm::LLT::getSizeInBits(),llvm::RegisterBankInfo::OperandsMapper::getVRegs(),llvm::details::FixedOrScalableQuantity< TypeSize, uint64_t >::isKnownLE(),llvm::MachineOperand::isReg(),llvm::LLT::isValid(),LLVM_DEBUG,MI,MRI,llvm::RegisterBankInfo::ValueMapping::NumBreakDowns,llvm::printReg(), andllvm::MachineOperand::setReg().

Referenced byapplyMapping(),llvm::AMDGPURegisterBankInfo::applyMappingBFE(),llvm::AMDGPURegisterBankInfo::applyMappingImage(),llvm::AMDGPURegisterBankInfo::applyMappingImpl(),llvm::MipsRegisterBankInfo::applyMappingImpl(),llvm::X86RegisterBankInfo::applyMappingImpl(),llvm::AMDGPURegisterBankInfo::applyMappingMAD_64_32(), andllvm::AMDGPURegisterBankInfo::applyMappingSMULU64().

ApplyOpdMapper.getInstrMapping() toOpdMapper.getMI().

After this callOpdMapper.getMI() may not be valid anymore.OpdMapper.getInstrMapping().getID() carries the information of what has been chosen to mapOpdMapper.getMI(). This ID is set by the various getInstrXXXMapping method.

Therefore, getting the mapping and applying it should be kept in sync.

Definition at line735 of fileRegisterBankInfo.h.

ReferencesapplyDefaultMapping(),applyMappingImpl(),DefaultMappingID,llvm::RegisterBankInfo::InstructionMapping::getID(), andllvm::RegisterBankInfo::OperandsMapper::getInstrMapping().

Referenced byllvm::RegBankSelect::applyMapping().

SeeapplyMapping.

Reimplemented inllvm::AMDGPURegisterBankInfo,llvm::MipsRegisterBankInfo, andllvm::X86RegisterBankInfo.

Definition at line576 of fileRegisterBankInfo.h.

Referencesllvm_unreachable.

Referenced byapplyMapping().

Returns

true if emitting a copy fromSrc toDst is impossible.

Definition at line643 of fileRegisterBankInfo.h.

ReferencescopyCost(), andSize.

Referenced byllvm::AMDGPURegisterBankInfo::getInstrMapping(), andgetInstrMappingImpl().

Constrain the (possibly generic) virtual registerReg toRC.

Precondition

Reg is a virtual register that either has a bank or a class.

Returns

The constrained register class, or nullptr if there is none.

Note

This is a generic variant ofMachineRegisterInfo::constrainRegClass

UseMachineRegisterInfo::constrainRegAttrs instead for any non-isel purpose, including non-select passes of GlobalISel

Definition at line132 of fileRegisterBankInfo.cpp.

Referencesllvm::RegisterBank::covers(), andMRI.

Referenced byllvm::AMDGPURegisterBankInfo::buildReadFirstLane(),llvm::AMDGPURegisterBankInfo::buildVCopy(),llvm::constrainRegToClass(),copySubReg(),selectCopy(), andselectDebugInstr().

Get the cost of a copy fromB toA, or put differently, get the cost of A = COPY B.

Since register banks may cover different size,Size specifies what will be the size in bits that will be copied around.

Note

Since this is a copy, both registers have the same size.

Reimplemented inllvm::AArch64RegisterBankInfo, andllvm::AMDGPURegisterBankInfo.

Definition at line633 of fileRegisterBankInfo.h.

ReferencesA, andB.

Referenced bycannotCopy(),llvm::AArch64RegisterBankInfo::copyCost(),llvm::AMDGPURegisterBankInfo::copyCost(), andllvm::RegBankSelect::getRepairCost().

Get the cost of usingValMapping to decompose a register.

This is similar tocopyCost, except for cases where multiple copy-like operations need to be inserted. If the register is used as a source operand and already has a bank assigned,CurBank is non-null.

Reimplemented inllvm::AMDGPURegisterBankInfo.

Definition at line653 of fileRegisterBankInfo.h.

Referenced byllvm::RegBankSelect::getRepairCost().

Get the alternative mappings forMI.

Alternative in the sense different from getInstrMapping.

Reimplemented inllvm::AArch64RegisterBankInfo,llvm::AMDGPURegisterBankInfo,llvm::PPCRegisterBankInfo, andllvm::X86RegisterBankInfo.

Definition at line434 of fileRegisterBankInfo.cpp.

Referenced byllvm::AArch64RegisterBankInfo::getInstrAlternativeMappings(),llvm::AMDGPURegisterBankInfo::getInstrAlternativeMappings(),llvm::PPCRegisterBankInfo::getInstrAlternativeMappings(),llvm::X86RegisterBankInfo::getInstrAlternativeMappings(),llvm::AMDGPURegisterBankInfo::getInstrAlternativeMappingsIntrinsic(),llvm::AMDGPURegisterBankInfo::getInstrAlternativeMappingsIntrinsicWSideEffects(), andgetInstrPossibleMappings().

Get the mapping of the different operands ofMI on the register bank.

This mapping should be the direct translation ofMI. In other words, whenMI is mapped with the returned mapping, only the register banks of the operands ofMI need to be updated. In particular, neither the opcode nor the type ofMI needs to be updated for this direct mapping.

The target independent implementation gives a mapping based on the register classes for the target specific opcode. It uses the IDRegisterBankInfo::DefaultMappingID for that mapping. Make sure you do not use that ID for the alternative mapping for MI. See getInstrAlternativeMappings for the alternative mappings.

For instance, ifMI is a vector add, the mapping should not be a scalarization of the add.

Postcondition

returnedVal.verify(MI).

Note

If returnedVal does not verify MI, this would probably mean that the target does not support that instruction.

Reimplemented inllvm::AArch64RegisterBankInfo,llvm::AMDGPURegisterBankInfo,llvm::ARMRegisterBankInfo,llvm::M68kRegisterBankInfo,llvm::MipsRegisterBankInfo,llvm::PPCRegisterBankInfo,llvm::RISCVRegisterBankInfo, andllvm::X86RegisterBankInfo.

Definition at line407 of fileRegisterBankInfo.cpp.

ReferencesgetInstrMappingImpl(),llvm::RegisterBankInfo::InstructionMapping::isValid(),llvm_unreachable, andMI.

Referenced byllvm::RegBankSelect::assignInstr(),llvm::RegisterBankInfo::OperandsMapper::createVRegs(),getInstrPossibleMappings(),llvm::RegisterBankInfo::OperandsMapper::getVRegs(),llvm::RegisterBankInfo::OperandsMapper::print(), andllvm::RegisterBankInfo::OperandsMapper::setVRegs().

Try to get the mapping ofMI.

See getInstrMapping for more details on what a mapping represents.

Unlike getInstrMapping the returnedInstructionMapping may be invalid (isValid() == false). This means that the target independent code is not smart enough to get the mapping ofMI and thus, the target has to provide the information forMI.

This implementation is able to get the mapping of:

• Target specific instructions by looking at the encoding constraints.
• Any instruction if all the register operands have already been assigned a register, a register class, or a register bank.
• Copies and phis if at least one of the operands has been assigned a register, a register class, or a register bank. In other words, this method will likely fail to find a mapping for any generic opcode that has not been lowered by target specific code.

Definition at line162 of fileRegisterBankInfo.cpp.

Referencesassert(),cannotCopy(),DefaultMappingID,llvm::TargetSubtargetInfo::getInstrInfo(),getInstructionMapping(),getInvalidInstructionMapping(),getOperandsMapping(),llvm::MachineOperand::getReg(),getRegBank(),getRegBankFromConstraints(),llvm::MachineFunction::getRegInfo(),llvm::TargetSubtargetInfo::getRegisterInfo(),getSizeInBits(),llvm::MachineFunction::getSubtarget(),getValueMapping(),isCopyLike(),llvm::MachineOperand::isReg(),MI,MRI,Size,TII, andTRI.

Referenced bygetInstrMapping(),llvm::AArch64RegisterBankInfo::getInstrMapping(),llvm::AMDGPURegisterBankInfo::getInstrMapping(),llvm::ARMRegisterBankInfo::getInstrMapping(),llvm::M68kRegisterBankInfo::getInstrMapping(),llvm::MipsRegisterBankInfo::getInstrMapping(),llvm::PPCRegisterBankInfo::getInstrMapping(),llvm::RISCVRegisterBankInfo::getInstrMapping(), andllvm::X86RegisterBankInfo::getInstrMapping().

Get the possible mapping forMI.

A mapping defines where the different operands may live and at what cost. For instance, let us consider: v0(16) = G_ADD <2 x i8> v1, v2 The possible mapping could be:

{/*ID*‍/VectorAdd, /*Cost*‍/1, /*v0*‍/{(0xFFFF, VPR)}, /*v1*‍/{(0xFFFF, VPR)}, /*v2*‍/{(0xFFFF, VPR)}} {/*ID*‍/ScalarAddx2, /*Cost*‍/2, /*v0*‍/{(0x00FF, GPR),(0xFF00, GPR)}, /*v1*‍/{(0x00FF, GPR),(0xFF00, GPR)}, /*v2*‍/{(0x00FF, GPR),(0xFF00, GPR)}}

Note

The first alternative of the returned mapping should be the direct translation ofMI current form.

Postcondition

!returnedVal.empty().

Definition at line415 of fileRegisterBankInfo.cpp.

Referencesllvm::append_range(),assert(),getInstrAlternativeMappings(),getInstrMapping(),MI, andllvm::SmallVectorTemplateBase< T, bool >::push_back().

Referenced byllvm::RegBankSelect::assignInstr().

Method to get a uniquely generatedInstructionMapping.

Definition at line534 of fileRegisterBankInfo.h.

Referenced byllvm::AMDGPURegisterBankInfo::addMappingFromTable(),llvm::AMDGPURegisterBankInfo::getDefaultMappingAllVGPR(),llvm::AMDGPURegisterBankInfo::getDefaultMappingSOP(),llvm::AMDGPURegisterBankInfo::getDefaultMappingVOP(),llvm::AMDGPURegisterBankInfo::getImageMapping(),llvm::AArch64RegisterBankInfo::getInstrAlternativeMappings(),llvm::AMDGPURegisterBankInfo::getInstrAlternativeMappings(),llvm::X86RegisterBankInfo::getInstrAlternativeMappings(),llvm::AArch64RegisterBankInfo::getInstrMapping(),llvm::AMDGPURegisterBankInfo::getInstrMapping(),llvm::ARMRegisterBankInfo::getInstrMapping(),llvm::M68kRegisterBankInfo::getInstrMapping(),llvm::MipsRegisterBankInfo::getInstrMapping(),llvm::PPCRegisterBankInfo::getInstrMapping(),llvm::RISCVRegisterBankInfo::getInstrMapping(),llvm::X86RegisterBankInfo::getInstrMapping(),llvm::AMDGPURegisterBankInfo::getInstrMappingForLoad(), andgetInstrMappingImpl().

Method to get a uniquely generated invalidInstructionMapping.

Definition at line542 of fileRegisterBankInfo.h.

Referenced byllvm::AArch64RegisterBankInfo::getInstrMapping(),llvm::AMDGPURegisterBankInfo::getInstrMapping(),llvm::ARMRegisterBankInfo::getInstrMapping(),llvm::M68kRegisterBankInfo::getInstrMapping(),llvm::MipsRegisterBankInfo::getInstrMapping(),llvm::PPCRegisterBankInfo::getInstrMapping(),llvm::X86RegisterBankInfo::getInstrMapping(), andgetInstrMappingImpl().

Get the maximum size in bits that fits in the given register bank.

Definition at line590 of fileRegisterBankInfo.h.

ReferencesHwMode,NumRegBanks, andSizes.

Referenced byllvm::AArch64RegisterBankInfo::AArch64RegisterBankInfo(),llvm::ARMRegisterBankInfo::ARMRegisterBankInfo(),llvm::RISCVRegisterBankInfo::getInstrMapping(),llvm::RegisterBankInfo::PartialMapping::verify(),llvm::RegisterBank::verify(), andllvm::X86RegisterBankInfo::X86RegisterBankInfo().

Get the MinimalPhysRegClass for Reg.

Precondition

Reg is a physical register.

Definition at line103 of fileRegisterBankInfo.cpp.

Referencesassert(),PhysRegMinimalRCs, andTRI.

Referenced bygetRegBank(), andgetSizeInBits().

Get the total number of register banks.

Definition at line603 of fileRegisterBankInfo.h.

ReferencesNumRegBanks.

Referenced bygetRegBank(),RegisterBankInfo(), andverify().

Get the uniquely generated array ofValueMapping for the elements ofOpdsMapping.

Elements ofOpdsMapping that are nullptr will be replaced by invalidValueMapping (ValueMapping::isValid == false).

Definition at line362 of fileRegisterBankInfo.cpp.

Referencesllvm::SmallVectorTemplateCommon< T, typename >::begin(),llvm::SmallVectorTemplateCommon< T, typename >::end(), andgetOperandsMapping().

Get the uniquely generated array ofValueMapping for the elements of betweenBegin andEnd.

Elements that are nullptr will be replaced by invalidValueMapping (ValueMapping::isValid == false).

Precondition

The pointers onValueMapping betweenBegin andEnd must uniquely identify aValueMapping. Otherwise, there is no guarantee that the return instance will be unique, i.e., another OperandsMapping could have the same content.

Definition at line333 of fileRegisterBankInfo.cpp.

ReferencesEnd,llvm::hash_combine_range(),Idx, andMapOfOperandsMappings.

Referenced byllvm::AMDGPURegisterBankInfo::addMappingFromTable(),llvm::AMDGPURegisterBankInfo::getDefaultMappingAllVGPR(),llvm::AMDGPURegisterBankInfo::getDefaultMappingSOP(),llvm::AMDGPURegisterBankInfo::getDefaultMappingVOP(),llvm::AMDGPURegisterBankInfo::getImageMapping(),llvm::AArch64RegisterBankInfo::getInstrAlternativeMappings(),llvm::AMDGPURegisterBankInfo::getInstrAlternativeMappings(),llvm::X86RegisterBankInfo::getInstrAlternativeMappings(),llvm::AArch64RegisterBankInfo::getInstrMapping(),llvm::AMDGPURegisterBankInfo::getInstrMapping(),llvm::ARMRegisterBankInfo::getInstrMapping(),llvm::M68kRegisterBankInfo::getInstrMapping(),llvm::MipsRegisterBankInfo::getInstrMapping(),llvm::PPCRegisterBankInfo::getInstrMapping(),llvm::RISCVRegisterBankInfo::getInstrMapping(),llvm::X86RegisterBankInfo::getInstrMapping(),llvm::AMDGPURegisterBankInfo::getInstrMappingForLoad(),getInstrMappingImpl(), andgetOperandsMapping().

Get the uniquely generated array ofValueMapping for the given arguments.

Arguments that are nullptr will be replaced by invalidValueMapping (ValueMapping::isValid == false).

Get the uniquely generatedPartialMapping for the given arguments.

Definition at line281 of fileRegisterBankInfo.cpp.

ReferenceshashPartialMapping(),llvm::Length, andMapOfPartialMappings.

Referenced bygetValueMapping().

Get the register bank ofReg.

If Reg has not been assigned a register, a register class, or a register bank, then this returns nullptr.

Precondition

Reg != 0 (NoRegister)

Definition at line84 of fileRegisterBankInfo.cpp.

ReferencesgetMinimalPhysRegClass(),getRegBankFromRegClass(),MRI, andTRI.

Get the register bank identified byID.

Definition at line440 of fileRegisterBankInfo.h.

Referencesassert(),getNumRegBanks(), andRegBanks.

Referenced byllvm::AArch64RegisterBankInfo::AArch64RegisterBankInfo(),llvm::AMDGPURegisterBankInfo::AMDGPURegisterBankInfo(),llvm::AMDGPURegisterBankInfo::applyMappingDynStackAlloc(),llvm::AMDGPURegisterBankInfo::applyMappingImpl(),llvm::ARMRegisterBankInfo::ARMRegisterBankInfo(),llvm::RegBankSelect::assignInstr(),llvm::RegBankSelect::assignmentMatch(),buildReadAnyLane(),llvm::AMDGPURegisterBankInfo::buildReadFirstLane(),llvm::AMDGPURegisterBankInfo::collectWaterfallOperands(),llvm::AMDGPURegisterBankInfo::constrainOpWithReadfirstlane(),llvm::AMDGPURegisterBankInfo::executeInWaterfallLoop(),llvm::GIMatchTableExecutor::executeMatchTable(),llvm::AArch64RegisterBankInfo::getInstrMapping(),llvm::AMDGPURegisterBankInfo::getInstrMapping(),llvm::RISCVRegisterBankInfo::getInstrMapping(),llvm::AMDGPURegisterBankInfo::getInstrMappingForLoad(),getInstrMappingImpl(),llvm::SIInstrInfo::getInstructionUniformity(),llvm::AMDGPURegisterBankInfo::getMappingType(),llvm::CombinerHelper::getRegBank(),getRegBank(),llvm::AArch64RegisterBankInfo::getRegBankFromRegClass(),llvm::PPCRegisterBankInfo::getRegBankFromRegClass(),llvm::AMDGPURegisterBankInfo::getRegBankID(),getRegClassesForCopy(),llvm::RegBankSelect::getRepairCost(),llvm::AMDGPURegisterBankInfo::getValueMappingForPtr(),llvm::AMDGPURegisterBankInfo::isSALUMapping(),llvm::SIRegisterInfo::isUniformReg(),selectCopy(),selectMergeValues(),selectUnmergeValues(),llvm::AMDGPURegisterBankInfo::setBufferOffsets(),llvm::MipsRegisterBankInfo::setRegBank(),llvm::AMDGPURegisterBankInfo::split64BitValueForMapping(),unmergeReadAnyLane(),unsupportedBinOp(),verify(), andllvm::X86RegisterBankInfo::X86RegisterBankInfo().

Get the register bank identified byID.

Definition at line585 of fileRegisterBankInfo.h.

ReferencesgetRegBank().

Get the register bank for theOpIdx-th operand ofMI form the encoding constraints, if any.

Returns

A register bank that covers the register class of the related encoding constraints or nullptr ifMI did not provide enough information to deduce it.

Definition at line112 of fileRegisterBankInfo.cpp.

Referencesassert(),llvm::RegisterBank::covers(),getRegBankFromRegClass(),MI,MRI,TII, andTRI.

Referenced bygetInstrMappingImpl().

Get a register bank that coversRC.

Precondition

RC is a user-defined register class (as opposed as one generated byTableGen).

Note

The mapping RC -> RegBank could be built while adding the coverage for the register banks. However, we do not do it, because, at least for now, we only need this information for register classes that are used in the description of instruction. In other words, there are just a handful of them and we do not want to waste space.

Todo:

This should beTableGen'ed.

Reimplemented inllvm::AArch64RegisterBankInfo,llvm::PPCRegisterBankInfo,llvm::SPIRVRegisterBankInfo, andllvm::AMDGPURegisterBankInfo.

Definition at line623 of fileRegisterBankInfo.h.

Referencesllvm_unreachable.

Referenced byllvm::GIMatchTableExecutor::executeMatchTable(),getRegBank(),getRegBankFromConstraints(),llvm::AArch64RegisterBankInfo::getRegBankFromRegClass(), andllvm::PPCRegisterBankInfo::getRegBankFromRegClass().

Get the size in bits ofReg.

Utility method to get the size of any registers. Unlike MachineRegisterInfo::getSize, the register does not need to be a virtual register.

Precondition

Reg != 0 (NoRegister).

Definition at line498 of fileRegisterBankInfo.cpp.

Referencesassert(),getMinimalPhysRegClass(),MRI, andTRI.

Referenced byllvm::AMDGPURegisterBankInfo::addMappingFromTable(),llvm::AMDGPURegisterBankInfo::getAGPROpMapping(),llvm::AMDGPURegisterBankInfo::getDefaultMappingAllVGPR(),llvm::AMDGPURegisterBankInfo::getDefaultMappingSOP(),llvm::AMDGPURegisterBankInfo::getDefaultMappingVOP(),llvm::AMDGPURegisterBankInfo::getImageMapping(),llvm::AArch64RegisterBankInfo::getInstrAlternativeMappings(),llvm::AMDGPURegisterBankInfo::getInstrAlternativeMappings(),llvm::X86RegisterBankInfo::getInstrAlternativeMappings(),llvm::AArch64RegisterBankInfo::getInstrMapping(),llvm::AMDGPURegisterBankInfo::getInstrMapping(),llvm::MipsRegisterBankInfo::getInstrMapping(),llvm::PPCRegisterBankInfo::getInstrMapping(),llvm::AMDGPURegisterBankInfo::getInstrMappingForLoad(),getInstrMappingImpl(),getRegClassesForCopy(),llvm::RegBankSelect::getRepairCost(),llvm::AMDGPURegisterBankInfo::getSGPROpMapping(),llvm::AMDGPURegisterBankInfo::getVGPROpMapping(),selectCopy(), andllvm::RegisterBankInfo::InstructionMapping::verify().

Get theValueMapping for the given arguments.

Definition at line315 of fileRegisterBankInfo.cpp.

ReferenceshashValueMapping(), andMapOfValueMappings.

The most commonValueMapping consists of a singlePartialMapping.

Feature a method for that.

Definition at line298 of fileRegisterBankInfo.cpp.

ReferencesgetPartialMapping(),getValueMapping(), andllvm::Length.

Referenced byllvm::AMDGPURegisterBankInfo::getInstrMapping(),getInstrMappingImpl(), andgetValueMapping().

Returns true if the register bank is considered divergent.

Reimplemented inllvm::AMDGPURegisterBankInfo.

Definition at line606 of fileRegisterBankInfo.h.

Referenced byllvm::SIRegisterInfo::isUniformReg().

Check that information hold by this instance make sense for the givenTRI.

Note

This method does not check anything when assertions are disabled.

Returns

True is the check was successful.

Definition at line70 of fileRegisterBankInfo.cpp.

Referencesassert(),llvm::dbgs(),End,llvm::RegisterBank::getID(),getNumRegBanks(),getRegBank(),Idx,LLVM_DEBUG,TRI, andllvm::RegisterBank::verify().

Identifier used when the related instruction mapping instance is generated by target independent code.

Make sure not to use that identifier to avoid possible collision.

Definition at line672 of fileRegisterBankInfo.h.

Referenced byapplyMapping(),llvm::AArch64RegisterBankInfo::getInstrMapping(),llvm::ARMRegisterBankInfo::getInstrMapping(),llvm::M68kRegisterBankInfo::getInstrMapping(),llvm::MipsRegisterBankInfo::getInstrMapping(),llvm::PPCRegisterBankInfo::getInstrMapping(),llvm::RISCVRegisterBankInfo::getInstrMapping(),llvm::X86RegisterBankInfo::getInstrMapping(), andgetInstrMappingImpl().

Current HwMode for the target.

Definition at line398 of fileRegisterBankInfo.h.

Referenced bygetMaximumSize().

Identifier used when the related instruction mapping instance is generated by the default constructor.

Make sure not to use that identifier.

Definition at line677 of fileRegisterBankInfo.h.

Referenced byllvm::RegisterBankInfo::InstructionMapping::isValid().

Keep dynamically allocatedInstructionMapping in a separate map.

This shouldn't be needed when everything getsTableGen'ed.

Definition at line418 of fileRegisterBankInfo.h.

Keep dynamically allocated array ofValueMapping in a separate map.

This shouldn't be needed when everything getsTableGen'ed.

Definition at line413 of fileRegisterBankInfo.h.

Referenced bygetOperandsMapping().

Keep dynamically allocatedPartialMapping in a separate map.

This shouldn't be needed when everything getsTableGen'ed.

Definition at line403 of fileRegisterBankInfo.h.

Referenced bygetPartialMapping().

Keep dynamically allocatedValueMapping in a separate map.

This shouldn't be needed when everything getsTableGen'ed.

Definition at line408 of fileRegisterBankInfo.h.

Referenced bygetValueMapping().

Total number of register banks.

Definition at line392 of fileRegisterBankInfo.h.

Referenced bygetMaximumSize(), andgetNumRegBanks().

Getting the minimal register class of a physreg is expensive.

Cache this information as we get it.

Definition at line422 of fileRegisterBankInfo.h.

Referenced bygetMinimalPhysRegClass().

Hold the set of supported register banks.

Definition at line389 of fileRegisterBankInfo.h.

Referenced bygetRegBank(), andRegisterBankInfo().

Hold the sizes of the register banks for all HwModes.

Definition at line395 of fileRegisterBankInfo.h.

Referenced byllvm::AMDGPURegisterBankInfo::addMappingFromTable(), andgetMaximumSize().