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LLVM 20.0.0git
Classes |Public Types |Public Member Functions |Static Public Member Functions |Friends |List of all members
llvm::MachineOperand Class Reference

MachineOperand class - Representation of each machine instruction operand.More...

#include "llvm/CodeGen/MachineOperand.h"

Public Types

enum  MachineOperandType : unsigned char {
  MO_Register,MO_Immediate,MO_CImmediate,MO_FPImmediate,
  MO_MachineBasicBlock,MO_FrameIndex,MO_ConstantPoolIndex,MO_TargetIndex,
  MO_JumpTableIndex,MO_ExternalSymbol,MO_GlobalAddress,MO_BlockAddress,
  MO_RegisterMask,MO_RegisterLiveOut,MO_Metadata,MO_MCSymbol,
  MO_CFIIndex,MO_IntrinsicID,MO_Predicate,MO_ShuffleMask,
  MO_DbgInstrRef,MO_Last = MO_DbgInstrRef
}
 

Public Member Functions

MachineOperandType getType ()const
 getType - Returns the MachineOperandType for this operand.
 
unsigned getTargetFlags ()const
 
void setTargetFlags (unsignedF)
 
void addTargetFlag (unsignedF)
 
MachineInstrgetParent ()
 getParent - Return the instruction that this operand belongs to.
 
constMachineInstrgetParent ()const
 
void clearParent ()
 clearParent - Reset the parent pointer.
 
unsigned getOperandNo ()const
 Returns the index of this operand in the instruction that it belongs to.
 
void print (raw_ostream &os,constTargetRegisterInfo *TRI=nullptr,constTargetIntrinsicInfo *IntrinsicInfo=nullptr)const
 Print theMachineOperand toos.
 
void print (raw_ostream &os,ModuleSlotTracker &MST,LLT TypeToPrint, std::optional<unsigned > OpIdx,bool PrintDef,bool IsStandalone,bool ShouldPrintRegisterTies,unsigned TiedOperandIdx,constTargetRegisterInfo *TRI,constTargetIntrinsicInfo *IntrinsicInfo)const
 More complex way of printing aMachineOperand.
 
void print (raw_ostream &os,LLT TypeToPrint,constTargetRegisterInfo *TRI=nullptr,constTargetIntrinsicInfo *IntrinsicInfo=nullptr)const
 Same as print(os, TRI, IntrinsicInfo), but allows to specify the low-level type to be printed the same way the full version of print(...) does it.
 
void dump ()const
 
bool isReg ()const
 isReg - Tests if this is a MO_Register operand.
 
bool isImm ()const
 isImm - Tests if this is a MO_Immediate operand.
 
bool isCImm ()const
 isCImm - Test if this is a MO_CImmediate operand.
 
bool isFPImm ()const
 isFPImm - Tests if this is a MO_FPImmediate operand.
 
bool isMBB ()const
 isMBB - Tests if this is a MO_MachineBasicBlock operand.
 
bool isFI ()const
 isFI - Tests if this is a MO_FrameIndex operand.
 
bool isCPI ()const
 isCPI - Tests if this is a MO_ConstantPoolIndex operand.
 
bool isTargetIndex ()const
 isTargetIndex - Tests if this is a MO_TargetIndex operand.
 
bool isJTI ()const
 isJTI - Tests if this is a MO_JumpTableIndex operand.
 
bool isGlobal ()const
 isGlobal - Tests if this is a MO_GlobalAddress operand.
 
bool isSymbol ()const
 isSymbol - Tests if this is a MO_ExternalSymbol operand.
 
bool isBlockAddress ()const
 isBlockAddress - Tests if this is a MO_BlockAddress operand.
 
bool isRegMask ()const
 isRegMask - Tests if this is a MO_RegisterMask operand.
 
bool isRegLiveOut ()const
 isRegLiveOut - Tests if this is a MO_RegisterLiveOut operand.
 
bool isMetadata ()const
 isMetadata - Tests if this is a MO_Metadata operand.
 
bool isMCSymbol ()const
 
bool isDbgInstrRef ()const
 
bool isCFIIndex ()const
 
bool isIntrinsicID ()const
 
bool isPredicate ()const
 
bool isShuffleMask ()const
 
Register getReg ()const
 getReg - Returns the register number.
 
unsigned getSubReg ()const
 
bool isUse ()const
 
bool isDef ()const
 
bool isImplicit ()const
 
bool isDead ()const
 
bool isKill ()const
 
bool isUndef ()const
 
bool isRenamable ()const
 isRenamable - Returns true if this register may be renamed, i.e.
 
bool isInternalRead ()const
 
bool isEarlyClobber ()const
 
bool isTied ()const
 
bool isDebug ()const
 
bool readsReg ()const
 readsReg - Returns true if this operand reads the previous value of its register.
 
bool isValidExcessOperand ()const
 Return true if this operand can validly be appended to an arbitrary operand list.
 
void setReg (RegisterReg)
 Change the register this operand corresponds to.
 
void setSubReg (unsigned subReg)
 
void substVirtReg (RegisterReg,unsigned SubIdx,constTargetRegisterInfo &)
 substVirtReg - Substitute the current register with the virtual subregister Reg:SubReg.
 
void substPhysReg (MCRegisterReg,constTargetRegisterInfo &)
 substPhysReg - Substitute the current register with the physical register Reg, taking any existing SubReg into account.
 
void setIsUse (bool Val=true)
 
void setIsDef (bool Val=true)
 Change a def to a use, or a use to a def.
 
void setImplicit (bool Val=true)
 
void setIsKill (bool Val=true)
 
void setIsDead (bool Val=true)
 
void setIsUndef (bool Val=true)
 
void setIsRenamable (bool Val=true)
 
void setIsInternalRead (bool Val=true)
 
void setIsEarlyClobber (bool Val=true)
 
void setIsDebug (bool Val=true)
 
int64_t getImm ()const
 
constConstantIntgetCImm ()const
 
constConstantFPgetFPImm ()const
 
MachineBasicBlockgetMBB ()const
 
int getIndex ()const
 
constGlobalValuegetGlobal ()const
 
constBlockAddressgetBlockAddress ()const
 
MCSymbolgetMCSymbol ()const
 
unsigned getInstrRefInstrIndex ()const
 
unsigned getInstrRefOpIndex ()const
 
unsigned getCFIIndex ()const
 
Intrinsic::ID getIntrinsicID ()const
 
unsigned getPredicate ()const
 
ArrayRef< int > getShuffleMask ()const
 
int64_t getOffset ()const
 Return the offset from the symbol in this operand.
 
constchargetSymbolName ()const
 
bool clobbersPhysReg (MCRegister PhysReg)const
 clobbersPhysReg - Returns true if this RegMask operand clobbers PhysReg.
 
constuint32_tgetRegMask ()const
 getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
 
constuint32_tgetRegLiveOut ()const
 getRegLiveOut - Returns a bit mask of live-out registers.
 
constMDNodegetMetadata ()const
 
void setImm (int64_t immVal)
 
void setCImm (constConstantInt *CI)
 
void setFPImm (constConstantFP *CFP)
 
void setOffset (int64_tOffset)
 
void setIndex (intIdx)
 
void setMetadata (constMDNode *MD)
 
void setInstrRefInstrIndex (unsigned InstrIdx)
 
void setInstrRefOpIndex (unsigned OpIdx)
 
void setMBB (MachineBasicBlock *MBB)
 
void setRegMask (constuint32_t *RegMaskPtr)
 Sets value of register mask operand referencing Mask.
 
void setIntrinsicID (Intrinsic::ID IID)
 
void setPredicate (unsignedPredicate)
 
bool isIdenticalTo (constMachineOperand &Other)const
 Returns true if this operand is identical to the specified operand except for liveness related flags (isKill, isUndef and isDead).
 
void ChangeToImmediate (int64_t ImmVal,unsigned TargetFlags=0)
 ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.
 
void ChangeToFPImmediate (constConstantFP *FPImm,unsigned TargetFlags=0)
 ChangeToFPImmediate - Replace this operand with a new FP immediate operand of the specified value.
 
void ChangeToES (constchar *SymName,unsigned TargetFlags=0)
 ChangeToES - Replace this operand with a new external symbol operand.
 
void ChangeToGA (constGlobalValue *GV, int64_tOffset,unsigned TargetFlags=0)
 ChangeToGA - Replace this operand with a new global address operand.
 
void ChangeToBA (constBlockAddress *BA, int64_tOffset,unsigned TargetFlags=0)
 ChangeToBA - Replace this operand with a new block address operand.
 
void ChangeToMCSymbol (MCSymbol *Sym,unsigned TargetFlags=0)
 ChangeToMCSymbol - Replace this operand with a new MC symbol operand.
 
void ChangeToFrameIndex (intIdx,unsigned TargetFlags=0)
 Replace this operand with a frame index.
 
void ChangeToTargetIndex (unsignedIdx, int64_tOffset,unsigned TargetFlags=0)
 Replace this operand with a target index.
 
void ChangeToDbgInstrRef (unsigned InstrIdx,unsigned OpIdx,unsigned TargetFlags=0)
 Replace this operand with anInstruction Reference.
 
void ChangeToRegister (RegisterReg,boolisDef,bool isImp=false,boolisKill=false,boolisDead=false,boolisUndef=false,boolisDebug=false)
 ChangeToRegister - Replace this operand with a new register operand of the specified value.
 
constchargetTargetIndexName ()const
 getTargetIndexName - If thisMachineOperand is a TargetIndex that has a name, attempt to get the name.
 

Static Public Member Functions

static void printSubRegIdx (raw_ostream &OS,uint64_tIndex,constTargetRegisterInfo *TRI)
 Print a subreg index operand.
 
static void printTargetFlags (raw_ostream &OS,constMachineOperand &Op)
 Print operand target flags.
 
static void printSymbol (raw_ostream &OS,MCSymbol &Sym)
 Print aMCSymbol as an operand.
 
static void printStackObjectReference (raw_ostream &OS,unsigned FrameIndex,bool IsFixed,StringRefName)
 Print a stack object reference.
 
static void printOperandOffset (raw_ostream &OS, int64_tOffset)
 Print the offset with explicit +/- signs.
 
static void printIRSlotNumber (raw_ostream &OS, int Slot)
 Print an IRSlotNumber.
 
staticbool clobbersPhysReg (constuint32_t *RegMask,MCRegister PhysReg)
 clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
 
staticunsigned getRegMaskSize (unsigned NumRegs)
 Returns number of elements needed for a regmask array.
 
staticMachineOperand CreateImm (int64_t Val)
 
staticMachineOperand CreateCImm (constConstantInt *CI)
 
staticMachineOperand CreateFPImm (constConstantFP *CFP)
 
staticMachineOperand CreateReg (RegisterReg,boolisDef,bool isImp=false,boolisKill=false,boolisDead=false,boolisUndef=false,boolisEarlyClobber=false,unsignedSubReg=0,boolisDebug=false,boolisInternalRead=false,boolisRenamable=false)
 
staticMachineOperand CreateMBB (MachineBasicBlock *MBB,unsigned TargetFlags=0)
 
staticMachineOperand CreateFI (intIdx)
 
staticMachineOperand CreateCPI (unsignedIdx, intOffset,unsigned TargetFlags=0)
 
staticMachineOperand CreateTargetIndex (unsignedIdx, int64_tOffset,unsigned TargetFlags=0)
 
staticMachineOperand CreateJTI (unsignedIdx,unsigned TargetFlags=0)
 
staticMachineOperand CreateGA (constGlobalValue *GV, int64_tOffset,unsigned TargetFlags=0)
 
staticMachineOperand CreateES (constchar *SymName,unsigned TargetFlags=0)
 
staticMachineOperand CreateBA (constBlockAddress *BA, int64_tOffset,unsigned TargetFlags=0)
 
staticMachineOperand CreateRegMask (constuint32_t *Mask)
 CreateRegMask - Creates a register mask operand referencing Mask.
 
staticMachineOperand CreateRegLiveOut (constuint32_t *Mask)
 
staticMachineOperand CreateMetadata (constMDNode *Meta)
 
staticMachineOperand CreateMCSymbol (MCSymbol *Sym,unsigned TargetFlags=0)
 
staticMachineOperand CreateDbgInstrRef (unsigned InstrIdx,unsigned OpIdx)
 
staticMachineOperand CreateCFIIndex (unsigned CFIIndex)
 
staticMachineOperand CreateIntrinsicID (Intrinsic::IDID)
 
staticMachineOperand CreatePredicate (unsigned Pred)
 
staticMachineOperand CreateShuffleMask (ArrayRef< int > Mask)
 

Friends

class MachineInstr
 
class MachineRegisterInfo
 
struct DenseMapInfo< MachineOperand >
 
hash_code hash_value (constMachineOperand &MO)
 MachineOperand hash_value overload.
 

Detailed Description

MachineOperand class - Representation of each machine instruction operand.

This class isn't a POD type because it has a private constructor, but its destructor must be trivial. Functions likeMachineInstr::addOperand(),MachineRegisterInfo::moveOperands(), and MF::DeleteMachineInstr() depend on not having to call theMachineOperand destructor.

Definition at line48 of fileMachineOperand.h.

Member Enumeration Documentation

◆ MachineOperandType

enumllvm::MachineOperand::MachineOperandType :unsignedchar
Enumerator
MO_Register 

Register operand.

MO_Immediate 

Immediate operand.

MO_CImmediate 

Immediate >64bit operand.

MO_FPImmediate 

Floating-point immediate operand.

MO_MachineBasicBlock 

MachineBasicBlock reference.

MO_FrameIndex 

Abstract Stack Frame Index.

MO_ConstantPoolIndex 

Address of indexedConstant inConstant Pool.

MO_TargetIndex 

Target-dependent index+offset operand.

MO_JumpTableIndex 

Address of indexed Jump Table for switch.

MO_ExternalSymbol 

Name of external global symbol.

MO_GlobalAddress 

Address of a global value.

MO_BlockAddress 

Address of a basic block.

MO_RegisterMask 

Mask of preserved registers.

MO_RegisterLiveOut 

Mask of live-out registers.

MO_Metadata 

Metadata reference (for debug info)

MO_MCSymbol 

MCSymbol reference (for debug/eh info)

MO_CFIIndex 

MCCFIInstruction index.

MO_IntrinsicID 

Intrinsic ID for ISel.

MO_Predicate 

Generic predicate for ISel.

MO_ShuffleMask 

Other IRConstant for ISel (shuffle masks)

MO_DbgInstrRef 

Integer indices referring to an instruction+operand.

MO_Last 

Definition at line50 of fileMachineOperand.h.

Member Function Documentation

◆ addTargetFlag()

void llvm::MachineOperand::addTargetFlag(unsigned F)
inline

Definition at line234 of fileMachineOperand.h.

Referencesassert(),F, andisReg().

Referenced byllvm::HexagonInstrInfo::immediateExtend().

◆ ChangeToBA()

void MachineOperand::ChangeToBA(constBlockAddressBA,
int64_t Offset,
unsigned TargetFlags =0 
)

ChangeToBA - Replace this operand with a new block address operand.

Definition at line209 of fileMachineOperand.cpp.

Referencesassert(),isReg(),isTied(),MO_BlockAddress,llvm::Offset,setOffset(), andsetTargetFlags().

◆ ChangeToDbgInstrRef()

void MachineOperand::ChangeToDbgInstrRef(unsigned InstrIdx,
unsigned OpIdx,
unsigned TargetFlags =0 
)

Replace this operand with anInstruction Reference.

Definition at line257 of fileMachineOperand.cpp.

Referencesassert(),isReg(),isTied(),MO_DbgInstrRef,setInstrRefInstrIndex(),setInstrRefOpIndex(), andsetTargetFlags().

◆ ChangeToES()

void MachineOperand::ChangeToES(constcharSymName,
unsigned TargetFlags =0 
)

ChangeToES - Replace this operand with a new external symbol operand.

Definition at line183 of fileMachineOperand.cpp.

Referencesassert(),isReg(),isTied(),MO_ExternalSymbol,setOffset(), andsetTargetFlags().

◆ ChangeToFPImmediate()

void MachineOperand::ChangeToFPImmediate(constConstantFPFPImm,
unsigned TargetFlags =0 
)

ChangeToFPImmediate - Replace this operand with a new FP immediate operand of the specified value.

If an operand is known to be an FP immediate already, the setFPImm method should be used.

Definition at line172 of fileMachineOperand.cpp.

Referencesassert(),isReg(),isTied(),MO_FPImmediate, andsetTargetFlags().

◆ ChangeToFrameIndex()

void MachineOperand::ChangeToFrameIndex(int Idx,
unsigned TargetFlags =0 
)

Replace this operand with a frame index.

Definition at line233 of fileMachineOperand.cpp.

Referencesassert(),Idx,isReg(),isTied(),MO_FrameIndex,setIndex(), andsetTargetFlags().

Referenced byswapRegAndNonRegOperand().

◆ ChangeToGA()

void MachineOperand::ChangeToGA(constGlobalValueGV,
int64_t Offset,
unsigned TargetFlags =0 
)

ChangeToGA - Replace this operand with a new global address operand.

Definition at line196 of fileMachineOperand.cpp.

Referencesassert(),isReg(),isTied(),MO_GlobalAddress,llvm::Offset,setOffset(), andsetTargetFlags().

Referenced byswapRegAndNonRegOperand().

◆ ChangeToImmediate()

void MachineOperand::ChangeToImmediate(int64_t ImmVal,
unsigned TargetFlags =0 
)

ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.

If an operand is known to be an immediate already, the setImm method should be used.

Definition at line162 of fileMachineOperand.cpp.

Referencesassert(),isReg(),isTied(),MO_Immediate, andsetTargetFlags().

Referenced byllvm::AArch64RegisterInfo::eliminateFrameIndex(),llvm::M68kRegisterInfo::eliminateFrameIndex(),llvm::X86RegisterInfo::eliminateFrameIndex(),llvm::SIRegisterInfo::eliminateFrameIndex(),llvm::SIInstrInfo::foldImmediate(),llvm::SIInstrInfo::legalizeOperandsVOP2(),llvm::rewriteARMFrameIndex(),llvm::ThumbRegisterInfo::rewriteFrameIndex(),llvm::rewriteT2FrameIndex(),swapRegAndNonRegOperand(), andllvm::updateDbgValueForSpill().

◆ ChangeToMCSymbol()

void MachineOperand::ChangeToMCSymbol(MCSymbolSym,
unsigned TargetFlags =0 
)

ChangeToMCSymbol - Replace this operand with a new MC symbol operand.

Definition at line222 of fileMachineOperand.cpp.

Referencesassert(),isReg(),isTied(),MO_MCSymbol,setTargetFlags(), andSym.

◆ ChangeToRegister()

void MachineOperand::ChangeToRegister(Register Reg,
bool isDef,
bool isImp =false,
bool isKill =false,
bool isDead =false,
bool isUndef =false,
bool isDebug =false 
)

ChangeToRegister - Replace this operand with a new register operand of the specified value.

If an operand is known to be an register already, the setReg method should be used.

Definition at line273 of fileMachineOperand.cpp.

Referencesllvm::MachineRegisterInfo::addRegOperandToUseList(),assert(),getMFIfAvailable(),getParent(),isDead(),isDebug(),isDef(),isKill(),isReg(),isUndef(),MI,MO_Register, andllvm::MachineRegisterInfo::removeRegOperandFromUseList().

Referenced byllvm::SIRegisterInfo::eliminateFrameIndex(),llvm::SIInstrInfo::legalizeOperands(),llvm::SIInstrInfo::legalizeOperandsVOP2(),llvm::SIInstrInfo::legalizeOperandsVOP3(),llvm::SIInstrInfo::legalizeOpWithMove(),llvm::SIRegisterInfo::resolveFrameIndex(),swapRegAndNonRegOperand(), andllvm::X86InstrInfo::unfoldMemoryOperand().

◆ ChangeToTargetIndex()

void MachineOperand::ChangeToTargetIndex(unsigned Idx,
int64_t Offset,
unsigned TargetFlags =0 
)

Replace this operand with a target index.

Definition at line244 of fileMachineOperand.cpp.

Referencesassert(),Idx,isReg(),isTied(),MO_TargetIndex,llvm::Offset,setIndex(),setOffset(), andsetTargetFlags().

◆ clearParent()

void llvm::MachineOperand::clearParent()
inline

clearParent - Reset the parent pointer.

TheMachineOperand copy constructor also copies ParentMI, expecting the original to be deleted. If aMachineOperand is ever stored outside aMachineInstr, the parent pointer must be cleared.

Never callclearParent() on an operand in aMachineInstr.

Definition at line254 of fileMachineOperand.h.

◆ clobbersPhysReg()[1/2]

staticbool llvm::MachineOperand::clobbersPhysReg(constuint32_tRegMask,
MCRegister PhysReg 
)
inlinestatic

clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.

It is sometimes necessary to detach the register mask pointer from its machine operand. This static method can be used for such detached bit mask pointers.

Definition at line646 of fileMachineOperand.h.

Referencesassert(),llvm::MCRegister::id(),llvm::MCRegister::isPhysical(), andllvm::MCRegister::isValid().

Referenced byllvm::LiveRegUnits::addRegsInMask(),canClobberPhysRegDefs(),canClobberReachingPhysRegUse(),CheckForLiveRegDefMasked(),clobbersAllYmmAndZmmRegs(),clobbersPhysReg(),llvm::MachineInstr::findRegisterDefOperandIdx(),llvm::M68kRegisterInfo::getReservedRegs(),handleRegMaskClobber(),llvm::ARMBaseInstrInfo::optimizeCompareInstr(),llvm::LanaiInstrInfo::optimizeCompareInstr(),llvm::CallLowering::parametersInCSRMatch(),llvm::TargetLowering::parametersInCSRMatch(),llvm::PhysicalRegisterUsageInfo::print(),llvm::LivePhysRegs::removeRegsInMask(),llvm::LiveRegUnits::removeRegsNotPreserved(),llvm::LivePhysRegs::stepForward(), andLiveDebugValues::MLocTracker::writeRegMask().

◆ clobbersPhysReg()[2/2]

bool llvm::MachineOperand::clobbersPhysReg(MCRegister PhysReg) const
inline

clobbersPhysReg - Returns true if this RegMask operand clobbers PhysReg.

Definition at line654 of fileMachineOperand.h.

ReferencesclobbersPhysReg(), andgetRegMask().

◆ CreateBA()

staticMachineOperand llvm::MachineOperand::CreateBA(constBlockAddressBA,
int64_t Offset,
unsigned TargetFlags =0 
)
inlinestatic

Definition at line913 of fileMachineOperand.h.

ReferencesMO_BlockAddress, andllvm::Offset.

Referenced byllvm::MachineInstrBuilder::addBlockAddress().

◆ CreateCFIIndex()

staticMachineOperand llvm::MachineOperand::CreateCFIIndex(unsigned CFIIndex)
inlinestatic

Definition at line967 of fileMachineOperand.h.

ReferencesMO_CFIIndex.

Referenced byllvm::MachineInstrBuilder::addCFIIndex().

◆ CreateCImm()

staticMachineOperand llvm::MachineOperand::CreateCImm(constConstantIntCI)
inlinestatic

Definition at line826 of fileMachineOperand.h.

ReferencesMO_CImmediate.

Referenced byllvm::MachineInstrBuilder::addCImm(),llvm::CSEMIRBuilder::buildConstant(),GetMOForConstDbgOp(), andprocessSwitchesConstants().

◆ CreateCPI()

staticMachineOperand llvm::MachineOperand::CreateCPI(unsigned Idx,
int Offset,
unsigned TargetFlags =0 
)
inlinestatic

Definition at line875 of fileMachineOperand.h.

ReferencesIdx,MO_ConstantPoolIndex, andllvm::Offset.

Referenced byllvm::MachineInstrBuilder::addConstantPoolIndex(),llvm::X86InstrInfo::foldMemoryOperandImpl(), andllvm::XtensaInstrInfo::insertIndirectBranch().

◆ CreateDbgInstrRef()

staticMachineOperand llvm::MachineOperand::CreateDbgInstrRef(unsigned InstrIdx,
unsigned OpIdx 
)
inlinestatic

Definition at line960 of fileMachineOperand.h.

ReferencesMO_DbgInstrRef.

Referenced byllvm::InstrEmitter::EmitDbgInstrRef().

◆ CreateES()

staticMachineOperand llvm::MachineOperand::CreateES(constcharSymName,
unsigned TargetFlags =0 
)
inlinestatic

Definition at line905 of fileMachineOperand.h.

ReferencesMO_ExternalSymbol.

Referenced byllvm::MachineInstrBuilder::addExternalSymbol(),createAtomicLibcall(),llvm::createLibcall(),llvm::createMemLibcall(), andgetMovOperand().

◆ CreateFI()

staticMachineOperand llvm::MachineOperand::CreateFI(int Idx)
inlinestatic

Definition at line870 of fileMachineOperand.h.

ReferencesIdx, andMO_FrameIndex.

Referenced byllvm::MachineInstrBuilder::addFrameIndex(),llvm::X86InstrInfo::foldMemoryOperandImpl(),llvm::X86AddressMode::getFullAddress(), andllvm::FastISel::lowerDbgValue().

◆ CreateFPImm()

staticMachineOperand llvm::MachineOperand::CreateFPImm(constConstantFPCFP)
inlinestatic

Definition at line832 of fileMachineOperand.h.

ReferencesMO_FPImmediate.

Referenced byllvm::MachineInstrBuilder::addFPImm(),llvm::CSEMIRBuilder::buildFConstant(),convertImplicitDefToConstZero(),GetMOForConstDbgOp(), andllvm::SPIRVInlineAsmLowering::lowerAsmOperandForConstraint().

◆ CreateGA()

staticMachineOperand llvm::MachineOperand::CreateGA(constGlobalValueGV,
int64_t Offset,
unsigned TargetFlags =0 
)
inlinestatic

Definition at line897 of fileMachineOperand.h.

ReferencesMO_GlobalAddress, andllvm::Offset.

Referenced byllvm::MachineInstrBuilder::addGlobalAddress(),llvm::X86AddressMode::getFullAddress(),getMovOperand(),llvm::CallLowering::lowerCall(),llvm::AMDGPUCallLowering::lowerChainCall(), andllvm::FastISel::selectPatchpoint().

◆ CreateImm()

staticMachineOperand llvm::MachineOperand::CreateImm(int64_t Val)
inlinestatic

Definition at line820 of fileMachineOperand.h.

ReferencesMO_Immediate.

Referenced byllvm::MachineInstrBuilder::addImm(),llvm::ARMTargetLowering::AdjustInstrPostInstrSelection(),llvm::HexagonInstrInfo::analyzeBranch(),llvm::MSP430InstrInfo::analyzeBranch(),llvm::PPCInstrInfo::analyzeBranch(),llvm::SystemZInstrInfo::analyzeBranch(),llvm::XCoreInstrInfo::analyzeBranch(),llvm::XtensaInstrInfo::analyzeBranch(),llvm::ARMBaseInstrInfo::analyzeBranch(),llvm::AVRInstrInfo::analyzeBranch(),llvm::WebAssemblyInstrInfo::analyzeBranch(),llvm::LanaiInstrInfo::analyzeBranch(),llvm::M68kInstrInfo::AnalyzeBranchImpl(),llvm::SIInstrInfo::analyzeBranchImpl(),llvm::AArch64InstrInfo::analyzeBranchPredicate(),llvm::X86InstrInfo::analyzeBranchPredicate(),llvm::SIInstrInfo::buildExtractSubRegOrImm(),llvm::X86InstrInfo::commuteInstructionImpl(),convertImplicitDefToConstZero(),llvm::AArch64InstrInfo::describeLoadedValue(),llvm::X86InstrInfo::describeLoadedValue(),llvm::SITargetLowering::EmitInstrWithCustomInserter(),llvm::PPCTargetLowering::EmitInstrWithCustomInserter(),llvm::AArch64FrameLowering::emitPrologue(),emitVFROUND_NOEXCEPT_MASK(),foldConstantsIntoIntrinsics(),llvm::X86InstrInfo::foldMemoryOperandImpl(),llvm::X86AddressMode::getFullAddress(),GetMOForConstDbgOp(),getMovOperand(),llvm::RISCVLegalizerInfo::legalizeCustom(),llvm::AMDGPULegalizerInfo::legalizeImageIntrinsic(),llvm::InlineAsmLowering::lowerAsmOperandForConstraint(),parseCondBranch(),llvm::predOps(),llvm::XtensaInstrInfo::removeBranch(),llvm::WebAssemblyInstrInfo::reverseBranchCondition(),llvm::FastISel::selectPatchpoint(),llvm::FastISel::selectStackmap(), andllvm::HexagonInstrInfo::setBundleNoShuf().

◆ CreateIntrinsicID()

staticMachineOperand llvm::MachineOperand::CreateIntrinsicID(Intrinsic::ID ID)
inlinestatic

Definition at line973 of fileMachineOperand.h.

ReferencesMO_IntrinsicID.

Referenced byllvm::MachineInstrBuilder::addIntrinsicID().

◆ CreateJTI()

staticMachineOperand llvm::MachineOperand::CreateJTI(unsigned Idx,
unsigned TargetFlags =0 
)
inlinestatic

Definition at line891 of fileMachineOperand.h.

ReferencesIdx, andMO_JumpTableIndex.

Referenced byllvm::MachineInstrBuilder::addJumpTableIndex(), andgetMovOperand().

◆ CreateMBB()

staticMachineOperand llvm::MachineOperand::CreateMBB(MachineBasicBlockMBB,
unsigned TargetFlags =0 
)
inlinestatic

Definition at line863 of fileMachineOperand.h.

ReferencesMBB, andMO_MachineBasicBlock.

Referenced byllvm::MachineInstrBuilder::addMBB(),llvm::PeelingModuloScheduleExpander::peelPrologAndEpilogs(),processBlockAddr(), andsplitEdge().

◆ CreateMCSymbol()

staticMachineOperand llvm::MachineOperand::CreateMCSymbol(MCSymbolSym,
unsigned TargetFlags =0 
)
inlinestatic

Definition at line951 of fileMachineOperand.h.

ReferencesMO_MCSymbol, andSym.

Referenced byllvm::MachineInstrBuilder::addSym(), andllvm::MipsTargetLowering::AdjustInstrPostInstrSelection().

◆ CreateMetadata()

staticMachineOperand llvm::MachineOperand::CreateMetadata(constMDNodeMeta)
inlinestatic

Definition at line945 of fileMachineOperand.h.

ReferencesMO_Metadata.

Referenced byllvm::MachineInstrBuilder::addMetadata().

◆ CreatePredicate()

staticMachineOperand llvm::MachineOperand::CreatePredicate(unsigned Pred)
inlinestatic

Definition at line979 of fileMachineOperand.h.

ReferencesMO_Predicate.

Referenced byllvm::MachineInstrBuilder::addPredicate().

◆ CreateReg()

staticMachineOperand llvm::MachineOperand::CreateReg(Register Reg,
bool isDef,
bool isImp =false,
bool isKill =false,
bool isDead =false,
bool isUndef =false,
bool isEarlyClobber =false,
unsigned SubReg =0,
bool isDebug =false,
bool isInternalRead =false,
bool isRenamable =false 
)
inlinestatic

Definition at line838 of fileMachineOperand.h.

Referencesassert(),isDead(),isDebug(),isDef(),isEarlyClobber(),isInternalRead(),isKill(),isRenamable(),isUndef(),MO_Register,Reg, andSubReg.

Referenced byaddConstantsToTrack(),llvm::MachineInstr::addImplicitDefUseOperands(),llvm::SITargetLowering::AddMemOpInit(),llvm::GISelInstProfileBuilder::addNodeIDRegType(),llvm::MachineInstrBuilder::addReg(),llvm::MachineInstr::addRegisterDead(),llvm::MachineInstr::addRegisterDefined(),llvm::MachineInstr::addRegisterKilled(),llvm::ARMTargetLowering::AdjustInstrPostInstrSelection(),llvm::RISCVTargetLowering::AdjustInstrPostInstrSelection(),llvm::R600InstrInfo::analyzeBranch(),llvm::PPCInstrInfo::analyzeBranch(),llvm::SIInstrInfo::buildExtractSubRegOrImm(),llvm::condCodeOp(),llvm::X86InstrInfo::convertToThreeAddress(),createCallWithOps(),llvm::TargetInstrInfo::describeLoadedValue(),llvm::MipsInstrInfo::describeLoadedValue(),describeMOVrrLoadedValue(),describeORRLoadedValue(),llvm::InstrEmitter::EmitDbgInstrRef(),llvm::RISCVTargetLowering::EmitInstrWithCustomInserter(),llvm::AArch64TargetLowering::EmitInstrWithCustomInserter(),llvm::PPCTargetLowering::EmitInstrWithCustomInserter(),LiveDebugValues::MLocTracker::emitLoc(),llvm::HexagonFrameLowering::emitPrologue(),emitVFROUND_NOEXCEPT_MASK(),llvm::SIInstrInfo::enforceOperandRCAlignment(),expandSGPRCopy(),llvm::X86InstrInfo::foldMemoryOperandImpl(),llvm::X86AddressMode::getFullAddress(),GetMOForConstDbgOp(),imposeStackOrdering(),INITIALIZE_PASS(),llvm::AArch64CallLowering::lowerCall(),llvm::CallLowering::lowerCall(),llvm::AMDGPUCallLowering::lowerChainCall(),llvm::FastISel::lowerDbgDeclare(),llvm::FastISel::lowerDbgValue(),llvm::PPCInstrInfo::optimizeCompareInstr(),llvm::RISCVInstrInfo::optimizeCondBranch(),parseCondBranch(),llvm::PeelingModuloScheduleExpander::peelPrologAndEpilogs(),llvm::predOps(),TransferTracker::recoverAsEntryValue(),llvm::rewriteT2FrameIndex(),llvm::FastISel::selectPatchpoint(),llvm::FastISel::selectStackmap(),llvm::FastISel::selectXRayCustomEvent(),llvm::FastISel::selectXRayTypedEvent(),llvm::t1CondCodeOp(), andllvm::tryFoldSPUpdateIntoPushPop().

◆ CreateRegLiveOut()

staticMachineOperand llvm::MachineOperand::CreateRegLiveOut(constuint32_tMask)
inlinestatic

Definition at line939 of fileMachineOperand.h.

Referencesassert(), andMO_RegisterLiveOut.

◆ CreateRegMask()

staticMachineOperand llvm::MachineOperand::CreateRegMask(constuint32_tMask)
inlinestatic

CreateRegMask - Creates a register mask operand referencing Mask.

The operand does not take ownership of the memory referenced by Mask, it must remain valid for the lifetime of the operand.

A RegMask operand represents a set of non-clobbered physical registers on an instruction that clobbers many registers, typically a call. The bit mask has a bit set for each physreg that is preserved by this instruction, as described in the documentation forTargetRegisterInfo::getCallPreservedMask().

Any physreg with a 0 bit in the mask is clobbered by the instruction.

Definition at line933 of fileMachineOperand.h.

Referencesassert(), andMO_RegisterMask.

Referenced byllvm::MachineInstrBuilder::addRegMask(), andllvm::FastISel::selectPatchpoint().

◆ CreateShuffleMask()

staticMachineOperand llvm::MachineOperand::CreateShuffleMask(ArrayRef< int > Mask)
inlinestatic

Definition at line985 of fileMachineOperand.h.

ReferencesMO_ShuffleMask.

Referenced byllvm::MachineInstrBuilder::addShuffleMask().

◆ CreateTargetIndex()

staticMachineOperand llvm::MachineOperand::CreateTargetIndex(unsigned Idx,
int64_t Offset,
unsigned TargetFlags =0 
)
inlinestatic

Definition at line883 of fileMachineOperand.h.

ReferencesIdx,MO_TargetIndex, andllvm::Offset.

Referenced byllvm::MachineInstrBuilder::addTargetIndex().

◆ dump()

LLVM_DUMP_METHOD void MachineOperand::dump() const

Definition at line1037 of fileMachineOperand.cpp.

Referencesllvm::dbgs().

Referenced byrescheduleCanonically().

◆ getBlockAddress()

constBlockAddress * llvm::MachineOperand::getBlockAddress() const
inline

Definition at line587 of fileMachineOperand.h.

Referencesassert(), andisBlockAddress().

Referenced byllvm::MachineInstrBuilder::addDisp(),llvm::LanaiMCInstLower::GetBlockAddressSymbol(),llvm::MSP430MCInstLower::GetBlockAddressSymbol(),llvm::SystemZMCInstLower::getExpr(),getMCSymbolForTOCPseudoMO(),llvm::hash_value(),INITIALIZE_PASS(),isIdenticalTo(),isSimilarDispOp(),llvm::lowerLoongArchMachineOperandToMCOperand(),llvm::M68kMCInstLower::LowerOperand(),LowerOperand(),llvm::ARMAsmPrinter::lowerOperand(),llvm::AArch64MCInstLower::lowerOperand(),llvm::CSKYMCInstLower::lowerOperand(),llvm::LowerPPCMachineOperandToMCOperand(),LowerSymbolOperand(),llvm::XtensaAsmPrinter::LowerSymbolOperand(),print(),llvm::M68kAsmPrinter::PrintAsmMemoryOperand(),llvm::CSKYAsmPrinter::PrintAsmOperand(),llvm::MipsAsmPrinter::printOperand(), andprocessBlockAddr().

◆ getCFIIndex()

unsigned llvm::MachineOperand::getCFIIndex() const
inline

Definition at line607 of fileMachineOperand.h.

Referencesassert(), andisCFIIndex().

Referenced byllvm::hash_value(),isIdenticalTo(),print(), andllvm::stableHashValue().

◆ getCImm()

constConstantInt * llvm::MachineOperand::getCImm() const
inline

Definition at line561 of fileMachineOperand.h.

Referencesassert(), andisCImm().

Referenced byllvm::GISelInstProfileBuilder::addNodeIDMachineOperand(),buildSpirvTypeName(),llvm::GIMatchTableExecutor::executeMatchTable(),foldConstantsIntoIntrinsics(),foldImm(),generateAssignInstrs(),llvm::generateGroupUniformInst(),llvm::generateSpecConstantInst(),getArrayComponentCount(),llvm::getConstFromIntrinsic(),getImmedFromMO(),llvm::GVScale::getSrc(),llvm::GStepVector::getStep(),llvm::hash_value(),isIdenticalTo(),llvm::LegalizerHelper::lowerConstant(),llvm::CombinerHelper::matchCombineUnmergeConstant(),llvm::matchUnaryPredicate(),print(),processSwitchesConstants(),llvm::stableHashValue(), andllvm::LegalizerHelper::widenScalar().

◆ getFPImm()

constConstantFP * llvm::MachineOperand::getFPImm() const
inline

Definition at line566 of fileMachineOperand.h.

Referencesassert(), andisFPImm().

Referenced byllvm::GISelInstProfileBuilder::addNodeIDMachineOperand(),generateAssignInstrs(),llvm::generateSpecConstantInst(),llvm::hash_value(),isIdenticalTo(),isSameScalarConst(),llvm::WebAssemblyMCInstLower::lower(),llvm::SPIRVMCInstLower::lower(),llvm::LegalizerHelper::lowerFConstant(),llvm::ARMAsmPrinter::lowerOperand(),llvm::CombinerHelper::matchCombineUnmergeConstant(),print(),llvm::stableHashValue(), andllvm::LegalizerHelper::widenScalar().

◆ getGlobal()

constGlobalValue * llvm::MachineOperand::getGlobal() const
inline

Definition at line582 of fileMachineOperand.h.

Referencesassert(), andisGlobal().

Referenced byllvm::MachineInstrBuilder::addDisp(),llvm::X86FrameLowering::adjustForHiPEPrologue(),llvm::BTFDebug::beginInstruction(),llvm::buildEnqueueKernel(),llvm::R600TargetLowering::EmitInstrWithCustomInserter(),llvm::getAddressFromInstr(),getCodeModel(),llvm::SystemZMCInstLower::getExpr(),llvm::AArch64MCInstLower::GetGlobalAddressSymbol(),llvm::BPFMCInstLower::GetGlobalAddressSymbol(),llvm::LanaiMCInstLower::GetGlobalAddressSymbol(),llvm::MSP430MCInstLower::GetGlobalAddressSymbol(),getMCSymbolForTOCPseudoMO(),getMovOperand(),llvm::M68kMCInstLower::GetSymbolFromOperand(),GetSymbolFromOperand(),GetSymbolRef(),getTOCEntryTypeForMO(),llvm::hash_value(),INITIALIZE_PASS(),llvm::BTFDebug::InstLower(),IsCallReturnTwice(),isIdenticalTo(),isSameScalarConst(),isSignExtendedW(),llvm::PPCInstrInfo::isSignOrZeroExtended(),isSimilarDispOp(),llvm::SPIRVMCInstLower::lower(),llvm::lowerLoongArchMachineOperandToMCOperand(),LowerOperand(),llvm::ARMAsmPrinter::lowerOperand(),AMDGPUMCInstLower::lowerOperand(),llvm::CSKYMCInstLower::lowerOperand(),LowerSymbolOperand(),llvm::XtensaAsmPrinter::LowerSymbolOperand(),llvm::AVRMCInstLower::lowerSymbolOperand(),llvm::AArch64MCInstLower::lowerSymbolOperandELF(),llvm::WebAssembly::mayThrow(),print(),llvm::AVRAsmPrinter::printOperand(),llvm::ARMAsmPrinter::PrintSymbolOperand(),llvm::AsmPrinter::PrintSymbolOperand(),llvm::ARMBaseInstrInfo::produceSameValue(),queryCallee(),llvm::DetectRoundChange::runOnMachineFunction(),smallData(),llvm::stableHashValue(),swapRegAndNonRegOperand(), andvalidateFunCall().

◆ getImm()

int64_t llvm::MachineOperand::getImm() const
inline

Definition at line556 of fileMachineOperand.h.

Referencesassert(), andisImm().

Referenced byaddConstantComments(),llvm::MachineInstrBuilder::addDisp(),llvm::R600InstrInfo::addFlag(),llvm::SITargetLowering::AddMemOpInit(),llvm::GISelInstProfileBuilder::addNodeIDMachineOperand(),llvm::HexagonInstrInfo::areMemAccessesTriviallyDisjoint(),llvm::buildAtomicCompareExchangeInst(),llvm::buildBoolRegister(),llvm::buildEnqueueKernel(),llvm::R600InstrInfo::buildSlotOfVectorInstruction(),canCombineShiftIntoShXAdd(),canCompareBeNewValueJump(),llvm::AArch64InstrInfo::canFoldIntoAddrMode(),llvm::RISCVInstrInfo::canFoldIntoAddrMode(),canFoldIntoCSel(),canInstrSubstituteCmpInstr(),llvm::R600InstrInfo::clearFlag(),collectInlineAsmInstrOperands(),llvm::PPCInstrInfo::combineRLWINM(),compareMachineOp(),llvm::SIInstrInfo::convertToThreeAddress(),createNewPtrType(),createPHIsForSelects(),llvm::ARCFrameLowering::eliminateCallFramePseudoInstr(),llvm::XCoreFrameLowering::eliminateCallFramePseudoInstr(),llvm::M68kRegisterInfo::eliminateFrameIndex(),llvm::SIRegisterInfo::eliminateFrameIndex(),llvm::WebAssemblyRegisterInfo::eliminateFrameIndex(),llvm::AArch64FrameLowering::emitEpilogue(),llvm::PPCFrameLowering::emitEpilogue(),EmitLoweredCascadedSelect(),llvm::GIMatchTableExecutor::executeMatchTable(),llvm::M68kInstrInfo::ExpandMOVEM(),llvm::M68kInstrInfo::ExpandMOVI(),ExpandMOVImmSExti8(),llvm::HexagonInstrInfo::expandPostRAPseudo(),expandSHXDROT(),llvm::RISCVInstrInfo::finalizeInsInstrs(),llvm::SPIRVTargetLowering::finalizeLowering(),llvm::MachineInstr::findInlineAsmFlagIdx(),findRedundantFlagInstr(),llvm::MachineInstr::findTiedOperandIdx(),fixupCalleeSaveRestoreStackOffset(),fixupSEHOpcode(),foldImm(),llvm::SIInstrInfo::foldImmediate(),foldInlineAsmMemOperand(),llvm::AArch64InstrInfo::genAlternativeCodeSequence(),llvm::generateImageMiscQueryInst(),llvm::generateImageSizeQueryInst(),genIndexedMultiply(),genShXAddAddShift(),llvm::getAddressFromInstr(),llvm::X86InstrInfo::getAddrModeFromMemoryOp(),getArgumentStackToRestore(),getAS(),llvm::HexagonInstrInfo::getBaseAndOffset(),llvm::HexagonInstrInfo::getBundleNoShuf(),llvm::PatchPointOpers::getCallingConv(),llvm::ARMAsmPrinter::getCodeViewJumpTableInfo(),llvm::HexagonInstrInfo::getCompoundOpcode(),llvm::X86InstrInfo::getConstValDefinedInReg(),llvm::TargetInstrInfo::getExtractSubregInputs(),llvm::SIRegisterInfo::getFrameIndexInstrOffset(),llvm::ARMBaseRegisterInfo::getFrameIndexInstrOffset(),llvm::StatepointOpers::getGCPointerMap(),getHWReg(),llvm::PatchPointOpers::getID(),getImmedFromMO(),llvm::HexagonInstrInfo::getIncrementValue(),llvm::GExtractSubvector::getIndexImm(),llvm::GInsertSubvector::getIndexImm(),llvm::MachineInstr::getInlineAsmDialect(),llvm::TargetInstrInfo::getInsertSubregInputs(),llvm::ARMBaseInstrInfo::getInsertSubregLikeInputs(),getLoadStoreOffsetSizeInBits(),llvm::SIInstrInfo::getMemOperandsWithOffsetWidth(),llvm::X86InstrInfo::getMemOperandsWithOffsetWidth(),llvm::LanaiInstrInfo::getMemOperandWithOffsetWidth(),llvm::PPCInstrInfo::getMemOperandWithOffsetWidth(),llvm::RISCVInstrInfo::getMemOperandWithOffsetWidth(),llvm::AArch64InstrInfo::getMemOperandWithOffsetWidth(),getMovOperand(),llvm::PatchPointOpers::getNumPatchBytes(),llvm::getNumSizeComponents(),llvm::SPIRVGlobalRegistry::getOrCreateConsIntVector(),llvm::SPIRVGlobalRegistry::getOrCreateConstVector(),getRegImmPairPreventingCompression(),llvm::TargetInstrInfo::getRegSequenceInputs(),llvm::SPIRVGlobalRegistry::getRegType(),getSingleUnwindDest(),llvm::R600InstrInfo::getSrcs(),hasAllNBitUsers(),llvm::RISCV::hasEqualFRM(),llvm::hash_value(),llvm::SIInstrInfo::hasModifiersSet(),llvm::MachineInstr::hasUnmodeledSideEffects(),INITIALIZE_PASS(),llvm::SystemZELFFrameLowering::inlineStackProbe(),llvm::isAArch64FrameOffsetLegal(),llvm::PPCInstrInfo::isADDIInstrEligibleForFolding(),llvm::MipsInstrInfo::isAddImmediate(),isAddressLdStPair(),isAddSub2RegAndConstOnePair(),llvm::HexagonInstrInfo::isConstExtended(),llvm::MachineInstr::isConvergent(),isConvertibleLEA(),isIdenticalTo(),isIdentityValue(),llvm::PPCInstrInfo::isImmInstrEligibleForFolding(),llvm::SIInstrInfo::isInlineConstant(),isLdOffsetInRangeOfSt(),isLiteralsPair(),llvm::HexagonInstrInfo::isLoadFromStackSlot(),isLoadStoreThatCanHandleDisplacement(),isMatchingStartStopPair(),llvm::SIInstrInfo::isOperandLegal(),llvm::GIndexedLoad::isPre(),llvm::GIndexedStore::isPre(),isRedundantFlagInstr(),isRelevantAddressingMode(),isSafeToFoldImmIntoCopy(),isSameScalarConst(),llvm::SPIRVGlobalRegistry::isScalarOrVectorSigned(),llvm::isScale(),llvm::MachineInstr::isStackAligningInlineAsm(),llvm::HexagonInstrInfo::isStoreToStackSlot(),llvm::RISCVLegalizerInfo::legalizeCustom(),llvm::SIInstrInfo::legalizeOperandsVOP2(),llvm::WebAssemblyMCInstLower::lower(),llvm::SPIRVMCInstLower::lower(),llvm::lowerLoongArchMachineOperandToMCOperand(),llvm::M68kMCInstLower::LowerOperand(),LowerOperand(),llvm::SystemZMCInstLower::lowerOperand(),llvm::MipsMCInstLower::LowerOperand(),llvm::ARMAsmPrinter::lowerOperand(),llvm::AArch64MCInstLower::lowerOperand(),AMDGPUMCInstLower::lowerOperand(),llvm::CSKYMCInstLower::lowerOperand(),llvm::ARCMCInstLower::LowerOperand(),llvm::XCoreMCInstLower::LowerOperand(),llvm::XtensaAsmPrinter::lowerOperand(),llvm::LowerPPCMachineOperandToMCOperand(),lowerRISCVVMachineInstrToMCInst(),llvm::LoongArchAsmPrinter::LowerSTATEPOINT(),llvm::SPIRV::make_descr_sampled_image(),llvm::MachineInstr::mayFoldInlineAsmRegOp(),llvm::MachineInstr::mayLoad(),mayOverlapWrite(),llvm::MachineInstr::mayStore(),llvm::SIInstrInfo::moveFlatAddrToVGPR(),llvm::SIInstrInfo::moveToVALUImpl(),llvm::SIInstrInfo::optimizeCompareInstr(),llvm::PPCInstrInfo::optimizeCompareInstr(),llvm::AArch64InstrInfo::optimizeCondBranch(),parseCondBranch(),llvm::SystemZInstrInfo::prepareCompareSwapOperands(),llvm::MachineInstr::print(),print(),llvm::LoongArchAsmPrinter::PrintAsmMemoryOperand(),llvm::M68kAsmPrinter::PrintAsmMemoryOperand(),llvm::MipsAsmPrinter::PrintAsmMemoryOperand(),llvm::AMDGPUAsmPrinter::PrintAsmOperand(),llvm::MipsAsmPrinter::PrintAsmOperand(),llvm::X86AsmPrinter::PrintAsmOperand(),llvm::AsmPrinter::PrintAsmOperand(),llvm::CSKYAsmPrinter::PrintAsmOperand(),llvm::LoongArchAsmPrinter::PrintAsmOperand(),llvm::WebAssemblyAsmPrinter::PrintAsmOperand(),llvm::ARMAsmPrinter::PrintAsmOperand(),llvm::MipsAsmPrinter::printFCCOperand(),llvm::ARMAsmPrinter::printOperand(),llvm::MipsAsmPrinter::printOperand(),llvm::AVRAsmPrinter::printOperand(),llvm::HexagonAsmPrinter::printOperand(),llvm::SIInstrInfo::reMaterialize(),llvm::SIRegisterInfo::resolveFrameIndex(),llvm::R600InstrInfo::reverseBranchCondition(),llvm::ARMBlockPlacement::revertWhileToDoLoop(),llvm::rewriteT2FrameIndex(),llvm::HexagonInstrInfo::setBundleNoShuf(),llvm::AArch64InstrInfo::shouldClusterMemOps(),llvm::stableHashValue(),swapImmOperands(),swapRegAndNonRegOperand(),llvm::SIInstrInfo::swapSourceModifiers(),llvm::X86InstrInfo::unfoldMemoryOperand(),updateOperandIfDifferent(),updateOperands(),validateLifetimeStart(),validatePtrUnwrapStructField(),verifyInsExtInstruction(),llvm::SIInstrInfo::verifyInstruction(), andllvm::RISCVInstrInfo::verifyInstruction().

◆ getIndex()

int llvm::MachineOperand::getIndex() const
inline

Definition at line576 of fileMachineOperand.h.

Referencesassert(),isCPI(),isFI(),isJTI(), andisTargetIndex().

Referenced byllvm::MachineInstrBuilder::addDisp(),llvm::ARCRegisterInfo::eliminateFrameIndex(),llvm::XCoreRegisterInfo::eliminateFrameIndex(),llvm::ARMAsmPrinter::emitJumpTableAddrs(),llvm::ARMAsmPrinter::emitJumpTableInsts(),llvm::ARMAsmPrinter::emitJumpTableTBInst(),llvm::TargetLoweringBase::emitPatchPoint(),llvm::getAddressFromInstr(),llvm::X86::getConstantFromPool(),llvm::LanaiMCInstLower::GetConstantPoolIndexSymbol(),llvm::MSP430MCInstLower::GetConstantPoolIndexSymbol(),llvm::XtensaAsmPrinter::GetConstantPoolIndexSymbol(),llvm::SystemZMCInstLower::getExpr(),getJumpTableIndexFromAddr(),llvm::LanaiMCInstLower::GetJumpTableSymbol(),llvm::MSP430MCInstLower::GetJumpTableSymbol(),llvm::XtensaAsmPrinter::GetJumpTableSymbol(),getMCSymbolForTOCPseudoMO(),getMovOperand(),getStartOrEndSlot(),getTargetIndexName(),llvm::hash_value(),hasSameBaseOpValue(),INITIALIZE_PASS(),isIdenticalTo(),llvm::HexagonInstrInfo::isLoadFromStackSlot(),isSimilarDispOp(),llvm::HexagonInstrInfo::isStoreToStackSlot(),llvm::lowerLoongArchMachineOperandToMCOperand(),llvm::M68kMCInstLower::LowerOperand(),LowerOperand(),llvm::ARMAsmPrinter::lowerOperand(),llvm::AArch64MCInstLower::lowerOperand(),llvm::CSKYMCInstLower::lowerOperand(),llvm::LowerPPCMachineOperandToMCOperand(),LowerSymbolOperand(),llvm::AArch64FrameLowering::orderFrameObjects(),llvm::SystemZELFFrameLowering::orderFrameObjects(),print(),llvm::ARMAsmPrinter::printOperand(),llvm::MipsAsmPrinter::printOperand(),llvm::HexagonAsmPrinter::printOperand(),llvm::ARMBaseInstrInfo::produceSameValue(),llvm::ARMBaseInstrInfo::reMaterialize(),llvm::AArch64InstrInfo::shouldClusterMemOps(),llvm::PPCInstrInfo::shouldClusterMemOps(),smallData(),llvm::stableHashValue(), andswapRegAndNonRegOperand().

◆ getInstrRefInstrIndex()

unsigned llvm::MachineOperand::getInstrRefInstrIndex() const
inline

Definition at line597 of fileMachineOperand.h.

Referencesassert(), andisDbgInstrRef().

Referenced byllvm::hash_value(),isIdenticalTo(),print(), andllvm::stableHashValue().

◆ getInstrRefOpIndex()

unsigned llvm::MachineOperand::getInstrRefOpIndex() const
inline

Definition at line602 of fileMachineOperand.h.

Referencesassert(), andisDbgInstrRef().

Referenced byllvm::hash_value(),isIdenticalTo(),print(), andllvm::stableHashValue().

◆ getIntrinsicID()

Intrinsic::ID llvm::MachineOperand::getIntrinsicID() const
inline

Definition at line612 of fileMachineOperand.h.

Referencesassert(), andisIntrinsicID().

Referenced byllvm::GIMatchTableExecutor::executeMatchTable(),llvm::AArch64GISelUtils::extractPtrauthBlendDiscriminators(),llvm::GIntrinsic::getIntrinsicID(),llvm::hash_value(),isIdenticalTo(),print(), andllvm::stableHashValue().

◆ getMBB()

MachineBasicBlock * llvm::MachineOperand::getMBB() const
inline

Definition at line571 of fileMachineOperand.h.

Referencesassert(), andisMBB().

Referenced byaddIncomingValuesToPHIs(),llvm::R600InstrInfo::analyzeBranch(),llvm::HexagonInstrInfo::analyzeBranch(),llvm::NVPTXInstrInfo::analyzeBranch(),llvm::PPCInstrInfo::analyzeBranch(),llvm::XCoreInstrInfo::analyzeBranch(),llvm::XtensaInstrInfo::analyzeBranch(),llvm::MipsInstrInfo::analyzeBranch(),llvm::AArch64InstrInfo::analyzeBranch(),llvm::SparcInstrInfo::analyzeBranch(),llvm::VEInstrInfo::analyzeBranch(),llvm::AArch64InstrInfo::analyzeBranchPredicate(),llvm::CombinerHelper::applyOptBrCondByInvertingCond(),BBIsJumpedOver(),bbIsJumpedOver(),llvm::HexagonEvaluator::evaluate(),findLoopComponents(),llvm::HexagonInstrInfo::getDotNewPredJumpOp(),llvm::SystemZMCInstLower::getExpr(),llvm::GPhi::getIncomingBlock(),llvm::PeelingModuloScheduleExpander::getPhiCanonicalReg(),getSingleUnwindDest(),llvm::M68kMCInstLower::GetSymbolFromOperand(),getTargetMBB(),llvm::hash_value(),INITIALIZE_PASS(),insertPHI(),isIdenticalTo(),isSimilarDispOp(),llvm::SPIRVMCInstLower::lower(),llvm::lowerLoongArchMachineOperandToMCOperand(),LowerOperand(),llvm::ARMAsmPrinter::lowerOperand(),llvm::AArch64MCInstLower::lowerOperand(),AMDGPUMCInstLower::lowerOperand(),llvm::CSKYMCInstLower::lowerOperand(),llvm::LowerPPCMachineOperandToMCOperand(),LowerSymbolOperand(),llvm::XtensaAsmPrinter::LowerSymbolOperand(),llvm::CombinerHelper::matchOptBrCondByInvertingCond(),parseCondBranch(),print(),llvm::WebAssemblyAsmPrinter::PrintAsmOperand(),llvm::ARMAsmPrinter::printOperand(),llvm::MipsAsmPrinter::printOperand(),llvm::AVRAsmPrinter::printOperand(),llvm::HexagonAsmPrinter::printOperand(),llvm::MachineBasicBlock::replacePhiUsesWith(),llvm::ARMBlockPlacement::revertWhileToDoLoop(),splitBlock(),splitEdge(),splitMBB(),updatePHIs(), andverifyCFIntrinsic().

◆ getMCSymbol()

MCSymbol * llvm::MachineOperand::getMCSymbol() const
inline

Definition at line592 of fileMachineOperand.h.

Referencesassert(), andisMCSymbol().

Referenced byemitDirectiveRelocJalr(),llvm::MipsInstrInfo::genInstrWithNewOpc(),llvm::hash_value(),isIdenticalTo(),isSimilarDispOp(),llvm::WebAssemblyMCInstLower::lower(),llvm::M68kMCInstLower::LowerOperand(),llvm::AArch64MCInstLower::lowerOperand(),AMDGPUMCInstLower::lowerOperand(),llvm::CSKYMCInstLower::lowerOperand(),llvm::LowerPPCMachineOperandToMCOperand(),print(), andllvm::stableHashValue().

◆ getMetadata()

constMDNode * llvm::MachineOperand::getMetadata() const
inline

Definition at line676 of fileMachineOperand.h.

Referencesassert(), andisMetadata().

Referenced bygenerateAssignInstrs(),llvm::getMachineInstrType(),llvm::hash_value(),isIdenticalTo(),llvm::MachineInstr::print(), andprint().

◆ getOffset()

int64_t llvm::MachineOperand::getOffset() const
inline

Return the offset from the symbol in this operand.

This always returns 0 for ExternalSymbol operands.

Definition at line629 of fileMachineOperand.h.

Referencesassert(),isBlockAddress(),isCPI(),isGlobal(),isMCSymbol(),isSymbol(), andisTargetIndex().

Referenced byllvm::MachineInstrBuilder::addDisp(),llvm::R600TargetLowering::EmitInstrWithCustomInserter(),llvm::SIInstrInfo::expandPostRAPseudo(),llvm::X86::getConstantFromPool(),llvm::SystemZMCInstLower::getExpr(),getMovOperand(),GetSymbolRef(),llvm::hash_value(),INITIALIZE_PASS(),isIdenticalTo(),AMDGPUMCInstLower::lowerOperand(),LowerSymbolOperand(),llvm::XtensaAsmPrinter::LowerSymbolOperand(),llvm::BPFMCInstLower::LowerSymbolOperand(),llvm::LanaiMCInstLower::LowerSymbolOperand(),llvm::M68kMCInstLower::LowerSymbolOperand(),llvm::MSP430MCInstLower::LowerSymbolOperand(),lowerSymbolOperand(),llvm::AVRMCInstLower::lowerSymbolOperand(),llvm::AArch64MCInstLower::lowerSymbolOperandCOFF(),llvm::AArch64MCInstLower::lowerSymbolOperandELF(),llvm::AArch64MCInstLower::lowerSymbolOperandMachO(),print(),llvm::WebAssemblyAsmPrinter::PrintAsmOperand(),llvm::MipsAsmPrinter::printOperand(),llvm::ARMAsmPrinter::PrintSymbolOperand(),llvm::AsmPrinter::PrintSymbolOperand(),llvm::ARMBaseInstrInfo::produceSameValue(),llvm::stableHashValue(), andswapRegAndNonRegOperand().

◆ getOperandNo()

unsigned MachineOperand::getOperandNo() const

Returns the index of this operand in the instruction that it belongs to.

Definition at line56 of fileMachineOperand.cpp.

Referencesassert(),llvm::MachineInstr::getOperandNo(), andgetParent().

Referenced bygetIntegerExtensionOperandEEW(),getOperandInfo(),getOperandLog2EEW(),isCandidateStore(),isCrossCopy(),llvm::SIInstrInfo::isInlineConstant(),isMaskOperand(),llvm::M68kInstrInfo::isPCRelRegisterOperandLegal(),isVectorOpUsedAsScalarOp(),llvm::SIInstrInfo::legalizeOperandsFLAT(),producesFalseLanesZero(),llvm::DeadLaneDetector::transferUsedLanes(), andvectorPseudoHasAllNBitUsers().

◆ getParent()[1/2]

MachineInstr * llvm::MachineOperand::getParent()
inline

getParent - Return the instruction that this operand belongs to.

Definition at line243 of fileMachineOperand.h.

Referenced byllvm::AnalyzeVirtRegInBundle(),llvm::CombinerHelper::applyCombineExtendingLoads(),canRenameMOP(),llvm::MachineInstr::changeDebugValuesDefReg(),ChangeToRegister(),llvm::constrainOperandRegClass(),createDeadDef(),findSingleRegUse(),findUseBetween(),getFoldableImm(),getImmedFromMO(),getLoadStoreOffsetSizeInBits(),getMFIfAvailable(),getOperandInfo(),getOperandLog2EEW(),getOperandNo(),GetSymbolRef(),llvm::MachineInstr::insert(),llvm::SIInstrInfo::isIgnorableUse(),llvm::SIInstrInfo::isInlineConstant(),llvm::SIInstrInfo::isLegalRegOperand(),isNoReturnDef(),llvm::M68kInstrInfo::isPCRelRegisterOperandLegal(),isRenamable(),isTiedToNotUndef(),isVectorOpUsedAsScalarOp(),llvm::AArch64MCInstLower::lowerSymbolOperandELF(),oneUseDominatesOtherUses(),print(),printAsmMRegister(),printAsmVRegister(),llvm::SPIRVGlobalRegistry::recordFunctionDefinition(),llvm::CombinerHelper::replaceRegOpWith(),scavengeVReg(),llvm::AArch64InstrInfo::shouldClusterMemOps(),llvm::PPCInstrInfo::shouldClusterMemOps(),llvm::stableHashValue(),llvm::RegBankSelect::tryAvoidingSplit(),llvm::FastISel::tryToFoldLoad(),vectorPseudoHasAllNBitUsers(), andllvm::MachineRegisterInfo::verifyUseList().

◆ getParent()[2/2]

constMachineInstr * llvm::MachineOperand::getParent() const
inline

Definition at line244 of fileMachineOperand.h.

◆ getPredicate()

unsigned llvm::MachineOperand::getPredicate() const
inline

Definition at line617 of fileMachineOperand.h.

Referencesassert(), andisPredicate().

Referenced byllvm::GISelInstProfileBuilder::addNodeIDMachineOperand(),llvm::CombinerHelper::applyNotCmp(),llvm::GIMatchTableExecutor::executeMatchTable(),llvm::GAnyCmp::getCond(),llvm::hash_value(),isIdenticalTo(),llvm::MIPatternMatch::CompareOp_match< Pred_P, LHS_P, RHS_P, Opcode, Commutable >::match(),print(), andllvm::stableHashValue().

◆ getReg()

Register llvm::MachineOperand::getReg() const
inline

getReg - Returns the register number.

Definition at line369 of fileMachineOperand.h.

Referencesassert(), andisReg().

Referenced byllvm::GISelInstProfileBuilder::addNodeIDMachineOperand(),llvm::ScheduleDAGInstrs::addPhysRegDataDeps(),llvm::ScheduleDAGInstrs::addPhysRegDeps(),llvm::MachineInstr::addRegisterDead(),llvm::MachineInstr::addRegisterDefined(),llvm::MachineInstr::addRegisterKilled(),llvm::MachineRegisterInfo::addRegOperandToUseList(),llvm::SrcOp::addSrcToMIB(),llvm::ScheduleDAGInstrs::addVRegDefDeps(),llvm::ScheduleDAGInstrs::addVRegUseDeps(),llvm::ARMTargetLowering::AdjustInstrPostInstrSelection(),llvm::AArch64Subtarget::adjustSchedDependency(),llvm::HexagonSubtarget::adjustSchedDependency(),allPhiOperandsUndefined(),llvm::AArch64InstrInfo::analyzeLoopForPipelining(),llvm::AnalyzeVirtRegInBundle(),llvm::HexagonSubtarget::BankConflictMutation::apply(),llvm::CombinerHelper::applyBuildFnMO(),llvm::CombinerHelper::applyCombineDivRem(),llvm::CombinerHelper::applyCombineExtendingLoads(),llvm::CombinerHelper::applyCombineTruncOfShift(),llvm::CombinerHelper::applyCombineUnmergeZExtToZExt(),llvm::RegisterBankInfo::applyDefaultMapping(),llvm::CombinerHelper::applyExtendThroughPhis(),llvm::AMDGPUCombinerHelper::applyFoldableFneg(),llvm::RegBankSelect::applyMapping(),llvm::CombinerHelper::applyOptBrCondByInvertingCond(),llvm::CombinerHelper::applyShiftOfShiftedLogic(),llvm::HexagonInstrInfo::areMemAccessesTriviallyDisjoint(),attemptDebugCopyProp(),llvm::CriticalAntiDepBreaker::BreakAntiDependencies(),llvm::ARMBaseInstrInfo::breakPartialRegDependency(),llvm::buildEnqueueKernel(),llvm::SIInstrInfo::buildExtractSubReg(),llvm::SPIRVGlobalRegistry::buildGlobalVariable(),llvm::BuildMI(),llvm::buildNDRange(),buildRegSequence(),llvm::ScheduleDAGInstrs::buildSchedGraph(),llvm::R600InstrInfo::buildSlotOfVectorInstruction(),buildSpirvTypeName(),llvm::ModuloScheduleExpanderMVE::canApply(),canCombine(),canCombineFPFusedMultiply(),canCreateUndefOrPoison(),canEmitConjunction(),llvm::HexagonInstrInfo::canExecuteInBundle(),canFoldCopy(),llvm::AArch64InstrInfo::canFoldIntoAddrMode(),llvm::RISCVInstrInfo::canFoldIntoAddrMode(),canFoldIntoCSel(),llvm::HexagonPacketizerList::canPromoteToNewValueStore(),canRenameMOP(),canRenameUntilSecondLoad(),canRenameUpToDef(),llvm::SIInstrInfo::canShrink(),castBufferRsrcArgToV4I32(),castBufferRsrcFromV4I32(),llvm::MachineInstr::changeDebugValuesDefReg(),llvm::checkVOPDRegConstraints(),clearKillFlags(),llvm::MachineInstr::clearRegisterDeads(),llvm::MachineInstr::clearRegisterKills(),cloneInstr(),collectInlineAsmInstrOperands(),collectRegDefs(),CombineCVTAToLocal(),combineFPFusedMultiply(),llvm::PPCInstrInfo::combineRLWINM(),compareMachineOp(),CompressEVEXImpl(),llvm::RegBankSelect::computeMapping(),llvm::TargetSchedModel::computeOutputLatency(),ConsecutiveInstr(),llvm::constrainOperandRegClass(),RegBankSelectHelper::constrainRegBankUse(),llvm::constrainSelectedInstRegOperands(),llvm::PPCInstrInfo::convertToImmediateForm(),llvm::SIInstrInfo::convertToThreeAddress(),llvm::ARMBaseInstrInfo::convertToThreeAddress(),llvm::X86InstrInfo::convertToThreeAddress(),createCallWithOps(),llvm::ScheduleDAGInstrs::deadDefHasNoUse(),llvm::ShapeT::deduceImm(),llvm::X86InstrInfo::describeLoadedValue(),llvm::HexagonRegisterInfo::eliminateFrameIndex(),llvm::SIRegisterInfo::eliminateFrameIndex(),llvm::WebAssemblyRegisterInfo::eliminateFrameIndex(),emitIndirectDst(),llvm::HexagonHazardRecognizer::EmitInstruction(),llvm::SITargetLowering::EmitInstrWithCustomInserter(),llvm::AArch64InstrInfo::emitLdStWithAddr(),llvm::RISCVInstrInfo::emitLdStWithAddr(),EmitLoweredCascadedSelect(),eraseGPOpnd(),llvm::GIMatchTableExecutor::executeMatchTable(),Expand2AddrUndef(),llvm::M68kInstrInfo::ExpandCCR(),llvm::M68kInstrInfo::ExpandMOVEM(),llvm::M68kInstrInfo::ExpandMOVI(),llvm::M68kInstrInfo::ExpandMOVSZX_RM(),llvm::M68kInstrInfo::ExpandMOVSZX_RR(),llvm::M68kInstrInfo::ExpandMOVX_RR(),llvm::HexagonInstrInfo::expandPostRAPseudo(),llvm::X86InstrInfo::expandPostRAPseudo(),llvm::M68kInstrInfo::ExpandPUSH_POP(),llvm::AArch64GISelUtils::extractPtrauthBlendDiscriminators(),llvm::PPCInstrInfo::finalizeInsInstrs(),findAssignTypeInstr(),findDeadCallerSavedReg(),findLoopComponents(),findNextInsertLocation(),findRedundantFlagInstr(),llvm::MachineInstr::findRegisterDefOperandIdx(),llvm::MachineInstr::findRegisterUseOperandIdx(),findStartOfTree(),llvm::ScheduleDAGInstrs::fixupKills(),llvm::SwingSchedulerDAG::fixupRegisterOverlaps(),foldConstantsIntoIntrinsics(),llvm::PPCInstrInfo::foldFrameOffset(),foldImm(),llvm::SIInstrInfo::foldImmediate(),llvm::ARMBaseInstrInfo::foldImmediate(),llvm::TargetInstrInfo::foldMemoryOperand(),llvm::AArch64InstrInfo::foldMemoryOperandImpl(),llvm::SystemZInstrInfo::foldMemoryOperandImpl(),llvm::X86InstrInfo::foldMemoryOperandImpl(),foldPatchpoint(),foldVGPRCopyIntoRegSequence(),llvm::TargetInstrInfo::genAlternativeCodeSequence(),llvm::RISCVInstrInfo::genAlternativeCodeSequence(),genAlternativeDpCodeSequence(),generateAssignInstrs(),llvm::generateCoopMatrInst(),llvm::generateImageSizeQueryInst(),genFNegatedMAD(),genFusedMultiply(),genIndexedMultiply(),genMaddR(),genShXAddAddShift(),genSubAdd2SubSub(),llvm::getAddressFromInstr(),llvm::X86InstrInfo::getAddrModeFromMemoryOp(),getArrayComponentCount(),llvm::GIndexedLoad::getBaseReg(),llvm::GIndexedStore::getBaseReg(),llvm::GInsertSubvector::getBigVec(),llvm::getBlockStructInstr(),getCallTargetRegOpnd(),llvm::HexagonInstrInfo::getCompoundOpcode(),llvm::getConstFromIntrinsic(),llvm::SIRegisterInfo::getConstrainedRegClassForOperand(),llvm::X86InstrInfo::getConstValDefinedInReg(),llvm::getDefInstrMaybeConstant(),getDefRegMask(),llvm::getDefSrcRegIgnoringCopies(),llvm::GIndexedLoad::getDstReg(),llvm::GAnyLoad::getDstReg(),llvm::GInsertVectorElement::getElementReg(),llvm::TargetInstrInfo::getExtractSubregInputs(),llvm::ARMBaseInstrInfo::getExtractSubregLikeInputs(),llvm::MachineInstr::getFirst2RegLLTs(),llvm::MachineInstr::getFirst3RegLLTs(),llvm::MachineInstr::getFirst4RegLLTs(),llvm::MachineInstr::getFirst5RegLLTs(),llvm::PPCInstrInfo::getFMAPatterns(),getFMULPatterns(),getFNEGPatterns(),getFoldableImm(),getFPReg(),llvm::MachineInstrExpressionTrait::getHashValue(),llvm::ARMBankConflictHazardRecognizer::getHazardType(),getImmedFromMO(),llvm::GPhi::getIncomingValue(),llvm::GExtractVectorElement::getIndexReg(),llvm::GInsertVectorElement::getIndexReg(),llvm::TargetInstrInfo::getInsertSubregInputs(),llvm::ARMBaseInstrInfo::getInsertSubregLikeInputs(),getInstReadLaneMask(),llvm::ARMRegisterBankInfo::getInstrMapping(),llvm::RegisterBankInfo::getInstrMappingImpl(),llvm::SIInstrInfo::getInstructionUniformity(),llvm::ScheduleDAGInstrs::getLaneMaskForMO(),llvm::GBinOpCarryOut::getLHSReg(),llvm::GSUCmp::getLHSReg(),llvm::SrcOp::getLLTTy(),llvm::getMachineInstrType(),llvm::ReachingDefAnalysis::getMIOperand(),getMopState(),getNewSource(),getNumDefTiles(),llvm::GIndexedLoad::getOffsetReg(),llvm::GIndexedStore::getOffsetReg(),llvm::ARMBaseInstrInfo::getOperandLatency(),llvm::HexagonInstrInfo::getOperandLatency(),llvm::PPCInstrInfo::getOperandLatency(),llvm::SPIRVGlobalRegistry::getOrCreateConstIntArray(),llvm::SPIRVGlobalRegistry::getOrCreateOpTypeSampledImage(),llvm::ARMBaseInstrInfo::getPartialRegUpdateClearance(),llvm::X86InstrInfo::getPartialRegUpdateClearance(),llvm::PeelingModuloScheduleExpander::getPhiCanonicalReg(),llvm::SPIRVGlobalRegistry::getPointeeType(),llvm::GLoadStore::getPointerReg(),llvm::SSAUpdaterTraits< MachineSSAUpdater >::GetPoisonVal(),getRC32(),llvm::SrcOp::getReg(),llvm::GenericMachineInstr::getReg(),llvm::PPCRegisterInfo::getRegAllocationHints(),llvm::SystemZRegisterInfo::getRegAllocationHints(),llvm::SPIRVGlobalRegistry::getRegClass(),llvm::SIRegisterInfo::getRegClassForOperandReg(),llvm::TargetInstrInfo::getRegSequenceInputs(),llvm::ARMBaseInstrInfo::getRegSequenceLikeInputs(),llvm::getRegState(),llvm::SPIRVGlobalRegistry::getRegType(),llvm::RegBankSelect::getRepairCost(),llvm::GBinOpCarryOut::getRHSReg(),llvm::GSUCmp::getRHSReg(),getSalvageOpsForTrunc(),llvm::GSplatVector::getScalarReg(),llvm::GShl::getShiftReg(),getShuffleComment(),llvm::GUnmerge::getSourceReg(),llvm::GFreeze::getSourceReg(),llvm::GShuffleVector::getSrc1Reg(),llvm::GShuffleVector::getSrc2Reg(),llvm::GCastOp::getSrcReg(),llvm::GShl::getSrcReg(),llvm::R600InstrInfo::getSrcs(),llvm::GExtractSubvector::getSrcVec(),llvm::GInsertSubvector::getSubVec(),getTypeReg(),llvm::X86InstrInfo::getUndefRegClearance(),llvm::MachineSSAUpdater::GetValueInMiddleOfBlock(),llvm::GIndexedStore::getValueReg(),llvm::GStore::getValueReg(),llvm::GExtractVectorElement::getVectorReg(),llvm::GInsertVectorElement::getVectorReg(),llvm::getVRegDef(),llvm::getVRegSubRegDef(),llvm::GIndexedLoad::getWritebackReg(),llvm::GIndexedStore::getWritebackReg(),handleADRP(),llvm::hash_value(),hasLiveThroughUse(),hasMoreUses(),hasRAWHazard(),llvm::TargetInstrInfo::hasReassociableOperands(),llvm::RISCVInstrInfo::hasReassociableOperands(),llvm::TargetInstrInfo::hasReassociableSibling(),llvm::RISCVInstrInfo::hasReassociableSibling(),hasRegisterDependency(),llvm::MachineInstr::hasRegisterImplicitUseOperand(),hasSameBaseOpValue(),indirectCopyToAGPR(),INITIALIZE_PASS(),llvm::insertAssignInstr(),llvm::HexagonInstrInfo::insertBranch(),insertDivByZeroTrap(),insertSEH(),llvm::AArch64InstrInfo::isAddImmediate(),llvm::ARMBaseInstrInfo::isAddImmediate(),llvm::MipsInstrInfo::isAddImmediate(),llvm::RISCVInstrInfo::isAddImmediate(),isAGPRCopy(),isArithmeticBccPair(),isBackwardPropagatableCopy(),llvm::GIMatchTableExecutor::isBaseWithConstantOffset(),isCandidate(),llvm::WebAssembly::isChild(),llvm::AArch64GISelUtils::isCMN(),llvm::MachineInstr::isConstantValuePHI(),isConstReg(),isConvertibleLEA(),isCrossCopy(),llvm::MachineInstr::isDead(),llvm::AArch64InstrInfo::isExtendLikelyToBeFolded(),isExtractHiElt(),isFIPlusImmOrVGPR(),isIdenticalOp(),llvm::MachineInstr::isIdenticalTo(),isIdenticalTo(),llvm::MachineInstr::isIdentityCopy(),llvm::SIInstrInfo::isIgnorableUse(),isImm(),llvm::PPCInstrInfo::isImmInstrEligibleForFolding(),isInvariantStore(),llvm::isKnownNeverNaN(),isLdStSafeToCluster(),llvm::SIInstrInfo::isLegalRegOperand(),llvm::HexagonPacketizerList::isLegalToPacketizeTogether(),isLogicalOpOnExec(),llvm::SMSchedule::isLoopCarriedDefOfUse(),llvm::SwingSchedulerDAG::isLoopCarriedDep(),isMaskOperand(),isMatchingStartStopPair(),isMergeableLdStUpdate(),isMMSourceRegister(),isMMThreeBitGPRegister(),isNonFoldablePartialRegisterLoad(),llvm::GIMatchTableExecutor::isOperandImmEqual(),isOperandKill(),llvm::SIInstrInfo::isOperandLegal(),isPromotableZeroStoreInst(),isRedundantFlagInstr(),isRegInClass(),isRelevantAddressingMode(),isRenamable(),IsSafeAndProfitableToMove(),llvm::SIInstrInfo::isSGPRStackAccess(),llvm::SIInstrInfo::isStackAccess(),isSubRegOf(),isSVERegOp(),isTileDef(),isTileRegDef(),llvm::HexagonInstrInfo::isToBeScheduledASAP(),isTwoAddrUse(),isValidRegDefOf(),isValidRegUseOf(),llvm::PPCInstrInfo::isValidToBeChangedReg(),isVirtualRegisterOperand(),isWaitInstr(),llvm::AArch64LegalizerInfo::legalizeIntrinsic(),llvm::SIInstrInfo::legalizeOperands(),llvm::SIInstrInfo::legalizeOperandsFLAT(),llvm::SIInstrInfo::legalizeOperandsSMRD(),llvm::SIInstrInfo::legalizeOperandsVOP2(),llvm::SIInstrInfo::legalizeOperandsVOP3(),llvm::WebAssemblyMCInstLower::lower(),llvm::SPIRVMCInstLower::lower(),LowerCallResults(),llvm::TargetInstrInfo::lowerCopy(),llvm::lowerLoongArchMachineOperandToMCOperand(),llvm::M68kMCInstLower::LowerOperand(),LowerOperand(),llvm::SystemZMCInstLower::lowerOperand(),llvm::MipsMCInstLower::LowerOperand(),llvm::ARMAsmPrinter::lowerOperand(),llvm::AArch64MCInstLower::lowerOperand(),AMDGPUMCInstLower::lowerOperand(),llvm::CSKYMCInstLower::lowerOperand(),llvm::ARCMCInstLower::LowerOperand(),llvm::XCoreMCInstLower::LowerOperand(),llvm::XtensaAsmPrinter::lowerOperand(),llvm::LowerPPCMachineOperandToMCOperand(),lowerRISCVVMachineInstrToMCInst(),llvm::LoongArchAsmPrinter::LowerSTATEPOINT(),llvm::MIPatternMatch::BinaryOp_match< LHS_P, RHS_P, Opcode, Commutable >::match(),llvm::MIPatternMatch::BinaryOpc_match< LHS_P, RHS_P, Commutable >::match(),llvm::MIPatternMatch::UnaryOp_match< SrcTy, Opcode >::match(),llvm::MIPatternMatch::CompareOp_match< Pred_P, LHS_P, RHS_P, Opcode, Commutable >::match(),llvm::MIPatternMatch::TernaryOp_match< Src0Ty, Src1Ty, Src2Ty, Opcode >::match(),llvm::CombinerHelper::matchAddOfVScale(),llvm::CombinerHelper::matchCombineExtractedVectorLoad(),llvm::CombinerHelper::matchCombineFAddFMAFMulToFMadOrFMA(),llvm::CombinerHelper::matchCombineFAddFpExtFMulToFMadOrFMA(),llvm::CombinerHelper::matchCombineFAddFpExtFMulToFMadOrFMAAggressive(),llvm::AMDGPUCombinerHelper::matchCombineFmulWithSelectToFldexp(),llvm::CombinerHelper::matchCombineFSubFNegFMulToFMadOrFMA(),llvm::CombinerHelper::matchCombineFSubFpExtFMulToFMadOrFMA(),llvm::CombinerHelper::matchCombineFSubFpExtFNegFMulToFMadOrFMA(),llvm::CombinerHelper::matchCombineInsertVecElts(),llvm::CombinerHelper::matchCombineTruncOfShift(),llvm::CombinerHelper::matchConstantFPOp(),llvm::CombinerHelper::matchConstantOp(),llvm::CombinerHelper::matchEqualDefs(),llvm::CombinerHelper::matchExtractVecEltBuildVec(),llvm::CombinerHelper::matchExtractVectorElementWithBuildVectorTrunc(),llvm::CombinerHelper::matchExtractVectorElementWithDifferentIndices(),llvm::AMDGPUCombinerHelper::matchFoldableFneg(),llvm::CombinerHelper::matchFreezeOfSingleMaybePoisonOperand(),llvm::CombinerHelper::matchHoistLogicOpWithSameOpcodeHands(),llvm::CombinerHelper::matchMulOfVScale(),llvm::CombinerHelper::matchNarrowBinopFeedingAnd(),llvm::CombinerHelper::matchNonNegZext(),llvm::CombinerHelper::matchOperandIsKnownToBeAPowerOfTwo(),llvm::CombinerHelper::matchOperandIsUndef(),llvm::CombinerHelper::matchPtrAddImmedChain(),llvm::CombinerHelper::matchSelectIMinMax(),llvm::CombinerHelper::matchSextOfTrunc(),llvm::CombinerHelper::matchShiftImmedChain(),llvm::CombinerHelper::matchShiftOfShiftedLogic(),llvm::CombinerHelper::matchShlOfVScale(),llvm::CombinerHelper::matchSubOfVScale(),llvm::CombinerHelper::matchUnmergeValuesAnyExtBuildVector(),llvm::CombinerHelper::matchZextOfTrunc(),MIIsInTerminatorSequence(),llvm::LegalizerHelper::moreElementsVectorDst(),llvm::SIInstrInfo::moveFlatAddrToVGPR(),llvm::PeelingModuloScheduleExpander::moveStageBetweenBlocks(),llvm::SIInstrInfo::moveToVALUImpl(),MoveVPNOTBeforeFirstUser(),oneUseDominatesOtherUses(),llvm::ShapeT::operator==(),llvm::PPCInstrInfo::optimizeCmpPostRA(),llvm::AArch64InstrInfo::optimizeCompareInstr(),llvm::ARMBaseInstrInfo::optimizeCompareInstr(),llvm::LanaiInstrInfo::optimizeCompareInstr(),llvm::X86InstrInfo::optimizeCompareInstr(),llvm::PPCInstrInfo::optimizeCompareInstr(),llvm::AArch64InstrInfo::optimizeCondBranch(),llvm::X86InstrInfo::optimizeLoadInstr(),llvm::LanaiInstrInfo::optimizeSelect(),llvm::ARMBaseInstrInfo::optimizeSelect(),llvm::RISCVInstrInfo::optimizeSelect(),llvm::CallLowering::parametersInCSRMatch(),parseCondBranch(),llvm::PeelSingleBlockLoop(),print(),llvm::CSKYAsmPrinter::PrintAsmMemoryOperand(),llvm::LoongArchAsmPrinter::PrintAsmMemoryOperand(),llvm::M68kAsmPrinter::PrintAsmMemoryOperand(),llvm::ARMAsmPrinter::PrintAsmMemoryOperand(),llvm::MipsAsmPrinter::PrintAsmMemoryOperand(),printAsmMRegister(),llvm::AMDGPUAsmPrinter::PrintAsmOperand(),llvm::MipsAsmPrinter::PrintAsmOperand(),llvm::CSKYAsmPrinter::PrintAsmOperand(),llvm::HexagonAsmPrinter::PrintAsmOperand(),llvm::LoongArchAsmPrinter::PrintAsmOperand(),llvm::SystemZAsmPrinter::PrintAsmOperand(),llvm::ARMAsmPrinter::PrintAsmOperand(),llvm::AVRAsmPrinter::PrintAsmOperand(),printAsmVRegister(),printDstRegisterName(),llvm::ARMAsmPrinter::printOperand(),llvm::MipsAsmPrinter::printOperand(),llvm::AVRAsmPrinter::printOperand(),llvm::HexagonAsmPrinter::printOperand(),processNewInstrs(),llvm::ARMBaseInstrInfo::produceSameValue(),producesFalseLanesZero(),llvm::PPCInstrInfo::promoteInstr32To64ForElimEXTSW(),llvm::MachineInstr::readsWritesVirtualRegister(),RegBankSelectHelper::reAssignRegBankOnDef(),llvm::TargetInstrInfo::reassociateOps(),TransferTracker::redefVar(),reduceDbgValsForwardScan(),llvm::WebAssemblyAsmPrinter::regToString(),reinsertVectorIndexAdd(),llvm::SIInstrInfo::reMaterialize(),llvm::ARMBaseInstrInfo::reMaterialize(),llvm::X86InstrInfo::reMaterialize(),removeCopies(),RemoveDeadAddBetweenLEAAndJT(),llvm::MachineRegisterInfo::removeRegOperandFromUseList(),llvm::LiveVariables::removeVirtualRegistersKilled(),llvm::RegBankSelect::RepairingPlacement::RepairingPlacement(),llvm::RegBankSelect::repairReg(),rescheduleCanonically(),llvm::R600InstrInfo::reverseBranchCondition(),llvm::MachineSSAUpdater::RewriteUse(),llvm::SelectionDAGISel::runOnMachineFunction(),llvm::MachineFunction::salvageCopySSAImpl(),llvm::R600SchedStrategy::schedNode(),setIsRenamable(),llvm::MachineInstr::setPhysRegsDeadExcept(),setReg(),llvm::MachineInstr::setRegisterDefReadUndef(),llvm::AArch64InstrInfo::shouldClusterMemOps(),llvm::PPCInstrInfo::shouldClusterMemOps(),shouldUseFormStridedPseudo(),SinkingPreventsImplicitNullCheck(),llvm::MachineBasicBlock::SplitCriticalEdge(),splitMBB(),llvm::stableHashValue(),llvm::MachineInstr::substituteRegister(),swapRegAndNonRegOperand(),llvm::RegBankSelect::tryAvoidingSplit(),llvm::LegalizationArtifactCombiner::tryCombineExtract(),llvm::tryFoldSPUpdateIntoPushPop(),llvm::LegalizationArtifactCombiner::tryFoldUnmergeCast(),AMDGPURegBankLegalizeCombiner::tryMatch(),llvm::CombinerHelper::tryReassocBinOp(),llvm::X86InstrInfo::unfoldMemoryOperand(),UpdateCPSRDef(),UpdateCPSRUse(),llvm::HexagonPacketizerList::updateOffset(),UpdateOperandRegClass(),updateOperandRegConstraints(),updatePhysDepsDownwards(),UseReg(),llvm::SIInstrInfo::usesConstantBus(),validateAccessChain(),validateFunCallMachineDef(),validateGroupWaitEventsPtr(),validatePtrTypes(),validatePtrUnwrapStructField(),valueIsKnownNeverF32Denorm(),llvm::RegisterBankInfo::InstructionMapping::verify(),verifyCFIntrinsic(),llvm::SIInstrInfo::verifyInstruction(),VerifyLowRegs(),llvm::MachineRegisterInfo::verifyUseList(), andllvm::VirtRegAuxInfo::weightCalcHelper().

◆ getRegLiveOut()

constuint32_t * llvm::MachineOperand::getRegLiveOut() const
inline

getRegLiveOut - Returns a bit mask of live-out registers.

Definition at line671 of fileMachineOperand.h.

Referencesassert(), andisRegLiveOut().

Referenced byprint().

◆ getRegMask()

constuint32_t * llvm::MachineOperand::getRegMask() const
inline

getRegMask - Returns a bit mask of registers preserved by this RegMask operand.

Definition at line660 of fileMachineOperand.h.

Referencesassert(), andisRegMask().

Referenced byclobbersPhysReg(),llvm::ScheduleDAGInstrs::fixupKills(),llvm::hash_value(),isIdenticalTo(),isMatchingStartStopPair(),print(),llvm::MIRParserImpl::setupRegisterInfo(), andllvm::stableHashValue().

◆ getRegMaskSize()

staticunsigned llvm::MachineOperand::getRegMaskSize(unsigned NumRegs)
inlinestatic

Returns number of elements needed for a regmask array.

Definition at line666 of fileMachineOperand.h.

Referenced byllvm::MachineFunction::allocateRegMask(),llvm::hash_value(),isIdenticalTo(),regMaskFromTemplate(),llvm::stableHashValue(), andllvm::AArch64RegisterInfo::UpdateCustomCallPreservedMask().

◆ getShuffleMask()

ArrayRef< int > llvm::MachineOperand::getShuffleMask() const
inline

Definition at line622 of fileMachineOperand.h.

Referencesassert(), andisShuffleMask().

Referenced byllvm::GShuffleVector::getMask(),llvm::hash_value(),isExtractHiElt(),isIdenticalTo(),print(), andllvm::stableHashValue().

◆ getSubReg()

unsigned llvm::MachineOperand::getSubReg() const
inline

Definition at line374 of fileMachineOperand.h.

Referencesassert(), andisReg().

Referenced byllvm::MachineInstr::addRegisterDefined(),llvm::ScheduleDAGInstrs::addVRegDefDeps(),llvm::HexagonInstrInfo::areMemAccessesTriviallyDisjoint(),attemptDebugCopyProp(),llvm::SIInstrInfo::buildExtractSubReg(),canFoldCopy(),llvm::HexagonInstrInfo::expandPostRAPseudo(),findUseBetween(),llvm::SIInstrInfo::foldImmediate(),llvm::AArch64InstrInfo::foldMemoryOperandImpl(),llvm::X86InstrInfo::foldMemoryOperandImpl(),foldPatchpoint(),foldVGPRCopyIntoRegSequence(),llvm::HexagonInstrInfo::getBaseAndOffset(),getDefRegMask(),llvm::TargetInstrInfo::getExtractSubregInputs(),llvm::ARMBaseInstrInfo::getExtractSubregLikeInputs(),llvm::TargetInstrInfo::getInsertSubregInputs(),llvm::ARMBaseInstrInfo::getInsertSubregLikeInputs(),getInstReadLaneMask(),llvm::ScheduleDAGInstrs::getLaneMaskForMO(),getNewSource(),llvm::SIInstrInfo::getOpSize(),llvm::ARMBaseInstrInfo::getPartialRegUpdateClearance(),getRC32(),llvm::PPCRegisterInfo::getRegAllocationHints(),llvm::RISCVRegisterInfo::getRegAllocationHints(),llvm::SystemZRegisterInfo::getRegAllocationHints(),llvm::MachineInstr::getRegClassConstraintEffect(),llvm::SIRegisterInfo::getRegClassForOperandReg(),llvm::TargetInstrInfo::getRegSequenceInputs(),llvm::ARMBaseInstrInfo::getRegSequenceLikeInputs(),llvm::hash_value(),INITIALIZE_PASS(),isAGPRCopy(),isCrossCopy(),llvm::MachineInstr::isFullCopy(),llvm::TargetInstrInfo::isFullCopyInstr(),isIdenticalTo(),llvm::MachineInstr::isIdentityCopy(),llvm::SIInstrInfo::isLegalRegOperand(),llvm::SIInstrInfo::isOperandLegal(),isSSA(),llvm::SIInstrInfo::legalizeOperandsVOP2(),llvm::ARMAsmPrinter::lowerOperand(),llvm::LowerPPCMachineOperandToMCOperand(),llvm::PPCInstrInfo::optimizeCompareInstr(),llvm::X86InstrInfo::optimizeLoadInstr(),print(),llvm::ARMAsmPrinter::printOperand(),readsReg(),llvm::MachineInstr::readsWritesVirtualRegister(),llvm::SIInstrInfo::reMaterialize(),llvm::MachineInstr::setRegisterDefReadUndef(),shouldUseFormStridedPseudo(),llvm::stableHashValue(),substPhysReg(),substVirtReg(),swapRegAndNonRegOperand(),llvm::SIInstrInfo::verifyInstruction(), andllvm::VirtRegAuxInfo::weightCalcHelper().

◆ getSymbolName()

constchar * llvm::MachineOperand::getSymbolName() const
inline

Definition at line637 of fileMachineOperand.h.

Referencesassert(), andisSymbol().

Referenced byllvm::BTFDebug::beginInstruction(),llvm::SystemZMCInstLower::getExpr(),llvm::AArch64MCInstLower::GetExternalSymbolSymbol(),llvm::BPFMCInstLower::GetExternalSymbolSymbol(),llvm::LanaiMCInstLower::GetExternalSymbolSymbol(),llvm::MSP430MCInstLower::GetExternalSymbolSymbol(),getMovOperand(),llvm::M68kMCInstLower::GetSymbolFromOperand(),GetSymbolFromOperand(),llvm::hash_value(),isIdenticalTo(),isSimilarDispOp(),llvm::lowerLoongArchMachineOperandToMCOperand(),LowerOperand(),llvm::ARMAsmPrinter::lowerOperand(),AMDGPUMCInstLower::lowerOperand(),llvm::CSKYMCInstLower::lowerOperand(),LowerSymbolOperand(),llvm::XtensaAsmPrinter::LowerSymbolOperand(),llvm::AArch64MCInstLower::lowerSymbolOperandELF(),llvm::WebAssembly::mayThrow(),optimizeCall(),print(),llvm::WebAssemblyAsmPrinter::PrintAsmOperand(),llvm::AVRAsmPrinter::printOperand(), andllvm::stableHashValue().

◆ getTargetFlags()

unsigned llvm::MachineOperand::getTargetFlags() const
inline

Definition at line226 of fileMachineOperand.h.

ReferencesisReg().

Referenced byllvm::MachineInstrBuilder::addDisp(),emitDirectiveRelocJalr(),llvm::R600TargetLowering::EmitInstrWithCustomInserter(),llvm::MipsInstrInfo::genInstrWithNewOpc(),llvm::MSP430MCInstLower::GetBlockAddressSymbol(),llvm::MSP430MCInstLower::GetConstantPoolIndexSymbol(),llvm::LoongArchII::getDirectFlags(),llvm::MSP430MCInstLower::GetExternalSymbolSymbol(),llvm::AArch64MCInstLower::GetGlobalAddressSymbol(),llvm::MSP430MCInstLower::GetGlobalAddressSymbol(),llvm::MSP430MCInstLower::GetJumpTableSymbol(),getMovOperand(),GetSymbolRef(),getTOCEntryTypeForMO(),llvm::hash_value(),llvm::LoongArchII::hasRelaxFlag(),INITIALIZE_PASS(),llvm::HexagonInstrInfo::isConstExtended(),isIdenticalTo(),llvm::WebAssemblyMCInstLower::lower(),llvm::SystemZMCInstLower::lowerOperand(),llvm::ARMAsmPrinter::lowerOperand(),AMDGPUMCInstLower::lowerOperand(),LowerSymbolOperand(),llvm::CSKYMCInstLower::lowerSymbolOperand(),llvm::LanaiMCInstLower::LowerSymbolOperand(),llvm::M68kMCInstLower::LowerSymbolOperand(),llvm::MSP430MCInstLower::LowerSymbolOperand(),lowerSymbolOperand(),llvm::AVRMCInstLower::lowerSymbolOperand(),llvm::AArch64MCInstLower::lowerSymbolOperandCOFF(),llvm::AArch64MCInstLower::lowerSymbolOperandELF(),llvm::AArch64MCInstLower::lowerSymbolOperandMachO(),llvm::ARMAsmPrinter::printOperand(),llvm::MipsAsmPrinter::printOperand(),llvm::ARMAsmPrinter::PrintSymbolOperand(),llvm::stableHashValue(),swapImmOperands(), andswapRegAndNonRegOperand().

◆ getTargetIndexName()

constchar * MachineOperand::getTargetIndexName() const

getTargetIndexName - If thisMachineOperand is a TargetIndex that has a name, attempt to get the name.

Returns nullptr if the TargetIndex does not have a name. Asserts if MO is not a TargetIndex.

Definition at line476 of fileMachineOperand.cpp.

ReferencesgetIndex(),getMFIfAvailable(), andgetTargetIndexName().

Referenced bygetTargetIndexName(),print(), andllvm::stableHashValue().

◆ getType()

MachineOperandType llvm::MachineOperand::getType() const
inline

getType - Returns the MachineOperandType for this operand.

Definition at line224 of fileMachineOperand.h.

Referenced byllvm::MachineInstrBuilder::addDisp(),compareMachineOp(),getCodeModel(),llvm::SystemZMCInstLower::getExpr(),getMCSymbolForTOCPseudoMO(),getMovOperand(),getTOCEntryTypeForMO(),llvm::hash_value(),INITIALIZE_PASS(),IsAnAddressOperand(),isIdenticalTo(),llvm::WebAssemblyMCInstLower::lower(),llvm::SPIRVMCInstLower::lower(),llvm::lowerLoongArchMachineOperandToMCOperand(),llvm::M68kMCInstLower::LowerOperand(),LowerOperand(),llvm::SystemZMCInstLower::lowerOperand(),llvm::MipsMCInstLower::LowerOperand(),llvm::ARMAsmPrinter::lowerOperand(),llvm::AArch64MCInstLower::lowerOperand(),AMDGPUMCInstLower::lowerOperand(),llvm::CSKYMCInstLower::lowerOperand(),llvm::ARCMCInstLower::LowerOperand(),llvm::XCoreMCInstLower::LowerOperand(),llvm::XtensaAsmPrinter::lowerOperand(),llvm::LowerPPCMachineOperandToMCOperand(),lowerRISCVVMachineInstrToMCInst(),llvm::LoongArchAsmPrinter::LowerSTATEPOINT(),LowerSymbolOperand(),print(),llvm::M68kAsmPrinter::PrintAsmMemoryOperand(),llvm::X86AsmPrinter::PrintAsmOperand(),llvm::CSKYAsmPrinter::PrintAsmOperand(),llvm::LoongArchAsmPrinter::PrintAsmOperand(),llvm::WebAssemblyAsmPrinter::PrintAsmOperand(),llvm::AVRAsmPrinter::PrintAsmOperand(),llvm::ARMAsmPrinter::printOperand(),llvm::MipsAsmPrinter::printOperand(),llvm::XtensaAsmPrinter::printOperand(),llvm::AVRAsmPrinter::printOperand(),llvm::HexagonAsmPrinter::printOperand(),llvm::AArch64InstrInfo::shouldClusterMemOps(), andllvm::stableHashValue().

◆ isBlockAddress()

bool llvm::MachineOperand::isBlockAddress() const
inline

isBlockAddress - Tests if this is a MO_BlockAddress operand.

Definition at line351 of fileMachineOperand.h.

ReferencesMO_BlockAddress.

Referenced bygetBlockAddress(),getOffset(),INITIALIZE_PASS(),llvm::HexagonInstrInfo::isConstExtended(),isSimilarDispOp(),isValidDispOp(),llvm::LoongArchAsmPrinter::PrintAsmMemoryOperand(),processBlockAddr(), andsetOffset().

◆ isCFIIndex()

bool llvm::MachineOperand::isCFIIndex() const
inline

Definition at line360 of fileMachineOperand.h.

ReferencesMO_CFIIndex.

Referenced bygetCFIIndex().

◆ isCImm()

bool llvm::MachineOperand::isCImm() const
inline

isCImm - Test if this is a MO_CImmediate operand.

Definition at line333 of fileMachineOperand.h.

ReferencesMO_CImmediate.

Referenced byllvm::GISelInstProfileBuilder::addNodeIDMachineOperand(),llvm::GIMatchTableExecutor::executeMatchTable(),llvm::generateGroupUniformInst(),llvm::generateSpecConstantInst(),getCImm(),llvm::getConstFromIntrinsic(),getImmedFromMO(),isCandidate(),setCImm(), andllvm::stableHashValue().

◆ isCPI()

bool llvm::MachineOperand::isCPI() const
inline

isCPI - Tests if this is a MO_ConstantPoolIndex operand.

Definition at line341 of fileMachineOperand.h.

ReferencesMO_ConstantPoolIndex.

Referenced byllvm::X86::getConstantFromPool(),getIndex(),getOffset(),INITIALIZE_PASS(),isAnImmediateOperand(),isCandidate(),llvm::HexagonInstrInfo::isConstExtended(),isSimilarDispOp(),isValidDispOp(),setIndex(),setOffset(), andsmallData().

◆ isDbgInstrRef()

bool llvm::MachineOperand::isDbgInstrRef() const
inline

Definition at line359 of fileMachineOperand.h.

ReferencesMO_DbgInstrRef.

Referenced bygetInstrRefInstrIndex(),getInstrRefOpIndex(),setInstrRefInstrIndex(), andsetInstrRefOpIndex().

◆ isDead()

bool llvm::MachineOperand::isDead() const
inline

Definition at line394 of fileMachineOperand.h.

Referencesassert(), andisReg().

Referenced byllvm::ScheduleDAGInstrs::addPhysRegDeps(),llvm::MachineInstr::addRegisterDead(),llvm::ScheduleDAGInstrs::addVRegDefDeps(),llvm::ARMTargetLowering::AdjustInstrPostInstrSelection(),llvm::MachineInstr::allDefsAreDead(),llvm::MachineInstr::allImplicitDefsAreDead(),ChangeToRegister(),llvm::ARMBaseInstrInfo::convertToThreeAddress(),CreateReg(),doesInstructionSetFPSW(),llvm::SIRegisterInfo::eliminateFrameIndex(),llvm::MachineInstr::findRegisterDefOperandIdx(),llvm::ARMBaseInstrInfo::foldImmediate(),getClobberType(),getMopState(),llvm::getRegState(),llvm::X86InstrInfo::hasReassociableOperands(),isCandidate(),llvm::MachineInstr::isDead(),llvm::MachineInstr::isIdenticalTo(),moveAndTeeForMultiUse(),print(),llvm::X86InstrInfo::setSpecialOperandAttr(),swapRegAndNonRegOperand(), andUpdateCPSRDef().

◆ isDebug()

bool llvm::MachineOperand::isDebug() const
inline

Definition at line455 of fileMachineOperand.h.

Referencesassert(), andisReg().

Referenced byllvm::MachineInstr::addRegisterKilled(),canRenameUpToDef(),ChangeToRegister(),CreateReg(),llvm::getRegState(),setIsDef(),setIsKill(), andswapRegAndNonRegOperand().

◆ isDef()

bool llvm::MachineOperand::isDef() const
inline

Definition at line384 of fileMachineOperand.h.

Referencesassert(), andisReg().

Referenced byllvm::GISelInstProfileBuilder::addNodeIDMachineOperand(),llvm::ScheduleDAGInstrs::addPhysRegDataDeps(),llvm::MachineInstr::addRegisterDead(),llvm::MachineRegisterInfo::addRegOperandToUseList(),llvm::ARMTargetLowering::AdjustInstrPostInstrSelection(),llvm::AnalyzeVirtRegInBundle(),llvm::BTFDebug::beginInstruction(),llvm::CriticalAntiDepBreaker::BreakAntiDependencies(),llvm::ScheduleDAGInstrs::buildSchedGraph(),canRenameMOP(),canRenameUpToDef(),ChangeToRegister(),collectInlineAsmInstrOperands(),llvm::constrainOperandRegClass(),llvm::PPCInstrInfo::convertToImmediateForm(),CreateReg(),llvm::HexagonHazardRecognizer::EmitInstruction(),findDeadCallerSavedReg(),findDefIdx(),llvm::MachineInstr::findRegisterDefOperandIdx(),findUseIdx(),llvm::ScheduleDAGInstrs::fixupKills(),llvm::X86InstrInfo::foldMemoryOperandImpl(),getDefRegMask(),llvm::MachineInstrExpressionTrait::getHashValue(),getInstReadLaneMask(),llvm::PPCInstrInfo::getInstrLatency(),llvm::PatchPointOpers::getNextScratchIdx(),llvm::MachineInstr::getNumExplicitDefs(),llvm::getRegState(),llvm::RegBankSelect::getRepairCost(),llvm::hash_value(),hasRegisterDependency(),INITIALIZE_PASS(),isCandidate(),llvm::WebAssembly::isChild(),llvm::MachineInstr::isIdenticalTo(),isIdenticalTo(),llvm::MachineInstr::isRegTiedToUseOperand(),isRenamable(),IsSafeAndProfitableToMove(),isValidRegDef(),MIIsInTerminatorSequence(),llvm::ARMBaseInstrInfo::optimizeCompareInstr(),llvm::LanaiInstrInfo::optimizeCompareInstr(),llvm::X86InstrInfo::optimizeLoadInstr(),llvm::MachineInstr::print(),print(),printImplicitRegisterFlag(),llvm::RegBankSelect::RepairingPlacement::RepairingPlacement(),llvm::RegBankSelect::repairReg(),rescheduleCanonically(),llvm::MachineInstr::setPhysRegsDeadExcept(),llvm::stableHashValue(),substPhysReg(),llvm::MachineInstr::tieOperands(),llvm::RegBankSelect::tryAvoidingSplit(), andUpdateCPSRUse().

◆ isEarlyClobber()

bool llvm::MachineOperand::isEarlyClobber() const
inline

Definition at line445 of fileMachineOperand.h.

Referencesassert(), andisReg().

Referenced bycanRenameMOP(),createDeadDef(),CreateReg(),dumpMachineInstrRangeWithSlotIndex(),getMopState(),llvm::PatchPointOpers::getNextScratchIdx(), andprint().

◆ isFI()

bool llvm::MachineOperand::isFI() const
inline

isFI - Tests if this is a MO_FrameIndex operand.

Definition at line339 of fileMachineOperand.h.

ReferencesMO_FrameIndex.

Referenced byllvm::X86InstrInfo::describeLoadedValue(),llvm::SIRegisterInfo::eliminateFrameIndex(),llvm::TargetLoweringBase::emitPatchPoint(),getIndex(),llvm::SIInstrInfo::getMemOperandsWithOffsetWidth(),llvm::PPCInstrInfo::getMemOperandWithOffsetWidth(),llvm::RISCVInstrInfo::getMemOperandWithOffsetWidth(),llvm::AArch64InstrInfo::getMemOperandWithOffsetWidth(),isFIPlusImmOrVGPR(),llvm::SIInstrInfo::isImmOperandLegal(),isLdStSafeToCluster(),llvm::SIInstrInfo::isLegalVSrcOperand(),llvm::HexagonInstrInfo::isLoadFromStackSlot(),llvm::SIInstrInfo::isOperandLegal(),isRegOrFI(),llvm::HexagonInstrInfo::isStoreToStackSlot(),LowerCallResults(),llvm::AArch64FrameLowering::orderFrameObjects(),llvm::SystemZELFFrameLowering::orderFrameObjects(),llvm::SIRegisterInfo::resolveFrameIndex(),setIndex(),llvm::AArch64InstrInfo::shouldClusterMemOps(),llvm::PPCInstrInfo::shouldClusterMemOps(),swapRegAndNonRegOperand(),UpdateOperandRegClass(), andllvm::SIInstrInfo::verifyInstruction().

◆ isFPImm()

bool llvm::MachineOperand::isFPImm() const
inline

isFPImm - Tests if this is a MO_FPImmediate operand.

Definition at line335 of fileMachineOperand.h.

ReferencesMO_FPImmediate.

Referenced byllvm::GISelInstProfileBuilder::addNodeIDMachineOperand(),getFPImm(),isCandidate(),llvm::HexagonInstrInfo::isConstExtended(),isSameScalarConst(),setFPImm(), andllvm::SIInstrInfo::verifyInstruction().

◆ isGlobal()

bool llvm::MachineOperand::isGlobal() const
inline

isGlobal - Tests if this is a MO_GlobalAddress operand.

Definition at line347 of fileMachineOperand.h.

ReferencesMO_GlobalAddress.

Referenced byllvm::X86FrameLowering::adjustForHiPEPrologue(),llvm::BTFDebug::beginInstruction(),createCall(),llvm::SIInstrInfo::expandPostRAPseudo(),llvm::getAddressFromInstr(),getGlobal(),getOffset(),llvm::R600InstrInfo::getSrcs(),llvm::M68kMCInstLower::GetSymbolFromOperand(),GetSymbolFromOperand(),GetSymbolRef(),INITIALIZE_PASS(),llvm::BTFDebug::InstLower(),isAnImmediateOperand(),IsCallReturnTwice(),isCandidate(),llvm::HexagonInstrInfo::isConstExtended(),llvm::SIInstrInfo::isImmOperandLegal(),llvm::SIInstrInfo::isLegalVSrcOperand(),llvm::SIInstrInfo::isOperandLegal(),isSameScalarConst(),isSignExtendedW(),llvm::PPCInstrInfo::isSignOrZeroExtended(),isSimilarDispOp(),isValidDispOp(),llvm::AVRMCInstLower::lowerSymbolOperand(),llvm::AArch64MCInstLower::lowerSymbolOperandELF(),llvm::WebAssembly::mayThrow(),llvm::LoongArchAsmPrinter::PrintAsmMemoryOperand(),llvm::AsmPrinter::PrintAsmOperand(),llvm::ARMAsmPrinter::PrintSymbolOperand(),llvm::AsmPrinter::PrintSymbolOperand(),queryCallee(),llvm::DetectRoundChange::runOnMachineFunction(),setOffset(),smallData(), andswapRegAndNonRegOperand().

◆ isIdenticalTo()

bool MachineOperand::isIdenticalTo(constMachineOperandOther) const

Returns true if this operand is identical to the specified operand except for liveness related flags (isKill, isUndef and isDead).

isIdenticalTo - Return true if this operand is identical to the specified operand.

Note that this should stay in sync with the hash_value overload below.

Definition at line319 of fileMachineOperand.cpp.

ReferencesgetBlockAddress(),getCFIIndex(),getCImm(),getFPImm(),getGlobal(),getImm(),getIndex(),getInstrRefInstrIndex(),getInstrRefOpIndex(),getIntrinsicID(),getMBB(),getMCSymbol(),getMetadata(),getMFIfAvailable(),getOffset(),getPredicate(),getReg(),getRegMask(),getRegMaskSize(),getShuffleMask(),getSubReg(),getSymbolName(),getTargetFlags(),getType(),isDef(),llvm_unreachable,MO_BlockAddress,MO_CFIIndex,MO_CImmediate,MO_ConstantPoolIndex,MO_DbgInstrRef,MO_ExternalSymbol,MO_FPImmediate,MO_FrameIndex,MO_GlobalAddress,MO_Immediate,MO_IntrinsicID,MO_JumpTableIndex,MO_MachineBasicBlock,MO_MCSymbol,MO_Metadata,MO_Predicate,MO_Register,MO_RegisterLiveOut,MO_RegisterMask,MO_ShuffleMask,MO_TargetIndex,llvm::Other, andTRI.

Referenced byllvm::X86InstrInfo::analyzeBranchPredicate(),llvm::AArch64InstrInfo::areMemAccessesTriviallyDisjoint(),llvm::LanaiInstrInfo::areMemAccessesTriviallyDisjoint(),llvm::PPCInstrInfo::areMemAccessesTriviallyDisjoint(),llvm::RISCVInstrInfo::areMemAccessesTriviallyDisjoint(),llvm::MachineInstr::isEquivalentDbgInstr(),isIdenticalOp(),llvm::MachineInstr::isIdenticalTo(),isImplicitOperandIn(),IsVPNOTEquivalent(),mayOverlapWrite(),LiveDebugValues::ResolvedDbgOp::operator==(),llvm::ARMBaseInstrInfo::produceSameValue(),llvm::AArch64InstrInfo::shouldClusterMemOps(), andllvm::SIInstrInfo::verifyInstruction().

◆ isImm()

bool llvm::MachineOperand::isImm() const
inline

isImm - Tests if this is a MO_Immediate operand.

Definition at line331 of fileMachineOperand.h.

ReferencesMO_Immediate.

Referenced byaddConstantComments(),llvm::GISelInstProfileBuilder::addNodeIDMachineOperand(),llvm::HexagonInstrInfo::analyzeCompare(),areCombinableOperations(),llvm::HexagonInstrInfo::areMemAccessesTriviallyDisjoint(),llvm::R600InstrInfo::buildSlotOfVectorInstruction(),canCompareBeNewValueJump(),llvm::RISCVInstrInfo::canFoldIntoAddrMode(),canFoldIntoCSel(),canInstrSubstituteCmpInstr(),collectInlineAsmInstrOperands(),llvm::PPCInstrInfo::combineRLWINM(),llvm::SIInstrInfo::commuteInstructionImpl(),llvm::SIInstrInfo::convertToThreeAddress(),llvm::SIRegisterInfo::eliminateFrameIndex(),llvm::WebAssemblyRegisterInfo::eliminateFrameIndex(),llvm::PPCFrameLowering::emitEpilogue(),llvm::GIMatchTableExecutor::executeMatchTable(),llvm::MachineInstr::findInlineAsmFlagIdx(),llvm::MachineInstr::findTiedOperandIdx(),llvm::SIInstrInfo::foldImmediate(),llvm::AArch64InstrInfo::genAlternativeCodeSequence(),llvm::X86InstrInfo::getAddrModeFromMemoryOp(),llvm::HexagonInstrInfo::getBaseAndOffset(),llvm::HexagonInstrInfo::getBundleNoShuf(),llvm::HexagonInstrInfo::getCompoundOpcode(),llvm::X86InstrInfo::getConstValDefinedInReg(),llvm::TargetInstrInfo::getExtractSubregInputs(),llvm::R600InstrInfo::getFlagOp(),llvm::SIRegisterInfo::getFrameIndexInstrOffset(),getImm(),getImmedFromMO(),llvm::HexagonInstrInfo::getIncrementValue(),llvm::TargetInstrInfo::getInsertSubregInputs(),llvm::AArch64InstrInfo::getMemOpBaseRegImmOfsOffsetOperand(),llvm::X86InstrInfo::getMemOperandsWithOffsetWidth(),llvm::LanaiInstrInfo::getMemOperandWithOffsetWidth(),llvm::PPCInstrInfo::getMemOperandWithOffsetWidth(),llvm::RISCVInstrInfo::getMemOperandWithOffsetWidth(),llvm::AArch64InstrInfo::getMemOperandWithOffsetWidth(),getRegImmPairPreventingCompression(),llvm::TargetInstrInfo::getRegSequenceInputs(),llvm::R600InstrInfo::getSrcs(),llvm::HexagonInstrInfo::immediateExtend(),indirectCopyToAGPR(),INITIALIZE_PASS(),llvm::PPCInstrInfo::isADDIInstrEligibleForFolding(),llvm::MipsInstrInfo::isAddImmediate(),isAddSub2RegAndConstOnePair(),isAnImmediateOperand(),isCandidate(),llvm::HexagonInstrInfo::isConstExtended(),isConvertibleLEA(),llvm::MachineInstr::isDebugOffsetImm(),isFIPlusImmOrVGPR(),isIdentityValue(),llvm::PPCInstrInfo::isImmInstrEligibleForFolding(),llvm::SIInstrInfo::isImmOperandLegal(),llvm::SIInstrInfo::isInlineConstant(),isInvariantStore(),llvm::SIInstrInfo::isLegalVSrcOperand(),llvm::HexagonInstrInfo::isLoadFromStackSlot(),isLoadStoreThatCanHandleDisplacement(),llvm::SIInstrInfo::isOperandLegal(),isRelevantAddressingMode(),isSafeToFoldImmIntoCopy(),isSameScalarConst(),llvm::isScale(),isSimilarDispOp(),llvm::HexagonInstrInfo::isStoreToStackSlot(),isValidDispOp(),llvm::SIInstrInfo::legalizeOperandsVOP2(),llvm::MachineInstr::mayFoldInlineAsmRegOp(),llvm::SIInstrInfo::moveFlatAddrToVGPR(),llvm::SIInstrInfo::moveToVALUImpl(),needReorderStoreMI(),llvm::SIInstrInfo::optimizeCompareInstr(),llvm::TargetInstrInfo::PredicateInstruction(),llvm::MachineInstr::print(),llvm::LoongArchAsmPrinter::PrintAsmMemoryOperand(),llvm::MipsAsmPrinter::PrintAsmMemoryOperand(),llvm::AMDGPUAsmPrinter::PrintAsmOperand(),llvm::MipsAsmPrinter::PrintAsmOperand(),llvm::X86AsmPrinter::PrintAsmOperand(),llvm::AsmPrinter::PrintAsmOperand(),llvm::LoongArchAsmPrinter::PrintAsmOperand(),llvm::ARMAsmPrinter::PrintAsmOperand(),llvm::recomputeVPTBlockMask(),llvm::SIRegisterInfo::resolveFrameIndex(),llvm::HexagonInstrInfo::setBundleNoShuf(),setImm(),swapRegAndNonRegOperand(),llvm::X86InstrInfo::unfoldMemoryOperand(),verifyInsExtInstruction(),llvm::SIInstrInfo::verifyInstruction(), andllvm::RISCVInstrInfo::verifyInstruction().

◆ isImplicit()

bool llvm::MachineOperand::isImplicit() const
inline

Definition at line389 of fileMachineOperand.h.

Referencesassert(), andisReg().

Referenced byllvm::GISelInstProfileBuilder::addNodeIDMachineOperand(),llvm::AggressiveAntiDepBreaker::BreakAntiDependencies(),canRenameMOP(),llvm::TargetSchedModel::computeOperandLatency(),llvm::MachineInstr::copyImplicitOps(),llvm::HexagonHazardRecognizer::EmitInstruction(),llvm::PPCInstrInfo::getInstrLatency(),getMopState(),llvm::PatchPointOpers::getNextScratchIdx(),llvm::MachineInstr::getNumExplicitDefs(),llvm::MachineInstr::getNumExplicitOperands(),llvm::HexagonInstrInfo::getOperandLatency(),llvm::getRegState(),insertSEH(),isCandidate(),llvm::WebAssembly::isChild(),llvm::SIInstrInfo::isIgnorableUse(),isValidExcessOperand(),llvm::WebAssemblyMCInstLower::lower(),llvm::lowerLoongArchMachineOperandToMCOperand(),llvm::M68kMCInstLower::LowerOperand(),LowerOperand(),llvm::MipsMCInstLower::LowerOperand(),llvm::ARMAsmPrinter::lowerOperand(),llvm::AArch64MCInstLower::lowerOperand(),llvm::CSKYMCInstLower::lowerOperand(),llvm::ARCMCInstLower::LowerOperand(),llvm::XCoreMCInstLower::LowerOperand(),llvm::XtensaAsmPrinter::lowerOperand(),llvm::LowerPPCMachineOperandToMCOperand(),llvm::MachineInstr::print(),print(),printImplicitRegisterFlag(),llvm::PPCInstrInfo::replaceInstrOperandWithImm(),llvm::tryFoldSPUpdateIntoPushPop(),llvm::SIInstrInfo::usesConstantBus(),llvm::SIInstrInfo::verifyInstruction(), andVerifyLowRegs().

◆ isInternalRead()

bool llvm::MachineOperand::isInternalRead() const
inline

Definition at line440 of fileMachineOperand.h.

Referencesassert(), andisReg().

Referenced byCreateReg(),llvm::getRegState(),print(), andreadsReg().

◆ isIntrinsicID()

bool llvm::MachineOperand::isIntrinsicID() const
inline

Definition at line361 of fileMachineOperand.h.

ReferencesMO_IntrinsicID.

Referenced byllvm::GIMatchTableExecutor::executeMatchTable(),getIntrinsicID(), andsetIntrinsicID().

◆ isJTI()

bool llvm::MachineOperand::isJTI() const
inline

isJTI - Tests if this is a MO_JumpTableIndex operand.

Definition at line345 of fileMachineOperand.h.

ReferencesMO_JumpTableIndex.

Referenced bygetIndex(),getJumpTableIndexFromAddr(),GetSymbolRef(),llvm::HexagonInstrInfo::isConstExtended(),isSimilarDispOp(),isValidDispOp(),LowerSymbolOperand(),llvm::BPFMCInstLower::LowerSymbolOperand(),llvm::LanaiMCInstLower::LowerSymbolOperand(),llvm::M68kMCInstLower::LowerSymbolOperand(),llvm::MSP430MCInstLower::LowerSymbolOperand(),lowerSymbolOperand(),llvm::AVRMCInstLower::lowerSymbolOperand(),llvm::AArch64MCInstLower::lowerSymbolOperandCOFF(),llvm::AArch64MCInstLower::lowerSymbolOperandELF(),llvm::AArch64MCInstLower::lowerSymbolOperandMachO(),setIndex(), andsmallData().

◆ isKill()

bool llvm::MachineOperand::isKill() const
inline

Definition at line399 of fileMachineOperand.h.

Referencesassert(), andisReg().

Referenced byllvm::MachineInstr::addRegisterKilled(),ChangeToRegister(),llvm::MachineInstr::clearRegisterKills(),combineFPFusedMultiply(),llvm::PPCInstrInfo::combineRLWINM(),copyFlagsToImplicitVCC(),CreateReg(),llvm::SIRegisterInfo::eliminateFrameIndex(),llvm::HexagonInstrInfo::expandPostRAPseudo(),llvm::MachineInstr::findRegisterUseOperandIdx(),llvm::PPCInstrInfo::foldFrameOffset(),llvm::SIInstrInfo::foldImmediate(),llvm::TargetInstrInfo::foldMemoryOperand(),llvm::AArch64InstrInfo::foldMemoryOperandImpl(),genAlternativeDpCodeSequence(),genFNegatedMAD(),genFusedMultiply(),genSubAdd2SubSub(),getMopState(),llvm::getRegState(),insertDivByZeroTrap(),isBackwardPropagatableCopy(),llvm::MachineInstr::isIdenticalTo(),llvm::PPCInstrInfo::isImmInstrEligibleForFolding(),isOperandKill(),llvm::PPCInstrInfo::isValidToBeChangedReg(),llvm::SIInstrInfo::legalizeOperandsVOP2(),llvm::TargetInstrInfo::lowerCopy(),preserveCondRegFlags(),print(),llvm::TargetInstrInfo::reassociateOps(),llvm::LiveVariables::removeVirtualRegistersKilled(),swapRegAndNonRegOperand(),UpdateCPSRUse(), andupdateKillStatus().

◆ isMBB()

bool llvm::MachineOperand::isMBB() const
inline

isMBB - Tests if this is a MO_MachineBasicBlock operand.

Definition at line337 of fileMachineOperand.h.

ReferencesMO_MachineBasicBlock.

Referenced byllvm::HexagonInstrInfo::analyzeBranch(),llvm::PPCInstrInfo::analyzeBranch(),llvm::XtensaInstrInfo::analyzeBranch(),llvm::HexagonInstrInfo::getDotNewPredJumpOp(),getMBB(),llvm::M68kMCInstLower::GetSymbolFromOperand(),getTargetMBB(),llvm::HexagonInstrInfo::immediateExtend(),llvm::HexagonInstrInfo::isConstExtended(),isSimilarDispOp(),isValidDispOp(),LowerSymbolOperand(),llvm::M68kMCInstLower::LowerSymbolOperand(),lowerSymbolOperand(),llvm::TargetInstrInfo::PredicateInstruction(),setMBB(), andsplitEdge().

◆ isMCSymbol()

bool llvm::MachineOperand::isMCSymbol() const
inline

Definition at line358 of fileMachineOperand.h.

ReferencesMO_MCSymbol.

Referenced byemitDirectiveRelocJalr(),llvm::MipsInstrInfo::genInstrWithNewOpc(),getMCSymbol(),getOffset(),INITIALIZE_PASS(),isSimilarDispOp(),isValidDispOp(),isValidExcessOperand(),llvm::LoongArchAsmPrinter::PrintAsmMemoryOperand(), andsetOffset().

◆ isMetadata()

bool llvm::MachineOperand::isMetadata() const
inline

isMetadata - Tests if this is a MO_Metadata operand.

Definition at line357 of fileMachineOperand.h.

ReferencesMO_Metadata.

Referenced bycollectInlineAsmInstrOperands(),getMetadata(),isValidExcessOperand(),llvm::MachineInstr::print(), andsetMetadata().

◆ isPredicate()

bool llvm::MachineOperand::isPredicate() const
inline

Definition at line362 of fileMachineOperand.h.

ReferencesMO_Predicate.

Referenced byllvm::GISelInstProfileBuilder::addNodeIDMachineOperand(),llvm::GIMatchTableExecutor::executeMatchTable(),getPredicate(), andsetPredicate().

◆ isReg()

bool llvm::MachineOperand::isReg() const
inline

isReg - Tests if this is a MO_Register operand.

Definition at line329 of fileMachineOperand.h.

ReferencesMO_Register.

Referenced byllvm::GISelInstProfileBuilder::addNodeIDMachineOperand(),llvm::MachineInstr::addOperand(),llvm::MachineInstr::addRegisterDead(),llvm::MachineInstr::addRegisterKilled(),addTargetFlag(),llvm::ARMTargetLowering::AdjustInstrPostInstrSelection(),llvm::HexagonSubtarget::adjustSchedDependency(),llvm::MachineInstr::allDefsAreDead(),llvm::MachineInstr::allImplicitDefsAreDead(),llvm::AnalyzeVirtRegInBundle(),llvm::HexagonSubtarget::BankConflictMutation::apply(),llvm::RegisterBankInfo::applyDefaultMapping(),llvm::BTFDebug::beginInstruction(),llvm::CriticalAntiDepBreaker::BreakAntiDependencies(),llvm::buildAtomicCompareExchangeInst(),llvm::buildEnqueueKernel(),llvm::BuildMI(),llvm::buildNDRange(),llvm::ScheduleDAGInstrs::buildSchedGraph(),llvm::ModuloScheduleExpanderMVE::canApply(),canCombine(),canCombineFPFusedMultiply(),llvm::HexagonInstrInfo::canExecuteInBundle(),llvm::AArch64InstrInfo::canFoldIntoAddrMode(),llvm::RISCVInstrInfo::canFoldIntoAddrMode(),llvm::HexagonPacketizerList::canPromoteToNewValueStore(),canRenameMOP(),canRenameUpToDef(),llvm::SIInstrInfo::canShrink(),ChangeToBA(),ChangeToDbgInstrRef(),ChangeToES(),ChangeToFPImmediate(),ChangeToFrameIndex(),ChangeToGA(),ChangeToImmediate(),ChangeToMCSymbol(),ChangeToRegister(),ChangeToTargetIndex(),llvm::checkVOPDRegConstraints(),llvm::MachineInstr::clearKillInfo(),llvm::MachineInstr::clearRegisterKills(),collectInlineAsmInstrOperands(),llvm::SIInstrInfo::commuteInstructionImpl(),CompressEVEXImpl(),llvm::RegBankSelect::computeMapping(),llvm::constrainSelectedInstRegOperands(),llvm::PPCInstrInfo::convertToImmediateForm(),llvm::SIInstrInfo::convertToThreeAddress(),llvm::MachineInstr::copyImplicitOps(),copyRegOperand(),createCall(),createCallWithOps(),llvm::X86InstrInfo::describeLoadedValue(),llvm::SIRegisterInfo::eliminateFrameIndex(),llvm::WebAssemblyRegisterInfo::eliminateFrameIndex(),emitIndirectDst(),llvm::HexagonHazardRecognizer::EmitInstruction(),llvm::SITargetLowering::EmitInstrWithCustomInserter(),llvm::TargetLoweringBase::emitPatchPoint(),eraseGPOpnd(),llvm::GIMatchTableExecutor::executeMatchTable(),findDeadCallerSavedReg(),findDefIdx(),findNextInsertLocation(),llvm::MachineInstr::findRegisterDefOperandIdx(),llvm::MachineInstr::findRegisterUseOperandIdx(),llvm::MachineInstr::findTiedOperandIdx(),findUseIdx(),llvm::ScheduleDAGInstrs::fixupKills(),llvm::SwingSchedulerDAG::fixupRegisterOverlaps(),llvm::SIInstrInfo::foldImmediate(),fuseInst(),llvm::getAddressFromInstr(),getArrayComponentCount(),llvm::getBlockStructInstr(),getCallTargetRegOpnd(),llvm::getConstFromIntrinsic(),getDefRegMask(),getFMAPatterns(),getFMULPatterns(),getFoldableImm(),getFPReg(),llvm::MachineInstrExpressionTrait::getHashValue(),getImmedFromMO(),getInstReadLaneMask(),llvm::PPCInstrInfo::getInstrLatency(),llvm::ARMRegisterBankInfo::getInstrMapping(),llvm::RegisterBankInfo::getInstrMappingImpl(),llvm::SIInstrInfo::getInstructionUniformity(),getMaddPatterns(),llvm::SIInstrInfo::getMemOperandsWithOffsetWidth(),llvm::HexagonInstrInfo::getMemOperandsWithOffsetWidth(),llvm::X86InstrInfo::getMemOperandsWithOffsetWidth(),llvm::LanaiInstrInfo::getMemOperandWithOffsetWidth(),llvm::PPCInstrInfo::getMemOperandWithOffsetWidth(),llvm::RISCVInstrInfo::getMemOperandWithOffsetWidth(),llvm::AArch64InstrInfo::getMemOperandWithOffsetWidth(),llvm::ReachingDefAnalysis::getMIOperand(),llvm::PatchPointOpers::getNextScratchIdx(),getNumDefTiles(),llvm::MachineInstr::getNumExplicitDefs(),llvm::MachineInstr::getNumExplicitOperands(),llvm::HexagonInstrInfo::getOperandLatency(),llvm::SIInstrInfo::getOpSize(),getPostIncrementOperand(),getReg(),llvm::MachineInstr::getRegClassConstraintEffect(),getRegOrUndef(),llvm::getRegState(),llvm::RegBankSelect::getRepairCost(),getShuffleComment(),getSubReg(),getTargetFlags(),llvm::getVRegSubRegDef(),hasLiveThroughUse(),llvm::TargetInstrInfo::hasReassociableOperands(),llvm::RISCVInstrInfo::hasReassociableOperands(),hasRegisterDependency(),llvm::MachineInstr::hasRegisterImplicitUseOperand(),hasSameBaseOpValue(),indirectCopyToAGPR(),INITIALIZE_PASS(),llvm::MachineInstr::insert(),insertSEH(),llvm::AArch64InstrInfo::isAddImmediate(),llvm::ARMBaseInstrInfo::isAddImmediate(),llvm::MipsInstrInfo::isAddImmediate(),llvm::RISCVInstrInfo::isAddImmediate(),isArithmeticBccPair(),llvm::GIMatchTableExecutor::isBaseWithConstantOffset(),isCandidate(),llvm::WebAssembly::isChild(),isConstReg(),isDead(),isDebug(),isDef(),isEarlyClobber(),isFIPlusImmOrVGPR(),isIdenticalOp(),llvm::MachineInstr::isIdenticalTo(),isImm(),llvm::PPCInstrInfo::isImmInstrEligibleForFolding(),isImplicit(),llvm::MachineInstr::isIndirectDebugValue(),llvm::SIInstrInfo::isInlineConstant(),isInternalRead(),isInvariantStore(),isKill(),isLdStSafeToCluster(),llvm::SIInstrInfo::isLegalRegOperand(),llvm::HexagonPacketizerList::isLegalToPacketizeTogether(),llvm::SIInstrInfo::isLegalToSwap(),llvm::SIInstrInfo::isLegalVSrcOperand(),isLogicalOpOnExec(),llvm::SMSchedule::isLoopCarriedDefOfUse(),isMaskOperand(),isMatchingStartStopPair(),isMMSourceRegister(),isMMThreeBitGPRegister(),llvm::GIMatchTableExecutor::isOperandImmEqual(),llvm::SIInstrInfo::isOperandLegal(),llvm::M68kInstrInfo::isPCRelRegisterOperandLegal(),isRedundantFlagInstr(),isRegInClass(),isRegOrFI(),llvm::MachineInstr::isRegTiedToDefOperand(),llvm::MachineInstr::isRegTiedToUseOperand(),isRelevantAddressingMode(),isRenamable(),IsSafeAndProfitableToMove(),isSVERegOp(),isTied(),isTileDef(),isTileRegDef(),llvm::HexagonInstrInfo::isToBeScheduledASAP(),isTwoAddrUse(),isUndef(),isUse(),isValidExcessOperand(),isVirtualRegisterOperand(),isWaitInstr(),llvm::SIInstrInfo::legalizeOperands(),llvm::SIInstrInfo::legalizeOperandsVOP2(),llvm::SIInstrInfo::legalizeOperandsVOP3(),llvm::SIInstrInfo::legalizeOpWithMove(),llvm::WebAssemblyMCInstLower::lower(),LowerCallResults(),lowerRISCVVMachineInstrToMCInst(),llvm::MIPatternMatch::operand_type_match::match(),llvm::CombinerHelper::matchConstantFPOp(),llvm::CombinerHelper::matchConstantOp(),llvm::CombinerHelper::matchEqualDefs(),llvm::CombinerHelper::matchHoistLogicOpWithSameOpcodeHands(),llvm::CombinerHelper::matchOperandIsUndef(),mergeOperations(),MIIsInTerminatorSequence(),llvm::PeelingModuloScheduleExpander::moveStageBetweenBlocks(),oneUseDominatesOtherUses(),llvm::ARMBaseInstrInfo::optimizeCompareInstr(),llvm::LanaiInstrInfo::optimizeCompareInstr(),llvm::X86InstrInfo::optimizeLoadInstr(),llvm::TargetInstrInfo::PredicateInstruction(),llvm::MachineInstr::print(),llvm::CSKYAsmPrinter::PrintAsmMemoryOperand(),llvm::LoongArchAsmPrinter::PrintAsmMemoryOperand(),llvm::ARMAsmPrinter::PrintAsmMemoryOperand(),llvm::AVRAsmPrinter::PrintAsmMemoryOperand(),llvm::MipsAsmPrinter::PrintAsmMemoryOperand(),llvm::AMDGPUAsmPrinter::PrintAsmOperand(),llvm::MipsAsmPrinter::PrintAsmOperand(),llvm::X86AsmPrinter::PrintAsmOperand(),llvm::AsmPrinter::PrintAsmOperand(),llvm::HexagonAsmPrinter::PrintAsmOperand(),llvm::SystemZAsmPrinter::PrintAsmOperand(),llvm::ARMAsmPrinter::PrintAsmOperand(),llvm::AVRAsmPrinter::PrintAsmOperand(),producesFalseLanesZero(),llvm::PPCInstrInfo::promoteInstr32To64ForElimEXTSW(),readsReg(),llvm::MachineInstr::readsWritesVirtualRegister(),TransferTracker::redefVar(),reduceDbgValsBackwardScan(),reduceDbgValsForwardScan(),removeRegisterOperands(),llvm::LiveVariables::removeVirtualRegistersKilled(),llvm::RegBankSelect::RepairingPlacement::RepairingPlacement(),rescheduleCanonically(),llvm::R600SchedStrategy::schedNode(),setImplicit(),setIsDead(),setIsDebug(),setIsDef(),setIsEarlyClobber(),setIsInternalRead(),setIsKill(),setIsRenamable(),setIsUndef(),llvm::MachineInstr::setPhysRegsDeadExcept(),setSubReg(),setTargetFlags(),llvm::AArch64InstrInfo::shouldClusterMemOps(),llvm::PPCInstrInfo::shouldClusterMemOps(),shouldUseFormStridedPseudo(),SinkingPreventsImplicitNullCheck(),llvm::MachineInstr::substituteRegister(),llvm::tryFoldSPUpdateIntoPushPop(),llvm::X86InstrInfo::unfoldMemoryOperand(),llvm::MachineInstr::untieRegOperand(),UpdateCPSRDef(),UpdateCPSRUse(),updateKillStatus(),UpdateOperandRegClass(),updateOperandRegConstraints(),UseReg(),llvm::SIInstrInfo::usesConstantBus(),llvm::RegisterBankInfo::InstructionMapping::verify(),llvm::SIInstrInfo::verifyInstruction(),llvm::RISCVInstrInfo::verifyInstruction(),VerifyLowRegs(), andllvm::MachineRegisterInfo::verifyUseList().

◆ isRegLiveOut()

bool llvm::MachineOperand::isRegLiveOut() const
inline

isRegLiveOut - Tests if this is a MO_RegisterLiveOut operand.

Definition at line355 of fileMachineOperand.h.

ReferencesMO_RegisterLiveOut.

Referenced bygetRegLiveOut().

◆ isRegMask()

bool llvm::MachineOperand::isRegMask() const
inline

isRegMask - Tests if this is a MO_RegisterMask operand.

Definition at line353 of fileMachineOperand.h.

ReferencesMO_RegisterMask.

Referenced byllvm::MachineInstr::copyImplicitOps(),llvm::MachineInstr::findRegisterDefOperandIdx(),llvm::ScheduleDAGInstrs::fixupKills(),getRegMask(),isValidExcessOperand(),llvm::ARMBaseInstrInfo::optimizeCompareInstr(),llvm::LanaiInstrInfo::optimizeCompareInstr(),llvm::MachineInstr::setPhysRegsDeadExcept(),setRegMask(), andllvm::MIRParserImpl::setupRegisterInfo().

◆ isRenamable()

bool MachineOperand::isRenamable() const

isRenamable - Returns true if this register may be renamed, i.e.

it does not generate a value that is somehow read in a way that is not represented by the Machine IR (e.g. to meet an ABI or ISA requirement). This is only valid on physical register operands. Virtual registers are assumed to always be renamable regardless of the value of this field.

Operands that are renamable can freely be changed to any other register that is a member of the register class returned by MI->getRegClassConstraint().

isRenamable can return false for several different reasons:

  • ABI constraints (since liveness is not always precisely modeled). We conservatively handle these cases by setting all physical register operands that didn’t start out as virtual regs to not be renamable. Also any physical register operands created after register allocation or whose register is changed after register allocation will not be renamable. This state is tracked in the MachineOperand::IsRenamable bit.
  • Opcode/target constraints: for opcodes that have complex register class requirements (e.g. that depend on other operands/instructions), we set hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq in the machine opcode description. Operands belonging to instructions with opcodes that are marked hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq return false fromisRenamable(). Additionally, the AllowRegisterRenaming target property prevents any operands from being marked renamable for targets that don't have detailed opcode hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq values.

Definition at line124 of fileMachineOperand.cpp.

Referencesassert(),getParent(),getReg(),llvm::MachineInstr::IgnoreBundle,isDef(),isReg(),isUse(), andMI.

Referenced bycanRenameMOP(),CreateReg(),getMopState(),llvm::getRegState(),isBackwardPropagatableCopy(),llvm::TargetInstrInfo::lowerCopy(), andprint().

◆ isShuffleMask()

bool llvm::MachineOperand::isShuffleMask() const
inline

Definition at line363 of fileMachineOperand.h.

ReferencesMO_ShuffleMask.

Referenced bygetShuffleMask().

◆ isSymbol()

bool llvm::MachineOperand::isSymbol() const
inline

isSymbol - Tests if this is a MO_ExternalSymbol operand.

Definition at line349 of fileMachineOperand.h.

ReferencesMO_ExternalSymbol.

Referenced bygetOffset(),llvm::M68kMCInstLower::GetSymbolFromOperand(),GetSymbolFromOperand(),getSymbolName(),isCandidate(),llvm::HexagonInstrInfo::isConstExtended(),isSimilarDispOp(),isValidDispOp(),llvm::AArch64MCInstLower::lowerSymbolOperandELF(),llvm::WebAssembly::mayThrow(),optimizeCall(), andsetOffset().

◆ isTargetIndex()

bool llvm::MachineOperand::isTargetIndex() const
inline

isTargetIndex - Tests if this is a MO_TargetIndex operand.

Definition at line343 of fileMachineOperand.h.

ReferencesMO_TargetIndex.

Referenced bygetIndex(),getOffset(),llvm::SIInstrInfo::isImmOperandLegal(),llvm::SIInstrInfo::isLegalVSrcOperand(),llvm::SIInstrInfo::isOperandLegal(),setIndex(), andsetOffset().

◆ isTied()

bool llvm::MachineOperand::isTied() const
inline

Definition at line450 of fileMachineOperand.h.

Referencesassert(), andisReg().

Referenced bycanRenameMOP(),ChangeToBA(),ChangeToDbgInstrRef(),ChangeToES(),ChangeToFPImmediate(),ChangeToFrameIndex(),ChangeToGA(),ChangeToImmediate(),ChangeToMCSymbol(),ChangeToTargetIndex(),llvm::TargetLoweringBase::emitPatchPoint(),llvm::MachineInstr::findTiedOperandIdx(),llvm::MachineInstr::insert(),llvm::MachineInstr::isRegTiedToDefOperand(),llvm::MachineInstr::isRegTiedToUseOperand(),isTiedToNotUndef(),lowerRISCVVMachineInstrToMCInst(),llvm::MachineInstr::print(),print(),llvm::MachineInstr::tieOperands(), andllvm::MachineInstr::untieRegOperand().

◆ isUndef()

bool llvm::MachineOperand::isUndef() const
inline

Definition at line404 of fileMachineOperand.h.

Referencesassert(), andisReg().

Referenced byllvm::MachineInstr::addRegisterKilled(),llvm::ScheduleDAGInstrs::addVRegDefDeps(),allPhiOperandsUndefined(),ChangeToRegister(),copyFlagsToImplicitVCC(),createCallWithOps(),CreateReg(),llvm::SIRegisterInfo::eliminateFrameIndex(),llvm::HexagonInstrInfo::expandPostRAPseudo(),expandSHXDROT(),findUseBetween(),llvm::AArch64InstrInfo::foldMemoryOperandImpl(),llvm::TargetInstrInfo::getExtractSubregInputs(),llvm::ARMBaseInstrInfo::getExtractSubregLikeInputs(),llvm::TargetInstrInfo::getInsertSubregInputs(),llvm::ARMBaseInstrInfo::getInsertSubregLikeInputs(),getInstReadLaneMask(),getMopState(),getRegOrUndef(),llvm::TargetInstrInfo::getRegSequenceInputs(),llvm::ARMBaseInstrInfo::getRegSequenceLikeInputs(),llvm::getRegState(),llvm::getVRegSubRegDef(),llvm::HexagonInstrInfo::insertBranch(),isTiedToNotUndef(),llvm::TargetInstrInfo::lowerCopy(),mergeOperations(),preserveCondRegFlags(),print(),readsReg(),llvm::MachineInstr::readsWritesVirtualRegister(),llvm::MachineBasicBlock::SplitCriticalEdge(),swapRegAndNonRegOperand(),UpdateCPSRDef(), andUpdateCPSRUse().

◆ isUse()

bool llvm::MachineOperand::isUse() const
inline

Definition at line379 of fileMachineOperand.h.

Referencesassert(), andisReg().

Referenced byllvm::MachineInstr::addOperand(),llvm::ScheduleDAGInstrs::addPhysRegDeps(),llvm::MachineInstr::addRegisterKilled(),llvm::HexagonSubtarget::adjustSchedDependency(),llvm::MachineInstr::allDefsAreDead(),llvm::MachineInstr::allImplicitDefsAreDead(),llvm::CriticalAntiDepBreaker::BreakAntiDependencies(),llvm::ScheduleDAGInstrs::buildSchedGraph(),llvm::MachineInstr::clearKillInfo(),llvm::MachineInstr::clearRegisterKills(),llvm::constrainOperandRegClass(),llvm::constrainSelectedInstRegOperands(),copyRegOperand(),llvm::MachineInstr::findRegisterUseOperandIdx(),llvm::MachineInstr::findTiedOperandIdx(),llvm::SwingSchedulerDAG::fixupRegisterOverlaps(),getCallTargetRegOpnd(),getInstReadLaneMask(),hasRegisterDependency(),llvm::MachineInstr::hasRegisterImplicitUseOperand(),llvm::MachineInstr::isRegTiedToDefOperand(),isRenamable(),isTwoAddrUse(),isValidRegUse(),producesFalseLanesZero(),readsReg(),llvm::MachineInstr::readsWritesVirtualRegister(),llvm::MachineInstr::tieOperands(),UpdateCPSRDef(),llvm::SIInstrInfo::usesConstantBus(), andllvm::SIInstrInfo::verifyInstruction().

◆ isValidExcessOperand()

bool llvm::MachineOperand::isValidExcessOperand() const
inline

Return true if this operand can validly be appended to an arbitrary operand list.

i.e. this behaves like an implicit operand.

Definition at line474 of fileMachineOperand.h.

ReferencesisImplicit(),isMCSymbol(),isMetadata(),isReg(), andisRegMask().

◆ print()[1/3]

void MachineOperand::print(raw_ostreamos,
constTargetRegisterInfoTRI =nullptr,
constTargetIntrinsicInfoIntrinsicInfo =nullptr 
) const

Print theMachineOperand toos.

Providing a validTRI andIntrinsicInfo results in a more target-specific printing. IfTRI andIntrinsicInfo are null, the function will try to pick it up from the parent.

Definition at line784 of fileMachineOperand.cpp.

ReferencesOS,print(), andTRI.

Referenced byllvm::operator<<(),print(), andllvm::MachineInstr::print().

◆ print()[2/3]

void MachineOperand::print(raw_ostreamos,
LLT TypeToPrint,
constTargetRegisterInfoTRI =nullptr,
constTargetIntrinsicInfoIntrinsicInfo =nullptr 
) const

Same as print(os, TRI, IntrinsicInfo), but allows to specify the low-level type to be printed the same way the full version of print(...) does it.

Definition at line789 of fileMachineOperand.cpp.

ReferencesOS,print(),TRI, andtryToGetTargetInfo().

◆ print()[3/3]

void MachineOperand::print(raw_ostreamos,
ModuleSlotTrackerMST,
LLT TypeToPrint,
std::optional<unsignedOpIdx,
bool PrintDef,
bool IsStandalone,
bool ShouldPrintRegisterTies,
unsigned TiedOperandIdx,
constTargetRegisterInfoTRI,
constTargetIntrinsicInfoIntrinsicInfo 
) const

More complex way of printing aMachineOperand.

Parameters
TypeToPrintspecifies the generic type to be printed on uses and defs. It can be determined usingMachineInstr::getTypeToPrint.
OpIdx- specifies the index of the operand in machine instruction. This will be used by target dependent MIR formatter. Could be std::nullopt if the index is unknown, e.g. called bydump().
PrintDef- whether we want to printdef on an operand which isDef. Sometimes, if the operand is printed before '=', we don't printdef.
IsStandalone- whether we want a verbose output of the MO. This prints extra information that can be easily inferred when printing the whole function, but not when printing only a fragment of it.
ShouldPrintRegisterTies- whether we want to print register ties. Sometimes they are easily determined by the instruction's descriptor (MachineInstr::hasComplexRegiterTies can determine if it's needed).
TiedOperandIdx- if we need to print register ties this needs to provide the index of the tied register. If not, it will be ignored.
TRI- provide more target-specific information to the printer. Unlike the previous function, this one will not try and get the information from it's parent.
IntrinsicInfo- same asTRI.

Definition at line800 of fileMachineOperand.cpp.

Referencesassert(),llvm::Intrinsic::getBaseName(),getBlockAddress(),getCFIIndex(),getCImm(),getFPImm(),llvm::BlockAddress::getFunction(),getGlobal(),getImm(),getIndex(),getInstrRefInstrIndex(),getInstrRefOpIndex(),getIntrinsicID(),getMBB(),getMCSymbol(),getMetadata(),getMFIfAvailable(),llvm::TargetIntrinsicInfo::getName(),getOffset(),getParent(),getPredicate(),getReg(),getRegLiveOut(),getRegMask(),getShuffleMask(),getSubReg(),getSymbolName(),getTargetIndexName(),getType(),isDead(),isDef(),isEarlyClobber(),isImplicit(),isInternalRead(),llvm::CmpInst::isIntPredicate(),isKill(),llvm::Register::isPhysical(),isRenamable(),isTied(),isUndef(),llvm::LLT::isValid(),MO_BlockAddress,MO_CFIIndex,MO_CImmediate,MO_ConstantPoolIndex,MO_DbgInstrRef,MO_ExternalSymbol,MO_FPImmediate,MO_FrameIndex,MO_GlobalAddress,MO_Immediate,MO_IntrinsicID,MO_JumpTableIndex,MO_MachineBasicBlock,MO_MCSymbol,MO_Metadata,MO_Predicate,MO_Register,MO_RegisterLiveOut,MO_RegisterMask,MO_ShuffleMask,MO_TargetIndex,MRI,Name,OS,llvm::Value::printAsOperand(),llvm::Metadata::printAsOperand(),printCFI(),printFrameIndex(),llvm::MIRFormatter::printImm(),printIRBlockReference(),llvm::printJumpTableEntryReference(),llvm::printLLVMNameWithoutPrefix(),llvm::printMBBReference(),printOperandOffset(),llvm::printReg(),llvm::printRegClassOrBank(),PrintRegMaskNumRegs,printSymbol(),printTargetFlags(),SubReg,TII, andTRI.

◆ printIRSlotNumber()

void MachineOperand::printIRSlotNumber(raw_ostreamOS,
int Slot 
)
static

Print an IRSlotNumber.

Definition at line657 of fileMachineOperand.cpp.

ReferencesOS.

Referenced byprintIRBlockReference(), andllvm::MIRFormatter::printIRValue().

◆ printOperandOffset()

void MachineOperand::printOperandOffset(raw_ostreamOS,
int64_t Offset 
)
static

Print the offset with explicit +/- signs.

Definition at line647 of fileMachineOperand.cpp.

Referencesllvm::Offset, andOS.

Referenced byprint(), andllvm::MachineMemOperand::print().

◆ printStackObjectReference()

void MachineOperand::printStackObjectReference(raw_ostreamOS,
unsigned FrameIndex,
bool IsFixed,
StringRef Name 
)
static

Print a stack object reference.

Definition at line634 of fileMachineOperand.cpp.

ReferencesName, andOS.

Referenced byprintFrameIndex(), andllvm::MIPrinter::printStackObjectReference().

◆ printSubRegIdx()

void MachineOperand::printSubRegIdx(raw_ostreamOS,
uint64_t Index,
constTargetRegisterInfoTRI 
)
static

Print a subreg index operand.

MO_Immediate operands can also be subreg idices. If it's the case, the subreg index name will be printed.MachineInstr::isOperandSubregIdx can be called to check this.

Definition at line569 of fileMachineOperand.cpp.

ReferencesOS, andTRI.

Referenced byllvm::MIPrinter::print(), andllvm::MachineInstr::print().

◆ printSymbol()

void MachineOperand::printSymbol(raw_ostreamOS,
MCSymbolSym 
)
static

Print aMCSymbol as an operand.

Definition at line630 of fileMachineOperand.cpp.

ReferencesOS, andSym.

Referenced byllvm::MIPrinter::print(),llvm::MachineInstr::print(),print(), andprintCFI().

◆ printTargetFlags()

void MachineOperand::printTargetFlags(raw_ostreamOS,
constMachineOperandOp 
)
static

Print operand target flags.

Definition at line578 of fileMachineOperand.cpp.

Referencesassert(),llvm::HexagonInstrInfo::decomposeMachineOperandsTargetFlags(),llvm::TargetSubtargetInfo::getInstrInfo(),getMFIfAvailable(),llvm::HexagonInstrInfo::getSerializableBitmaskMachineOperandTargetFlags(),llvm::MachineFunction::getSubtarget(),getTargetFlagName(),Name,OS, andTII.

Referenced byllvm::MIPrinter::print(), andprint().

◆ readsReg()

bool llvm::MachineOperand::readsReg() const
inline

readsReg - Returns true if this operand reads the previous value of its register.

A use operand with the <undef> flag set doesn't read its register. A sub-register def implicitly reads the other parts of the register being redefined unless the <undef> flag is set.

This refers to reading the register value from before the current instruction or bundle. Internal bundle reads are not included.

Definition at line467 of fileMachineOperand.h.

Referencesassert(),getSubReg(),isInternalRead(),isReg(),isUndef(), andisUse().

Referenced byllvm::AnalyzeVirtRegInBundle(),llvm::ScheduleDAGInstrs::buildSchedGraph(),findUseIdx(),llvm::ARMBaseInstrInfo::getPartialRegUpdateClearance(), andllvm::X86InstrInfo::getPartialRegUpdateClearance().

◆ setCImm()

void llvm::MachineOperand::setCImm(constConstantIntCI)
inline

Definition at line690 of fileMachineOperand.h.

Referencesassert(), andisCImm().

Referenced byllvm::LegalizerHelper::widenScalar().

◆ setFPImm()

void llvm::MachineOperand::setFPImm(constConstantFPCFP)
inline

Definition at line695 of fileMachineOperand.h.

Referencesassert(), andisFPImm().

◆ setImm()

void llvm::MachineOperand::setImm(int64_t immVal)
inline

Definition at line685 of fileMachineOperand.h.

Referencesassert(), andisImm().

Referenced byllvm::R600InstrInfo::addFlag(),llvm::SwingSchedulerDAG::applyInstrChange(),llvm::R600InstrInfo::buildSlotOfVectorInstruction(),llvm::R600InstrInfo::clearFlag(),llvm::X86InstrInfo::commuteInstructionImpl(),llvm::ARMBaseInstrInfo::commuteInstructionImpl(),llvm::SIRegisterInfo::eliminateFrameIndex(),llvm::WebAssemblyRegisterInfo::eliminateFrameIndex(),fixupCalleeSaveRestoreStackOffset(),llvm::SwingSchedulerDAG::fixupRegisterOverlaps(),fixupSEHOpcode(),llvm::PPCInstrInfo::foldFrameOffset(),foldInlineAsmMemOperand(),llvm::R600InstrInfo::insertBranch(),llvm::PPCInstrInfo::optimizeCompareInstr(),llvm::TargetInstrInfo::PredicateInstruction(),llvm::ARMBaseInstrInfo::PredicateInstruction(),llvm::SystemZInstrInfo::prepareCompareSwapOperands(),llvm::recomputeVPTBlockMask(),llvm::SIInstrInfo::reMaterialize(),llvm::SIRegisterInfo::resolveFrameIndex(),llvm::R600InstrInfo::reverseBranchCondition(),llvm::HexagonInstrInfo::setBundleNoShuf(),swapImmOperands(),llvm::SIInstrInfo::swapSourceModifiers(),updateOperandIfDifferent(), andupdateOperands().

◆ setImplicit()

void llvm::MachineOperand::setImplicit(bool Val =true)
inline

Definition at line514 of fileMachineOperand.h.

Referencesassert(), andisReg().

Referenced byllvm::X86InstrInfo::classifyLEAReg(),llvm::SIInstrInfo::insertVectorSelect(),makeImplicit(),llvm::LanaiInstrInfo::optimizeSelect(), andllvm::ARMBaseInstrInfo::optimizeSelect().

◆ setIndex()

void llvm::MachineOperand::setIndex(int Idx)
inline

Definition at line708 of fileMachineOperand.h.

Referencesassert(),Idx,isCPI(),isFI(),isJTI(), andisTargetIndex().

Referenced byChangeToFrameIndex(), andChangeToTargetIndex().

◆ setInstrRefInstrIndex()

void llvm::MachineOperand::setInstrRefInstrIndex(unsigned InstrIdx)
inline

Definition at line719 of fileMachineOperand.h.

Referencesassert(), andisDbgInstrRef().

Referenced byChangeToDbgInstrRef().

◆ setInstrRefOpIndex()

void llvm::MachineOperand::setInstrRefOpIndex(unsigned OpIdx)
inline

Definition at line723 of fileMachineOperand.h.

Referencesassert(), andisDbgInstrRef().

Referenced byChangeToDbgInstrRef().

◆ setIntrinsicID()

void llvm::MachineOperand::setIntrinsicID(Intrinsic::ID IID)
inline

Definition at line742 of fileMachineOperand.h.

Referencesassert(), andisIntrinsicID().

◆ setIsDead()

void llvm::MachineOperand::setIsDead(bool Val =true)
inline

Definition at line525 of fileMachineOperand.h.

Referencesassert(), andisReg().

Referenced byllvm::MachineInstr::addRegisterDead(),buildScratchExecCopy(),llvm::MachineInstr::clearRegisterDeads(),llvm::SIInstrInfo::convertToThreeAddress(),llvm::ARMBaseInstrInfo::convertToThreeAddress(),copyRegOperand(),llvm::SystemZInstrInfo::foldMemoryOperandImpl(),llvm::SIInstrInfo::insertScratchExecCopy(),maybeRewriteToDrop(),llvm::SIInstrInfo::optimizeCompareInstr(),llvm::X86InstrInfo::optimizeCompareInstr(),llvm::SGPRSpillBuilder::readWriteTmpVGPR(),llvm::X86FrameLowering::restoreWin32EHStackPointers(),llvm::MachineInstr::setPhysRegsDeadExcept(),llvm::X86InstrInfo::setSpecialOperandAttr(), andtransferDeadCC().

◆ setIsDebug()

void llvm::MachineOperand::setIsDebug(bool Val =true)
inline

Definition at line547 of fileMachineOperand.h.

Referencesassert(), andisReg().

Referenced byllvm::MachineInstr::addOperand().

◆ setIsDef()

void MachineOperand::setIsDef(bool Val =true)

Change a def to a use, or a use to a def.

Definition at line107 of fileMachineOperand.cpp.

Referencesassert(),getMFIfAvailable(),isDebug(),isReg(), andMRI.

Referenced byllvm::ARMTargetLowering::AdjustInstrPostInstrSelection(),llvm::RevertLoopDec(), andsetIsUse().

◆ setIsEarlyClobber()

void llvm::MachineOperand::setIsEarlyClobber(bool Val =true)
inline

Definition at line542 of fileMachineOperand.h.

Referencesassert(), andisReg().

Referenced byllvm::MachineInstr::addOperand().

◆ setIsInternalRead()

void llvm::MachineOperand::setIsInternalRead(bool Val =true)
inline

Definition at line537 of fileMachineOperand.h.

Referencesassert(), andisReg().

Referenced byllvm::TargetInstrInfo::commuteInstructionImpl().

◆ setIsKill()

void llvm::MachineOperand::setIsKill(bool Val =true)
inline

Definition at line519 of fileMachineOperand.h.

Referencesassert(),isDebug(), andisReg().

Referenced byllvm::ScheduleDAGInstrs::addPhysRegDeps(),llvm::MachineInstr::addRegisterKilled(),clearKillFlags(),llvm::MachineInstr::clearKillInfo(),llvm::MachineInstr::clearRegisterKills(),llvm::PPCInstrInfo::combineRLWINM(),llvm::TargetInstrInfo::commuteInstructionImpl(),llvm::R600InstrInfo::copyPhysReg(),copyRegOperand(),llvm::SIRegisterInfo::eliminateFrameIndex(),llvm::SIInstrInfo::foldImmediate(),indirectCopyToAGPR(),llvm::SIInstrInfo::insertBranch(),insertDivByZeroTrap(),llvm::X86InstrInfo::loadStoreTileReg(),LowerMemcpy(),LowerMemset(),MoveVPNOTBeforeFirstUser(),llvm::AArch64InstrInfo::optimizeCondBranch(),preserveCondRegFlags(),llvm::LiveVariables::removeVirtualRegistersKilled(),llvm::X86InstrInfo::unfoldMemoryOperand(), andupdateKillStatus().

◆ setIsRenamable()

void MachineOperand::setIsRenamable(bool Val =true)

Definition at line142 of fileMachineOperand.cpp.

Referencesassert(),getReg(), andisReg().

Referenced byllvm::TargetInstrInfo::commuteInstructionImpl(), andllvm::SIRegisterInfo::eliminateFrameIndex().

◆ setIsUndef()

void llvm::MachineOperand::setIsUndef(bool Val =true)
inline

Definition at line530 of fileMachineOperand.h.

Referencesassert(), andisReg().

Referenced byllvm::ScheduleDAGInstrs::addVRegDefDeps(),llvm::TargetInstrInfo::commuteInstructionImpl(),copyRegOperand(),llvm::SITargetLowering::EmitInstrWithCustomInserter(),llvm::SIInstrInfo::expandPostRAPseudo(),llvm::X86InstrInfo::expandPostRAPseudo(),llvm::AArch64InstrInfo::foldMemoryOperandImpl(),llvm::SIInstrInfo::insertBranch(),mergeOperations(),preserveCondRegFlags(),llvm::MachineInstr::setRegisterDefReadUndef(), andsubstPhysReg().

◆ setIsUse()

void llvm::MachineOperand::setIsUse(bool Val =true)
inline

Definition at line509 of fileMachineOperand.h.

ReferencessetIsDef().

◆ setMBB()

void llvm::MachineOperand::setMBB(MachineBasicBlockMBB)
inline

Definition at line728 of fileMachineOperand.h.

Referencesassert(),isMBB(), andMBB.

Referenced byllvm::CombinerHelper::applyOptBrCondByInvertingCond(),llvm::LoongArchInstrInfo::insertIndirectBranch(),llvm::AMDGPULegalizerInfo::legalizeIntrinsic(),llvm::PeelingModuloScheduleExpander::moveStageBetweenBlocks(),llvm::TargetInstrInfo::PredicateInstruction(),llvm::MachineBasicBlock::replacePhiUsesWith(),splitEdge(), andupdatePHIs().

◆ setMetadata()

void llvm::MachineOperand::setMetadata(constMDNodeMD)
inline

Definition at line714 of fileMachineOperand.h.

Referencesassert(), andisMetadata().

Referenced byllvm::salvageDebugInfoForDbgValue(), andllvm::updateDbgValueForSpill().

◆ setOffset()

void llvm::MachineOperand::setOffset(int64_t Offset)
inline

Definition at line700 of fileMachineOperand.h.

Referencesassert(),isBlockAddress(),isCPI(),isGlobal(),isMCSymbol(),isSymbol(),isTargetIndex(), andllvm::Offset.

Referenced byChangeToBA(),ChangeToES(),ChangeToGA(),ChangeToTargetIndex(), andllvm::SIInstrInfo::expandPostRAPseudo().

◆ setPredicate()

void llvm::MachineOperand::setPredicate(unsigned Predicate)
inline

Definition at line747 of fileMachineOperand.h.

Referencesassert(), andisPredicate().

Referenced byllvm::CombinerHelper::applyNotCmp().

◆ setReg()

void MachineOperand::setReg(Register Reg)

Change the register this operand corresponds to.

Definition at line61 of fileMachineOperand.cpp.

ReferencesgetMFIfAvailable(),getReg(), andMRI.

Referenced byllvm::ARMTargetLowering::AdjustInstrPostInstrSelection(),llvm::CombinerHelper::applyCombineExtendingLoads(),llvm::RegisterBankInfo::applyDefaultMapping(),llvm::SwingSchedulerDAG::applyInstrChange(),llvm::CombinerHelper::applyOptBrCondByInvertingCond(),llvm::LegalizerHelper::bitcastDst(),llvm::R600InstrInfo::buildSlotOfVectorInstruction(),castBufferRsrcArgToV4I32(),castBufferRsrcFromV4I32(),cloneInstr(),llvm::WebAssemblyDebugValueManager::cloneSink(),llvm::TargetInstrInfo::commuteInstructionImpl(),llvm::constrainOperandRegClass(),RegBankSelectHelper::constrainRegBankUse(),copyRegOperand(),copySubReg(),llvm::SIRegisterInfo::eliminateFrameIndex(),llvm::SITargetLowering::EmitInstrWithCustomInserter(),llvm::M68kInstrInfo::ExpandCCR(),llvm::M68kInstrInfo::ExpandMOVI(),ExpandMOVImmSExti8(),llvm::M68kInstrInfo::ExpandMOVSZX_RM(),llvm::M68kInstrInfo::ExpandMOVX_RR(),expandNOVLXLoad(),expandNOVLXStore(),llvm::X86InstrInfo::expandPostRAPseudo(),llvm::SwingSchedulerDAG::fixupRegisterOverlaps(),llvm::SIInstrInfo::foldImmediate(),llvm::X86InstrInfo::foldMemoryOperandImpl(),genAlternativeDpCodeSequence(),llvm::insertAssignInstr(),llvm::RISCVLegalizerInfo::legalizeCustom(),llvm::SIInstrInfo::legalizeOperands(),llvm::SIInstrInfo::legalizeOperandsFLAT(),llvm::SIInstrInfo::legalizeOperandsSMRD(),llvm::X86InstrInfo::loadStoreTileReg(),llvm::X86CallLowering::lowerCall(),llvm::AMDGPUCallLowering::lowerTailCall(),maybeRewriteToDrop(),llvm::LegalizerHelper::moreElementsVector(),llvm::LegalizerHelper::moreElementsVectorDst(),llvm::LegalizerHelper::moreElementsVectorSrc(),llvm::PeelingModuloScheduleExpander::moveStageBetweenBlocks(),llvm::SIInstrInfo::moveToVALUImpl(),llvm::LegalizerHelper::narrowScalar(),llvm::LegalizerHelper::narrowScalarDst(),llvm::LegalizerHelper::narrowScalarSrc(),llvm::PeelSingleBlockLoop(),llvm::TargetInstrInfo::PredicateInstruction(),llvm::R600InstrInfo::PredicateInstruction(),RegBankSelectHelper::reAssignRegBankOnDef(),reinsertVectorIndexAdd(),llvm::SIInstrInfo::reMaterialize(),llvm::CombinerHelper::replaceRegOpWith(),llvm::R600InstrInfo::reverseBranchCondition(),llvm::salvageDebugInfoForDbgValue(),selectCopy(),substituteSimpleCopyRegs(),substPhysReg(),substVirtReg(),llvm::WebAssemblyDebugValueManager::updateReg(),llvm::LegalizerHelper::widenScalarDst(), andllvm::LegalizerHelper::widenScalarSrc().

◆ setRegMask()

void llvm::MachineOperand::setRegMask(constuint32_tRegMaskPtr)
inline

Sets value of register mask operand referencing Mask.

The operand does not take ownership of the memory referenced by Mask, it must remain valid for the lifetime of the operand. SeeCreateRegMask().Any physreg with a 0 bit in the mask is clobbered by the instruction.

Definition at line737 of fileMachineOperand.h.

Referencesassert(), andisRegMask().

◆ setSubReg()

void llvm::MachineOperand::setSubReg(unsigned subReg)
inline

Definition at line490 of fileMachineOperand.h.

Referencesassert(), andisReg().

Referenced byllvm::TargetInstrInfo::commuteInstructionImpl(),copyRegOperand(),llvm::SIInstrInfo::foldImmediate(),llvm::AArch64InstrInfo::foldMemoryOperandImpl(),llvm::X86InstrInfo::foldMemoryOperandImpl(),INITIALIZE_PASS(),insertDivByZeroTrap(),llvm::SIInstrInfo::legalizeOperandsVOP2(),llvm::AArch64InstrInfo::optimizeCondBranch(),llvm::SIInstrInfo::reMaterialize(),substPhysReg(),substVirtReg(), andswapRegAndNonRegOperand().

◆ setTargetFlags()

void llvm::MachineOperand::setTargetFlags(unsigned F)
inline

Definition at line229 of fileMachineOperand.h.

Referencesassert(),F, andisReg().

Referenced byChangeToBA(),ChangeToDbgInstrRef(),ChangeToES(),ChangeToFPImmediate(),ChangeToFrameIndex(),ChangeToGA(),ChangeToImmediate(),ChangeToMCSymbol(),ChangeToTargetIndex(),llvm::MipsCallLowering::lowerCall(),swapImmOperands(), andswapRegAndNonRegOperand().

◆ substPhysReg()

void MachineOperand::substPhysReg(MCRegister Reg,
constTargetRegisterInfoTRI 
)

substPhysReg - Substitute the current register with the physical register Reg, taking any existing SubReg into account.

For instance, substPhysReg(eax) will change reg1024:sub_8bit to al.

Definition at line93 of fileMachineOperand.cpp.

Referencesassert(),getSubReg(),isDef(),setIsUndef(),setReg(),setSubReg(), andTRI.

Referenced byllvm::MachineInstr::substituteRegister().

◆ substVirtReg()

void MachineOperand::substVirtReg(Register Reg,
unsigned SubIdx,
constTargetRegisterInfoTRI 
)

substVirtReg - Substitute the current register with the virtual subregister Reg:SubReg.

Take any existing SubReg index into account, usingTargetRegisterInfo to compose the subreg indices if necessary. Reg must be a virtual register, SubIdx can be 0.

Definition at line83 of fileMachineOperand.cpp.

Referencesassert(),getSubReg(),setReg(),setSubReg(), andTRI.

Referenced byllvm::MachineInstr::substituteRegister().

Friends And Related Function Documentation

◆ DenseMapInfo< MachineOperand >

friend structDenseMapInfo<MachineOperand >
friend

Definition at line997 of fileMachineOperand.h.

◆ hash_value

hash_code hash_value(constMachineOperandMO)
friend

MachineOperand hash_value overload.

Note that this includes the same information in the hash that isIdenticalTo uses for comparison. It is thus suited for use in hash tables which use that function for equality comparisons only. This must stay exactly in sync with isIdenticalTo above.

◆ MachineInstr

friend classMachineInstr
friend

Definition at line991 of fileMachineOperand.h.

◆ MachineRegisterInfo

friend classMachineRegisterInfo
friend

Definition at line992 of fileMachineOperand.h.

Member Data Documentation

◆ OffsetLo

unsigned llvm::MachineOperand::OffsetLo

Definition at line160 of fileMachineOperand.h.

◆ RegNo

unsigned llvm::MachineOperand::RegNo

Definition at line159 of fileMachineOperand.h.


The documentation for this class was generated from the following files:

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