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1//===-- XCoreInstrInfo.cpp - XCore Instruction Information ----------------===//

2//

3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.

4// See https://llvm.org/LICENSE.txt for license information.

5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception

6//

7//===----------------------------------------------------------------------===//

8//

9// This file contains the XCore implementation of the TargetInstrInfo class.

10//

11//===----------------------------------------------------------------------===//

13#include "XCoreInstrInfo.h"

14#include "XCore.h"

15#include "llvm/CodeGen/MachineConstantPool.h"

16#include "llvm/CodeGen/MachineFrameInfo.h"

17#include "llvm/CodeGen/MachineInstrBuilder.h"

18#include "llvm/CodeGen/MachineMemOperand.h"

19#include "llvm/IR/Constants.h"

20#include "llvm/IR/Function.h"

21#include "llvm/MC/MCContext.h"

22#include "llvm/Support/ErrorHandling.h"

24using namespacellvm;

26#define GET_INSTRINFO_CTOR_DTOR

27#include "XCoreGenInstrInfo.inc"

29namespacellvm {

30namespaceXCore {

32// XCore Condition Codes

33enumCondCode {

34COND_TRUE,

35COND_FALSE,

36COND_INVALID

37 };

38}

39}

41// Pin the vtable to this file.

42void XCoreInstrInfo::anchor() {}

44XCoreInstrInfo::XCoreInstrInfo()

45 :XCoreGenInstrInfo(XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP),

46 RI() {

47}

49staticboolisZeroImm(constMachineOperand &op) {

50returnop.isImm() &&op.getImm() == 0;

51}

53/// isLoadFromStackSlot - If the specified machine instruction is a direct

54/// load from a stack slot, return the virtual or physical register number of

55/// the destination along with the FrameIndex of the loaded stack slot. If

56/// not, return 0. This predicate must return 0 if the instruction has

57/// any side effects other than loading from the stack slot.

58Register XCoreInstrInfo::isLoadFromStackSlot(constMachineInstr &MI,

59int &FrameIndex) const{

60int Opcode =MI.getOpcode();

61if (Opcode == XCore::LDWFI)

62 {

63if ((MI.getOperand(1).isFI()) &&// is a stack slot

64 (MI.getOperand(2).isImm()) &&// the imm is zero

65 (isZeroImm(MI.getOperand(2)))) {

66 FrameIndex =MI.getOperand(1).getIndex();

67returnMI.getOperand(0).getReg();

68 }

69 }

70return 0;

71}

73 /// isStoreToStackSlot - If the specified machine instruction is a direct

74 /// store to a stack slot, return the virtual or physical register number of

75 /// the source reg along with the FrameIndex of the loaded stack slot. If

76 /// not, return 0. This predicate must return 0 if the instruction has

77 /// any side effects other than storing to the stack slot.

78Register XCoreInstrInfo::isStoreToStackSlot(constMachineInstr &MI,

79int &FrameIndex) const{

80int Opcode =MI.getOpcode();

81if (Opcode == XCore::STWFI)

82 {

83if ((MI.getOperand(1).isFI()) &&// is a stack slot

84 (MI.getOperand(2).isImm()) &&// the imm is zero

85 (isZeroImm(MI.getOperand(2)))) {

86 FrameIndex =MI.getOperand(1).getIndex();

87returnMI.getOperand(0).getReg();

88 }

89 }

90return 0;

91}

93//===----------------------------------------------------------------------===//

94// Branch Analysis

95//===----------------------------------------------------------------------===//

97staticinlineboolIsBRU(unsigned BrOpc) {

98return BrOpc == XCore::BRFU_u6

99 || BrOpc == XCore::BRFU_lu6

100 || BrOpc == XCore::BRBU_u6

101 || BrOpc == XCore::BRBU_lu6;

102}

103

104staticinlineboolIsBRT(unsigned BrOpc) {

105return BrOpc == XCore::BRFT_ru6

106 || BrOpc == XCore::BRFT_lru6

107 || BrOpc == XCore::BRBT_ru6

108 || BrOpc == XCore::BRBT_lru6;

109}

110

111staticinlineboolIsBRF(unsigned BrOpc) {

112return BrOpc == XCore::BRFF_ru6

113 || BrOpc == XCore::BRFF_lru6

114 || BrOpc == XCore::BRBF_ru6

115 || BrOpc == XCore::BRBF_lru6;

116}

117

118staticinlineboolIsCondBranch(unsigned BrOpc) {

119returnIsBRF(BrOpc) ||IsBRT(BrOpc);

120}

121

122staticinlineboolIsBR_JT(unsigned BrOpc) {

123return BrOpc == XCore::BR_JT

124 || BrOpc == XCore::BR_JT32;

125}

126

127/// GetCondFromBranchOpc - Return the XCore CC that matches

128/// the correspondent Branch instruction opcode.

129staticXCore::CondCode GetCondFromBranchOpc(unsigned BrOpc)

130{

131if (IsBRT(BrOpc)) {

132returnXCore::COND_TRUE;

133 }elseif (IsBRF(BrOpc)) {

134returnXCore::COND_FALSE;

135 }else {

136returnXCore::COND_INVALID;

137 }

138}

139

140/// GetCondBranchFromCond - Return the Branch instruction

141/// opcode that matches the cc.

142staticinlineunsignedGetCondBranchFromCond(XCore::CondCode CC)

143{

144switch (CC) {

145default:llvm_unreachable("Illegal condition code!");

146caseXCore::COND_TRUE :return XCore::BRFT_lru6;

147caseXCore::COND_FALSE :return XCore::BRFF_lru6;

148 }

149}

150

151/// GetOppositeBranchCondition - Return the inverse of the specified

152/// condition, e.g. turning COND_E to COND_NE.

153staticinlineXCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC)

154{

155switch (CC) {

156default:llvm_unreachable("Illegal condition code!");

157caseXCore::COND_TRUE :returnXCore::COND_FALSE;

158caseXCore::COND_FALSE :returnXCore::COND_TRUE;

159 }

160}

161

162/// analyzeBranch - Analyze the branching code at the end of MBB, returning

163/// true if it cannot be understood (e.g. it's a switch dispatch or isn't

164/// implemented for a target). Upon success, this returns false and returns

165/// with the following information in various cases:

166///

167/// 1. If this block ends with no branches (it just falls through to its succ)

168/// just return false, leaving TBB/FBB null.

169/// 2. If this block ends with only an unconditional branch, it sets TBB to be

170/// the destination block.

171/// 3. If this block ends with an conditional branch and it falls through to

172/// an successor block, it sets TBB to be the branch destination block and a

173/// list of operands that evaluate the condition. These

174/// operands can be passed to other TargetInstrInfo methods to create new

175/// branches.

176/// 4. If this block ends with an conditional branch and an unconditional

177/// block, it returns the 'true' destination in TBB, the 'false' destination

178/// in FBB, and a list of operands that evaluate the condition. These

179/// operands can be passed to other TargetInstrInfo methods to create new

180/// branches.

181///

182/// Note that removeBranch and insertBranch must be implemented to support

183/// cases where this method returns success.

184///

185boolXCoreInstrInfo::analyzeBranch(MachineBasicBlock &MBB,

186MachineBasicBlock *&TBB,

187MachineBasicBlock *&FBB,

188SmallVectorImpl<MachineOperand> &Cond,

189bool AllowModify) const{

190// If the block has no terminators, it just falls into the block after it.

191MachineBasicBlock::iterator I =MBB.getLastNonDebugInstr();

192if (I ==MBB.end())

193returnfalse;

194

195if (!isUnpredicatedTerminator(*I))

196returnfalse;

197

198// Get the last instruction in the block.

199MachineInstr *LastInst = &*I;

200

201// If there is only one terminator instruction, process it.

202if (I ==MBB.begin() || !isUnpredicatedTerminator(*--I)) {

203if (IsBRU(LastInst->getOpcode())) {

204TBB = LastInst->getOperand(0).getMBB();

205returnfalse;

206 }

207

208XCore::CondCode BranchCode =GetCondFromBranchOpc(LastInst->getOpcode());

209if (BranchCode ==XCore::COND_INVALID)

210returntrue;// Can't handle indirect branch.

211

212// Conditional branch

213// Block ends with fall-through condbranch.

214

215TBB = LastInst->getOperand(1).getMBB();

216Cond.push_back(MachineOperand::CreateImm(BranchCode));

217Cond.push_back(LastInst->getOperand(0));

218returnfalse;

219 }

220

221// Get the instruction before it if it's a terminator.

222MachineInstr *SecondLastInst = &*I;

223

224// If there are three terminators, we don't know what sort of block this is.

225if (SecondLastInst &&I !=MBB.begin() && isUnpredicatedTerminator(*--I))

226returntrue;

227

228unsigned SecondLastOpc = SecondLastInst->getOpcode();

229XCore::CondCode BranchCode =GetCondFromBranchOpc(SecondLastOpc);

230

231// If the block ends with conditional branch followed by unconditional,

232// handle it.

233if (BranchCode !=XCore::COND_INVALID

234 &&IsBRU(LastInst->getOpcode())) {

235

236TBB = SecondLastInst->getOperand(1).getMBB();

237Cond.push_back(MachineOperand::CreateImm(BranchCode));

238Cond.push_back(SecondLastInst->getOperand(0));

239

240 FBB = LastInst->getOperand(0).getMBB();

241returnfalse;

242 }

243

244// If the block ends with two unconditional branches, handle it. The second

245// one is not executed, so remove it.

246if (IsBRU(SecondLastInst->getOpcode()) &&

247IsBRU(LastInst->getOpcode())) {

248TBB = SecondLastInst->getOperand(0).getMBB();

249I = LastInst;

250if (AllowModify)

251I->eraseFromParent();

252returnfalse;

253 }

254

255// Likewise if it ends with a branch table followed by an unconditional branch.

256if (IsBR_JT(SecondLastInst->getOpcode()) &&IsBRU(LastInst->getOpcode())) {

257I = LastInst;

258if (AllowModify)

259I->eraseFromParent();

260returntrue;

261 }

262

263// Otherwise, can't handle this.

264returntrue;

265}

266

267unsignedXCoreInstrInfo::insertBranch(MachineBasicBlock &MBB,

268MachineBasicBlock *TBB,

269MachineBasicBlock *FBB,

270ArrayRef<MachineOperand>Cond,

271constDebugLoc &DL,

272int *BytesAdded) const{

273// Shouldn't be a fall through.

274assert(TBB &&"insertBranch must not be told to insert a fallthrough");

275assert((Cond.size() == 2 ||Cond.size() == 0) &&

276"Unexpected number of components!");

277assert(!BytesAdded &&"code size not handled");

278

279if (!FBB) {// One way branch.

280if (Cond.empty()) {

281// Unconditional branch

282BuildMI(&MBB,DL,get(XCore::BRFU_lu6)).addMBB(TBB);

283 }else {

284// Conditional branch.

285unsigned Opc =GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());

286BuildMI(&MBB,DL,get(Opc)).addReg(Cond[1].getReg())

287 .addMBB(TBB);

288 }

289return 1;

290 }

291

292// Two-way Conditional branch.

293assert(Cond.size() == 2 &&"Unexpected number of components!");

294unsigned Opc =GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());

295BuildMI(&MBB,DL,get(Opc)).addReg(Cond[1].getReg())

296 .addMBB(TBB);

297BuildMI(&MBB,DL,get(XCore::BRFU_lu6)).addMBB(FBB);

298return 2;

299}

300

301unsigned

302XCoreInstrInfo::removeBranch(MachineBasicBlock &MBB,int *BytesRemoved) const{

303assert(!BytesRemoved &&"code size not handled");

304

305MachineBasicBlock::iterator I =MBB.getLastNonDebugInstr();

306if (I ==MBB.end())

307return 0;

308

309if (!IsBRU(I->getOpcode()) && !IsCondBranch(I->getOpcode()))

310return 0;

311

312// Remove the branch.

313I->eraseFromParent();

314

315I =MBB.end();

316

317if (I ==MBB.begin())return 1;

318 --I;

319if (!IsCondBranch(I->getOpcode()))

320return 1;

321

322// Remove the branch.

323I->eraseFromParent();

324return 2;

325}

326

327voidXCoreInstrInfo::copyPhysReg(MachineBasicBlock &MBB,

328MachineBasicBlock::iterator I,

329constDebugLoc &DL,MCRegister DestReg,

330MCRegister SrcReg,bool KillSrc,

331bool RenamableDest,bool RenamableSrc) const{

332bool GRDest = XCore::GRRegsRegClass.contains(DestReg);

333bool GRSrc = XCore::GRRegsRegClass.contains(SrcReg);

334

335if (GRDest && GRSrc) {

336BuildMI(MBB,I,DL,get(XCore::ADD_2rus), DestReg)

337 .addReg(SrcReg,getKillRegState(KillSrc))

338 .addImm(0);

339return;

340 }

341

342if (GRDest && SrcReg == XCore::SP) {

343BuildMI(MBB,I,DL,get(XCore::LDAWSP_ru6), DestReg).addImm(0);

344return;

345 }

346

347if (DestReg == XCore::SP && GRSrc) {

348BuildMI(MBB,I,DL,get(XCore::SETSP_1r))

349 .addReg(SrcReg,getKillRegState(KillSrc));

350return;

351 }

352llvm_unreachable("Impossible reg-to-reg copy");

353}

354

355voidXCoreInstrInfo::storeRegToStackSlot(

356MachineBasicBlock &MBB,MachineBasicBlock::iterator I,Register SrcReg,

357bool isKill,int FrameIndex,constTargetRegisterClass *RC,

358constTargetRegisterInfo *TRI,Register VReg,

359MachineInstr::MIFlag Flags) const{

360DebugLoc DL;

361if (I !=MBB.end() && !I->isDebugInstr())

362DL =I->getDebugLoc();

363MachineFunction *MF =MBB.getParent();

364constMachineFrameInfo &MFI = MF->getFrameInfo();

365MachineMemOperand *MMO = MF->getMachineMemOperand(

366MachinePointerInfo::getFixedStack(*MF, FrameIndex),

367MachineMemOperand::MOStore, MFI.getObjectSize(FrameIndex),

368 MFI.getObjectAlign(FrameIndex));

369BuildMI(MBB,I,DL,get(XCore::STWFI))

370 .addReg(SrcReg,getKillRegState(isKill))

371 .addFrameIndex(FrameIndex)

372 .addImm(0)

373 .addMemOperand(MMO);

374}

375

376voidXCoreInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,

377MachineBasicBlock::iterator I,

378Register DestReg,int FrameIndex,

379constTargetRegisterClass *RC,

380constTargetRegisterInfo *TRI,

381Register VReg,

382MachineInstr::MIFlag Flags) const{

383DebugLoc DL;

384if (I !=MBB.end() && !I->isDebugInstr())

385DL =I->getDebugLoc();

386MachineFunction *MF =MBB.getParent();

387constMachineFrameInfo &MFI = MF->getFrameInfo();

388MachineMemOperand *MMO = MF->getMachineMemOperand(

389MachinePointerInfo::getFixedStack(*MF, FrameIndex),

390MachineMemOperand::MOLoad, MFI.getObjectSize(FrameIndex),

391 MFI.getObjectAlign(FrameIndex));

392BuildMI(MBB,I,DL,get(XCore::LDWFI), DestReg)

393 .addFrameIndex(FrameIndex)

394 .addImm(0)

395 .addMemOperand(MMO);

396}

397

398boolXCoreInstrInfo::

399reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const{

400assert((Cond.size() == 2) &&

401"Invalid XCore branch condition!");

402Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Cond[0].getImm()));

403returnfalse;

404}

405

406staticinlineboolisImmU6(unsigned val) {

407return val < (1 << 6);

408}

409

410staticinlineboolisImmU16(unsigned val) {

411return val < (1 << 16);

412}

413

414staticboolisImmMskBitp(unsigned val) {

415if (!isMask_32(val)) {

416returnfalse;

417 }

418intN =llvm::bit_width(val);

419return (N >= 1 &&N <= 8) ||N == 16 ||N == 24 ||N == 32;

420}

421

422MachineBasicBlock::iterator XCoreInstrInfo::loadImmediate(

423MachineBasicBlock &MBB,

424MachineBasicBlock::iterator MI,

425unsigned Reg,uint64_t Value) const{

426DebugLoc dl;

427if (MI !=MBB.end() && !MI->isDebugInstr())

428 dl =MI->getDebugLoc();

429if (isImmMskBitp(Value)) {

430intN =llvm::bit_width(Value);

431returnBuildMI(MBB,MI, dl,get(XCore::MKMSK_rus), Reg)

432 .addImm(N)

433 .getInstr();

434 }

435if (isImmU16(Value)) {

436int Opcode =isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6;

437returnBuildMI(MBB,MI, dl,get(Opcode), Reg).addImm(Value).getInstr();

438 }

439MachineConstantPool *ConstantPool =MBB.getParent()->getConstantPool();

440constConstant *C = ConstantInt::get(

441Type::getInt32Ty(MBB.getParent()->getFunction().getContext()),Value);

442unsignedIdx =ConstantPool->getConstantPoolIndex(C,Align(4));

443returnBuildMI(MBB,MI, dl,get(XCore::LDWCP_lru6), Reg)

444 .addConstantPoolIndex(Idx)

445 .getInstr();

446}

isZeroImm

static bool isZeroImm(const MachineOperand &Op)

Definition:ARCInstrInfo.cpp:49

MBB

MachineBasicBlock & MBB

Definition:ARMSLSHardening.cpp:71

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

Definition:ARMSLSHardening.cpp:73

Constants.h

This file contains the declarations for the subclasses of Constant, which represent the different fla...

Idx

Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx

Definition:DeadArgumentElimination.cpp:353

#define op(i)

IRTranslator LLVM IR MI

Definition:IRTranslator.cpp:112

Function.h

MCContext.h

#define I(x, y, z)

Definition:MD5.cpp:58

MachineConstantPool.h

This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...

MachineFrameInfo.h

MachineInstrBuilder.h

MachineMemOperand.h

TRI

unsigned const TargetRegisterInfo * TRI

Definition:MachineSink.cpp:2029

getReg

static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)

Definition:MipsDisassembler.cpp:520

TBB

const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB

Definition:RISCVRedundantCopyElimination.cpp:76

Cond

const SmallVectorImpl< MachineOperand > & Cond

Definition:RISCVRedundantCopyElimination.cpp:75

auto CC

Definition:RISCVRedundantCopyElimination.cpp:79

assert

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

GetOppositeBranchCondition

static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC)

Definition:SparcInstrInfo.cpp:82

isImmU16

static bool isImmU16(unsigned val)

Definition:XCoreFrameLowering.cpp:40

isImmU6

static bool isImmU6(unsigned val)

Definition:XCoreFrameLowering.cpp:36

GetCondFromBranchOpc

static XCore::CondCode GetCondFromBranchOpc(unsigned BrOpc)

GetCondFromBranchOpc - Return the XCore CC that matches the correspondent Branch instruction opcode.

Definition:XCoreInstrInfo.cpp:129

IsBRU

static bool IsBRU(unsigned BrOpc)

Definition:XCoreInstrInfo.cpp:97

IsBR_JT

static bool IsBR_JT(unsigned BrOpc)

Definition:XCoreInstrInfo.cpp:122

isImmMskBitp

static bool isImmMskBitp(unsigned val)

Definition:XCoreInstrInfo.cpp:414

IsBRT

static bool IsBRT(unsigned BrOpc)

Definition:XCoreInstrInfo.cpp:104

IsBRF

static bool IsBRF(unsigned BrOpc)

Definition:XCoreInstrInfo.cpp:111

IsCondBranch

static bool IsCondBranch(unsigned BrOpc)

Definition:XCoreInstrInfo.cpp:118

GetCondBranchFromCond

static unsigned GetCondBranchFromCond(XCore::CondCode CC)

GetCondBranchFromCond - Return the Branch instruction opcode that matches the cc.

Definition:XCoreInstrInfo.cpp:142

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

Definition:ArrayRef.h:41

llvm::ConstantPool

Definition:ConstantPools.h:43

llvm::Constant

This is an important base class in LLVM.

Definition:Constant.h:42

llvm::DebugLoc

A debug info location.

Definition:DebugLoc.h:33

llvm::Function::getContext

LLVMContext & getContext() const

getContext - Return a reference to the LLVMContext associated with this function.

Definition:Function.cpp:369

llvm::MCRegister

Wrapper class representing physical registers. Should be passed by value.

Definition:MCRegister.h:33

llvm::MachineBasicBlock

Definition:MachineBasicBlock.h:125

llvm::MachineBasicBlock::begin

iterator begin()

Definition:MachineBasicBlock.h:355

llvm::MachineBasicBlock::getLastNonDebugInstr

iterator getLastNonDebugInstr(bool SkipPseudoOp=true)

Returns an iterator to the last non-debug instruction in the basic block, or end().

Definition:MachineBasicBlock.cpp:273

llvm::MachineBasicBlock::end

iterator end()

Definition:MachineBasicBlock.h:357

llvm::MachineBasicBlock::getParent

const MachineFunction * getParent() const

Return the MachineFunction containing this basic block.

Definition:MachineBasicBlock.h:311

llvm::MachineConstantPool

The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...

Definition:MachineConstantPool.h:117

llvm::MachineFrameInfo

The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.

Definition:MachineFrameInfo.h:106

llvm::MachineFrameInfo::getObjectAlign

Align getObjectAlign(int ObjectIdx) const

Return the alignment of the specified stack object.

Definition:MachineFrameInfo.h:486

llvm::MachineFrameInfo::getObjectSize

int64_t getObjectSize(int ObjectIdx) const

Return the size of the specified object.

Definition:MachineFrameInfo.h:472

llvm::MachineFunction

Definition:MachineFunction.h:267

llvm::MachineFunction::getMachineMemOperand

MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)

getMachineMemOperand - Allocate a new MachineMemOperand.

Definition:MachineFunction.cpp:536

llvm::MachineFunction::getFrameInfo

MachineFrameInfo & getFrameInfo()

getFrameInfo - Return the frame info object for the current function.

Definition:MachineFunction.h:749

llvm::MachineFunction::getFunction

Function & getFunction()

Return the LLVM function that this machine code represents.

Definition:MachineFunction.h:704

llvm::MachineFunction::getConstantPool

MachineConstantPool * getConstantPool()

getConstantPool - Return the constant pool object for the current function.

Definition:MachineFunction.h:765

llvm::MachineInstrBuilder::addImm

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

Definition:MachineInstrBuilder.h:133

llvm::MachineInstrBuilder::addFrameIndex

const MachineInstrBuilder & addFrameIndex(int Idx) const

Definition:MachineInstrBuilder.h:154

llvm::MachineInstrBuilder::addConstantPoolIndex

const MachineInstrBuilder & addConstantPoolIndex(unsigned Idx, int Offset=0, unsigned TargetFlags=0) const

Definition:MachineInstrBuilder.h:160

llvm::MachineInstrBuilder::addReg

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

Definition:MachineInstrBuilder.h:99

llvm::MachineInstrBuilder::addMBB

const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const

Definition:MachineInstrBuilder.h:148

llvm::MachineInstrBuilder::addMemOperand

const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const

Definition:MachineInstrBuilder.h:204

llvm::MachineInstrBuilder::getInstr

MachineInstr * getInstr() const

If conversion operators fail, use this method to get the MachineInstr explicitly.

Definition:MachineInstrBuilder.h:91

llvm::MachineInstrBundleIterator< MachineInstr >

llvm::MachineInstr

Representation of each machine instruction.

Definition:MachineInstr.h:71

llvm::MachineInstr::getOpcode

unsigned getOpcode() const

Returns the opcode of this MachineInstr.

Definition:MachineInstr.h:577

llvm::MachineInstr::MIFlag

MIFlag

Definition:MachineInstr.h:85

llvm::MachineInstr::getOperand

const MachineOperand & getOperand(unsigned i) const

Definition:MachineInstr.h:587

llvm::MachineMemOperand

A description of a memory reference used in the backend.

Definition:MachineMemOperand.h:129

llvm::MachineMemOperand::MOLoad

@ MOLoad

The memory access reads data.

Definition:MachineMemOperand.h:136

llvm::MachineMemOperand::MOStore

@ MOStore

The memory access writes data.

Definition:MachineMemOperand.h:138

llvm::MachineOperand

MachineOperand class - Representation of each machine instruction operand.

Definition:MachineOperand.h:48

llvm::MachineOperand::getMBB

MachineBasicBlock * getMBB() const

Definition:MachineOperand.h:571

llvm::MachineOperand::CreateImm

static MachineOperand CreateImm(int64_t Val)

Definition:MachineOperand.h:820

llvm::Register

Wrapper class representing virtual and physical registers.

Definition:Register.h:19

llvm::SmallVectorImpl

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

Definition:SmallVector.h:573

llvm::TargetRegisterClass

Definition:TargetRegisterInfo.h:44

llvm::TargetRegisterInfo

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

Definition:TargetRegisterInfo.h:235

llvm::Type::getInt32Ty

static IntegerType * getInt32Ty(LLVMContext &C)

llvm::Value

LLVM Value Representation.

Definition:Value.h:74

llvm::XCoreInstrInfo::analyzeBranch

bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override

analyzeBranch - Analyze the branching code at the end of MBB, returning true if it cannot be understo...

Definition:XCoreInstrInfo.cpp:185

llvm::XCoreInstrInfo::loadImmediate

MachineBasicBlock::iterator loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Reg, uint64_t Value) const

Definition:XCoreInstrInfo.cpp:422

llvm::XCoreInstrInfo::reverseBranchCondition

bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override

Definition:XCoreInstrInfo.cpp:399

llvm::XCoreInstrInfo::loadRegFromStackSlot

void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override

Definition:XCoreInstrInfo.cpp:376

llvm::XCoreInstrInfo::isLoadFromStackSlot

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot,...

Definition:XCoreInstrInfo.cpp:58

llvm::XCoreInstrInfo::isStoreToStackSlot

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot,...

Definition:XCoreInstrInfo.cpp:78

llvm::XCoreInstrInfo::storeRegToStackSlot

void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override

Definition:XCoreInstrInfo.cpp:355

llvm::XCoreInstrInfo::removeBranch

unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override

Definition:XCoreInstrInfo.cpp:302

llvm::XCoreInstrInfo::XCoreInstrInfo

XCoreInstrInfo()

Definition:XCoreInstrInfo.cpp:44

llvm::XCoreInstrInfo::insertBranch

unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override

Definition:XCoreInstrInfo.cpp:267

llvm::XCoreInstrInfo::copyPhysReg

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override

Definition:XCoreInstrInfo.cpp:327

uint64_t

ErrorHandling.h

llvm_unreachable

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

Definition:ErrorHandling.h:143

llvm::CallingConv::C

@ C

The default llvm calling convention, compatible with C.

Definition:CallingConv.h:34

llvm::XCore::CondCode