1//===-- WebAssemblyRegStackify.cpp - Register Stackification --------------===// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7//===----------------------------------------------------------------------===// 10/// This file implements a register stacking pass. 12/// This pass reorders instructions to put register uses and defs in an order 13/// such that they form single-use expression trees. Registers fitting this form 14/// are then marked as "stackified", meaning references to them are replaced by 15/// "push" and "pop" from the value stack. 17/// This is primarily a code size optimization, since temporary values on the 18/// value stack don't need to be named. 20//===----------------------------------------------------------------------===// 40#define DEBUG_TYPE "wasm-reg-stackify" 45return"WebAssembly Register Stackify";
63staticcharID;
// Pass identification, replacement for typeid 66}
// end anonymous namespace 68char WebAssemblyRegStackify::ID = 0;
70"Reorder instructions to use the WebAssembly value stack",
74returnnew WebAssemblyRegStackify();
77// Decorate the given instruction with implicit operands that enforce the 78// expression stack ordering constraints for an instruction which is on 79// the expression stack. 81// Write the opaque VALUE_STACK register. 82if (!
MI->definesRegister(WebAssembly::VALUE_STACK,
/*TRI=*/nullptr))
87// Also read the opaque VALUE_STACK register. 88if (!
MI->readsRegister(WebAssembly::VALUE_STACK,
/*TRI=*/nullptr))
94// Convert an IMPLICIT_DEF instruction into an instruction which defines 95// a constant zero value. 101assert(
MI->getOpcode() == TargetOpcode::IMPLICIT_DEF);
103constauto *RegClass =
MRI.getRegClass(
MI->getOperand(0).getReg());
104if (RegClass == &WebAssembly::I32RegClass) {
105MI->setDesc(
TII->get(WebAssembly::CONST_I32));
107 }
elseif (RegClass == &WebAssembly::I64RegClass) {
108MI->setDesc(
TII->get(WebAssembly::CONST_I64));
110 }
elseif (RegClass == &WebAssembly::F32RegClass) {
111MI->setDesc(
TII->get(WebAssembly::CONST_F32));
115 }
elseif (RegClass == &WebAssembly::F64RegClass) {
116MI->setDesc(
TII->get(WebAssembly::CONST_F64));
120 }
elseif (RegClass == &WebAssembly::V128RegClass) {
121MI->setDesc(
TII->get(WebAssembly::CONST_V128_I64x2));
129// Determine whether a call to the callee referenced by 130// MI->getOperand(CalleeOpNo) reads memory, writes memory, and/or has side 133bool &Effects,
bool &StackPointer) {
134// All calls can use the stack pointer. 140if (
constauto *GA = dyn_cast<GlobalAlias>(GV))
141if (!GA->isInterposable())
142 GV = GA->getAliasee();
144if (
constauto *
F = dyn_cast<Function>(GV)) {
145if (!
F->doesNotThrow())
147if (
F->doesNotAccessMemory())
149if (
F->onlyReadsMemory()) {
162// Determine whether MI reads memory, writes memory, has side effects, 163// and/or uses the stack pointer value. 165bool &Effects,
bool &StackPointer) {
168if (
MI.isDebugInstr() ||
MI.isPosition())
172if (
MI.mayLoad() && !
MI.isDereferenceableInvariantLoad())
178 }
elseif (
MI.hasOrderedMemoryRef()) {
179switch (
MI.getOpcode()) {
180case WebAssembly::DIV_S_I32:
181case WebAssembly::DIV_S_I64:
182case WebAssembly::REM_S_I32:
183case WebAssembly::REM_S_I64:
184case WebAssembly::DIV_U_I32:
185case WebAssembly::DIV_U_I64:
186case WebAssembly::REM_U_I32:
187case WebAssembly::REM_U_I64:
188case WebAssembly::I32_TRUNC_S_F32:
189case WebAssembly::I64_TRUNC_S_F32:
190case WebAssembly::I32_TRUNC_S_F64:
191case WebAssembly::I64_TRUNC_S_F64:
192case WebAssembly::I32_TRUNC_U_F32:
193case WebAssembly::I64_TRUNC_U_F32:
194case WebAssembly::I32_TRUNC_U_F64:
195case WebAssembly::I64_TRUNC_U_F64:
196// These instruction have hasUnmodeledSideEffects() returning true 197// because they trap on overflow and invalid so they can't be arbitrarily 198// moved, however hasOrderedMemoryRef() interprets this plus their lack 199// of memoperands as having a potential unknown memory reference. 202// Record volatile accesses, unless it's a call, as calls are handled 212// Check for side effects. 213if (
MI.hasUnmodeledSideEffects()) {
214switch (
MI.getOpcode()) {
215case WebAssembly::DIV_S_I32:
216case WebAssembly::DIV_S_I64:
217case WebAssembly::REM_S_I32:
218case WebAssembly::REM_S_I64:
219case WebAssembly::DIV_U_I32:
220case WebAssembly::DIV_U_I64:
221case WebAssembly::REM_U_I32:
222case WebAssembly::REM_U_I64:
223case WebAssembly::I32_TRUNC_S_F32:
224case WebAssembly::I64_TRUNC_S_F32:
225case WebAssembly::I32_TRUNC_S_F64:
226case WebAssembly::I64_TRUNC_S_F64:
227case WebAssembly::I32_TRUNC_U_F32:
228case WebAssembly::I64_TRUNC_U_F32:
229case WebAssembly::I32_TRUNC_U_F64:
230case WebAssembly::I64_TRUNC_U_F64:
231// These instructions have hasUnmodeledSideEffects() returning true 232// because they trap on overflow and invalid so they can't be arbitrarily 233// moved, however in the specific case of register stackifying, it is safe 234// to move them because overflow and invalid are Undefined Behavior. 242// Check for writes to __stack_pointer global. 243if ((
MI.getOpcode() == WebAssembly::GLOBAL_SET_I32 ||
244MI.getOpcode() == WebAssembly::GLOBAL_SET_I64) &&
245 strcmp(
MI.getOperand(0).getSymbolName(),
"__stack_pointer") == 0)
254// Test whether Def is safe and profitable to rematerialize. 257return Def.isAsCheapAsAMove() &&
TII->isTriviallyReMaterializable(Def);
260// Identify the definition for this register at this point. This is a 261// generalization of MachineRegisterInfo::getUniqueVRegDef that uses 262// LiveIntervals to handle complex cases. 266// Most registers are in SSA form here so we try a quick MRI query first. 270// MRI doesn't know what the Def is. Try asking LIS. 278// Test whether Reg, as defined at Def, has exactly one use. This is a 279// generalization of MachineRegisterInfo::hasOneNonDBGUse that uses 280// LiveIntervals to handle complex cases. 284// Most registers are in SSA form here so we try a quick MRI query first. 285if (
MRI.hasOneNonDBGUse(Reg))
293for (
auto &
I :
MRI.use_nodbg_operands(Reg)) {
295if (Result.valueIn() == DefVNI) {
306// Test whether it's safe to move Def to just before Insert. 307// TODO: Compute memory dependencies in a way that doesn't require always 309// TODO: Compute memory dependencies in a way that uses AliasAnalysis to be 320// The first def of a multivalue instruction can be stackified by moving, 321// since the later defs can always be placed into locals if necessary. Later 322// defs can only be stackified if all previous defs are already stackified 323// since ExplicitLocals will not know how to place a def in a local if a 324// subsequent def is stackified. But only one def can be stackified by moving 325// the instruction, so it must be the first one. 327// TODO: This could be loosened to be the first *live* def, but care would 328// have to be taken to ensure the drops of the initial dead defs can be 329// placed. This would require checking that no previous defs are used in the 330// same instruction as subsequent defs. 331if (Def != DefI->
defs().begin())
334// If any subsequent def is used prior to the current value by the same 335// instruction in which the current value is used, we cannot 336// stackify. Stackifying in this case would require that def moving below the 337// current def in the stack, which cannot be achieved, even with locals. 338// Also ensure we don't sink the def past any other prior uses. 343for (
constauto &PriorUse :
I->uses()) {
346if (PriorUse.isReg() && SubsequentDef.getReg() == PriorUse.getReg())
352// If moving is a semantic nop, it is always allowed 355for (
auto E =
MBB->
end(); NextI != E && NextI->isDebugInstr(); ++NextI)
360// 'catch' and 'catch_all' should be the first instruction of a BB and cannot 365// Check for register dependencies. 368if (!MO.isReg() || MO.isUndef())
372// If the register is dead here and at Insert, ignore it. 373if (MO.isDead() && Insert->definesRegister(Reg,
/*TRI=*/nullptr) &&
374 !Insert->readsRegister(Reg,
/*TRI=*/nullptr))
377if (Reg.isPhysical()) {
378// Ignore ARGUMENTS; it's just used to keep the ARGUMENT_* instructions 379// from moving down, and we've already checked for that. 380if (Reg == WebAssembly::ARGUMENTS)
382// If the physical register is never modified, ignore it. 383if (!
MRI.isPhysRegModified(Reg))
385// Otherwise, it's a physical register with unknown liveness. 389// If one of the operands isn't in SSA form, it has different values at 390// different times, and we need to make sure we don't move our use across 392if (!MO.isDef() && !
MRI.hasOneDef(Reg))
396boolRead =
false,
Write =
false, Effects =
false, StackPointer =
false;
399// If the instruction does not access memory and has no side effects, it has 400// no additional dependencies. 401bool HasMutableRegisters = !MutableRegisters.
empty();
402if (!
Read && !
Write && !Effects && !StackPointer && !HasMutableRegisters)
405// Scan through the intervening instructions between DefI and Insert. 407for (--
I;
I !=
D; --
I) {
408bool InterveningRead =
false;
409bool InterveningWrite =
false;
410bool InterveningEffects =
false;
411bool InterveningStackPointer =
false;
412query(*
I, InterveningRead, InterveningWrite, InterveningEffects,
413 InterveningStackPointer);
414if (Effects && InterveningEffects)
416if (
Read && InterveningWrite)
418if (
Write && (InterveningRead || InterveningWrite))
420if (StackPointer && InterveningStackPointer)
423for (
unsigned Reg : MutableRegisters)
425if (MO.isReg() && MO.isDef() && MO.getReg() == Reg)
432/// Test whether OneUse, a use of Reg, dominates all of Reg's other uses. 451if (UseVNI != OneUseVNI)
454if (UseInst == OneUseInst) {
455// Another use in the same instruction. We need to ensure that the one 456// selected use happens "before" it. 460// Test that the use is dominated by the one selected use. 461while (!MDT.
dominates(OneUseInst, UseInst)) {
462// Actually, dominating is over-conservative. Test that the use would 463// happen after the one selected use in the stack evaluation order. 465// This is needed as a consequence of using implicit local.gets for 466// uses and implicit local.sets for defs. 478if (NewUseInst == OneUseInst) {
479if (&OneUse > &NewUse)
483 UseInst = NewUseInst;
490/// Get the appropriate tee opcode for the given register class. 492if (RC == &WebAssembly::I32RegClass)
493return WebAssembly::TEE_I32;
494if (RC == &WebAssembly::I64RegClass)
495return WebAssembly::TEE_I64;
496if (RC == &WebAssembly::F32RegClass)
497return WebAssembly::TEE_F32;
498if (RC == &WebAssembly::F64RegClass)
499return WebAssembly::TEE_F64;
500if (RC == &WebAssembly::V128RegClass)
501return WebAssembly::TEE_V128;
502if (RC == &WebAssembly::EXTERNREFRegClass)
503return WebAssembly::TEE_EXTERNREF;
504if (RC == &WebAssembly::FUNCREFRegClass)
505return WebAssembly::TEE_FUNCREF;
506if (RC == &WebAssembly::EXNREFRegClass)
507return WebAssembly::TEE_EXNREF;
511// Shrink LI to its uses, cleaning up LI. 519/// A single-use def in the same block with no intervening memory or register 520/// dependencies; move the def down and nest it with the current instruction. 532if (
MRI.hasOneDef(Reg) &&
MRI.hasOneNonDBGUse(Reg)) {
533// No one else is using this register for anything so we can just stackify 537// The register may have unrelated uses or defs; create a new register for 538// just our one def and use so that we can stackify it. 543// Tell LiveIntervals about the new register. 546// Tell LiveIntervals about the changes to the old register. 550/*RemoveDeadValNo=*/true);
562for (
auto *
I =
MI->getPrevNode();
I;
I =
I->getPrevNode())
563if (!
I->isDebugInstr())
568/// A trivially cloneable instruction; clone it and nest the new copy with the 569/// current instruction. 592// Shrink the interval. 600// If that was the last use of the original, delete the original. 613/// A multiple-use def in the same block with no intervening memory or register 614/// dependencies; move the def down, nest it with the current instruction, and 615/// insert a tee to satisfy the rest of the uses. As an illustration, rewrite 618/// Reg = INST ... // Def 619/// INST ..., Reg, ... // Insert 620/// INST ..., Reg, ... 621/// INST ..., Reg, ... 625/// DefReg = INST ... // Def (to become the new Insert) 626/// TeeReg, Reg = TEE_... DefReg 627/// INST ..., TeeReg, ... // Insert 628/// INST ..., Reg, ... 629/// INST ..., Reg, ... 631/// with DefReg and TeeReg stackified. This eliminates a local.get from the 639constauto *RegClass =
MRI.getRegClass(Reg);
640Register TeeReg =
MRI.createVirtualRegister(RegClass);
641Register DefReg =
MRI.createVirtualRegister(RegClass);
643// Move Def into place. 648// Create the Tee and attach the registers. 659// Tell LiveIntervals we moved the original vreg def from Def to Tee. 667// Finish stackifying the new regs. 675// Even though 'TeeReg, Reg = TEE ...', has two defs, we don't need to clone 676// DBG_VALUEs for both of them, given that the latter will cancel the former 677// anyway. Here we only clone DBG_VALUEs for TeeReg, which will be converted 678// to a local index in ExplicitLocals pass. 679 DefDIs.
cloneSink(Insert, TeeReg,
/* CloneDef */false);
687/// A stack for walking the tree of instructions being built, visiting the 688/// MachineOperands in DFS order. 689classTreeWalkerState {
691usingmop_reverse_iterator = std::reverse_iterator<mop_iterator>;
702bool done()
const{
return Worklist.
empty(); }
711"Empty ranges shouldn't remain in the worklist");
715 /// Push Instr's operands onto the stack to be visited. 722 /// Some of Instr's operands are on the top of the stack; remove them and 723 /// re-insert them starting from the beginning (because we've commuted them). 725assert(hasRemainingOperands(Instr) &&
726"Reseting operands should only be done when the instruction has " 727"an operand still on the stack");
731 /// Test whether Instr has operands remaining to be visited at the top of 733bool hasRemainingOperands(
constMachineInstr *Instr)
const{
740 /// Test whether the given register is present on the stack, indicating an 741 /// operand in the tree that we haven't visited yet. Moving a definition of 742 /// Reg to a point in the tree after that would change its value. 744 /// This is needed as a consequence of using implicit local.gets for 745 /// uses and implicit local.sets for defs. 746bool isOnStack(
unsigned Reg)
const{
747for (
const RangeTy &
Range : Worklist)
749if (MO.isReg() && MO.getReg() == Reg)
755/// State to keep track of whether commuting is in flight or whether it's been 756/// tried for the current instruction and didn't work. 758 /// There are effectively three states: the initial state where we haven't 759 /// started commuting anything and we don't know anything yet, the tentative 760 /// state where we've commuted the operands of the current instruction and are 761 /// revisiting it, and the declined state where we've reverted the operands 762 /// back to their original order and will no longer commute it further. 763bool TentativelyCommuting =
false;
766 /// During the tentative state, these hold the operand indices of the commuted 768unsigned Operand0, Operand1;
771 /// Stackification for an operand was not successful due to ordering 772 /// constraints. If possible, and if we haven't already tried it and declined 773 /// it, commute Insert's operands and prepare to revisit it. 774void maybeCommute(
MachineInstr *Insert, TreeWalkerState &TreeWalker,
776if (TentativelyCommuting) {
778"Don't decline commuting until you've finished trying it");
779// Commuting didn't help. Revert it. 780TII->commuteInstruction(*Insert,
/*NewMI=*/false, Operand0, Operand1);
781 TentativelyCommuting =
false;
783 }
elseif (!Declined && TreeWalker.hasRemainingOperands(Insert)) {
786if (
TII->findCommutedOpIndices(*Insert, Operand0, Operand1)) {
787// Tentatively commute the operands and try again. 788TII->commuteInstruction(*Insert,
/*NewMI=*/false, Operand0, Operand1);
789 TreeWalker.resetTopOperands(Insert);
790 TentativelyCommuting =
true;
796 /// Stackification for some operand was successful. Reset to the default 799 TentativelyCommuting =
false;
803}
// end anonymous namespace 805bool WebAssemblyRegStackify::runOnMachineFunction(
MachineFunction &MF) {
807"********** Function: " 815auto &MDT = getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
816auto &LIS = getAnalysis<LiveIntervalsWrapperPass>().getLIS();
818// Walk the instructions from the bottom up. Currently we don't look past 819// block boundaries, and the blocks aren't ordered so the block visitation 820// order isn't significant, but we may want to change this in the future. 822// Don't use a range-based for loop, because we modify the list as we're 823// iterating over it and the end iterator may change. 826// Don't nest anything inside an inline asm, because we don't have 827// constraints for $push inputs. 831// Ignore debugging intrinsics. 832if (
Insert->isDebugValue())
835// Iterate through the inputs in reverse order, since we'll be pulling 836// operands off the stack in LIFO order. 837 CommutingState Commuting;
838 TreeWalkerState TreeWalker(Insert);
839while (!TreeWalker.done()) {
842// We're only interested in explicit virtual register operands. 847assert(
Use.isUse() &&
"explicit_uses() should only iterate over uses");
849"explicit_uses() should only iterate over explicit operands");
853// Identify the definition for this register at this point. 858// Don't nest an INLINE_ASM def into anything, because we don't have 859// constraints for $pop outputs. 863// Argument instructions represent live-in registers and not real 872// Decide which strategy to take. Prefer to move a single-use value 873// over cloning it, and prefer cloning over introducing a tee. 874// For moving, we require the def to be in the same block as the use; 875// this makes things simpler (LiveIntervals' handleMove function only 876// supports intra-block moves) and it's MachineSink's job to catch all 877// the sinking opportunities anyway. 880 !TreeWalker.isOnStack(Reg);
884// If we are removing the frame base reg completely, remove the debug 886// TODO: Encode this properly as a stackified value. 898// We failed to stackify the operand. If the problem was ordering 899// constraints, Commuting may be able to help. 900if (!CanMove && SameBlock)
901 Commuting.maybeCommute(Insert, TreeWalker,
TII);
902// Proceed to the next operand. 906// Stackifying a multivalue def may unlock in-place stackification of 907// subsequent defs. TODO: Handle the case where the consecutive uses are 908// not all in the same instruction. 909auto *SubsequentDef =
Insert->defs().begin();
910auto *SubsequentUse = &
Use;
911while (SubsequentDef !=
Insert->defs().end() &&
912 SubsequentUse !=
Use.getParent()->
uses().end()) {
913if (!SubsequentDef->isReg() || !SubsequentUse->isReg())
915Register DefReg = SubsequentDef->getReg();
917// TODO: This single-use restriction could be relaxed by using tees 918if (DefReg !=
UseReg || !
MRI.hasOneNonDBGUse(DefReg))
925// If the instruction we just stackified is an IMPLICIT_DEF, convert it 926// to a constant 0 so that the def is explicit, and the push/pop 927// correspondence is maintained. 928if (
Insert->getOpcode() == TargetOpcode::IMPLICIT_DEF)
931// We stackified an operand. Add the defining instruction's operands to 932// the worklist stack now to continue to build an ever deeper tree. 934 TreeWalker.pushOperands(Insert);
937// If we stackified any operands, skip over the tree to start looking for 938// the next instruction we can build a tree on. 939if (Insert != &*MII) {
947// If we used VALUE_STACK anywhere, add it to the live-in sets everywhere so 948// that it never looks like a use-before-def. 950 MF.getRegInfo().addLiveIn(WebAssembly::VALUE_STACK);
956// Verify that pushes and pops are performed in LIFO order. 960if (
MI.isDebugInstr())
968"Register stack pop should be paired with a push");
975Stack.push_back(MO.getReg());
978// TODO: Generalize this code to support keeping values on the stack across 979// basic block boundaries. 981"Register stack pushes and pops should be balanced");
unsigned const MachineRegisterInfo * MRI
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
static Register UseReg(const MachineOperand &MO)
const HexagonInstrInfo * TII
unsigned const TargetRegisterInfo * TRI
ConstantRange Range(APInt(BitWidth, Low), APInt(BitWidth, High))
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file contains the declaration of the WebAssembly-specific manager for DebugValues associated wit...
This file provides WebAssembly-specific target descriptions.
This file declares WebAssembly-specific per-machine-function information.
static MachineInstr * rematerializeCheapDef(unsigned Reg, MachineOperand &Op, MachineInstr &Def, MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator Insert, LiveIntervals &LIS, WebAssemblyFunctionInfo &MFI, MachineRegisterInfo &MRI, const WebAssemblyInstrInfo *TII, const WebAssemblyRegisterInfo *TRI)
A trivially cloneable instruction; clone it and nest the new copy with the current instruction.
static unsigned getTeeOpcode(const TargetRegisterClass *RC)
Get the appropriate tee opcode for the given register class.
static MachineInstr * getVRegDef(unsigned Reg, const MachineInstr *Insert, const MachineRegisterInfo &MRI, const LiveIntervals &LIS)
static void convertImplicitDefToConstZero(MachineInstr *MI, MachineRegisterInfo &MRI, const TargetInstrInfo *TII, MachineFunction &MF, LiveIntervals &LIS)
static bool hasOneNonDBGUse(unsigned Reg, MachineInstr *Def, MachineRegisterInfo &MRI, MachineDominatorTree &MDT, LiveIntervals &LIS)
static bool isSafeToMove(const MachineOperand *Def, const MachineOperand *Use, const MachineInstr *Insert, const WebAssemblyFunctionInfo &MFI, const MachineRegisterInfo &MRI)
static MachineInstr * moveForSingleUse(unsigned Reg, MachineOperand &Op, MachineInstr *Def, MachineBasicBlock &MBB, MachineInstr *Insert, LiveIntervals &LIS, WebAssemblyFunctionInfo &MFI, MachineRegisterInfo &MRI)
A single-use def in the same block with no intervening memory or register dependencies; move the def ...
static void imposeStackOrdering(MachineInstr *MI)
static void query(const MachineInstr &MI, bool &Read, bool &Write, bool &Effects, bool &StackPointer)
static void shrinkToUses(LiveInterval &LI, LiveIntervals &LIS)
static MachineInstr * getPrevNonDebugInst(MachineInstr *MI)
static bool shouldRematerialize(const MachineInstr &Def, const WebAssemblyInstrInfo *TII)
static MachineInstr * moveAndTeeForMultiUse(unsigned Reg, MachineOperand &Op, MachineInstr *Def, MachineBasicBlock &MBB, MachineInstr *Insert, LiveIntervals &LIS, WebAssemblyFunctionInfo &MFI, MachineRegisterInfo &MRI, const WebAssemblyInstrInfo *TII)
A multiple-use def in the same block with no intervening memory or register dependencies; move the de...
static bool oneUseDominatesOtherUses(unsigned Reg, const MachineOperand &OneUse, const MachineBasicBlock &MBB, const MachineRegisterInfo &MRI, const MachineDominatorTree &MDT, LiveIntervals &LIS, WebAssemblyFunctionInfo &MFI)
Test whether OneUse, a use of Reg, dominates all of Reg's other uses.
static void queryCallee(const MachineInstr &MI, bool &Read, bool &Write, bool &Effects, bool &StackPointer)
This file declares the WebAssembly-specific subclass of TargetSubtarget.
This file contains the declaration of the WebAssembly-specific utility functions.
This file contains the entry points for global functions defined in the LLVM WebAssembly back-end.
Represent the analysis usage information of a pass.
AnalysisUsage & addPreservedID(const void *ID)
AnalysisUsage & addRequired()
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
This is an important base class in LLVM.
static Constant * getNullValue(Type *Ty)
Constructor to create a '0' constant of arbitrary type.
This class represents an Operation in the Expression.
FunctionPass class - This class is used to implement most global optimizations.
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
LiveInterval - This class represents the liveness of a register, or stack slot.
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
SlotIndex InsertMachineInstrInMaps(MachineInstr &MI)
void handleMove(MachineInstr &MI, bool UpdateFlags=false)
Call this method to notify LiveIntervals that instruction MI has been moved within a basic block.
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
void RemoveMachineInstrFromMaps(MachineInstr &MI)
LiveInterval & getInterval(Register Reg)
void removeInterval(Register Reg)
Interval removal.
bool shrinkToUses(LiveInterval *li, SmallVectorImpl< MachineInstr * > *dead=nullptr)
After removing some uses of a register, shrink its live range to just the remaining uses.
void removePhysRegDefAt(MCRegister Reg, SlotIndex Pos)
Remove value numbers and related live segments starting at position Pos that are part of any liverang...
void splitSeparateComponents(LiveInterval &LI, SmallVectorImpl< LiveInterval * > &SplitLIs)
Split separate components in LiveInterval LI into separate intervals.
LiveInterval & createAndComputeVirtRegInterval(Register Reg)
bool liveAt(SlotIndex index) const
LiveQueryResult Query(SlotIndex Idx) const
Query Liveness at Idx.
VNInfo * getVNInfoBefore(SlotIndex Idx) const
getVNInfoBefore - Return the VNInfo that is live up to but not necessarily including Idx,...
iterator FindSegmentContaining(SlotIndex Idx)
Return an iterator to the segment that contains the specified index, or end() if there is none.
void removeSegment(SlotIndex Start, SlotIndex End, bool RemoveDeadValNo=false)
Remove the specified interval from this live range.
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
static MCRegister from(unsigned Val)
Check the provided unsigned value is a valid MCRegister.
Instructions::iterator instr_iterator
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
reverse_iterator rbegin()
MachineInstrBundleIterator< MachineInstr > iterator
Analysis pass which computes a MachineDominatorTree.
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
bool dominates(const MachineInstr *A, const MachineInstr *B) const
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
reverse_iterator getReverse() const
Get a reverse iterator to the same node.
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
const MachineBasicBlock * getParent() const
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
iterator_range< mop_iterator > operands()
iterator_range< mop_iterator > defs()
Returns a range over all explicit operands that are register definitions.
MachineOperand * mop_iterator
iterator/begin/end - Iterate over all operands of a machine instruction.
const MachineOperand & getOperand(unsigned i) const
MachineOperand * findRegisterDefOperand(Register Reg, const TargetRegisterInfo *TRI, bool isDead=false, bool Overlap=false)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
MachineOperand class - Representation of each machine instruction operand.
const GlobalValue * getGlobal() const
static MachineOperand CreateFPImm(const ConstantFP *CFP)
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
static MachineOperand CreateImm(int64_t Val)
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
Register getReg() const
getReg - Returns the register number.
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Wrapper class representing virtual and physical registers.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
SlotIndex - An opaque wrapper around machine indexes.
SlotIndex getDeadSlot() const
Returns the dead def kill slot for the current instruction.
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def.
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
TargetInstrInfo - Interface to description of machine instruction set.
static const unsigned CommuteAnyOperandIndex
static Type * getDoubleTy(LLVMContext &C)
static Type * getFloatTy(LLVMContext &C)
A Use represents the edge between a Value definition and its users.
VNInfo - Value Number Information.
SlotIndex def
The index of the defining instruction.
iterator_range< use_iterator > uses()
void updateReg(Register Reg)
void cloneSink(MachineInstr *Insert, Register NewReg=Register(), bool CloneDef=true) const
void sink(MachineInstr *Insert)
This class is derived from MachineFunctionInfo and contains private WebAssembly-specific information ...
bool isVRegStackified(unsigned VReg) const
unsigned getFrameBaseVreg() const
void stackifyVReg(MachineRegisterInfo &MRI, unsigned VReg)
void clearFrameBaseVreg()
bool isFrameBaseVirtual() const
A range adaptor for a pair of iterators.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ Define
Register definition.
bool isArgument(unsigned Opc)
const MachineOperand & getCalleeOp(const MachineInstr &MI)
Returns the operand number of a callee, assuming the argument is a call instruction.
bool isCatch(unsigned Opc)
Reg
All possible values of the reg field in the ModR/M byte.
NodeAddr< InstrNode * > Instr
NodeAddr< DefNode * > Def
This is an optimization pass for GlobalISel generic memory operations.
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
void dump(const SparseBitVector< ElementSize > &LHS, raw_ostream &out)
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
auto reverse(ContainerTy &&C)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
unsigned getUndefRegState(bool B)
DWARFExpression::Operation Op
char & LiveVariablesID
LiveVariables pass - This pass computes the set of blocks in which each variable is life and sets mac...
FunctionPass * createWebAssemblyRegStackify()
