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1//===- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ----===//

2//

3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.

4// See https://llvm.org/LICENSE.txt for license information.

5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception

6//

7//===----------------------------------------------------------------------===//

8//

9// This implements the TargetLoweringBase class.

10//

11//===----------------------------------------------------------------------===//

13#include "llvm/ADT/BitVector.h"

14#include "llvm/ADT/STLExtras.h"

15#include "llvm/ADT/SmallVector.h"

16#include "llvm/ADT/StringExtras.h"

17#include "llvm/ADT/StringRef.h"

18#include "llvm/ADT/Twine.h"

19#include "llvm/Analysis/Loads.h"

20#include "llvm/Analysis/TargetTransformInfo.h"

21#include "llvm/CodeGen/Analysis.h"

22#include "llvm/CodeGen/ISDOpcodes.h"

23#include "llvm/CodeGen/MachineBasicBlock.h"

24#include "llvm/CodeGen/MachineFrameInfo.h"

25#include "llvm/CodeGen/MachineFunction.h"

26#include "llvm/CodeGen/MachineInstr.h"

27#include "llvm/CodeGen/MachineInstrBuilder.h"

28#include "llvm/CodeGen/MachineMemOperand.h"

29#include "llvm/CodeGen/MachineOperand.h"

30#include "llvm/CodeGen/MachineRegisterInfo.h"

31#include "llvm/CodeGen/RuntimeLibcallUtil.h"

32#include "llvm/CodeGen/StackMaps.h"

33#include "llvm/CodeGen/TargetLowering.h"

34#include "llvm/CodeGen/TargetOpcodes.h"

35#include "llvm/CodeGen/TargetRegisterInfo.h"

36#include "llvm/CodeGen/ValueTypes.h"

37#include "llvm/CodeGenTypes/MachineValueType.h"

38#include "llvm/IR/Attributes.h"

39#include "llvm/IR/CallingConv.h"

40#include "llvm/IR/DataLayout.h"

41#include "llvm/IR/DerivedTypes.h"

42#include "llvm/IR/Function.h"

43#include "llvm/IR/GlobalValue.h"

44#include "llvm/IR/GlobalVariable.h"

45#include "llvm/IR/IRBuilder.h"

46#include "llvm/IR/Module.h"

47#include "llvm/IR/Type.h"

48#include "llvm/Support/Casting.h"

49#include "llvm/Support/CommandLine.h"

50#include "llvm/Support/Compiler.h"

51#include "llvm/Support/ErrorHandling.h"

52#include "llvm/Support/MathExtras.h"

53#include "llvm/Target/TargetMachine.h"

54#include "llvm/Target/TargetOptions.h"

55#include "llvm/TargetParser/Triple.h"

56#include "llvm/Transforms/Utils/SizeOpts.h"

57#include <algorithm>

58#include <cassert>

59#include <cstdint>

60#include <cstring>

61#include <iterator>

62#include <string>

63#include <tuple>

64#include <utility>

66using namespacellvm;

68staticcl::opt<bool>JumpIsExpensiveOverride(

69"jump-is-expensive",cl::init(false),

70cl::desc("Do not create extra branches to split comparison logic."),

71cl::Hidden);

73staticcl::opt<unsigned>MinimumJumpTableEntries

74 ("min-jump-table-entries",cl::init(4),cl::Hidden,

75cl::desc("Set minimum number of entries to use a jump table."));

77staticcl::opt<unsigned>MaximumJumpTableSize

78 ("max-jump-table-size",cl::init(UINT_MAX),cl::Hidden,

79cl::desc("Set maximum size of jump tables."));

81/// Minimum jump table density for normal functions.

82staticcl::opt<unsigned>

83JumpTableDensity("jump-table-density",cl::init(10),cl::Hidden,

84cl::desc("Minimum density for building a jump table in "

85"a normal function"));

87/// Minimum jump table density for -Os or -Oz functions.

88staticcl::opt<unsigned>OptsizeJumpTableDensity(

89"optsize-jump-table-density",cl::init(40),cl::Hidden,

90cl::desc("Minimum density for building a jump table in "

91"an optsize function"));

93// FIXME: This option is only to test if the strict fp operation processed

94// correctly by preventing mutating strict fp operation to normal fp operation

95// during development. When the backend supports strict float operation, this

96// option will be meaningless.

97staticcl::opt<bool>DisableStrictNodeMutation("disable-strictnode-mutation",

98cl::desc("Don't mutate strict-float node to a legalize node"),

99cl::init(false),cl::Hidden);

100

101/// GetFPLibCall - Helper to return the right libcall for the given floating

102/// point type, or UNKNOWN_LIBCALL if there is none.

103RTLIB::Libcall RTLIB::getFPLibCall(EVT VT,

104RTLIB::Libcall Call_F32,

105RTLIB::Libcall Call_F64,

106RTLIB::Libcall Call_F80,

107RTLIB::Libcall Call_F128,

108RTLIB::Libcall Call_PPCF128) {

109return

110 VT == MVT::f32 ? Call_F32 :

111 VT == MVT::f64 ? Call_F64 :

112 VT == MVT::f80 ? Call_F80 :

113 VT == MVT::f128 ? Call_F128 :

114 VT == MVT::ppcf128 ? Call_PPCF128 :

115 RTLIB::UNKNOWN_LIBCALL;

116}

117

118/// getFPEXT - Return the FPEXT_*_* value for the given types, or

119/// UNKNOWN_LIBCALL if there is none.

120RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT,EVT RetVT) {

121if (OpVT == MVT::f16) {

122if (RetVT == MVT::f32)

123return FPEXT_F16_F32;

124if (RetVT == MVT::f64)

125return FPEXT_F16_F64;

126if (RetVT == MVT::f80)

127return FPEXT_F16_F80;

128if (RetVT == MVT::f128)

129return FPEXT_F16_F128;

130 }elseif (OpVT == MVT::f32) {

131if (RetVT == MVT::f64)

132return FPEXT_F32_F64;

133if (RetVT == MVT::f128)

134return FPEXT_F32_F128;

135if (RetVT == MVT::ppcf128)

136return FPEXT_F32_PPCF128;

137 }elseif (OpVT == MVT::f64) {

138if (RetVT == MVT::f128)

139return FPEXT_F64_F128;

140elseif (RetVT == MVT::ppcf128)

141return FPEXT_F64_PPCF128;

142 }elseif (OpVT == MVT::f80) {

143if (RetVT == MVT::f128)

144return FPEXT_F80_F128;

145 }elseif (OpVT == MVT::bf16) {

146if (RetVT == MVT::f32)

147return FPEXT_BF16_F32;

148 }

149

150return UNKNOWN_LIBCALL;

151}

152

153/// getFPROUND - Return the FPROUND_*_* value for the given types, or

154/// UNKNOWN_LIBCALL if there is none.

155RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT,EVT RetVT) {

156if (RetVT == MVT::f16) {

157if (OpVT == MVT::f32)

158return FPROUND_F32_F16;

159if (OpVT == MVT::f64)

160return FPROUND_F64_F16;

161if (OpVT == MVT::f80)

162return FPROUND_F80_F16;

163if (OpVT == MVT::f128)

164return FPROUND_F128_F16;

165if (OpVT == MVT::ppcf128)

166return FPROUND_PPCF128_F16;

167 }elseif (RetVT == MVT::bf16) {

168if (OpVT == MVT::f32)

169return FPROUND_F32_BF16;

170if (OpVT == MVT::f64)

171return FPROUND_F64_BF16;

172if (OpVT == MVT::f80)

173return FPROUND_F80_BF16;

174if (OpVT == MVT::f128)

175return FPROUND_F128_BF16;

176 }elseif (RetVT == MVT::f32) {

177if (OpVT == MVT::f64)

178return FPROUND_F64_F32;

179if (OpVT == MVT::f80)

180return FPROUND_F80_F32;

181if (OpVT == MVT::f128)

182return FPROUND_F128_F32;

183if (OpVT == MVT::ppcf128)

184return FPROUND_PPCF128_F32;

185 }elseif (RetVT == MVT::f64) {

186if (OpVT == MVT::f80)

187return FPROUND_F80_F64;

188if (OpVT == MVT::f128)

189return FPROUND_F128_F64;

190if (OpVT == MVT::ppcf128)

191return FPROUND_PPCF128_F64;

192 }elseif (RetVT == MVT::f80) {

193if (OpVT == MVT::f128)

194return FPROUND_F128_F80;

195 }

196

197return UNKNOWN_LIBCALL;

198}

199

200/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or

201/// UNKNOWN_LIBCALL if there is none.

202RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT,EVT RetVT) {

203if (OpVT == MVT::f16) {

204if (RetVT == MVT::i32)

205return FPTOSINT_F16_I32;

206if (RetVT == MVT::i64)

207return FPTOSINT_F16_I64;

208if (RetVT == MVT::i128)

209return FPTOSINT_F16_I128;

210 }elseif (OpVT == MVT::f32) {

211if (RetVT == MVT::i32)

212return FPTOSINT_F32_I32;

213if (RetVT == MVT::i64)

214return FPTOSINT_F32_I64;

215if (RetVT == MVT::i128)

216return FPTOSINT_F32_I128;

217 }elseif (OpVT == MVT::f64) {

218if (RetVT == MVT::i32)

219return FPTOSINT_F64_I32;

220if (RetVT == MVT::i64)

221return FPTOSINT_F64_I64;

222if (RetVT == MVT::i128)

223return FPTOSINT_F64_I128;

224 }elseif (OpVT == MVT::f80) {

225if (RetVT == MVT::i32)

226return FPTOSINT_F80_I32;

227if (RetVT == MVT::i64)

228return FPTOSINT_F80_I64;

229if (RetVT == MVT::i128)

230return FPTOSINT_F80_I128;

231 }elseif (OpVT == MVT::f128) {

232if (RetVT == MVT::i32)

233return FPTOSINT_F128_I32;

234if (RetVT == MVT::i64)

235return FPTOSINT_F128_I64;

236if (RetVT == MVT::i128)

237return FPTOSINT_F128_I128;

238 }elseif (OpVT == MVT::ppcf128) {

239if (RetVT == MVT::i32)

240return FPTOSINT_PPCF128_I32;

241if (RetVT == MVT::i64)

242return FPTOSINT_PPCF128_I64;

243if (RetVT == MVT::i128)

244return FPTOSINT_PPCF128_I128;

245 }

246return UNKNOWN_LIBCALL;

247}

248

249/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or

250/// UNKNOWN_LIBCALL if there is none.

251RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT,EVT RetVT) {

252if (OpVT == MVT::f16) {

253if (RetVT == MVT::i32)

254return FPTOUINT_F16_I32;

255if (RetVT == MVT::i64)

256return FPTOUINT_F16_I64;

257if (RetVT == MVT::i128)

258return FPTOUINT_F16_I128;

259 }elseif (OpVT == MVT::f32) {

260if (RetVT == MVT::i32)

261return FPTOUINT_F32_I32;

262if (RetVT == MVT::i64)

263return FPTOUINT_F32_I64;

264if (RetVT == MVT::i128)

265return FPTOUINT_F32_I128;

266 }elseif (OpVT == MVT::f64) {

267if (RetVT == MVT::i32)

268return FPTOUINT_F64_I32;

269if (RetVT == MVT::i64)

270return FPTOUINT_F64_I64;

271if (RetVT == MVT::i128)

272return FPTOUINT_F64_I128;

273 }elseif (OpVT == MVT::f80) {

274if (RetVT == MVT::i32)

275return FPTOUINT_F80_I32;

276if (RetVT == MVT::i64)

277return FPTOUINT_F80_I64;

278if (RetVT == MVT::i128)

279return FPTOUINT_F80_I128;

280 }elseif (OpVT == MVT::f128) {

281if (RetVT == MVT::i32)

282return FPTOUINT_F128_I32;

283if (RetVT == MVT::i64)

284return FPTOUINT_F128_I64;

285if (RetVT == MVT::i128)

286return FPTOUINT_F128_I128;

287 }elseif (OpVT == MVT::ppcf128) {

288if (RetVT == MVT::i32)

289return FPTOUINT_PPCF128_I32;

290if (RetVT == MVT::i64)

291return FPTOUINT_PPCF128_I64;

292if (RetVT == MVT::i128)

293return FPTOUINT_PPCF128_I128;

294 }

295return UNKNOWN_LIBCALL;

296}

297

298/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or

299/// UNKNOWN_LIBCALL if there is none.

300RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT,EVT RetVT) {

301if (OpVT == MVT::i32) {

302if (RetVT == MVT::f16)

303return SINTTOFP_I32_F16;

304if (RetVT == MVT::f32)

305return SINTTOFP_I32_F32;

306if (RetVT == MVT::f64)

307return SINTTOFP_I32_F64;

308if (RetVT == MVT::f80)

309return SINTTOFP_I32_F80;

310if (RetVT == MVT::f128)

311return SINTTOFP_I32_F128;

312if (RetVT == MVT::ppcf128)

313return SINTTOFP_I32_PPCF128;

314 }elseif (OpVT == MVT::i64) {

315if (RetVT == MVT::f16)

316return SINTTOFP_I64_F16;

317if (RetVT == MVT::f32)

318return SINTTOFP_I64_F32;

319if (RetVT == MVT::f64)

320return SINTTOFP_I64_F64;

321if (RetVT == MVT::f80)

322return SINTTOFP_I64_F80;

323if (RetVT == MVT::f128)

324return SINTTOFP_I64_F128;

325if (RetVT == MVT::ppcf128)

326return SINTTOFP_I64_PPCF128;

327 }elseif (OpVT == MVT::i128) {

328if (RetVT == MVT::f16)

329return SINTTOFP_I128_F16;

330if (RetVT == MVT::f32)

331return SINTTOFP_I128_F32;

332if (RetVT == MVT::f64)

333return SINTTOFP_I128_F64;

334if (RetVT == MVT::f80)

335return SINTTOFP_I128_F80;

336if (RetVT == MVT::f128)

337return SINTTOFP_I128_F128;

338if (RetVT == MVT::ppcf128)

339return SINTTOFP_I128_PPCF128;

340 }

341return UNKNOWN_LIBCALL;

342}

343

344/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or

345/// UNKNOWN_LIBCALL if there is none.

346RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT,EVT RetVT) {

347if (OpVT == MVT::i32) {

348if (RetVT == MVT::f16)

349return UINTTOFP_I32_F16;

350if (RetVT == MVT::f32)

351return UINTTOFP_I32_F32;

352if (RetVT == MVT::f64)

353return UINTTOFP_I32_F64;

354if (RetVT == MVT::f80)

355return UINTTOFP_I32_F80;

356if (RetVT == MVT::f128)

357return UINTTOFP_I32_F128;

358if (RetVT == MVT::ppcf128)

359return UINTTOFP_I32_PPCF128;

360 }elseif (OpVT == MVT::i64) {

361if (RetVT == MVT::f16)

362return UINTTOFP_I64_F16;

363if (RetVT == MVT::f32)

364return UINTTOFP_I64_F32;

365if (RetVT == MVT::f64)

366return UINTTOFP_I64_F64;

367if (RetVT == MVT::f80)

368return UINTTOFP_I64_F80;

369if (RetVT == MVT::f128)

370return UINTTOFP_I64_F128;

371if (RetVT == MVT::ppcf128)

372return UINTTOFP_I64_PPCF128;

373 }elseif (OpVT == MVT::i128) {

374if (RetVT == MVT::f16)

375return UINTTOFP_I128_F16;

376if (RetVT == MVT::f32)

377return UINTTOFP_I128_F32;

378if (RetVT == MVT::f64)

379return UINTTOFP_I128_F64;

380if (RetVT == MVT::f80)

381return UINTTOFP_I128_F80;

382if (RetVT == MVT::f128)

383return UINTTOFP_I128_F128;

384if (RetVT == MVT::ppcf128)

385return UINTTOFP_I128_PPCF128;

386 }

387return UNKNOWN_LIBCALL;

388}

389

390RTLIB::Libcall RTLIB::getPOWI(EVT RetVT) {

391returngetFPLibCall(RetVT, POWI_F32, POWI_F64, POWI_F80, POWI_F128,

392 POWI_PPCF128);

393}

394

395RTLIB::Libcall RTLIB::getLDEXP(EVT RetVT) {

396returngetFPLibCall(RetVT, LDEXP_F32, LDEXP_F64, LDEXP_F80, LDEXP_F128,

397 LDEXP_PPCF128);

398}

399

400RTLIB::Libcall RTLIB::getFREXP(EVT RetVT) {

401returngetFPLibCall(RetVT, FREXP_F32, FREXP_F64, FREXP_F80, FREXP_F128,

402 FREXP_PPCF128);

403}

404

405RTLIB::Libcall RTLIB::getFSINCOS(EVT RetVT) {

406returngetFPLibCall(RetVT, SINCOS_F32, SINCOS_F64, SINCOS_F80, SINCOS_F128,

407 SINCOS_PPCF128);

408}

409

410RTLIB::Libcall RTLIB::getOutlineAtomicHelper(constLibcall (&LC)[5][4],

411AtomicOrdering Order,

412uint64_t MemSize) {

413unsigned ModeN, ModelN;

414switch (MemSize) {

415case 1:

416 ModeN = 0;

417break;

418case 2:

419 ModeN = 1;

420break;

421case 4:

422 ModeN = 2;

423break;

424case 8:

425 ModeN = 3;

426break;

427case 16:

428 ModeN = 4;

429break;

430default:

431return RTLIB::UNKNOWN_LIBCALL;

432 }

433

434switch (Order) {

435case AtomicOrdering::Monotonic:

436 ModelN = 0;

437break;

438case AtomicOrdering::Acquire:

439 ModelN = 1;

440break;

441case AtomicOrdering::Release:

442 ModelN = 2;

443break;

444case AtomicOrdering::AcquireRelease:

445case AtomicOrdering::SequentiallyConsistent:

446 ModelN = 3;

447break;

448default:

449return UNKNOWN_LIBCALL;

450 }

451

452return LC[ModeN][ModelN];

453}

454

455RTLIB::Libcall RTLIB::getOUTLINE_ATOMIC(unsigned Opc,AtomicOrdering Order,

456MVT VT) {

457if (!VT.isScalarInteger())

458return UNKNOWN_LIBCALL;

459uint64_t MemSize = VT.getScalarSizeInBits() / 8;

460

461#define LCALLS(A, B) \

462 { A##B##_RELAX, A##B##_ACQ, A##B##_REL, A##B##_ACQ_REL }

463#define LCALL5(A) \

464 LCALLS(A, 1), LCALLS(A, 2), LCALLS(A, 4), LCALLS(A, 8), LCALLS(A, 16)

465switch (Opc) {

466caseISD::ATOMIC_CMP_SWAP: {

467constLibcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_CAS)};

468returngetOutlineAtomicHelper(LC, Order, MemSize);

469 }

470caseISD::ATOMIC_SWAP: {

471constLibcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_SWP)};

472returngetOutlineAtomicHelper(LC, Order, MemSize);

473 }

474caseISD::ATOMIC_LOAD_ADD: {

475constLibcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDADD)};

476returngetOutlineAtomicHelper(LC, Order, MemSize);

477 }

478caseISD::ATOMIC_LOAD_OR: {

479constLibcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDSET)};

480returngetOutlineAtomicHelper(LC, Order, MemSize);

481 }

482caseISD::ATOMIC_LOAD_CLR: {

483constLibcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDCLR)};

484returngetOutlineAtomicHelper(LC, Order, MemSize);

485 }

486caseISD::ATOMIC_LOAD_XOR: {

487constLibcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDEOR)};

488returngetOutlineAtomicHelper(LC, Order, MemSize);

489 }

490default:

491return UNKNOWN_LIBCALL;

492 }

493#undef LCALLS

494#undef LCALL5

495}

496

497RTLIB::Libcall RTLIB::getSYNC(unsigned Opc,MVT VT) {

498#define OP_TO_LIBCALL(Name, Enum) \

499 case Name: \

500 switch (VT.SimpleTy) { \

501 default: \

502 return UNKNOWN_LIBCALL; \

503 case MVT::i8: \

504 return Enum##_1; \

505 case MVT::i16: \

506 return Enum##_2; \

507 case MVT::i32: \

508 return Enum##_4; \

509 case MVT::i64: \

510 return Enum##_8; \

511 case MVT::i128: \

512 return Enum##_16; \

513 }

514

515switch (Opc) {

516OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET)

517OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP)

518OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD)

519OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB)

520OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND)

521OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR)

522OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR)

523OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND)

524OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX)

525OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX)

526OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN)

527OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN)

528 }

529

530#undef OP_TO_LIBCALL

531

532return UNKNOWN_LIBCALL;

533}

534

535RTLIB::Libcall RTLIB::getMEMCPY_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize) {

536switch (ElementSize) {

537case 1:

538return MEMCPY_ELEMENT_UNORDERED_ATOMIC_1;

539case 2:

540return MEMCPY_ELEMENT_UNORDERED_ATOMIC_2;

541case 4:

542return MEMCPY_ELEMENT_UNORDERED_ATOMIC_4;

543case 8:

544return MEMCPY_ELEMENT_UNORDERED_ATOMIC_8;

545case 16:

546return MEMCPY_ELEMENT_UNORDERED_ATOMIC_16;

547default:

548return UNKNOWN_LIBCALL;

549 }

550}

551

552RTLIB::Libcall RTLIB::getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize) {

553switch (ElementSize) {

554case 1:

555return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_1;

556case 2:

557return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_2;

558case 4:

559return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_4;

560case 8:

561return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_8;

562case 16:

563return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_16;

564default:

565return UNKNOWN_LIBCALL;

566 }

567}

568

569RTLIB::Libcall RTLIB::getMEMSET_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize) {

570switch (ElementSize) {

571case 1:

572return MEMSET_ELEMENT_UNORDERED_ATOMIC_1;

573case 2:

574return MEMSET_ELEMENT_UNORDERED_ATOMIC_2;

575case 4:

576return MEMSET_ELEMENT_UNORDERED_ATOMIC_4;

577case 8:

578return MEMSET_ELEMENT_UNORDERED_ATOMIC_8;

579case 16:

580return MEMSET_ELEMENT_UNORDERED_ATOMIC_16;

581default:

582return UNKNOWN_LIBCALL;

583 }

584}

585

586voidRTLIB::initCmpLibcallCCs(ISD::CondCode *CmpLibcallCCs) {

587 std::fill(CmpLibcallCCs, CmpLibcallCCs + RTLIB::UNKNOWN_LIBCALL,

588ISD::SETCC_INVALID);

589 CmpLibcallCCs[RTLIB::OEQ_F32] =ISD::SETEQ;

590 CmpLibcallCCs[RTLIB::OEQ_F64] =ISD::SETEQ;

591 CmpLibcallCCs[RTLIB::OEQ_F128] =ISD::SETEQ;

592 CmpLibcallCCs[RTLIB::OEQ_PPCF128] =ISD::SETEQ;

593 CmpLibcallCCs[RTLIB::UNE_F32] =ISD::SETNE;

594 CmpLibcallCCs[RTLIB::UNE_F64] =ISD::SETNE;

595 CmpLibcallCCs[RTLIB::UNE_F128] =ISD::SETNE;

596 CmpLibcallCCs[RTLIB::UNE_PPCF128] =ISD::SETNE;

597 CmpLibcallCCs[RTLIB::OGE_F32] =ISD::SETGE;

598 CmpLibcallCCs[RTLIB::OGE_F64] =ISD::SETGE;

599 CmpLibcallCCs[RTLIB::OGE_F128] =ISD::SETGE;

600 CmpLibcallCCs[RTLIB::OGE_PPCF128] =ISD::SETGE;

601 CmpLibcallCCs[RTLIB::OLT_F32] =ISD::SETLT;

602 CmpLibcallCCs[RTLIB::OLT_F64] =ISD::SETLT;

603 CmpLibcallCCs[RTLIB::OLT_F128] =ISD::SETLT;

604 CmpLibcallCCs[RTLIB::OLT_PPCF128] =ISD::SETLT;

605 CmpLibcallCCs[RTLIB::OLE_F32] =ISD::SETLE;

606 CmpLibcallCCs[RTLIB::OLE_F64] =ISD::SETLE;

607 CmpLibcallCCs[RTLIB::OLE_F128] =ISD::SETLE;

608 CmpLibcallCCs[RTLIB::OLE_PPCF128] =ISD::SETLE;

609 CmpLibcallCCs[RTLIB::OGT_F32] =ISD::SETGT;

610 CmpLibcallCCs[RTLIB::OGT_F64] =ISD::SETGT;

611 CmpLibcallCCs[RTLIB::OGT_F128] =ISD::SETGT;

612 CmpLibcallCCs[RTLIB::OGT_PPCF128] =ISD::SETGT;

613 CmpLibcallCCs[RTLIB::UO_F32] =ISD::SETNE;

614 CmpLibcallCCs[RTLIB::UO_F64] =ISD::SETNE;

615 CmpLibcallCCs[RTLIB::UO_F128] =ISD::SETNE;

616 CmpLibcallCCs[RTLIB::UO_PPCF128] =ISD::SETNE;

617}

618

619/// NOTE: The TargetMachine owns TLOF.

620TargetLoweringBase::TargetLoweringBase(constTargetMachine &tm)

621 : TM(tm), Libcalls(TM.getTargetTriple()) {

622initActions();

623

624// Perform these initializations only once.

625MaxStoresPerMemset =MaxStoresPerMemcpy =MaxStoresPerMemmove =

626MaxLoadsPerMemcmp = 8;

627MaxGluedStoresPerMemcpy = 0;

628MaxStoresPerMemsetOptSize =MaxStoresPerMemcpyOptSize =

629MaxStoresPerMemmoveOptSize =MaxLoadsPerMemcmpOptSize = 4;

630 HasMultipleConditionRegisters =false;

631 HasExtractBitsInsn =false;

632 JumpIsExpensive =JumpIsExpensiveOverride;

633PredictableSelectIsExpensive =false;

634EnableExtLdPromotion =false;

635 StackPointerRegisterToSaveRestore = 0;

636 BooleanContents =UndefinedBooleanContent;

637 BooleanFloatContents =UndefinedBooleanContent;

638 BooleanVectorContents =UndefinedBooleanContent;

639 SchedPreferenceInfo =Sched::ILP;

640GatherAllAliasesMaxDepth = 18;

641IsStrictFPEnabled =DisableStrictNodeMutation;

642 MaxBytesForAlignment = 0;

643 MaxAtomicSizeInBitsSupported = 0;

644

645// Assume that even with libcalls, no target supports wider than 128 bit

646// division.

647 MaxDivRemBitWidthSupported = 128;

648

649 MaxLargeFPConvertBitWidthSupported =llvm::IntegerType::MAX_INT_BITS;

650

651 MinCmpXchgSizeInBits = 0;

652 SupportsUnalignedAtomics =false;

653

654RTLIB::initCmpLibcallCCs(CmpLibcallCCs);

655}

656

657voidTargetLoweringBase::initActions() {

658// All operations default to being supported.

659 memset(OpActions, 0,sizeof(OpActions));

660 memset(LoadExtActions, 0,sizeof(LoadExtActions));

661 memset(TruncStoreActions, 0,sizeof(TruncStoreActions));

662 memset(IndexedModeActions, 0,sizeof(IndexedModeActions));

663 memset(CondCodeActions, 0,sizeof(CondCodeActions));

664 std::fill(std::begin(RegClassForVT), std::end(RegClassForVT),nullptr);

665 std::fill(std::begin(TargetDAGCombineArray),

666 std::end(TargetDAGCombineArray), 0);

667

668// Let extending atomic loads be unsupported by default.

669for (MVT ValVT :MVT::all_valuetypes())

670for (MVT MemVT :MVT::all_valuetypes())

671setAtomicLoadExtAction({ISD::SEXTLOAD,ISD::ZEXTLOAD}, ValVT, MemVT,

672Expand);

673

674// We're somewhat special casing MVT::i2 and MVT::i4. Ideally we want to

675// remove this and targets should individually set these types if not legal.

676for (ISD::NodeType NT :enum_seq(ISD::DELETED_NODE,ISD::BUILTIN_OP_END,

677force_iteration_on_noniterable_enum)) {

678for (MVT VT : {MVT::i2, MVT::i4})

679 OpActions[(unsigned)VT.SimpleTy][NT] =Expand;

680 }

681for (MVT AVT :MVT::all_valuetypes()) {

682for (MVT VT : {MVT::i2, MVT::i4, MVT::v128i2, MVT::v64i4}) {

683setTruncStoreAction(AVT, VT,Expand);

684setLoadExtAction(ISD::EXTLOAD, AVT, VT,Expand);

685setLoadExtAction(ISD::ZEXTLOAD, AVT, VT,Expand);

686 }

687 }

688for (unsigned IM = (unsigned)ISD::PRE_INC;

689 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {

690for (MVT VT : {MVT::i2, MVT::i4}) {

691setIndexedLoadAction(IM, VT,Expand);

692setIndexedStoreAction(IM, VT,Expand);

693setIndexedMaskedLoadAction(IM, VT,Expand);

694setIndexedMaskedStoreAction(IM, VT,Expand);

695 }

696 }

697

698for (MVT VT :MVT::fp_valuetypes()) {

699MVT IntVT =MVT::getIntegerVT(VT.getFixedSizeInBits());

700if (IntVT.isValid()) {

701setOperationAction(ISD::ATOMIC_SWAP, VT,Promote);

702AddPromotedToType(ISD::ATOMIC_SWAP, VT, IntVT);

703 }

704 }

705

706// Set default actions for various operations.

707for (MVT VT :MVT::all_valuetypes()) {

708// Default all indexed load / store to expand.

709for (unsigned IM = (unsigned)ISD::PRE_INC;

710 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {

711setIndexedLoadAction(IM, VT,Expand);

712setIndexedStoreAction(IM, VT,Expand);

713setIndexedMaskedLoadAction(IM, VT,Expand);

714setIndexedMaskedStoreAction(IM, VT,Expand);

715 }

716

717// Most backends expect to see the node which just returns the value loaded.

718setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT,Expand);

719

720// These operations default to expand.

721setOperationAction({ISD::FGETSIGN,ISD::CONCAT_VECTORS,

722ISD::FMINNUM,ISD::FMAXNUM,

723ISD::FMINNUM_IEEE,ISD::FMAXNUM_IEEE,

724ISD::FMINIMUM,ISD::FMAXIMUM,

725ISD::FMINIMUMNUM,ISD::FMAXIMUMNUM,

726ISD::FMAD,ISD::SMIN,

727ISD::SMAX,ISD::UMIN,

728ISD::UMAX,ISD::ABS,

729ISD::FSHL,ISD::FSHR,

730ISD::SADDSAT,ISD::UADDSAT,

731ISD::SSUBSAT,ISD::USUBSAT,

732ISD::SSHLSAT,ISD::USHLSAT,

733ISD::SMULFIX,ISD::SMULFIXSAT,

734ISD::UMULFIX,ISD::UMULFIXSAT,

735ISD::SDIVFIX,ISD::SDIVFIXSAT,

736ISD::UDIVFIX,ISD::UDIVFIXSAT,

737ISD::FP_TO_SINT_SAT,ISD::FP_TO_UINT_SAT,

738ISD::IS_FPCLASS},

739 VT,Expand);

740

741// Overflow operations default to expand

742setOperationAction({ISD::SADDO,ISD::SSUBO,ISD::UADDO,ISD::USUBO,

743ISD::SMULO,ISD::UMULO},

744 VT,Expand);

745

746// Carry-using overflow operations default to expand.

747setOperationAction({ISD::UADDO_CARRY,ISD::USUBO_CARRY,ISD::SETCCCARRY,

748ISD::SADDO_CARRY,ISD::SSUBO_CARRY},

749 VT,Expand);

750

751// ADDC/ADDE/SUBC/SUBE default to expand.

752setOperationAction({ISD::ADDC,ISD::ADDE,ISD::SUBC,ISD::SUBE}, VT,

753Expand);

754

755// [US]CMP default to expand

756setOperationAction({ISD::UCMP,ISD::SCMP}, VT,Expand);

757

758// Halving adds

759setOperationAction(

760 {ISD::AVGFLOORS,ISD::AVGFLOORU,ISD::AVGCEILS,ISD::AVGCEILU}, VT,

761Expand);

762

763// Absolute difference

764setOperationAction({ISD::ABDS,ISD::ABDU}, VT,Expand);

765

766// Saturated trunc

767setOperationAction(ISD::TRUNCATE_SSAT_S, VT,Expand);

768setOperationAction(ISD::TRUNCATE_SSAT_U, VT,Expand);

769setOperationAction(ISD::TRUNCATE_USAT_U, VT,Expand);

770

771// These default to Expand so they will be expanded to CTLZ/CTTZ by default.

772setOperationAction({ISD::CTLZ_ZERO_UNDEF,ISD::CTTZ_ZERO_UNDEF}, VT,

773Expand);

774

775setOperationAction({ISD::BITREVERSE,ISD::PARITY}, VT,Expand);

776

777// These library functions default to expand.

778setOperationAction(

779 {ISD::FROUND,ISD::FPOWI,ISD::FLDEXP,ISD::FFREXP,ISD::FSINCOS}, VT,

780Expand);

781

782// These operations default to expand for vector types.

783if (VT.isVector())

784setOperationAction(

785 {ISD::FCOPYSIGN,ISD::SIGN_EXTEND_INREG,ISD::ANY_EXTEND_VECTOR_INREG,

786ISD::SIGN_EXTEND_VECTOR_INREG,ISD::ZERO_EXTEND_VECTOR_INREG,

787ISD::SPLAT_VECTOR,ISD::LRINT,ISD::LLRINT,ISD::LROUND,

788ISD::LLROUND,ISD::FTAN,ISD::FACOS,ISD::FASIN,ISD::FATAN,

789ISD::FCOSH,ISD::FSINH,ISD::FTANH,ISD::FATAN2},

790 VT,Expand);

791

792// Constrained floating-point operations default to expand.

793#define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \

794 setOperationAction(ISD::STRICT_##DAGN, VT, Expand);

795#include "llvm/IR/ConstrainedOps.def"

796

797// For most targets @llvm.get.dynamic.area.offset just returns 0.

798setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, VT,Expand);

799

800// Vector reduction default to expand.

801setOperationAction(

802 {ISD::VECREDUCE_FADD,ISD::VECREDUCE_FMUL,ISD::VECREDUCE_ADD,

803ISD::VECREDUCE_MUL,ISD::VECREDUCE_AND,ISD::VECREDUCE_OR,

804ISD::VECREDUCE_XOR,ISD::VECREDUCE_SMAX,ISD::VECREDUCE_SMIN,

805ISD::VECREDUCE_UMAX,ISD::VECREDUCE_UMIN,ISD::VECREDUCE_FMAX,

806ISD::VECREDUCE_FMIN,ISD::VECREDUCE_FMAXIMUM,ISD::VECREDUCE_FMINIMUM,

807ISD::VECREDUCE_SEQ_FADD,ISD::VECREDUCE_SEQ_FMUL},

808 VT,Expand);

809

810// Named vector shuffles default to expand.

811setOperationAction(ISD::VECTOR_SPLICE, VT,Expand);

812

813// Only some target support this vector operation. Most need to expand it.

814setOperationAction(ISD::VECTOR_COMPRESS, VT,Expand);

815

816// VP operations default to expand.

817#define BEGIN_REGISTER_VP_SDNODE(SDOPC, ...) \

818 setOperationAction(ISD::SDOPC, VT, Expand);

819#include "llvm/IR/VPIntrinsics.def"

820

821// Masked vector extracts default to expand.

822setOperationAction(ISD::VECTOR_FIND_LAST_ACTIVE, VT,Expand);

823

824// FP environment operations default to expand.

825setOperationAction(ISD::GET_FPENV, VT,Expand);

826setOperationAction(ISD::SET_FPENV, VT,Expand);

827setOperationAction(ISD::RESET_FPENV, VT,Expand);

828 }

829

830// Most targets ignore the @llvm.prefetch intrinsic.

831setOperationAction(ISD::PREFETCH, MVT::Other,Expand);

832

833// Most targets also ignore the @llvm.readcyclecounter intrinsic.

834setOperationAction(ISD::READCYCLECOUNTER, MVT::i64,Expand);

835

836// Most targets also ignore the @llvm.readsteadycounter intrinsic.

837setOperationAction(ISD::READSTEADYCOUNTER, MVT::i64,Expand);

838

839// ConstantFP nodes default to expand. Targets can either change this to

840// Legal, in which case all fp constants are legal, or use isFPImmLegal()

841// to optimize expansions for certain constants.

842setOperationAction(ISD::ConstantFP,

843 {MVT::bf16, MVT::f16, MVT::f32, MVT::f64, MVT::f80, MVT::f128},

844Expand);

845

846// These library functions default to expand.

847setOperationAction({ISD::FCBRT,ISD::FLOG,ISD::FLOG2,ISD::FLOG10,

848ISD::FEXP,ISD::FEXP2,ISD::FEXP10,ISD::FFLOOR,

849ISD::FNEARBYINT,ISD::FCEIL,ISD::FRINT,ISD::FTRUNC,

850ISD::FROUNDEVEN,ISD::FTAN,ISD::FACOS,ISD::FASIN,

851ISD::FATAN,ISD::FCOSH,ISD::FSINH,ISD::FTANH,

852ISD::FATAN2},

853 {MVT::f32, MVT::f64, MVT::f128},Expand);

854

855// FIXME: Query RuntimeLibCalls to make the decision.

856setOperationAction({ISD::LRINT,ISD::LLRINT,ISD::LROUND,ISD::LLROUND},

857 {MVT::f32, MVT::f64, MVT::f128},LibCall);

858

859setOperationAction({ISD::FTAN,ISD::FACOS,ISD::FASIN,ISD::FATAN,ISD::FCOSH,

860ISD::FSINH,ISD::FTANH,ISD::FATAN2},

861 MVT::f16,Promote);

862// Default ISD::TRAP to expand (which turns it into abort).

863setOperationAction(ISD::TRAP, MVT::Other,Expand);

864

865// On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"

866// here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.

867setOperationAction(ISD::DEBUGTRAP, MVT::Other,Expand);

868

869setOperationAction(ISD::UBSANTRAP, MVT::Other,Expand);

870

871setOperationAction(ISD::GET_FPENV_MEM, MVT::Other,Expand);

872setOperationAction(ISD::SET_FPENV_MEM, MVT::Other,Expand);

873

874for (MVT VT : {MVT::i8, MVT::i16, MVT::i32, MVT::i64}) {

875setOperationAction(ISD::GET_FPMODE, VT,Expand);

876setOperationAction(ISD::SET_FPMODE, VT,Expand);

877 }

878setOperationAction(ISD::RESET_FPMODE, MVT::Other,Expand);

879

880// This one by default will call __clear_cache unless the target

881// wants something different.

882setOperationAction(ISD::CLEAR_CACHE, MVT::Other,LibCall);

883}

884

885MVT TargetLoweringBase::getScalarShiftAmountTy(constDataLayout &DL,

886EVT) const{

887returnMVT::getIntegerVT(DL.getPointerSizeInBits(0));

888}

889

890EVT TargetLoweringBase::getShiftAmountTy(EVT LHSTy,

891constDataLayout &DL) const{

892assert(LHSTy.isInteger() &&"Shift amount is not an integer type!");

893if (LHSTy.isVector())

894return LHSTy;

895MVT ShiftVT =getScalarShiftAmountTy(DL, LHSTy);

896// If any possible shift value won't fit in the prefered type, just use

897// something safe. Assume it will be legalized when the shift is expanded.

898if (ShiftVT.getSizeInBits() <Log2_32_Ceil(LHSTy.getSizeInBits()))

899 ShiftVT = MVT::i32;

900assert(ShiftVT.getSizeInBits() >=Log2_32_Ceil(LHSTy.getSizeInBits()) &&

901"ShiftVT is still too small!");

902return ShiftVT;

903}

904

905boolTargetLoweringBase::canOpTrap(unsignedOp,EVT VT) const{

906assert(isTypeLegal(VT));

907switch (Op) {

908default:

909returnfalse;

910caseISD::SDIV:

911caseISD::UDIV:

912caseISD::SREM:

913caseISD::UREM:

914returntrue;

915 }

916}

917

918boolTargetLoweringBase::isFreeAddrSpaceCast(unsigned SrcAS,

919unsigned DestAS) const{

920return TM.isNoopAddrSpaceCast(SrcAS, DestAS);

921}

922

923unsignedTargetLoweringBase::getBitWidthForCttzElements(

924Type *RetTy,ElementCount EC,bool ZeroIsPoison,

925constConstantRange *VScaleRange) const{

926// Find the smallest "sensible" element type to use for the expansion.

927ConstantRange CR(APInt(64, EC.getKnownMinValue()));

928if (EC.isScalable())

929 CR = CR.umul_sat(*VScaleRange);

930

931if (ZeroIsPoison)

932 CR = CR.subtract(APInt(64, 1));

933

934unsigned EltWidth =RetTy->getScalarSizeInBits();

935 EltWidth = std::min(EltWidth, (unsigned)CR.getActiveBits());

936 EltWidth = std::max(llvm::bit_ceil(EltWidth), (unsigned)8);

937

938return EltWidth;

939}

940

941voidTargetLoweringBase::setJumpIsExpensive(bool isExpensive) {

942// If the command-line option was specified, ignore this request.

943if (!JumpIsExpensiveOverride.getNumOccurrences())

944 JumpIsExpensive = isExpensive;

945}

946

947TargetLoweringBase::LegalizeKind

948TargetLoweringBase::getTypeConversion(LLVMContext &Context,EVT VT) const{

949// If this is a simple type, use the ComputeRegisterProp mechanism.

950if (VT.isSimple()) {

951MVT SVT = VT.getSimpleVT();

952assert((unsigned)SVT.SimpleTy < std::size(TransformToType));

953MVT NVT = TransformToType[SVT.SimpleTy];

954LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT);

955

956assert((LA ==TypeLegal || LA ==TypeSoftenFloat ||

957 LA ==TypeSoftPromoteHalf ||

958 (NVT.isVector() ||

959 ValueTypeActions.getTypeAction(NVT) !=TypePromoteInteger)) &&

960"Promote may not follow Expand or Promote");

961

962if (LA ==TypeSplitVector)

963returnLegalizeKind(LA,EVT(SVT).getHalfNumVectorElementsVT(Context));

964if (LA ==TypeScalarizeVector)

965returnLegalizeKind(LA, SVT.getVectorElementType());

966returnLegalizeKind(LA, NVT);

967 }

968

969// Handle Extended Scalar Types.

970if (!VT.isVector()) {

971assert(VT.isInteger() &&"Float types must be simple");

972unsigned BitSize = VT.getSizeInBits();

973// First promote to a power-of-two size, then expand if necessary.

974if (BitSize < 8 || !isPowerOf2_32(BitSize)) {

975EVT NVT = VT.getRoundIntegerType(Context);

976assert(NVT != VT &&"Unable to round integer VT");

977LegalizeKind NextStep =getTypeConversion(Context, NVT);

978// Avoid multi-step promotion.

979if (NextStep.first ==TypePromoteInteger)

980return NextStep;

981// Return rounded integer type.

982returnLegalizeKind(TypePromoteInteger, NVT);

983 }

984

985returnLegalizeKind(TypeExpandInteger,

986EVT::getIntegerVT(Context, VT.getSizeInBits() / 2));

987 }

988

989// Handle vector types.

990ElementCount NumElts = VT.getVectorElementCount();

991EVT EltVT = VT.getVectorElementType();

992

993// Vectors with only one element are always scalarized.

994if (NumElts.isScalar())

995returnLegalizeKind(TypeScalarizeVector, EltVT);

996

997// Try to widen vector elements until the element type is a power of two and

998// promote it to a legal type later on, for example:

999// <3 x i8> -> <4 x i8> -> <4 x i32>

1000if (EltVT.isInteger()) {

1001// Vectors with a number of elements that is not a power of two are always

1002// widened, for example <3 x i8> -> <4 x i8>.

1003if (!VT.isPow2VectorType()) {

1004 NumElts = NumElts.coefficientNextPowerOf2();

1005EVT NVT =EVT::getVectorVT(Context, EltVT, NumElts);

1006returnLegalizeKind(TypeWidenVector, NVT);

1007 }

1008

1009// Examine the element type.

1010LegalizeKind LK =getTypeConversion(Context, EltVT);

1011

1012// If type is to be expanded, split the vector.

1013// <4 x i140> -> <2 x i140>

1014if (LK.first ==TypeExpandInteger) {

1015if (VT.getVectorElementCount().isScalable())

1016returnLegalizeKind(TypeScalarizeScalableVector, EltVT);

1017returnLegalizeKind(TypeSplitVector,

1018 VT.getHalfNumVectorElementsVT(Context));

1019 }

1020

1021// Promote the integer element types until a legal vector type is found

1022// or until the element integer type is too big. If a legal type was not

1023// found, fallback to the usual mechanism of widening/splitting the

1024// vector.

1025EVT OldEltVT = EltVT;

1026while (true) {

1027// Increase the bitwidth of the element to the next pow-of-two

1028// (which is greater than 8 bits).

1029 EltVT =EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits())

1030 .getRoundIntegerType(Context);

1031

1032// Stop trying when getting a non-simple element type.

1033// Note that vector elements may be greater than legal vector element

1034// types. Example: X86 XMM registers hold 64bit element on 32bit

1035// systems.

1036if (!EltVT.isSimple())

1037break;

1038

1039// Build a new vector type and check if it is legal.

1040MVT NVT =MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);

1041// Found a legal promoted vector type.

1042if (NVT !=MVT() && ValueTypeActions.getTypeAction(NVT) ==TypeLegal)

1043returnLegalizeKind(TypePromoteInteger,

1044EVT::getVectorVT(Context, EltVT, NumElts));

1045 }

1046

1047// Reset the type to the unexpanded type if we did not find a legal vector

1048// type with a promoted vector element type.

1049 EltVT = OldEltVT;

1050 }

1051

1052// Try to widen the vector until a legal type is found.

1053// If there is no wider legal type, split the vector.

1054while (true) {

1055// Round up to the next power of 2.

1056 NumElts = NumElts.coefficientNextPowerOf2();

1057

1058// If there is no simple vector type with this many elements then there

1059// cannot be a larger legal vector type. Note that this assumes that

1060// there are no skipped intermediate vector types in the simple types.

1061if (!EltVT.isSimple())

1062break;

1063MVT LargerVector =MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);

1064if (LargerVector ==MVT())

1065break;

1066

1067// If this type is legal then widen the vector.

1068if (ValueTypeActions.getTypeAction(LargerVector) ==TypeLegal)

1069returnLegalizeKind(TypeWidenVector, LargerVector);

1070 }

1071

1072// Widen odd vectors to next power of two.

1073if (!VT.isPow2VectorType()) {

1074EVT NVT = VT.getPow2VectorType(Context);

1075returnLegalizeKind(TypeWidenVector, NVT);

1076 }

1077

1078if (VT.getVectorElementCount() ==ElementCount::getScalable(1))

1079returnLegalizeKind(TypeScalarizeScalableVector, EltVT);

1080

1081// Vectors with illegal element types are expanded.

1082EVT NVT =EVT::getVectorVT(Context, EltVT,

1083 VT.getVectorElementCount().divideCoefficientBy(2));

1084returnLegalizeKind(TypeSplitVector, NVT);

1085}

1086

1087staticunsignedgetVectorTypeBreakdownMVT(MVT VT,MVT &IntermediateVT,

1088unsigned &NumIntermediates,

1089MVT &RegisterVT,

1090TargetLoweringBase *TLI) {

1091// Figure out the right, legal destination reg to copy into.

1092ElementCount EC = VT.getVectorElementCount();

1093MVT EltTy = VT.getVectorElementType();

1094

1095unsigned NumVectorRegs = 1;

1096

1097// Scalable vectors cannot be scalarized, so splitting or widening is

1098// required.

1099if (VT.isScalableVector() && !isPowerOf2_32(EC.getKnownMinValue()))

1100llvm_unreachable(

1101"Splitting or widening of non-power-of-2 MVTs is not implemented.");

1102

1103// FIXME: We don't support non-power-of-2-sized vectors for now.

1104// Ideally we could break down into LHS/RHS like LegalizeDAG does.

1105if (!isPowerOf2_32(EC.getKnownMinValue())) {

1106// Split EC to unit size (scalable property is preserved).

1107 NumVectorRegs = EC.getKnownMinValue();

1108 EC =ElementCount::getFixed(1);

1109 }

1110

1111// Divide the input until we get to a supported size. This will

1112// always end up with an EC that represent a scalar or a scalable

1113// scalar.

1114while (EC.getKnownMinValue() > 1 &&

1115 !TLI->isTypeLegal(MVT::getVectorVT(EltTy, EC))) {

1116 EC = EC.divideCoefficientBy(2);

1117 NumVectorRegs <<= 1;

1118 }

1119

1120 NumIntermediates = NumVectorRegs;

1121

1122MVT NewVT =MVT::getVectorVT(EltTy, EC);

1123if (!TLI->isTypeLegal(NewVT))

1124 NewVT = EltTy;

1125 IntermediateVT = NewVT;

1126

1127unsigned LaneSizeInBits = NewVT.getScalarSizeInBits();

1128

1129// Convert sizes such as i33 to i64.

1130 LaneSizeInBits =llvm::bit_ceil(LaneSizeInBits);

1131

1132MVT DestVT = TLI->getRegisterType(NewVT);

1133 RegisterVT = DestVT;

1134if (EVT(DestVT).bitsLT(NewVT))// Value is expanded, e.g. i64 -> i16.

1135return NumVectorRegs * (LaneSizeInBits / DestVT.getScalarSizeInBits());

1136

1137// Otherwise, promotion or legal types use the same number of registers as

1138// the vector decimated to the appropriate level.

1139return NumVectorRegs;

1140}

1141

1142/// isLegalRC - Return true if the value types that can be represented by the

1143/// specified register class are all legal.

1144boolTargetLoweringBase::isLegalRC(constTargetRegisterInfo &TRI,

1145constTargetRegisterClass &RC) const{

1146for (constauto *I =TRI.legalclasstypes_begin(RC); *I != MVT::Other; ++I)

1147if (isTypeLegal(*I))

1148returntrue;

1149returnfalse;

1150}

1151

1152/// Replace/modify any TargetFrameIndex operands with a targte-dependent

1153/// sequence of memory operands that is recognized by PrologEpilogInserter.

1154MachineBasicBlock *

1155TargetLoweringBase::emitPatchPoint(MachineInstr &InitialMI,

1156MachineBasicBlock *MBB) const{

1157MachineInstr *MI = &InitialMI;

1158MachineFunction &MF = *MI->getMF();

1159MachineFrameInfo &MFI = MF.getFrameInfo();

1160

1161// We're handling multiple types of operands here:

1162// PATCHPOINT MetaArgs - live-in, read only, direct

1163// STATEPOINT Deopt Spill - live-through, read only, indirect

1164// STATEPOINT Deopt Alloca - live-through, read only, direct

1165// (We're currently conservative and mark the deopt slots read/write in

1166// practice.)

1167// STATEPOINT GC Spill - live-through, read/write, indirect

1168// STATEPOINT GC Alloca - live-through, read/write, direct

1169// The live-in vs live-through is handled already (the live through ones are

1170// all stack slots), but we need to handle the different type of stackmap

1171// operands and memory effects here.

1172

1173if (llvm::none_of(MI->operands(),

1174 [](MachineOperand &Operand) { return Operand.isFI(); }))

1175returnMBB;

1176

1177MachineInstrBuilder MIB =BuildMI(MF,MI->getDebugLoc(),MI->getDesc());

1178

1179// Inherit previous memory operands.

1180 MIB.cloneMemRefs(*MI);

1181

1182for (unsigned i = 0; i <MI->getNumOperands(); ++i) {

1183MachineOperand &MO =MI->getOperand(i);

1184if (!MO.isFI()) {

1185// Index of Def operand this Use it tied to.

1186// Since Defs are coming before Uses, if Use is tied, then

1187// index of Def must be smaller that index of that Use.

1188// Also, Defs preserve their position in new MI.

1189unsigned TiedTo = i;

1190if (MO.isReg() && MO.isTied())

1191 TiedTo =MI->findTiedOperandIdx(i);

1192 MIB.add(MO);

1193if (TiedTo < i)

1194 MIB->tieOperands(TiedTo, MIB->getNumOperands() - 1);

1195continue;

1196 }

1197

1198// foldMemoryOperand builds a new MI after replacing a single FI operand

1199// with the canonical set of five x86 addressing-mode operands.

1200int FI = MO.getIndex();

1201

1202// Add frame index operands recognized by stackmaps.cpp

1203if (MFI.isStatepointSpillSlotObjectIndex(FI)) {

1204// indirect-mem-ref tag, size, #FI, offset.

1205// Used for spills inserted by StatepointLowering. This codepath is not

1206// used for patchpoints/stackmaps at all, for these spilling is done via

1207// foldMemoryOperand callback only.

1208assert(MI->getOpcode() == TargetOpcode::STATEPOINT &&"sanity");

1209 MIB.addImm(StackMaps::IndirectMemRefOp);

1210 MIB.addImm(MFI.getObjectSize(FI));

1211 MIB.add(MO);

1212 MIB.addImm(0);

1213 }else {

1214// direct-mem-ref tag, #FI, offset.

1215// Used by patchpoint, and direct alloca arguments to statepoints

1216 MIB.addImm(StackMaps::DirectMemRefOp);

1217 MIB.add(MO);

1218 MIB.addImm(0);

1219 }

1220

1221assert(MIB->mayLoad() &&"Folded a stackmap use to a non-load!");

1222

1223// Add a new memory operand for this FI.

1224assert(MFI.getObjectOffset(FI) != -1);

1225

1226// Note: STATEPOINT MMOs are added during SelectionDAG. STACKMAP, and

1227// PATCHPOINT should be updated to do the same. (TODO)

1228if (MI->getOpcode() != TargetOpcode::STATEPOINT) {

1229auto Flags =MachineMemOperand::MOLoad;

1230MachineMemOperand *MMO = MF.getMachineMemOperand(

1231MachinePointerInfo::getFixedStack(MF, FI), Flags,

1232 MF.getDataLayout().getPointerSize(), MFI.getObjectAlign(FI));

1233 MIB->addMemOperand(MF, MMO);

1234 }

1235 }

1236MBB->insert(MachineBasicBlock::iterator(MI), MIB);

1237MI->eraseFromParent();

1238returnMBB;

1239}

1240

1241/// findRepresentativeClass - Return the largest legal super-reg register class

1242/// of the register class for the specified type and its associated "cost".

1243// This function is in TargetLowering because it uses RegClassForVT which would

1244// need to be moved to TargetRegisterInfo and would necessitate moving

1245// isTypeLegal over as well - a massive change that would just require

1246// TargetLowering having a TargetRegisterInfo class member that it would use.

1247std::pair<const TargetRegisterClass *, uint8_t>

1248TargetLoweringBase::findRepresentativeClass(constTargetRegisterInfo *TRI,

1249MVT VT) const{

1250constTargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];

1251if (!RC)

1252return std::make_pair(RC, 0);

1253

1254// Compute the set of all super-register classes.

1255BitVector SuperRegRC(TRI->getNumRegClasses());

1256for (SuperRegClassIterator RCI(RC,TRI); RCI.isValid(); ++RCI)

1257 SuperRegRC.setBitsInMask(RCI.getMask());

1258

1259// Find the first legal register class with the largest spill size.

1260constTargetRegisterClass *BestRC = RC;

1261for (unsigned i : SuperRegRC.set_bits()) {

1262constTargetRegisterClass *SuperRC =TRI->getRegClass(i);

1263// We want the largest possible spill size.

1264if (TRI->getSpillSize(*SuperRC) <=TRI->getSpillSize(*BestRC))

1265continue;

1266if (!isLegalRC(*TRI, *SuperRC))

1267continue;

1268 BestRC = SuperRC;

1269 }

1270return std::make_pair(BestRC, 1);

1271}

1272

1273/// computeRegisterProperties - Once all of the register classes are added,

1274/// this allows us to compute derived properties we expose.

1275voidTargetLoweringBase::computeRegisterProperties(

1276constTargetRegisterInfo *TRI) {

1277// Everything defaults to needing one register.

1278for (unsigned i = 0; i !=MVT::VALUETYPE_SIZE; ++i) {

1279 NumRegistersForVT[i] = 1;

1280 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;

1281 }

1282// ...except isVoid, which doesn't need any registers.

1283 NumRegistersForVT[MVT::isVoid] = 0;

1284

1285// Find the largest integer register class.

1286unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;

1287for (; RegClassForVT[LargestIntReg] ==nullptr; --LargestIntReg)

1288assert(LargestIntReg != MVT::i1 &&"No integer registers defined!");

1289

1290// Every integer value type larger than this largest register takes twice as

1291// many registers to represent as the previous ValueType.

1292for (unsigned ExpandedReg = LargestIntReg + 1;

1293 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {

1294 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];

1295 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;

1296 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);

1297 ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg,

1298TypeExpandInteger);

1299 }

1300

1301// Inspect all of the ValueType's smaller than the largest integer

1302// register to see which ones need promotion.

1303unsigned LegalIntReg = LargestIntReg;

1304for (unsigned IntReg = LargestIntReg - 1;

1305 IntReg >= (unsigned)MVT::i1; --IntReg) {

1306MVT IVT = (MVT::SimpleValueType)IntReg;

1307if (isTypeLegal(IVT)) {

1308 LegalIntReg = IntReg;

1309 }else {

1310 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =

1311 (MVT::SimpleValueType)LegalIntReg;

1312 ValueTypeActions.setTypeAction(IVT,TypePromoteInteger);

1313 }

1314 }

1315

1316// ppcf128 type is really two f64's.

1317if (!isTypeLegal(MVT::ppcf128)) {

1318if (isTypeLegal(MVT::f64)) {

1319 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];

1320 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;

1321 TransformToType[MVT::ppcf128] = MVT::f64;

1322 ValueTypeActions.setTypeAction(MVT::ppcf128,TypeExpandFloat);

1323 }else {

1324 NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128];

1325 RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128];

1326 TransformToType[MVT::ppcf128] = MVT::i128;

1327 ValueTypeActions.setTypeAction(MVT::ppcf128,TypeSoftenFloat);

1328 }

1329 }

1330

1331// Decide how to handle f128. If the target does not have native f128 support,

1332// expand it to i128 and we will be generating soft float library calls.

1333if (!isTypeLegal(MVT::f128)) {

1334 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];

1335 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];

1336 TransformToType[MVT::f128] = MVT::i128;

1337 ValueTypeActions.setTypeAction(MVT::f128,TypeSoftenFloat);

1338 }

1339

1340// Decide how to handle f80. If the target does not have native f80 support,

1341// expand it to i96 and we will be generating soft float library calls.

1342if (!isTypeLegal(MVT::f80)) {

1343 NumRegistersForVT[MVT::f80] = 3*NumRegistersForVT[MVT::i32];

1344 RegisterTypeForVT[MVT::f80] = RegisterTypeForVT[MVT::i32];

1345 TransformToType[MVT::f80] = MVT::i32;

1346 ValueTypeActions.setTypeAction(MVT::f80,TypeSoftenFloat);

1347 }

1348

1349// Decide how to handle f64. If the target does not have native f64 support,

1350// expand it to i64 and we will be generating soft float library calls.

1351if (!isTypeLegal(MVT::f64)) {

1352 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];

1353 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];

1354 TransformToType[MVT::f64] = MVT::i64;

1355 ValueTypeActions.setTypeAction(MVT::f64,TypeSoftenFloat);

1356 }

1357

1358// Decide how to handle f32. If the target does not have native f32 support,

1359// expand it to i32 and we will be generating soft float library calls.

1360if (!isTypeLegal(MVT::f32)) {

1361 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];

1362 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];

1363 TransformToType[MVT::f32] = MVT::i32;

1364 ValueTypeActions.setTypeAction(MVT::f32,TypeSoftenFloat);

1365 }

1366

1367// Decide how to handle f16. If the target does not have native f16 support,

1368// promote it to f32, because there are no f16 library calls (except for

1369// conversions).

1370if (!isTypeLegal(MVT::f16)) {

1371// Allow targets to control how we legalize half.

1372bool SoftPromoteHalfType =softPromoteHalfType();

1373bool UseFPRegsForHalfType = !SoftPromoteHalfType ||useFPRegsForHalfType();

1374

1375if (!UseFPRegsForHalfType) {

1376 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::i16];

1377 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::i16];

1378 }else {

1379 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32];

1380 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32];

1381 }

1382 TransformToType[MVT::f16] = MVT::f32;

1383if (SoftPromoteHalfType) {

1384 ValueTypeActions.setTypeAction(MVT::f16,TypeSoftPromoteHalf);

1385 }else {

1386 ValueTypeActions.setTypeAction(MVT::f16,TypePromoteFloat);

1387 }

1388 }

1389

1390// Decide how to handle bf16. If the target does not have native bf16 support,

1391// promote it to f32, because there are no bf16 library calls (except for

1392// converting from f32 to bf16).

1393if (!isTypeLegal(MVT::bf16)) {

1394 NumRegistersForVT[MVT::bf16] = NumRegistersForVT[MVT::f32];

1395 RegisterTypeForVT[MVT::bf16] = RegisterTypeForVT[MVT::f32];

1396 TransformToType[MVT::bf16] = MVT::f32;

1397 ValueTypeActions.setTypeAction(MVT::bf16,TypeSoftPromoteHalf);

1398 }

1399

1400// Loop over all of the vector value types to see which need transformations.

1401for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;

1402 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {

1403MVT VT = (MVT::SimpleValueType) i;

1404if (isTypeLegal(VT))

1405continue;

1406

1407MVT EltVT = VT.getVectorElementType();

1408ElementCount EC = VT.getVectorElementCount();

1409bool IsLegalWiderType =false;

1410bool IsScalable = VT.isScalableVector();

1411LegalizeTypeAction PreferredAction =getPreferredVectorAction(VT);

1412switch (PreferredAction) {

1413caseTypePromoteInteger: {

1414MVT::SimpleValueType EndVT = IsScalable ?

1415 MVT::LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE :

1416 MVT::LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE;

1417// Try to promote the elements of integer vectors. If no legal

1418// promotion was found, fall through to the widen-vector method.

1419for (unsigned nVT = i + 1;

1420 (MVT::SimpleValueType)nVT <= EndVT; ++nVT) {

1421MVT SVT = (MVT::SimpleValueType) nVT;

1422// Promote vectors of integers to vectors with the same number

1423// of elements, with a wider element type.

1424if (SVT.getScalarSizeInBits() > EltVT.getFixedSizeInBits() &&

1425 SVT.getVectorElementCount() == EC &&isTypeLegal(SVT)) {

1426 TransformToType[i] = SVT;

1427 RegisterTypeForVT[i] = SVT;

1428 NumRegistersForVT[i] = 1;

1429 ValueTypeActions.setTypeAction(VT,TypePromoteInteger);

1430 IsLegalWiderType =true;

1431break;

1432 }

1433 }

1434if (IsLegalWiderType)

1435break;

1436 [[fallthrough]];

1437 }

1438

1439caseTypeWidenVector:

1440if (isPowerOf2_32(EC.getKnownMinValue())) {

1441// Try to widen the vector.

1442for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {

1443MVT SVT = (MVT::SimpleValueType) nVT;

1444if (SVT.getVectorElementType() == EltVT &&

1445 SVT.isScalableVector() == IsScalable &&

1446 SVT.getVectorElementCount().getKnownMinValue() >

1447 EC.getKnownMinValue() &&

1448isTypeLegal(SVT)) {

1449 TransformToType[i] = SVT;

1450 RegisterTypeForVT[i] = SVT;

1451 NumRegistersForVT[i] = 1;

1452 ValueTypeActions.setTypeAction(VT,TypeWidenVector);

1453 IsLegalWiderType =true;

1454break;

1455 }

1456 }

1457if (IsLegalWiderType)

1458break;

1459 }else {

1460// Only widen to the next power of 2 to keep consistency with EVT.

1461MVT NVT = VT.getPow2VectorType();

1462if (isTypeLegal(NVT)) {

1463 TransformToType[i] = NVT;

1464 ValueTypeActions.setTypeAction(VT,TypeWidenVector);

1465 RegisterTypeForVT[i] = NVT;

1466 NumRegistersForVT[i] = 1;

1467break;

1468 }

1469 }

1470 [[fallthrough]];

1471

1472caseTypeSplitVector:

1473caseTypeScalarizeVector: {

1474MVT IntermediateVT;

1475MVT RegisterVT;

1476unsigned NumIntermediates;

1477unsigned NumRegisters =getVectorTypeBreakdownMVT(VT, IntermediateVT,

1478 NumIntermediates, RegisterVT,this);

1479 NumRegistersForVT[i] = NumRegisters;

1480assert(NumRegistersForVT[i] == NumRegisters &&

1481"NumRegistersForVT size cannot represent NumRegisters!");

1482 RegisterTypeForVT[i] = RegisterVT;

1483

1484MVT NVT = VT.getPow2VectorType();

1485if (NVT == VT) {

1486// Type is already a power of 2. The default action is to split.

1487 TransformToType[i] = MVT::Other;

1488if (PreferredAction ==TypeScalarizeVector)

1489 ValueTypeActions.setTypeAction(VT,TypeScalarizeVector);

1490elseif (PreferredAction ==TypeSplitVector)

1491 ValueTypeActions.setTypeAction(VT,TypeSplitVector);

1492elseif (EC.getKnownMinValue() > 1)

1493 ValueTypeActions.setTypeAction(VT,TypeSplitVector);

1494else

1495 ValueTypeActions.setTypeAction(VT, EC.isScalable()

1496 ?TypeScalarizeScalableVector

1497 :TypeScalarizeVector);

1498 }else {

1499 TransformToType[i] = NVT;

1500 ValueTypeActions.setTypeAction(VT,TypeWidenVector);

1501 }

1502break;

1503 }

1504default:

1505llvm_unreachable("Unknown vector legalization action!");

1506 }

1507 }

1508

1509// Determine the 'representative' register class for each value type.

1510// An representative register class is the largest (meaning one which is

1511// not a sub-register class / subreg register class) legal register class for

1512// a group of value types. For example, on i386, i8, i16, and i32

1513// representative would be GR32; while on x86_64 it's GR64.

1514for (unsigned i = 0; i !=MVT::VALUETYPE_SIZE; ++i) {

1515constTargetRegisterClass* RRC;

1516uint8_t Cost;

1517 std::tie(RRC,Cost) =findRepresentativeClass(TRI, (MVT::SimpleValueType)i);

1518 RepRegClassForVT[i] = RRC;

1519 RepRegClassCostForVT[i] =Cost;

1520 }

1521}

1522

1523EVT TargetLoweringBase::getSetCCResultType(constDataLayout &DL,LLVMContext &,

1524EVT VT) const{

1525assert(!VT.isVector() &&"No default SetCC type for vectors!");

1526returngetPointerTy(DL).SimpleTy;

1527}

1528

1529MVT::SimpleValueType TargetLoweringBase::getCmpLibcallReturnType() const{

1530return MVT::i32;// return the default value

1531}

1532

1533/// getVectorTypeBreakdown - Vector types are broken down into some number of

1534/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32

1535/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.

1536/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.

1537///

1538/// This method returns the number of registers needed, and the VT for each

1539/// register. It also returns the VT and quantity of the intermediate values

1540/// before they are promoted/expanded.

1541unsignedTargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context,

1542EVT VT,EVT &IntermediateVT,

1543unsigned &NumIntermediates,

1544MVT &RegisterVT) const{

1545ElementCount EltCnt = VT.getVectorElementCount();

1546

1547// If there is a wider vector type with the same element type as this one,

1548// or a promoted vector type that has the same number of elements which

1549// are wider, then we should convert to that legal vector type.

1550// This handles things like <2 x float> -> <4 x float> and

1551// <4 x i1> -> <4 x i32>.

1552LegalizeTypeAction TA =getTypeAction(Context, VT);

1553if (!EltCnt.isScalar() &&

1554 (TA ==TypeWidenVector || TA ==TypePromoteInteger)) {

1555EVT RegisterEVT =getTypeToTransformTo(Context, VT);

1556if (isTypeLegal(RegisterEVT)) {

1557 IntermediateVT = RegisterEVT;

1558 RegisterVT = RegisterEVT.getSimpleVT();

1559 NumIntermediates = 1;

1560return 1;

1561 }

1562 }

1563

1564// Figure out the right, legal destination reg to copy into.

1565EVT EltTy = VT.getVectorElementType();

1566

1567unsigned NumVectorRegs = 1;

1568

1569// Scalable vectors cannot be scalarized, so handle the legalisation of the

1570// types like done elsewhere in SelectionDAG.

1571if (EltCnt.isScalable()) {

1572LegalizeKind LK;

1573EVT PartVT = VT;

1574do {

1575// Iterate until we've found a legal (part) type to hold VT.

1576 LK =getTypeConversion(Context, PartVT);

1577 PartVT = LK.second;

1578 }while (LK.first !=TypeLegal);

1579

1580if (!PartVT.isVector()) {

1581report_fatal_error(

1582"Don't know how to legalize this scalable vector type");

1583 }

1584

1585 NumIntermediates =

1586divideCeil(VT.getVectorElementCount().getKnownMinValue(),

1587 PartVT.getVectorElementCount().getKnownMinValue());

1588 IntermediateVT = PartVT;

1589 RegisterVT =getRegisterType(Context, IntermediateVT);

1590return NumIntermediates;

1591 }

1592

1593// FIXME: We don't support non-power-of-2-sized vectors for now. Ideally

1594// we could break down into LHS/RHS like LegalizeDAG does.

1595if (!isPowerOf2_32(EltCnt.getKnownMinValue())) {

1596 NumVectorRegs = EltCnt.getKnownMinValue();

1597 EltCnt =ElementCount::getFixed(1);

1598 }

1599

1600// Divide the input until we get to a supported size. This will always

1601// end with a scalar if the target doesn't support vectors.

1602while (EltCnt.getKnownMinValue() > 1 &&

1603 !isTypeLegal(EVT::getVectorVT(Context, EltTy, EltCnt))) {

1604 EltCnt = EltCnt.divideCoefficientBy(2);

1605 NumVectorRegs <<= 1;

1606 }

1607

1608 NumIntermediates = NumVectorRegs;

1609

1610EVT NewVT =EVT::getVectorVT(Context, EltTy, EltCnt);

1611if (!isTypeLegal(NewVT))

1612 NewVT = EltTy;

1613 IntermediateVT = NewVT;

1614

1615MVT DestVT =getRegisterType(Context, NewVT);

1616 RegisterVT = DestVT;

1617

1618if (EVT(DestVT).bitsLT(NewVT)) {// Value is expanded, e.g. i64 -> i16.

1619TypeSize NewVTSize = NewVT.getSizeInBits();

1620// Convert sizes such as i33 to i64.

1621if (!llvm::has_single_bit<uint32_t>(NewVTSize.getKnownMinValue()))

1622 NewVTSize = NewVTSize.coefficientNextPowerOf2();

1623return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());

1624 }

1625

1626// Otherwise, promotion or legal types use the same number of registers as

1627// the vector decimated to the appropriate level.

1628return NumVectorRegs;

1629}

1630

1631boolTargetLoweringBase::isSuitableForJumpTable(constSwitchInst *SI,

1632uint64_t NumCases,

1633uint64_t Range,

1634ProfileSummaryInfo *PSI,

1635BlockFrequencyInfo *BFI) const{

1636// FIXME: This function check the maximum table size and density, but the

1637// minimum size is not checked. It would be nice if the minimum size is

1638// also combined within this function. Currently, the minimum size check is

1639// performed in findJumpTable() in SelectionDAGBuiler and

1640// getEstimatedNumberOfCaseClusters() in BasicTTIImpl.

1641constbool OptForSize =

1642llvm::shouldOptimizeForSize(SI->getParent(), PSI, BFI);

1643constunsigned MinDensity =getMinimumJumpTableDensity(OptForSize);

1644constunsigned MaxJumpTableSize =getMaximumJumpTableSize();

1645

1646// Check whether the number of cases is small enough and

1647// the range is dense enough for a jump table.

1648return (OptForSize ||Range <= MaxJumpTableSize) &&

1649 (NumCases * 100 >=Range * MinDensity);

1650}

1651

1652MVT TargetLoweringBase::getPreferredSwitchConditionType(LLVMContext &Context,

1653EVT ConditionVT) const{

1654returngetRegisterType(Context, ConditionVT);

1655}

1656

1657/// Get the EVTs and ArgFlags collections that represent the legalized return

1658/// type of the given function. This does not require a DAG or a return value,

1659/// and is suitable for use before any DAGs for the function are constructed.

1660/// TODO: Move this out of TargetLowering.cpp.

1661voidllvm::GetReturnInfo(CallingConv::ID CC,Type *ReturnType,

1662AttributeList attr,

1663SmallVectorImpl<ISD::OutputArg> &Outs,

1664constTargetLowering &TLI,constDataLayout &DL) {

1665SmallVector<EVT, 4> ValueVTs;

1666ComputeValueVTs(TLI,DL, ReturnType, ValueVTs);

1667unsigned NumValues = ValueVTs.size();

1668if (NumValues == 0)return;

1669

1670for (unsigned j = 0, f = NumValues; j != f; ++j) {

1671EVT VT = ValueVTs[j];

1672ISD::NodeType ExtendKind =ISD::ANY_EXTEND;

1673

1674if (attr.hasRetAttr(Attribute::SExt))

1675 ExtendKind =ISD::SIGN_EXTEND;

1676elseif (attr.hasRetAttr(Attribute::ZExt))

1677 ExtendKind =ISD::ZERO_EXTEND;

1678

1679if (ExtendKind !=ISD::ANY_EXTEND && VT.isInteger())

1680 VT = TLI.getTypeForExtReturn(ReturnType->getContext(), VT, ExtendKind);

1681

1682unsigned NumParts =

1683 TLI.getNumRegistersForCallingConv(ReturnType->getContext(),CC, VT);

1684MVT PartVT =

1685 TLI.getRegisterTypeForCallingConv(ReturnType->getContext(),CC, VT);

1686

1687// 'inreg' on function refers to return value

1688ISD::ArgFlagsTy Flags =ISD::ArgFlagsTy();

1689if (attr.hasRetAttr(Attribute::InReg))

1690 Flags.setInReg();

1691

1692// Propagate extension type if any

1693if (attr.hasRetAttr(Attribute::SExt))

1694 Flags.setSExt();

1695elseif (attr.hasRetAttr(Attribute::ZExt))

1696 Flags.setZExt();

1697

1698for (unsigned i = 0; i < NumParts; ++i)

1699 Outs.push_back(ISD::OutputArg(Flags, PartVT, VT,/*isfixed=*/true, 0, 0));

1700 }

1701}

1702

1703Align TargetLoweringBase::getByValTypeAlignment(Type *Ty,

1704constDataLayout &DL) const{

1705returnDL.getABITypeAlign(Ty);

1706}

1707

1708boolTargetLoweringBase::allowsMemoryAccessForAlignment(

1709LLVMContext &Context,constDataLayout &DL,EVT VT,unsigned AddrSpace,

1710Align Alignment,MachineMemOperand::Flags Flags,unsigned *Fast) const{

1711// Check if the specified alignment is sufficient based on the data layout.

1712// TODO: While using the data layout works in practice, a better solution

1713// would be to implement this check directly (make this a virtual function).

1714// For example, the ABI alignment may change based on software platform while

1715// this function should only be affected by hardware implementation.

1716Type *Ty = VT.getTypeForEVT(Context);

1717if (VT.isZeroSized() || Alignment >=DL.getABITypeAlign(Ty)) {

1718// Assume that an access that meets the ABI-specified alignment is fast.

1719if (Fast !=nullptr)

1720 *Fast = 1;

1721returntrue;

1722 }

1723

1724// This is a misaligned access.

1725returnallowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment, Flags,Fast);

1726}

1727

1728boolTargetLoweringBase::allowsMemoryAccessForAlignment(

1729LLVMContext &Context,constDataLayout &DL,EVT VT,

1730constMachineMemOperand &MMO,unsigned *Fast) const{

1731returnallowsMemoryAccessForAlignment(Context,DL, VT, MMO.getAddrSpace(),

1732 MMO.getAlign(), MMO.getFlags(),Fast);

1733}

1734

1735boolTargetLoweringBase::allowsMemoryAccess(LLVMContext &Context,

1736constDataLayout &DL,EVT VT,

1737unsigned AddrSpace,Align Alignment,

1738MachineMemOperand::Flags Flags,

1739unsigned *Fast) const{

1740returnallowsMemoryAccessForAlignment(Context,DL, VT, AddrSpace, Alignment,

1741 Flags,Fast);

1742}

1743

1744boolTargetLoweringBase::allowsMemoryAccess(LLVMContext &Context,

1745constDataLayout &DL,EVT VT,

1746constMachineMemOperand &MMO,

1747unsigned *Fast) const{

1748returnallowsMemoryAccess(Context,DL, VT, MMO.getAddrSpace(), MMO.getAlign(),

1749 MMO.getFlags(),Fast);

1750}

1751

1752boolTargetLoweringBase::allowsMemoryAccess(LLVMContext &Context,

1753constDataLayout &DL,LLT Ty,

1754constMachineMemOperand &MMO,

1755unsigned *Fast) const{

1756EVT VT =getApproximateEVTForLLT(Ty, Context);

1757returnallowsMemoryAccess(Context,DL, VT, MMO.getAddrSpace(), MMO.getAlign(),

1758 MMO.getFlags(),Fast);

1759}

1760

1761//===----------------------------------------------------------------------===//

1762// TargetTransformInfo Helpers

1763//===----------------------------------------------------------------------===//

1764

1765intTargetLoweringBase::InstructionOpcodeToISD(unsigned Opcode) const{

1766enum InstructionOpcodes {

1767#define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,

1768#define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM

1769#include "llvm/IR/Instruction.def"

1770 };

1771switch (static_cast<InstructionOpcodes>(Opcode)) {

1772case Ret:return 0;

1773case Br:return 0;

1774case Switch:return 0;

1775case IndirectBr:return 0;

1776case Invoke:return 0;

1777case CallBr:return 0;

1778case Resume:return 0;

1779case Unreachable:return 0;

1780case CleanupRet:return 0;

1781case CatchRet:return 0;

1782case CatchPad:return 0;

1783case CatchSwitch:return 0;

1784case CleanupPad:return 0;

1785case FNeg:returnISD::FNEG;

1786caseAdd:returnISD::ADD;

1787caseFAdd:returnISD::FADD;

1788case Sub:returnISD::SUB;

1789case FSub:returnISD::FSUB;

1790caseMul:returnISD::MUL;

1791caseFMul:returnISD::FMUL;

1792case UDiv:returnISD::UDIV;

1793case SDiv:returnISD::SDIV;

1794case FDiv:returnISD::FDIV;

1795case URem:returnISD::UREM;

1796case SRem:returnISD::SREM;

1797case FRem:returnISD::FREM;

1798case Shl:returnISD::SHL;

1799case LShr:returnISD::SRL;

1800case AShr:returnISD::SRA;

1801caseAnd:returnISD::AND;

1802caseOr:returnISD::OR;

1803caseXor:returnISD::XOR;

1804case Alloca:return 0;

1805case Load:returnISD::LOAD;

1806case Store:returnISD::STORE;

1807case GetElementPtr:return 0;

1808case Fence:return 0;

1809case AtomicCmpXchg:return 0;

1810case AtomicRMW:return 0;

1811case Trunc:returnISD::TRUNCATE;

1812case ZExt:returnISD::ZERO_EXTEND;

1813case SExt:returnISD::SIGN_EXTEND;

1814case FPToUI:returnISD::FP_TO_UINT;

1815case FPToSI:returnISD::FP_TO_SINT;

1816case UIToFP:returnISD::UINT_TO_FP;

1817case SIToFP:returnISD::SINT_TO_FP;

1818case FPTrunc:returnISD::FP_ROUND;

1819case FPExt:returnISD::FP_EXTEND;

1820case PtrToInt:returnISD::BITCAST;

1821case IntToPtr:returnISD::BITCAST;

1822case BitCast:returnISD::BITCAST;

1823case AddrSpaceCast:returnISD::ADDRSPACECAST;

1824case ICmp:returnISD::SETCC;

1825case FCmp:returnISD::SETCC;

1826casePHI:return 0;

1827case Call:return 0;

1828caseSelect:returnISD::SELECT;

1829case UserOp1:return 0;

1830case UserOp2:return 0;

1831case VAArg:return 0;

1832case ExtractElement:returnISD::EXTRACT_VECTOR_ELT;

1833case InsertElement:returnISD::INSERT_VECTOR_ELT;

1834case ShuffleVector:returnISD::VECTOR_SHUFFLE;

1835case ExtractValue:returnISD::MERGE_VALUES;

1836case InsertValue:returnISD::MERGE_VALUES;

1837case LandingPad:return 0;

1838case Freeze:returnISD::FREEZE;

1839 }

1840

1841llvm_unreachable("Unknown instruction type encountered!");

1842}

1843

1844intTargetLoweringBase::IntrinsicIDToISD(Intrinsic::ID ID) const{

1845switch (ID) {

1846case Intrinsic::exp:

1847returnISD::FEXP;

1848case Intrinsic::exp2:

1849returnISD::FEXP2;

1850default:

1851returnISD::DELETED_NODE;

1852 }

1853}

1854

1855Value *

1856TargetLoweringBase::getDefaultSafeStackPointerLocation(IRBuilderBase &IRB,

1857bool UseTLS) const{

1858// compiler-rt provides a variable with a magic name. Targets that do not

1859// link with compiler-rt may also provide such a variable.

1860Module *M = IRB.GetInsertBlock()->getParent()->getParent();

1861constchar *UnsafeStackPtrVar ="__safestack_unsafe_stack_ptr";

1862auto UnsafeStackPtr =

1863 dyn_cast_or_null<GlobalVariable>(M->getNamedValue(UnsafeStackPtrVar));

1864

1865constDataLayout &DL = M->getDataLayout();

1866PointerType *StackPtrTy =DL.getAllocaPtrType(M->getContext());

1867

1868if (!UnsafeStackPtr) {

1869auto TLSModel = UseTLS ?

1870GlobalValue::InitialExecTLSModel :

1871GlobalValue::NotThreadLocal;

1872// The global variable is not defined yet, define it ourselves.

1873// We use the initial-exec TLS model because we do not support the

1874// variable living anywhere other than in the main executable.

1875 UnsafeStackPtr =newGlobalVariable(

1876 *M, StackPtrTy,false,GlobalValue::ExternalLinkage,nullptr,

1877 UnsafeStackPtrVar,nullptr, TLSModel);

1878 }else {

1879// The variable exists, check its type and attributes.

1880//

1881// FIXME: Move to IR verifier.

1882if (UnsafeStackPtr->getValueType() != StackPtrTy)

1883report_fatal_error(Twine(UnsafeStackPtrVar) +" must have void* type");

1884if (UseTLS != UnsafeStackPtr->isThreadLocal())

1885report_fatal_error(Twine(UnsafeStackPtrVar) +" must " +

1886 (UseTLS ?"" :"not ") +"be thread-local");

1887 }

1888return UnsafeStackPtr;

1889}

1890

1891Value *

1892TargetLoweringBase::getSafeStackPointerLocation(IRBuilderBase &IRB) const{

1893if (!TM.getTargetTriple().isAndroid())

1894returngetDefaultSafeStackPointerLocation(IRB,true);

1895

1896// Android provides a libc function to retrieve the address of the current

1897// thread's unsafe stack pointer.

1898Module *M = IRB.GetInsertBlock()->getParent()->getParent();

1899auto *PtrTy =PointerType::getUnqual(M->getContext());

1900FunctionCallee Fn =

1901 M->getOrInsertFunction("__safestack_pointer_address", PtrTy);

1902return IRB.CreateCall(Fn);

1903}

1904

1905//===----------------------------------------------------------------------===//

1906// Loop Strength Reduction hooks

1907//===----------------------------------------------------------------------===//

1908

1909/// isLegalAddressingMode - Return true if the addressing mode represented

1910/// by AM is legal for this target, for a load/store of the specified type.

1911boolTargetLoweringBase::isLegalAddressingMode(constDataLayout &DL,

1912constAddrMode &AM,Type *Ty,

1913unsigned AS,Instruction *I) const{

1914// The default implementation of this implements a conservative RISCy, r+r and

1915// r+i addr mode.

1916

1917// Scalable offsets not supported

1918if (AM.ScalableOffset)

1919returnfalse;

1920

1921// Allows a sign-extended 16-bit immediate field.

1922if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)

1923returnfalse;

1924

1925// No global is ever allowed as a base.

1926if (AM.BaseGV)

1927returnfalse;

1928

1929// Only support r+r,

1930switch (AM.Scale) {

1931case 0:// "r+i" or just "i", depending on HasBaseReg.

1932break;

1933case 1:

1934if (AM.HasBaseReg && AM.BaseOffs)// "r+r+i" is not allowed.

1935returnfalse;

1936// Otherwise we have r+r or r+i.

1937break;

1938case 2:

1939if (AM.HasBaseReg || AM.BaseOffs)// 2*r+r or 2*r+i is not allowed.

1940returnfalse;

1941// Allow 2*r as r+r.

1942break;

1943default:// Don't allow n * r

1944returnfalse;

1945 }

1946

1947returntrue;

1948}

1949

1950//===----------------------------------------------------------------------===//

1951// Stack Protector

1952//===----------------------------------------------------------------------===//

1953

1954// For OpenBSD return its special guard variable. Otherwise return nullptr,

1955// so that SelectionDAG handle SSP.

1956Value *TargetLoweringBase::getIRStackGuard(IRBuilderBase &IRB) const{

1957if (getTargetMachine().getTargetTriple().isOSOpenBSD()) {

1958Module &M = *IRB.GetInsertBlock()->getParent()->getParent();

1959PointerType *PtrTy =PointerType::getUnqual(M.getContext());

1960Constant *C = M.getOrInsertGlobal("__guard_local", PtrTy);

1961if (GlobalVariable *G = dyn_cast_or_null<GlobalVariable>(C))

1962G->setVisibility(GlobalValue::HiddenVisibility);

1963returnC;

1964 }

1965returnnullptr;

1966}

1967

1968// Currently only support "standard" __stack_chk_guard.

1969// TODO: add LOAD_STACK_GUARD support.

1970voidTargetLoweringBase::insertSSPDeclarations(Module &M) const{

1971if (!M.getNamedValue("__stack_chk_guard")) {

1972auto *GV =newGlobalVariable(M,PointerType::getUnqual(M.getContext()),

1973false,GlobalVariable::ExternalLinkage,

1974nullptr,"__stack_chk_guard");

1975

1976// FreeBSD has "__stack_chk_guard" defined externally on libc.so

1977if (M.getDirectAccessExternalData() &&

1978 !TM.getTargetTriple().isWindowsGNUEnvironment() &&

1979 !(TM.getTargetTriple().isPPC64() &&

1980 TM.getTargetTriple().isOSFreeBSD()) &&

1981 (!TM.getTargetTriple().isOSDarwin() ||

1982 TM.getRelocationModel() ==Reloc::Static))

1983 GV->setDSOLocal(true);

1984 }

1985}

1986

1987// Currently only support "standard" __stack_chk_guard.

1988// TODO: add LOAD_STACK_GUARD support.

1989Value *TargetLoweringBase::getSDagStackGuard(constModule &M) const{

1990return M.getNamedValue("__stack_chk_guard");

1991}

1992

1993Function *TargetLoweringBase::getSSPStackGuardCheck(constModule &M) const{

1994returnnullptr;

1995}

1996

1997unsignedTargetLoweringBase::getMinimumJumpTableEntries() const{

1998returnMinimumJumpTableEntries;

1999}

2000

2001voidTargetLoweringBase::setMinimumJumpTableEntries(unsigned Val) {

2002MinimumJumpTableEntries = Val;

2003}

2004

2005unsignedTargetLoweringBase::getMinimumJumpTableDensity(bool OptForSize) const{

2006return OptForSize ?OptsizeJumpTableDensity :JumpTableDensity;

2007}

2008

2009unsignedTargetLoweringBase::getMaximumJumpTableSize() const{

2010returnMaximumJumpTableSize;

2011}

2012

2013voidTargetLoweringBase::setMaximumJumpTableSize(unsigned Val) {

2014MaximumJumpTableSize = Val;

2015}

2016

2017boolTargetLoweringBase::isJumpTableRelative() const{

2018returngetTargetMachine().isPositionIndependent();

2019}

2020

2021Align TargetLoweringBase::getPrefLoopAlignment(MachineLoop *ML) const{

2022if (TM.Options.LoopAlignment)

2023returnAlign(TM.Options.LoopAlignment);

2024return PrefLoopAlignment;

2025}

2026

2027unsignedTargetLoweringBase::getMaxPermittedBytesForAlignment(

2028MachineBasicBlock *MBB) const{

2029return MaxBytesForAlignment;

2030}

2031

2032//===----------------------------------------------------------------------===//

2033// Reciprocal Estimates

2034//===----------------------------------------------------------------------===//

2035

2036/// Get the reciprocal estimate attribute string for a function that will

2037/// override the target defaults.

2038staticStringRef getRecipEstimateForFunc(MachineFunction &MF) {

2039constFunction &F = MF.getFunction();

2040returnF.getFnAttribute("reciprocal-estimates").getValueAsString();

2041}

2042

2043/// Construct a string for the given reciprocal operation of the given type.

2044/// This string should match the corresponding option to the front-end's

2045/// "-mrecip" flag assuming those strings have been passed through in an

2046/// attribute string. For example, "vec-divf" for a division of a vXf32.

2047static std::stringgetReciprocalOpName(bool IsSqrt,EVT VT) {

2048 std::stringName = VT.isVector() ?"vec-" :"";

2049

2050Name += IsSqrt ?"sqrt" :"div";

2051

2052// TODO: Handle other float types?

2053if (VT.getScalarType() == MVT::f64) {

2054Name +="d";

2055 }elseif (VT.getScalarType() == MVT::f16) {

2056Name +="h";

2057 }else {

2058assert(VT.getScalarType() == MVT::f32 &&

2059"Unexpected FP type for reciprocal estimate");

2060Name +="f";

2061 }

2062

2063returnName;

2064}

2065

2066/// Return the character position and value (a single numeric character) of a

2067/// customized refinement operation in the input string if it exists. Return

2068/// false if there is no customized refinement step count.

2069staticboolparseRefinementStep(StringRef In,size_t &Position,

2070uint8_t &Value) {

2071constchar RefStepToken =':';

2072 Position = In.find(RefStepToken);

2073if (Position ==StringRef::npos)

2074returnfalse;

2075

2076StringRef RefStepString = In.substr(Position + 1);

2077// Allow exactly one numeric character for the additional refinement

2078// step parameter.

2079if (RefStepString.size() == 1) {

2080char RefStepChar = RefStepString[0];

2081if (isDigit(RefStepChar)) {

2082Value = RefStepChar -'0';

2083returntrue;

2084 }

2085 }

2086report_fatal_error("Invalid refinement step for -recip.");

2087}

2088

2089/// For the input attribute string, return one of the ReciprocalEstimate enum

2090/// status values (enabled, disabled, or not specified) for this operation on

2091/// the specified data type.

2092staticintgetOpEnabled(bool IsSqrt,EVT VT,StringRef Override) {

2093if (Override.empty())

2094returnTargetLoweringBase::ReciprocalEstimate::Unspecified;

2095

2096SmallVector<StringRef, 4> OverrideVector;

2097 Override.split(OverrideVector,',');

2098unsigned NumArgs = OverrideVector.size();

2099

2100// Check if "all", "none", or "default" was specified.

2101if (NumArgs == 1) {

2102// Look for an optional setting of the number of refinement steps needed

2103// for this type of reciprocal operation.

2104size_t RefPos;

2105uint8_t RefSteps;

2106if (parseRefinementStep(Override, RefPos, RefSteps)) {

2107// Split the string for further processing.

2108 Override = Override.substr(0, RefPos);

2109 }

2110

2111// All reciprocal types are enabled.

2112if (Override =="all")

2113returnTargetLoweringBase::ReciprocalEstimate::Enabled;

2114

2115// All reciprocal types are disabled.

2116if (Override =="none")

2117returnTargetLoweringBase::ReciprocalEstimate::Disabled;

2118

2119// Target defaults for enablement are used.

2120if (Override =="default")

2121returnTargetLoweringBase::ReciprocalEstimate::Unspecified;

2122 }

2123

2124// The attribute string may omit the size suffix ('f'/'d').

2125 std::string VTName =getReciprocalOpName(IsSqrt, VT);

2126 std::string VTNameNoSize = VTName;

2127 VTNameNoSize.pop_back();

2128staticconstchar DisabledPrefix ='!';

2129

2130for (StringRef RecipType : OverrideVector) {

2131size_t RefPos;

2132uint8_t RefSteps;

2133if (parseRefinementStep(RecipType, RefPos, RefSteps))

2134 RecipType = RecipType.substr(0, RefPos);

2135

2136// Ignore the disablement token for string matching.

2137bool IsDisabled = RecipType[0] == DisabledPrefix;

2138if (IsDisabled)

2139 RecipType = RecipType.substr(1);

2140

2141if (RecipType == VTName || RecipType == VTNameNoSize)

2142return IsDisabled ?TargetLoweringBase::ReciprocalEstimate::Disabled

2143 :TargetLoweringBase::ReciprocalEstimate::Enabled;

2144 }

2145

2146returnTargetLoweringBase::ReciprocalEstimate::Unspecified;

2147}

2148

2149/// For the input attribute string, return the customized refinement step count

2150/// for this operation on the specified data type. If the step count does not

2151/// exist, return the ReciprocalEstimate enum value for unspecified.

2152staticintgetOpRefinementSteps(bool IsSqrt,EVT VT,StringRef Override) {

2153if (Override.empty())

2154returnTargetLoweringBase::ReciprocalEstimate::Unspecified;

2155

2156SmallVector<StringRef, 4> OverrideVector;

2157 Override.split(OverrideVector,',');

2158unsigned NumArgs = OverrideVector.size();

2159

2160// Check if "all", "default", or "none" was specified.

2161if (NumArgs == 1) {

2162// Look for an optional setting of the number of refinement steps needed

2163// for this type of reciprocal operation.

2164size_t RefPos;

2165uint8_t RefSteps;

2166if (!parseRefinementStep(Override, RefPos, RefSteps))

2167returnTargetLoweringBase::ReciprocalEstimate::Unspecified;

2168

2169// Split the string for further processing.

2170 Override = Override.substr(0, RefPos);

2171assert(Override !="none" &&

2172"Disabled reciprocals, but specifed refinement steps?");

2173

2174// If this is a general override, return the specified number of steps.

2175if (Override =="all" || Override =="default")

2176return RefSteps;

2177 }

2178

2179// The attribute string may omit the size suffix ('f'/'d').

2180 std::string VTName =getReciprocalOpName(IsSqrt, VT);

2181 std::string VTNameNoSize = VTName;

2182 VTNameNoSize.pop_back();

2183

2184for (StringRef RecipType : OverrideVector) {

2185size_t RefPos;

2186uint8_t RefSteps;

2187if (!parseRefinementStep(RecipType, RefPos, RefSteps))

2188continue;

2189

2190 RecipType = RecipType.substr(0, RefPos);

2191if (RecipType == VTName || RecipType == VTNameNoSize)

2192return RefSteps;

2193 }

2194

2195returnTargetLoweringBase::ReciprocalEstimate::Unspecified;

2196}

2197

2198intTargetLoweringBase::getRecipEstimateSqrtEnabled(EVT VT,

2199MachineFunction &MF) const{

2200returngetOpEnabled(true, VT,getRecipEstimateForFunc(MF));

2201}

2202

2203intTargetLoweringBase::getRecipEstimateDivEnabled(EVT VT,

2204MachineFunction &MF) const{

2205returngetOpEnabled(false, VT,getRecipEstimateForFunc(MF));

2206}

2207

2208intTargetLoweringBase::getSqrtRefinementSteps(EVT VT,

2209MachineFunction &MF) const{

2210returngetOpRefinementSteps(true, VT,getRecipEstimateForFunc(MF));

2211}

2212

2213intTargetLoweringBase::getDivRefinementSteps(EVT VT,

2214MachineFunction &MF) const{

2215returngetOpRefinementSteps(false, VT,getRecipEstimateForFunc(MF));

2216}

2217

2218boolTargetLoweringBase::isLoadBitCastBeneficial(

2219EVT LoadVT,EVT BitcastVT,constSelectionDAG &DAG,

2220constMachineMemOperand &MMO) const{

2221// Single-element vectors are scalarized, so we should generally avoid having

2222// any memory operations on such types, as they would get scalarized too.

2223if (LoadVT.isFixedLengthVector() && BitcastVT.isFixedLengthVector() &&

2224 BitcastVT.getVectorNumElements() == 1)

2225returnfalse;

2226

2227// Don't do if we could do an indexed load on the original type, but not on

2228// the new one.

2229if (!LoadVT.isSimple() || !BitcastVT.isSimple())

2230returntrue;

2231

2232MVT LoadMVT = LoadVT.getSimpleVT();

2233

2234// Don't bother doing this if it's just going to be promoted again later, as

2235// doing so might interfere with other combines.

2236if (getOperationAction(ISD::LOAD, LoadMVT) ==Promote &&

2237getTypeToPromoteTo(ISD::LOAD, LoadMVT) == BitcastVT.getSimpleVT())

2238returnfalse;

2239

2240unsignedFast = 0;

2241returnallowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), BitcastVT,

2242 MMO, &Fast) &&

2243Fast;

2244}

2245

2246voidTargetLoweringBase::finalizeLowering(MachineFunction &MF) const{

2247 MF.getRegInfo().freezeReservedRegs();

2248}

2249

2250MachineMemOperand::Flags TargetLoweringBase::getLoadMemOperandFlags(

2251constLoadInst &LI,constDataLayout &DL,AssumptionCache *AC,

2252constTargetLibraryInfo *LibInfo) const{

2253MachineMemOperand::Flags Flags =MachineMemOperand::MOLoad;

2254if (LI.isVolatile())

2255 Flags |=MachineMemOperand::MOVolatile;

2256

2257if (LI.hasMetadata(LLVMContext::MD_nontemporal))

2258 Flags |=MachineMemOperand::MONonTemporal;

2259

2260if (LI.hasMetadata(LLVMContext::MD_invariant_load))

2261 Flags |=MachineMemOperand::MOInvariant;

2262

2263if (isDereferenceableAndAlignedPointer(LI.getPointerOperand(), LI.getType(),

2264 LI.getAlign(),DL, &LI, AC,

2265/*DT=*/nullptr, LibInfo))

2266 Flags |=MachineMemOperand::MODereferenceable;

2267

2268 Flags |=getTargetMMOFlags(LI);

2269return Flags;

2270}

2271

2272MachineMemOperand::Flags

2273TargetLoweringBase::getStoreMemOperandFlags(constStoreInst &SI,

2274constDataLayout &DL) const{

2275MachineMemOperand::Flags Flags =MachineMemOperand::MOStore;

2276

2277if (SI.isVolatile())

2278 Flags |=MachineMemOperand::MOVolatile;

2279

2280if (SI.hasMetadata(LLVMContext::MD_nontemporal))

2281 Flags |=MachineMemOperand::MONonTemporal;

2282

2283// FIXME: Not preserving dereferenceable

2284 Flags |=getTargetMMOFlags(SI);

2285return Flags;

2286}

2287

2288MachineMemOperand::Flags

2289TargetLoweringBase::getAtomicMemOperandFlags(constInstruction &AI,

2290constDataLayout &DL) const{

2291auto Flags =MachineMemOperand::MOLoad |MachineMemOperand::MOStore;

2292

2293if (constAtomicRMWInst *RMW = dyn_cast<AtomicRMWInst>(&AI)) {

2294if (RMW->isVolatile())

2295 Flags |=MachineMemOperand::MOVolatile;

2296 }elseif (constAtomicCmpXchgInst *CmpX = dyn_cast<AtomicCmpXchgInst>(&AI)) {

2297if (CmpX->isVolatile())

2298 Flags |=MachineMemOperand::MOVolatile;

2299 }else

2300llvm_unreachable("not an atomic instruction");

2301

2302// FIXME: Not preserving dereferenceable

2303 Flags |=getTargetMMOFlags(AI);

2304return Flags;

2305}

2306

2307Instruction *TargetLoweringBase::emitLeadingFence(IRBuilderBase &Builder,

2308Instruction *Inst,

2309AtomicOrdering Ord) const{

2310if (isReleaseOrStronger(Ord) && Inst->hasAtomicStore())

2311return Builder.CreateFence(Ord);

2312else

2313returnnullptr;

2314}

2315

2316Instruction *TargetLoweringBase::emitTrailingFence(IRBuilderBase &Builder,

2317Instruction *Inst,

2318AtomicOrdering Ord) const{

2319if (isAcquireOrStronger(Ord))

2320return Builder.CreateFence(Ord);

2321else

2322returnnullptr;

2323}

2324

2325//===----------------------------------------------------------------------===//

2326// GlobalISel Hooks

2327//===----------------------------------------------------------------------===//

2328

2329boolTargetLoweringBase::shouldLocalize(constMachineInstr &MI,

2330constTargetTransformInfo *TTI) const{

2331auto &MF = *MI.getMF();

2332auto &MRI = MF.getRegInfo();

2333// Assuming a spill and reload of a value has a cost of 1 instruction each,

2334// this helper function computes the maximum number of uses we should consider

2335// for remat. E.g. on arm64 global addresses take 2 insts to materialize. We

2336// break even in terms of code size when the original MI has 2 users vs

2337// choosing to potentially spill. Any more than 2 users we we have a net code

2338// size increase. This doesn't take into account register pressure though.

2339auto maxUses = [](unsigned RematCost) {

2340// A cost of 1 means remats are basically free.

2341if (RematCost == 1)

2342return std::numeric_limits<unsigned>::max();

2343if (RematCost == 2)

2344return 2U;

2345

2346// Remat is too expensive, only sink if there's one user.

2347if (RematCost > 2)

2348return 1U;

2349llvm_unreachable("Unexpected remat cost");

2350 };

2351

2352switch (MI.getOpcode()) {

2353default:

2354returnfalse;

2355// Constants-like instructions should be close to their users.

2356// We don't want long live-ranges for them.

2357case TargetOpcode::G_CONSTANT:

2358case TargetOpcode::G_FCONSTANT:

2359case TargetOpcode::G_FRAME_INDEX:

2360case TargetOpcode::G_INTTOPTR:

2361returntrue;

2362case TargetOpcode::G_GLOBAL_VALUE: {

2363unsigned RematCost =TTI->getGISelRematGlobalCost();

2364Register Reg =MI.getOperand(0).getReg();

2365unsigned MaxUses = maxUses(RematCost);

2366if (MaxUses == UINT_MAX)

2367returntrue;// Remats are "free" so always localize.

2368returnMRI.hasAtMostUserInstrs(Reg, MaxUses);

2369 }

2370 }

2371}

MRI

unsigned const MachineRegisterInfo * MRI

Definition:AArch64AdvSIMDScalarPass.cpp:105

Select

AMDGPU Register Bank Select

Definition:AMDGPURegBankSelect.cpp:71

PHI

Rewrite undef for PHI

Definition:AMDGPURewriteUndefForPHI.cpp:100

MBB

MachineBasicBlock & MBB

Definition:ARMSLSHardening.cpp:71

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

Definition:ARMSLSHardening.cpp:73

Attributes.h

This file contains the simple types necessary to represent the attributes associated with functions a...

BitVector.h

This file implements the BitVector class.

return RetTy

Definition:DeadArgumentElimination.cpp:361

DerivedTypes.h

Name

std::string Name

Definition:ELFObjHandler.cpp:77

GlobalValue.h

GlobalVariable.h

IRBuilder.h

IRTranslator LLVM IR MI

Definition:IRTranslator.cpp:112

Function.h

Module.h

Module.h This file contains the declarations for the Module class.

Type.h

ISDOpcodes.h

InlinePriorityMode::ML

@ ML

Loads.h

#define F(x, y, z)

Definition:MD5.cpp:55

#define I(x, y, z)

Definition:MD5.cpp:58

#define G(x, y, z)

Definition:MD5.cpp:56

MachineBasicBlock.h

MachineFrameInfo.h

MachineFunction.h

MachineInstrBuilder.h

MachineInstr.h

MachineMemOperand.h

MachineOperand.h

MachineRegisterInfo.h

TRI

unsigned const TargetRegisterInfo * TRI

Definition:MachineSink.cpp:2029

MachineValueType.h

MathExtras.h

Range

ConstantRange Range(APInt(BitWidth, Low), APInt(BitWidth, High))

auto CC

Definition:RISCVRedundantCopyElimination.cpp:79

RuntimeLibcallUtil.h

isDigit

static bool isDigit(const char C)

Definition:RustDemangle.cpp:170

assert

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

STLExtras.h

This file contains some templates that are useful if you are working with the STL at all.

SizeOpts.h

SmallVector.h

This file defines the SmallVector class.

StackMaps.h

StringExtras.h

This file contains some functions that are useful when dealing with strings.

StringRef.h

JumpIsExpensiveOverride

static cl::opt< bool > JumpIsExpensiveOverride("jump-is-expensive", cl::init(false), cl::desc("Do not create extra branches to split comparison logic."), cl::Hidden)

OP_TO_LIBCALL

#define OP_TO_LIBCALL(Name, Enum)

MinimumJumpTableEntries

static cl::opt< unsigned > MinimumJumpTableEntries("min-jump-table-entries", cl::init(4), cl::Hidden, cl::desc("Set minimum number of entries to use a jump table."))

DisableStrictNodeMutation

static cl::opt< bool > DisableStrictNodeMutation("disable-strictnode-mutation", cl::desc("Don't mutate strict-float node to a legalize node"), cl::init(false), cl::Hidden)

parseRefinementStep

static bool parseRefinementStep(StringRef In, size_t &Position, uint8_t &Value)

Return the character position and value (a single numeric character) of a customized refinement opera...

Definition:TargetLoweringBase.cpp:2069

MaximumJumpTableSize

static cl::opt< unsigned > MaximumJumpTableSize("max-jump-table-size", cl::init(UINT_MAX), cl::Hidden, cl::desc("Set maximum size of jump tables."))

JumpTableDensity

static cl::opt< unsigned > JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden, cl::desc("Minimum density for building a jump table in " "a normal function"))

Minimum jump table density for normal functions.

getVectorTypeBreakdownMVT

static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT, TargetLoweringBase *TLI)

Definition:TargetLoweringBase.cpp:1087

getReciprocalOpName

static std::string getReciprocalOpName(bool IsSqrt, EVT VT)

Construct a string for the given reciprocal operation of the given type.

Definition:TargetLoweringBase.cpp:2047

LCALL5

#define LCALL5(A)

getOpRefinementSteps

static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override)

For the input attribute string, return the customized refinement step count for this operation on the...

Definition:TargetLoweringBase.cpp:2152

getOpEnabled

static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override)

For the input attribute string, return one of the ReciprocalEstimate enum status values (enabled,...

Definition:TargetLoweringBase.cpp:2092

getRecipEstimateForFunc

static StringRef getRecipEstimateForFunc(MachineFunction &MF)

Get the reciprocal estimate attribute string for a function that will override the target defaults.

Definition:TargetLoweringBase.cpp:2038

OptsizeJumpTableDensity

static cl::opt< unsigned > OptsizeJumpTableDensity("optsize-jump-table-density", cl::init(40), cl::Hidden, cl::desc("Minimum density for building a jump table in " "an optsize function"))

Minimum jump table density for -Os or -Oz functions.

TargetLowering.h

This file describes how to lower LLVM code to machine code.

TargetOpcodes.h

TargetOptions.h

TargetRegisterInfo.h

TargetTransformInfo.h

This pass exposes codegen information to IR-level passes.

Class for arbitrary precision integers.

Definition:APInt.h:78

llvm::AssumptionCache

A cache of @llvm.assume calls within a function.

Definition:AssumptionCache.h:42

llvm::AtomicCmpXchgInst

An instruction that atomically checks whether a specified value is in a memory location,...

Definition:Instructions.h:501

llvm::AtomicRMWInst

an instruction that atomically reads a memory location, combines it with another value,...

Definition:Instructions.h:704

llvm::AttributeList

Definition:Attributes.h:490

llvm::AttributeList::hasRetAttr

bool hasRetAttr(Attribute::AttrKind Kind) const

Return true if the attribute exists for the return value.

Definition:Attributes.h:848

llvm::BasicBlock::getParent

const Function * getParent() const

Return the enclosing method, or null if none.

Definition:BasicBlock.h:220

llvm::BitVector

Definition:BitVector.h:82

llvm::BitVector::setBitsInMask

void setBitsInMask(const uint32_t *Mask, unsigned MaskWords=~0u)

setBitsInMask - Add '1' bits from Mask to this vector.

Definition:BitVector.h:707

llvm::BitVector::set_bits

iterator_range< const_set_bits_iterator > set_bits() const

Definition:BitVector.h:140

llvm::BlockFrequencyInfo

BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...

Definition:BlockFrequencyInfo.h:37

llvm::ConstantRange

This class represents a range of values.

Definition:ConstantRange.h:47

llvm::ConstantRange::getActiveBits

unsigned getActiveBits() const

Compute the maximal number of active bits needed to represent every value in this range.

Definition:ConstantRange.cpp:534

llvm::ConstantRange::umul_sat

ConstantRange umul_sat(const ConstantRange &Other) const

Perform an unsigned saturating multiplication of two constant ranges.

Definition:ConstantRange.cpp:1885

llvm::ConstantRange::subtract

ConstantRange subtract(const APInt &CI) const

Subtract the specified constant from the endpoints of this constant range.

Definition:ConstantRange.cpp:549

llvm::Constant

This is an important base class in LLVM.

Definition:Constant.h:42

llvm::DWARFExpression::Operation

This class represents an Operation in the Expression.

Definition:DWARFExpression.h:32

llvm::DataLayout

A parsed version of the target data layout string in and methods for querying it.

Definition:DataLayout.h:63

llvm::DataLayout::getPointerSize

unsigned getPointerSize(unsigned AS=0) const

Layout pointer size in bytes, rounded up to a whole number of bytes.

Definition:DataLayout.cpp:739

llvm::ElementCount

Definition:TypeSize.h:300

llvm::ElementCount::getScalable

static constexpr ElementCount getScalable(ScalarTy MinVal)

Definition:TypeSize.h:314

llvm::ElementCount::getFixed

static constexpr ElementCount getFixed(ScalarTy MinVal)

Definition:TypeSize.h:311

llvm::ElementCount::isScalar

constexpr bool isScalar() const

Exactly one element.

Definition:TypeSize.h:322

llvm::FunctionCallee

A handy container for a FunctionType+Callee-pointer pair, which can be passed around as a single enti...

Definition:DerivedTypes.h:170

llvm::Function

Definition:Function.h:63

llvm::GlobalValue::NotThreadLocal

@ NotThreadLocal

Definition:GlobalValue.h:197

llvm::GlobalValue::InitialExecTLSModel

@ InitialExecTLSModel

Definition:GlobalValue.h:200

llvm::GlobalValue::getParent

Module * getParent()

Get the module that this global value is contained inside of...

Definition:GlobalValue.h:657

llvm::GlobalValue::HiddenVisibility

@ HiddenVisibility

The GV is hidden.

Definition:GlobalValue.h:68

llvm::GlobalValue::ExternalLinkage

@ ExternalLinkage

Externally visible function.

Definition:GlobalValue.h:52

llvm::GlobalVariable

Definition:GlobalVariable.h:39

llvm::IRBuilderBase

Common base class shared among various IRBuilders.

Definition:IRBuilder.h:113

llvm::IRBuilderBase::CreateFence

FenceInst * CreateFence(AtomicOrdering Ordering, SyncScope::ID SSID=SyncScope::System, const Twine &Name="")

Definition:IRBuilder.h:1842

llvm::IRBuilderBase::GetInsertBlock

BasicBlock * GetInsertBlock() const

Definition:IRBuilder.h:193

llvm::IRBuilderBase::CreateCall

CallInst * CreateCall(FunctionType *FTy, Value *Callee, ArrayRef< Value * > Args={}, const Twine &Name="", MDNode *FPMathTag=nullptr)

Definition:IRBuilder.h:2449

llvm::InstructionCost

Definition:InstructionCost.h:29

llvm::Instruction

Definition:Instruction.h:68

llvm::Instruction::hasAtomicStore

bool hasAtomicStore() const LLVM_READONLY

Return true if this atomic instruction stores to memory.

Definition:Instruction.cpp:1058

llvm::Instruction::hasMetadata

bool hasMetadata() const

Return true if this instruction has any metadata attached to it.

Definition:Instruction.h:385

llvm::IntegerType::MAX_INT_BITS

@ MAX_INT_BITS

Maximum number of bits that can be specified.

Definition:DerivedTypes.h:54

llvm::LLT

Definition:LowLevelType.h:39

llvm::LLVMContext

This is an important class for using LLVM in a threaded context.

Definition:LLVMContext.h:67

llvm::LoadInst

An instruction for reading from memory.

Definition:Instructions.h:176

llvm::LoadInst::getPointerOperand

Value * getPointerOperand()

Definition:Instructions.h:255

llvm::LoadInst::isVolatile

bool isVolatile() const

Return true if this is a load from a volatile memory location.

Definition:Instructions.h:205

llvm::LoadInst::getAlign

Align getAlign() const

Return the alignment of the access that is being performed.

Definition:Instructions.h:211

llvm::MVT

Machine Value Type.

Definition:MachineValueType.h:35

llvm::MVT::SimpleValueType

SimpleValueType

Definition:MachineValueType.h:37

llvm::MVT::VALUETYPE_SIZE

@ VALUETYPE_SIZE

Definition:MachineValueType.h:49

llvm::MVT::SimpleTy

SimpleValueType SimpleTy

Definition:MachineValueType.h:55

llvm::MVT::getScalarSizeInBits

uint64_t getScalarSizeInBits() const

Definition:MachineValueType.h:346

llvm::MVT::isVector

bool isVector() const

Return true if this is a vector value type.

Definition:MachineValueType.h:106

llvm::MVT::isScalableVector

bool isScalableVector() const

Return true if this is a vector value type where the runtime length is machine dependent.

Definition:MachineValueType.h:113

llvm::MVT::all_valuetypes

static auto all_valuetypes()

SimpleValueType Iteration.

Definition:MachineValueType.h:520

llvm::MVT::getSizeInBits

TypeSize getSizeInBits() const

Returns the size of the specified MVT in bits.

Definition:MachineValueType.h:308

llvm::MVT::getFixedSizeInBits

uint64_t getFixedSizeInBits() const

Return the size of the specified fixed width value type in bits.

Definition:MachineValueType.h:342

llvm::MVT::getVectorElementCount

ElementCount getVectorElementCount() const

Definition:MachineValueType.h:290

llvm::MVT::isScalarInteger

bool isScalarInteger() const

Return true if this is an integer, not including vectors.

Definition:MachineValueType.h:100

llvm::MVT::getVectorVT

static MVT getVectorVT(MVT VT, unsigned NumElements)

Definition:MachineValueType.h:451

llvm::MVT::getVectorElementType

MVT getVectorElementType() const

Definition:MachineValueType.h:263

llvm::MVT::isValid

bool isValid() const

Return true if this is a valid simple valuetype.

Definition:MachineValueType.h:74

llvm::MVT::getIntegerVT

static MVT getIntegerVT(unsigned BitWidth)

Definition:MachineValueType.h:441

llvm::MVT::fp_valuetypes

static auto fp_valuetypes()

Definition:MachineValueType.h:531

llvm::MVT::getPow2VectorType

MVT getPow2VectorType() const

Widens the length of the given vector MVT up to the nearest power of 2 and returns that type.

Definition:MachineValueType.h:248

llvm::MachineBasicBlock

Definition:MachineBasicBlock.h:125

llvm::MachineBasicBlock::insert

instr_iterator insert(instr_iterator I, MachineInstr *M)

Insert MI into the instruction list before I, possibly inside a bundle.

Definition:MachineBasicBlock.cpp:1456

llvm::MachineFrameInfo

The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.

Definition:MachineFrameInfo.h:106

llvm::MachineFrameInfo::isStatepointSpillSlotObjectIndex

bool isStatepointSpillSlotObjectIndex(int ObjectIdx) const

Definition:MachineFrameInfo.h:743

llvm::MachineFrameInfo::getObjectAlign

Align getObjectAlign(int ObjectIdx) const

Return the alignment of the specified stack object.

Definition:MachineFrameInfo.h:486

llvm::MachineFrameInfo::getObjectSize

int64_t getObjectSize(int ObjectIdx) const

Return the size of the specified object.

Definition:MachineFrameInfo.h:472

llvm::MachineFrameInfo::getObjectOffset

int64_t getObjectOffset(int ObjectIdx) const

Return the assigned stack offset of the specified object from the incoming stack pointer.

Definition:MachineFrameInfo.h:528

llvm::MachineFunction

Definition:MachineFunction.h:267

llvm::MachineFunction::getMachineMemOperand

MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)

getMachineMemOperand - Allocate a new MachineMemOperand.

Definition:MachineFunction.cpp:536

llvm::MachineFunction::getFrameInfo

MachineFrameInfo & getFrameInfo()

getFrameInfo - Return the frame info object for the current function.

Definition:MachineFunction.h:749

llvm::MachineFunction::getRegInfo

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

Definition:MachineFunction.h:743

llvm::MachineFunction::getDataLayout

const DataLayout & getDataLayout() const

Return the DataLayout attached to the Module associated to this MF.

Definition:MachineFunction.cpp:309

llvm::MachineFunction::getFunction

Function & getFunction()

Return the LLVM function that this machine code represents.

Definition:MachineFunction.h:704

llvm::MachineInstrBuilder

Definition:MachineInstrBuilder.h:71

llvm::MachineInstrBuilder::addImm

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

Definition:MachineInstrBuilder.h:133

llvm::MachineInstrBuilder::add

const MachineInstrBuilder & add(const MachineOperand &MO) const

Definition:MachineInstrBuilder.h:226

llvm::MachineInstrBuilder::cloneMemRefs

const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const

Definition:MachineInstrBuilder.h:215

llvm::MachineInstrBundleIterator< MachineInstr >

llvm::MachineInstr

Representation of each machine instruction.

Definition:MachineInstr.h:71

llvm::MachineInstr::getNumOperands

unsigned getNumOperands() const

Retuns the total number of operands.

Definition:MachineInstr.h:580

llvm::MachineInstr::mayLoad

bool mayLoad(QueryType Type=AnyInBundle) const

Return true if this instruction could possibly read memory.

Definition:MachineInstr.h:1145

llvm::MachineInstr::tieOperands

void tieOperands(unsigned DefIdx, unsigned UseIdx)

Add a tie between the register operands at DefIdx and UseIdx.

Definition:MachineInstr.cpp:1168

llvm::MachineInstr::addMemOperand

void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)

Add a MachineMemOperand to the machine instruction.

Definition:MachineInstr.cpp:382

llvm::MachineLoop

Definition:MachineLoopInfo.h:46

llvm::MachineMemOperand

A description of a memory reference used in the backend.

Definition:MachineMemOperand.h:129

llvm::MachineMemOperand::getAddrSpace

unsigned getAddrSpace() const

Definition:MachineMemOperand.h:233

llvm::MachineMemOperand::Flags

Flags

Flags values. These may be or'd together.

Definition:MachineMemOperand.h:132

llvm::MachineMemOperand::MOVolatile

@ MOVolatile

The memory access is volatile.

Definition:MachineMemOperand.h:140

llvm::MachineMemOperand::MODereferenceable

@ MODereferenceable

The memory access is dereferenceable (i.e., doesn't trap).

Definition:MachineMemOperand.h:144

llvm::MachineMemOperand::MOLoad

@ MOLoad

The memory access reads data.

Definition:MachineMemOperand.h:136

llvm::MachineMemOperand::MONonTemporal

@ MONonTemporal

The memory access is non-temporal.

Definition:MachineMemOperand.h:142

llvm::MachineMemOperand::MOInvariant

@ MOInvariant

The memory access always returns the same value (or traps).

Definition:MachineMemOperand.h:146

llvm::MachineMemOperand::MOStore

@ MOStore

The memory access writes data.

Definition:MachineMemOperand.h:138

llvm::MachineMemOperand::getFlags

Flags getFlags() const

Return the raw flags of the source value,.

Definition:MachineMemOperand.h:224

llvm::MachineMemOperand::getAlign

Align getAlign() const

Return the minimum known alignment in bytes of the actual memory reference.

Definition:MachineOperand.cpp:1146

llvm::MachineOperand

MachineOperand class - Representation of each machine instruction operand.

Definition:MachineOperand.h:48

llvm::MachineOperand::isReg

bool isReg() const

isReg - Tests if this is a MO_Register operand.

Definition:MachineOperand.h:329

llvm::MachineOperand::isTied

bool isTied() const

Definition:MachineOperand.h:450

llvm::MachineOperand::getIndex

int getIndex() const

Definition:MachineOperand.h:576

llvm::MachineOperand::isFI

bool isFI() const

isFI - Tests if this is a MO_FrameIndex operand.

Definition:MachineOperand.h:339

llvm::MachineRegisterInfo::freezeReservedRegs

void freezeReservedRegs()

freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...

Definition:MachineRegisterInfo.cpp:521

llvm::Module

A Module instance is used to store all the information related to an LLVM module.

Definition:Module.h:65

llvm::PointerType

Class to represent pointers.

Definition:DerivedTypes.h:670

llvm::PointerType::getUnqual

static PointerType * getUnqual(Type *ElementType)

This constructs a pointer to an object of the specified type in the default address space (address sp...

Definition:DerivedTypes.h:686

llvm::ProfileSummaryInfo

Analysis providing profile information.

Definition:ProfileSummaryInfo.h:41

llvm::Register

Wrapper class representing virtual and physical registers.

Definition:Register.h:19

llvm::SelectionDAG

This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...

Definition:SelectionDAG.h:228

llvm::SelectionDAG::getDataLayout

const DataLayout & getDataLayout() const

Definition:SelectionDAG.h:497

llvm::SelectionDAG::getContext

LLVMContext * getContext() const

Definition:SelectionDAG.h:510

llvm::SmallVectorBase::size

size_t size() const

Definition:SmallVector.h:78

llvm::SmallVectorImpl

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

Definition:SmallVector.h:573

llvm::SmallVectorTemplateBase::push_back

void push_back(const T &Elt)

Definition:SmallVector.h:413

llvm::SmallVector

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

Definition:SmallVector.h:1196

llvm::StoreInst

An instruction for storing to memory.

Definition:Instructions.h:292

llvm::StringRef

StringRef - Represent a constant reference to a string, i.e.

Definition:StringRef.h:51

llvm::StringRef::split

std::pair< StringRef, StringRef > split(char Separator) const

Split into two substrings around the first occurrence of a separator character.

Definition:StringRef.h:700

llvm::StringRef::substr

constexpr StringRef substr(size_t Start, size_t N=npos) const

Return a reference to the substring from [Start, Start + N).

Definition:StringRef.h:571

llvm::StringRef::empty

constexpr bool empty() const

empty - Check if the string is empty.

Definition:StringRef.h:147

llvm::StringRef::size

constexpr size_t size() const

size - Get the string size.

Definition:StringRef.h:150

llvm::StringRef::npos

static constexpr size_t npos

Definition:StringRef.h:53

llvm::SuperRegClassIterator

Definition:TargetRegisterInfo.h:1254

llvm::SuperRegClassIterator::isValid

bool isValid() const

Returns true if this iterator is still pointing at a valid entry.

Definition:TargetRegisterInfo.h:1273

llvm::SwitchInst

Multiway switch.

Definition:Instructions.h:3154

llvm::TargetLibraryInfo

Provides information about what library functions are available for the current target.

Definition:TargetLibraryInfo.h:280

llvm::TargetLoweringBase::ValueTypeActionImpl::getTypeAction

LegalizeTypeAction getTypeAction(MVT VT) const

Definition:TargetLowering.h:1110

llvm::TargetLoweringBase::ValueTypeActionImpl::setTypeAction

void setTypeAction(MVT VT, LegalizeTypeAction Action)

Definition:TargetLowering.h:1114

llvm::TargetLoweringBase

This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from ...

Definition:TargetLowering.h:195

llvm::TargetLoweringBase::getByValTypeAlignment

virtual Align getByValTypeAlignment(Type *Ty, const DataLayout &DL) const

Returns the desired alignment for ByVal or InAlloca aggregate function arguments in the caller parame...

Definition:TargetLoweringBase.cpp:1703

llvm::TargetLoweringBase::InstructionOpcodeToISD

int InstructionOpcodeToISD(unsigned Opcode) const

Get the ISD node that corresponds to the Instruction class opcode.

Definition:TargetLoweringBase.cpp:1765

llvm::TargetLoweringBase::setOperationAction

void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)

Indicate that the specified operation does not work with the specified type and indicate what to do a...

Definition:TargetLowering.h:2562

llvm::TargetLoweringBase::finalizeLowering

virtual void finalizeLowering(MachineFunction &MF) const

Execute target specific actions to finalize target lowering.

Definition:TargetLoweringBase.cpp:2246

llvm::TargetLoweringBase::initActions

void initActions()

Initialize all of the actions to default values.

Definition:TargetLoweringBase.cpp:657

llvm::TargetLoweringBase::Enabled

@ Enabled

Definition:TargetLowering.h:576

llvm::TargetLoweringBase::Disabled

@ Disabled

Definition:TargetLowering.h:575

llvm::TargetLoweringBase::Unspecified

@ Unspecified

Definition:TargetLowering.h:574

llvm::TargetLoweringBase::PredictableSelectIsExpensive

bool PredictableSelectIsExpensive

Tells the code generator that select is more expensive than a branch if the branch is usually predict...

Definition:TargetLowering.h:3757

llvm::TargetLoweringBase::Expand

@ Expand

Definition:TargetLowering.h:202

llvm::TargetLoweringBase::Promote

@ Promote

Definition:TargetLowering.h:201

llvm::TargetLoweringBase::LibCall

@ LibCall

Definition:TargetLowering.h:203

llvm::TargetLoweringBase::MaxStoresPerMemcpyOptSize

unsigned MaxStoresPerMemcpyOptSize

Likewise for functions with the OptSize attribute.

Definition:TargetLowering.h:3718

llvm::TargetLoweringBase::emitPatchPoint

MachineBasicBlock * emitPatchPoint(MachineInstr &MI, MachineBasicBlock *MBB) const

Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that...

Definition:TargetLoweringBase.cpp:1155

llvm::TargetLoweringBase::getSafeStackPointerLocation

virtual Value * getSafeStackPointerLocation(IRBuilderBase &IRB) const

Returns the target-specific address of the unsafe stack pointer.

Definition:TargetLoweringBase.cpp:1892

llvm::TargetLoweringBase::getRecipEstimateSqrtEnabled

int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const

Return a ReciprocalEstimate enum value for a square root of the given type based on the function's at...

Definition:TargetLoweringBase.cpp:2198

llvm::TargetLoweringBase::canOpTrap

virtual bool canOpTrap(unsigned Op, EVT VT) const

Returns true if the operation can trap for the value type.

Definition:TargetLoweringBase.cpp:905

llvm::TargetLoweringBase::shouldLocalize

virtual bool shouldLocalize(const MachineInstr &MI, const TargetTransformInfo *TTI) const

Check whether or not MI needs to be moved close to its uses.

Definition:TargetLoweringBase.cpp:2329

llvm::TargetLoweringBase::getMaxPermittedBytesForAlignment

virtual unsigned getMaxPermittedBytesForAlignment(MachineBasicBlock *MBB) const

Return the maximum amount of bytes allowed to be emitted when padding for alignment.

Definition:TargetLoweringBase.cpp:2027

llvm::TargetLoweringBase::setMaximumJumpTableSize

void setMaximumJumpTableSize(unsigned)

Indicate the maximum number of entries in jump tables.

Definition:TargetLoweringBase.cpp:2013

llvm::TargetLoweringBase::getMinimumJumpTableEntries

virtual unsigned getMinimumJumpTableEntries() const

Return lower limit for number of blocks in a jump table.

Definition:TargetLoweringBase.cpp:1997

llvm::TargetLoweringBase::getTargetMachine

const TargetMachine & getTargetMachine() const

Definition:TargetLowering.h:364

llvm::TargetLoweringBase::MaxLoadsPerMemcmp

unsigned MaxLoadsPerMemcmp

Specify maximum number of load instructions per memcmp call.

Definition:TargetLowering.h:3737

llvm::TargetLoweringBase::getNumRegistersForCallingConv

virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const

Certain targets require unusual breakdowns of certain types.

Definition:TargetLowering.h:1795

llvm::TargetLoweringBase::getTargetMMOFlags

virtual MachineMemOperand::Flags getTargetMMOFlags(const Instruction &I) const

This callback is used to inspect load/store instructions and add target-specific MachineMemOperand fl...

Definition:TargetLowering.h:434

llvm::TargetLoweringBase::MaxGluedStoresPerMemcpy

unsigned MaxGluedStoresPerMemcpy

Specify max number of store instructions to glue in inlined memcpy.

Definition:TargetLowering.h:3724

llvm::TargetLoweringBase::getRegisterTypeForCallingConv

virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const

Certain combinations of ABIs, Targets and features require that types are legal for some operations a...

Definition:TargetLowering.h:1787

llvm::TargetLoweringBase::LegalizeTypeAction

LegalizeTypeAction

This enum indicates whether a types are legal for a target, and if not, what action should be used to...

Definition:TargetLowering.h:209

llvm::TargetLoweringBase::TypePromoteInteger

@ TypePromoteInteger

Definition:TargetLowering.h:211

llvm::TargetLoweringBase::TypeSoftenFloat

@ TypeSoftenFloat

Definition:TargetLowering.h:213

llvm::TargetLoweringBase::TypeSplitVector

@ TypeSplitVector

Definition:TargetLowering.h:216

llvm::TargetLoweringBase::TypeExpandFloat

@ TypeExpandFloat

Definition:TargetLowering.h:214

llvm::TargetLoweringBase::TypeWidenVector

@ TypeWidenVector

Definition:TargetLowering.h:217

llvm::TargetLoweringBase::TypeExpandInteger

@ TypeExpandInteger

Definition:TargetLowering.h:212

llvm::TargetLoweringBase::TypeScalarizeScalableVector

@ TypeScalarizeScalableVector

Definition:TargetLowering.h:220

llvm::TargetLoweringBase::TypeSoftPromoteHalf

@ TypeSoftPromoteHalf

Definition:TargetLowering.h:219

llvm::TargetLoweringBase::TypePromoteFloat

@ TypePromoteFloat

Definition:TargetLowering.h:218

llvm::TargetLoweringBase::TypeScalarizeVector

@ TypeScalarizeVector

Definition:TargetLowering.h:215

llvm::TargetLoweringBase::TypeLegal

@ TypeLegal

Definition:TargetLowering.h:210

llvm::TargetLoweringBase::isSuitableForJumpTable

virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases, uint64_t Range, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const

Return true if lowering to a jump table is suitable for a set of case clusters which may contain NumC...

Definition:TargetLoweringBase.cpp:1631

llvm::TargetLoweringBase::setIndexedMaskedLoadAction

void setIndexedMaskedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)

Indicate that the specified indexed masked load does or does not work with the specified type and ind...

Definition:TargetLowering.h:2669

llvm::TargetLoweringBase::getSDagStackGuard

virtual Value * getSDagStackGuard(const Module &M) const

Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nul...

Definition:TargetLoweringBase.cpp:1989

llvm::TargetLoweringBase::useFPRegsForHalfType

virtual bool useFPRegsForHalfType() const

Definition:TargetLowering.h:538

llvm::TargetLoweringBase::isLoadBitCastBeneficial

virtual bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT, const SelectionDAG &DAG, const MachineMemOperand &MMO) const

Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On arch...

Definition:TargetLoweringBase.cpp:2218

llvm::TargetLoweringBase::setIndexedLoadAction

void setIndexedLoadAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)

Indicate that the specified indexed load does or does not work with the specified type and indicate w...

Definition:TargetLowering.h:2635

llvm::TargetLoweringBase::softPromoteHalfType

virtual bool softPromoteHalfType() const

Definition:TargetLowering.h:532

llvm::TargetLoweringBase::getMaximumJumpTableSize

unsigned getMaximumJumpTableSize() const

Return upper limit for number of entries in a jump table.

Definition:TargetLoweringBase.cpp:2009

llvm::TargetLoweringBase::getCmpLibcallReturnType

virtual MVT::SimpleValueType getCmpLibcallReturnType() const

Return the ValueType for comparison libcalls.

Definition:TargetLoweringBase.cpp:1529

llvm::TargetLoweringBase::getBitWidthForCttzElements

unsigned getBitWidthForCttzElements(Type *RetTy, ElementCount EC, bool ZeroIsPoison, const ConstantRange *VScaleRange) const

Return the minimum number of bits required to hold the maximum possible number of trailing zero vecto...

Definition:TargetLoweringBase.cpp:923

llvm::TargetLoweringBase::isLegalRC

bool isLegalRC(const TargetRegisterInfo &TRI, const TargetRegisterClass &RC) const

Return true if the value types that can be represented by the specified register class are all legal.

Definition:TargetLoweringBase.cpp:1144

llvm::TargetLoweringBase::getPreferredVectorAction

virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const

Return the preferred vector type legalization action.

Definition:TargetLowering.h:517

llvm::TargetLoweringBase::setAtomicLoadExtAction

void setAtomicLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)

Let target indicate that an extending atomic load of the specified type is legal.

Definition:TargetLowering.h:2601

llvm::TargetLoweringBase::getDefaultSafeStackPointerLocation

Value * getDefaultSafeStackPointerLocation(IRBuilderBase &IRB, bool UseTLS) const

Definition:TargetLoweringBase.cpp:1856

llvm::TargetLoweringBase::getSSPStackGuardCheck

virtual Function * getSSPStackGuardCheck(const Module &M) const

If the target has a standard stack protection check function that performs validation and error handl...

Definition:TargetLoweringBase.cpp:1993

llvm::TargetLoweringBase::getAtomicMemOperandFlags

MachineMemOperand::Flags getAtomicMemOperandFlags(const Instruction &AI, const DataLayout &DL) const

Definition:TargetLoweringBase.cpp:2289

llvm::TargetLoweringBase::allowsMisalignedMemoryAccesses

virtual bool allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *=nullptr) const

Determine if the target supports unaligned memory accesses.

Definition:TargetLowering.h:1918

llvm::TargetLoweringBase::MaxStoresPerMemsetOptSize

unsigned MaxStoresPerMemsetOptSize

Likewise for functions with the OptSize attribute.

Definition:TargetLowering.h:3703

llvm::TargetLoweringBase::getShiftAmountTy

EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL) const

Returns the type for the shift amount of a shift opcode.

Definition:TargetLoweringBase.cpp:890

llvm::TargetLoweringBase::MaxStoresPerMemmove

unsigned MaxStoresPerMemmove

Specify maximum number of store instructions per memmove call.

Definition:TargetLowering.h:3751

llvm::TargetLoweringBase::getPrefLoopAlignment

virtual Align getPrefLoopAlignment(MachineLoop *ML=nullptr) const

Return the preferred loop alignment.

Definition:TargetLoweringBase.cpp:2021

llvm::TargetLoweringBase::computeRegisterProperties

void computeRegisterProperties(const TargetRegisterInfo *TRI)

Once all of the register classes are added, this allows us to compute derived properties we expose.

Definition:TargetLoweringBase.cpp:1275

llvm::TargetLoweringBase::getDivRefinementSteps

int getDivRefinementSteps(EVT VT, MachineFunction &MF) const

Return the refinement step count for a division of the given type based on the function's attributes.

Definition:TargetLoweringBase.cpp:2213

llvm::TargetLoweringBase::getSetCCResultType

virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const

Return the ValueType of the result of SETCC operations.

Definition:TargetLoweringBase.cpp:1523

llvm::TargetLoweringBase::getLoadMemOperandFlags

MachineMemOperand::Flags getLoadMemOperandFlags(const LoadInst &LI, const DataLayout &DL, AssumptionCache *AC=nullptr, const TargetLibraryInfo *LibInfo=nullptr) const

Definition:TargetLoweringBase.cpp:2250

llvm::TargetLoweringBase::getTypeToTransformTo

virtual EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const

For types supported by the target, this is an identity function.

Definition:TargetLowering.h:1156

llvm::TargetLoweringBase::MaxStoresPerMemmoveOptSize

unsigned MaxStoresPerMemmoveOptSize

Likewise for functions with the OptSize attribute.

Definition:TargetLowering.h:3753

llvm::TargetLoweringBase::getIRStackGuard

virtual Value * getIRStackGuard(IRBuilderBase &IRB) const

If the target has a standard location for the stack protector guard, returns the address of that loca...

Definition:TargetLoweringBase.cpp:1956

llvm::TargetLoweringBase::getPreferredSwitchConditionType

virtual MVT getPreferredSwitchConditionType(LLVMContext &Context, EVT ConditionVT) const

Returns preferred type for switch condition.

Definition:TargetLoweringBase.cpp:1652

llvm::TargetLoweringBase::isTypeLegal

bool isTypeLegal(EVT VT) const

Return true if the target has native support for the specified value type.

Definition:TargetLowering.h:1093

llvm::TargetLoweringBase::EnableExtLdPromotion

bool EnableExtLdPromotion

Definition:TargetLowering.h:3760

llvm::TargetLoweringBase::getRecipEstimateDivEnabled

int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const

Return a ReciprocalEstimate enum value for a division of the given type based on the function's attri...

Definition:TargetLoweringBase.cpp:2203

llvm::TargetLoweringBase::setIndexedStoreAction

void setIndexedStoreAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)

Indicate that the specified indexed store does or does not work with the specified type and indicate ...

Definition:TargetLowering.h:2652

llvm::TargetLoweringBase::isJumpTableRelative

virtual bool isJumpTableRelative() const

Definition:TargetLoweringBase.cpp:2017

llvm::TargetLoweringBase::getScalarShiftAmountTy

virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const

Return the type to use for a scalar shift opcode, given the shifted amount type.

Definition:TargetLoweringBase.cpp:885

llvm::TargetLoweringBase::getPointerTy

virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const

Return the pointer type for the given address space, defaults to the pointer type from the data layou...

Definition:TargetLowering.h:371

llvm::TargetLoweringBase::isFreeAddrSpaceCast

virtual bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const

Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g.

Definition:TargetLoweringBase.cpp:918

llvm::TargetLoweringBase::setIndexedMaskedStoreAction

void setIndexedMaskedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)

Indicate that the specified indexed masked store does or does not work with the specified type and in...

Definition:TargetLowering.h:2679

llvm::TargetLoweringBase::MaxStoresPerMemset

unsigned MaxStoresPerMemset

Specify maximum number of store instructions per memset call.

Definition:TargetLowering.h:3701

llvm::TargetLoweringBase::setMinimumJumpTableEntries

void setMinimumJumpTableEntries(unsigned Val)

Indicate the minimum number of blocks to generate jump tables.

Definition:TargetLoweringBase.cpp:2001

llvm::TargetLoweringBase::setTruncStoreAction

void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)

Indicate that the specified truncating store does not work with the specified type and indicate what ...

Definition:TargetLowering.h:2625

llvm::TargetLoweringBase::UndefinedBooleanContent

@ UndefinedBooleanContent

Definition:TargetLowering.h:235

llvm::TargetLoweringBase::allowsMemoryAccess

virtual bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const

Return true if the target supports a memory access of this type for the given address space and align...

Definition:TargetLoweringBase.cpp:1735

llvm::TargetLoweringBase::MaxLoadsPerMemcmpOptSize

unsigned MaxLoadsPerMemcmpOptSize

Likewise for functions with the OptSize attribute.

Definition:TargetLowering.h:3739

llvm::TargetLoweringBase::getStoreMemOperandFlags

MachineMemOperand::Flags getStoreMemOperandFlags(const StoreInst &SI, const DataLayout &DL) const

Definition:TargetLoweringBase.cpp:2273

llvm::TargetLoweringBase::AddPromotedToType

void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)

If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...

Definition:TargetLowering.h:2710

llvm::TargetLoweringBase::getMinimumJumpTableDensity

unsigned getMinimumJumpTableDensity(bool OptForSize) const

Return lower limit of the density in a jump table.

Definition:TargetLoweringBase.cpp:2005

llvm::TargetLoweringBase::findRepresentativeClass

virtual std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const

Return the largest legal super-reg register class of the register class for the specified type and it...

Definition:TargetLoweringBase.cpp:1248

llvm::TargetLoweringBase::TargetLoweringBase

TargetLoweringBase(const TargetMachine &TM)

NOTE: The TargetMachine owns TLOF.

Definition:TargetLoweringBase.cpp:620

llvm::TargetLoweringBase::getTypeConversion

LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const

Return pair that represents the legalization kind (first) that needs to happen to EVT (second) in ord...

Definition:TargetLoweringBase.cpp:948

llvm::TargetLoweringBase::setLoadExtAction

void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)

Indicate that the specified load with extension does not work with the specified type and indicate wh...

Definition:TargetLowering.h:2579

llvm::TargetLoweringBase::GatherAllAliasesMaxDepth

unsigned GatherAllAliasesMaxDepth

Depth that GatherAllAliases should continue looking for chain dependencies when trying to find a more...

Definition:TargetLowering.h:3689

llvm::TargetLoweringBase::IntrinsicIDToISD

int IntrinsicIDToISD(Intrinsic::ID ID) const

Get the ISD node that corresponds to the Intrinsic ID.

Definition:TargetLoweringBase.cpp:1844

llvm::TargetLoweringBase::getTypeAction

LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const

Return how we should legalize values of this type, either it is already legal (return 'Legal') or we ...

Definition:TargetLowering.h:1143

llvm::TargetLoweringBase::getSqrtRefinementSteps

int getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const

Return the refinement step count for a square root of the given type based on the function's attribut...

Definition:TargetLoweringBase.cpp:2208

llvm::TargetLoweringBase::IsStrictFPEnabled

bool IsStrictFPEnabled

Definition:TargetLowering.h:3772

llvm::TargetLoweringBase::allowsMemoryAccessForAlignment

bool allowsMemoryAccessForAlignment(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const

This function returns true if the memory access is aligned or if the target allows this specific unal...

Definition:TargetLoweringBase.cpp:1708

llvm::TargetLoweringBase::emitTrailingFence

virtual Instruction * emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const

Definition:TargetLoweringBase.cpp:2316

llvm::TargetLoweringBase::emitLeadingFence

virtual Instruction * emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const

Inserts in the IR a target-specific intrinsic specifying a fence.

Definition:TargetLoweringBase.cpp:2307

llvm::TargetLoweringBase::MaxStoresPerMemcpy

unsigned MaxStoresPerMemcpy

Specify maximum number of store instructions per memcpy call.

Definition:TargetLowering.h:3716

llvm::TargetLoweringBase::getRegisterType

MVT getRegisterType(MVT VT) const

Return the type of registers that this ValueType will eventually require.

Definition:TargetLowering.h:1728

llvm::TargetLoweringBase::insertSSPDeclarations

virtual void insertSSPDeclarations(Module &M) const

Inserts necessary declarations for SSP (stack protection) purpose.

Definition:TargetLoweringBase.cpp:1970

llvm::TargetLoweringBase::setJumpIsExpensive

void setJumpIsExpensive(bool isExpensive=true)

Tells the code generator not to expand logic operations on comparison predicates into separate sequen...

Definition:TargetLoweringBase.cpp:941

llvm::TargetLoweringBase::getOperationAction

LegalizeAction getOperationAction(unsigned Op, EVT VT) const

Return how this operation should be treated: either it is legal, needs to be promoted to a larger siz...

Definition:TargetLowering.h:1270

llvm::TargetLoweringBase::getTypeToPromoteTo

MVT getTypeToPromoteTo(unsigned Op, MVT VT) const

If the action for this operation is to promote, this method returns the ValueType to promote to.

Definition:TargetLowering.h:1643

llvm::TargetLoweringBase::isLegalAddressingMode

virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AddrSpace, Instruction *I=nullptr) const

Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...

Definition:TargetLoweringBase.cpp:1911

llvm::TargetLoweringBase::getVectorTypeBreakdown

unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const

Vector types are broken down into some number of legal first class types.

Definition:TargetLoweringBase.cpp:1541

llvm::TargetLoweringBase::LegalizeKind

std::pair< LegalizeTypeAction, EVT > LegalizeKind

LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it.

Definition:TargetLowering.h:231

llvm::TargetLowering

This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...

Definition:TargetLowering.h:3780

llvm::TargetLowering::getTypeForExtReturn

virtual EVT getTypeForExtReturn(LLVMContext &Context, EVT VT, ISD::NodeType) const

Return the type that should be used to zero or sign extend a zeroext/signext integer return value.

Definition:TargetLowering.h:4832

llvm::TargetMachine

Primary interface to the complete machine description for the target machine.

Definition:TargetMachine.h:77

llvm::TargetMachine::isPositionIndependent

bool isPositionIndependent() const

Definition:TargetMachine.cpp:117

llvm::TargetMachine::isNoopAddrSpaceCast

virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const

Returns true if a cast between SrcAS and DestAS is a noop.

Definition:TargetMachine.h:330

llvm::TargetMachine::getTargetTriple

const Triple & getTargetTriple() const

Definition:TargetMachine.h:126

llvm::TargetMachine::getRelocationModel

Reloc::Model getRelocationModel() const

Returns the code generation relocation model.

Definition:TargetMachine.cpp:144

llvm::TargetMachine::Options

TargetOptions Options

Definition:TargetMachine.h:118

llvm::TargetOptions::LoopAlignment

unsigned LoopAlignment

If greater than 0, override TargetLoweringBase::PrefLoopAlignment.

Definition:TargetOptions.h:394

llvm::TargetRegisterClass

Definition:TargetRegisterInfo.h:44

llvm::TargetRegisterInfo

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

Definition:TargetRegisterInfo.h:235

llvm::TargetTransformInfo

This pass provides access to the codegen interfaces that are needed for IR-level transformations.

Definition:TargetTransformInfo.h:212

llvm::TargetTransformInfo::getGISelRematGlobalCost

unsigned getGISelRematGlobalCost() const

Definition:TargetTransformInfo.cpp:1408

llvm::Triple::isWindowsGNUEnvironment

bool isWindowsGNUEnvironment() const

Definition:Triple.h:688

llvm::Triple::isAndroid

bool isAndroid() const

Tests whether the target is Android.

Definition:Triple.h:800

llvm::Triple::isOSFreeBSD

bool isOSFreeBSD() const

Definition:Triple.h:614

llvm::Triple::isPPC64

bool isPPC64() const

Tests whether the target is 64-bit PowerPC (little and big endian).

Definition:Triple.h:1004

llvm::Triple::isOSDarwin

bool isOSDarwin() const

Is this a "Darwin" OS (macOS, iOS, tvOS, watchOS, XROS, or DriverKit).

Definition:Triple.h:588

llvm::Twine

Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...

Definition:Twine.h:81

llvm::TypeSize

Definition:TypeSize.h:334

llvm::Type

The instances of the Type class are immutable: once they are created, they are never changed.

Definition:Type.h:45

llvm::Value

LLVM Value Representation.

Definition:Value.h:74

llvm::Value::getType

Type * getType() const

All values are typed, get the type of this value.

Definition:Value.h:255

llvm::cl::Option::getNumOccurrences

int getNumOccurrences() const

Definition:CommandLine.h:399

llvm::cl::opt

Definition:CommandLine.h:1423

llvm::details::FixedOrScalableQuantity::coefficientNextPowerOf2

constexpr LeafTy coefficientNextPowerOf2() const

Definition:TypeSize.h:262

llvm::details::FixedOrScalableQuantity::isScalable

constexpr bool isScalable() const

Returns whether the quantity is scaled by a runtime quantity (vscale).

Definition:TypeSize.h:171

llvm::details::FixedOrScalableQuantity::getKnownMinValue

constexpr ScalarTy getKnownMinValue() const

Returns the minimum value this quantity can represent.

Definition:TypeSize.h:168

llvm::details::FixedOrScalableQuantity::divideCoefficientBy

constexpr LeafTy divideCoefficientBy(ScalarTy RHS) const

We do not provide the '/' operator here because division for polynomial types does not work in the sa...

Definition:TypeSize.h:254

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

Definition:ErrorHandling.h:143

TargetMachine.h

llvm::CallingConv::Fast

@ Fast

Attempts to make calls as fast as possible (e.g.

Definition:CallingConv.h:41

llvm::CallingConv::C

@ C

The default llvm calling convention, compatible with C.

Definition:CallingConv.h:34

llvm::ISD::NodeType

NodeType

ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.

Definition:ISDOpcodes.h:40

llvm::ISD::SETCC

@ SETCC

SetCC operator - This evaluates to a true value iff the condition is true.

Definition:ISDOpcodes.h:780

llvm::ISD::MERGE_VALUES

@ MERGE_VALUES

MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...

Definition:ISDOpcodes.h:243

llvm::ISD::CTLZ_ZERO_UNDEF

@ CTLZ_ZERO_UNDEF

Definition:ISDOpcodes.h:753

llvm::ISD::STORE

@ STORE

Definition:ISDOpcodes.h:1103

llvm::ISD::LRINT

@ LRINT

Definition:ISDOpcodes.h:1021

llvm::ISD::DELETED_NODE

@ DELETED_NODE

DELETED_NODE - This is an illegal value that is used to catch errors.

Definition:ISDOpcodes.h:44

llvm::ISD::SET_FPENV

@ SET_FPENV

Sets the current floating-point environment.

Definition:ISDOpcodes.h:1069

llvm::ISD::VECREDUCE_SEQ_FADD

@ VECREDUCE_SEQ_FADD

Generic reduction nodes.

Definition:ISDOpcodes.h:1417

llvm::ISD::FLOG10

@ FLOG10

Definition:ISDOpcodes.h:1008

llvm::ISD::VECREDUCE_SMIN

@ VECREDUCE_SMIN

Definition:ISDOpcodes.h:1450

llvm::ISD::SREM

@ SREM

Definition:ISDOpcodes.h:251

llvm::ISD::FGETSIGN

@ FGETSIGN

INT = FGETSIGN(FP) - Return the sign bit of the specified floating point value as an integer 0/1 valu...

Definition:ISDOpcodes.h:512

llvm::ISD::SSUBO_CARRY

@ SSUBO_CARRY

Definition:ISDOpcodes.h:321

llvm::ISD::ATOMIC_LOAD_NAND

@ ATOMIC_LOAD_NAND

Definition:ISDOpcodes.h:1340

llvm::ISD::UDIV

@ UDIV

Definition:ISDOpcodes.h:250

llvm::ISD::UINT_TO_FP

@ UINT_TO_FP

Definition:ISDOpcodes.h:842

llvm::ISD::UMIN

@ UMIN

Definition:ISDOpcodes.h:699

llvm::ISD::SMULFIX

@ SMULFIX

RESULT = [US]MULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication on 2 integers with the same...

Definition:ISDOpcodes.h:374

llvm::ISD::ConstantFP

@ ConstantFP

Definition:ISDOpcodes.h:77

llvm::ISD::ATOMIC_LOAD_MAX

@ ATOMIC_LOAD_MAX

Definition:ISDOpcodes.h:1342

llvm::ISD::UADDO

@ UADDO

Definition:ISDOpcodes.h:331

llvm::ISD::FTRUNC

@ FTRUNC

Definition:ISDOpcodes.h:1013

llvm::ISD::SDIV

@ SDIV

Definition:ISDOpcodes.h:249

llvm::ISD::ATOMIC_LOAD_UMIN

@ ATOMIC_LOAD_UMIN

Definition:ISDOpcodes.h:1343

llvm::ISD::ADDC

@ ADDC

Carry-setting nodes for multiple precision addition and subtraction.

Definition:ISDOpcodes.h:276

llvm::ISD::RESET_FPENV

@ RESET_FPENV

Set floating-point environment to default state.

Definition:ISDOpcodes.h:1073

llvm::ISD::FMAD

@ FMAD

FMAD - Perform a * b + c, while getting the same result as the separately rounded operations.

Definition:ISDOpcodes.h:502

llvm::ISD::FMAXNUM_IEEE

@ FMAXNUM_IEEE

Definition:ISDOpcodes.h:1045

llvm::ISD::LLRINT

@ LLRINT

Definition:ISDOpcodes.h:1022

llvm::ISD::ADD

@ ADD

Simple integer binary arithmetic operators.

Definition:ISDOpcodes.h:246

llvm::ISD::LOAD

@ LOAD

LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...

Definition:ISDOpcodes.h:1102

llvm::ISD::SMULFIXSAT

@ SMULFIXSAT

Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...

Definition:ISDOpcodes.h:380

llvm::ISD::SET_FPMODE

@ SET_FPMODE

Sets the current dynamic floating-point control modes.

Definition:ISDOpcodes.h:1092

llvm::ISD::ANY_EXTEND

@ ANY_EXTEND

ANY_EXTEND - Used for integer types. The high bits are undefined.

Definition:ISDOpcodes.h:814

llvm::ISD::FSUB

@ FSUB

Definition:ISDOpcodes.h:398

llvm::ISD::UMULFIX

@ UMULFIX

Definition:ISDOpcodes.h:375

llvm::ISD::VECTOR_FIND_LAST_ACTIVE

@ VECTOR_FIND_LAST_ACTIVE

Definition:ISDOpcodes.h:1485

llvm::ISD::FATAN2

@ FATAN2

FATAN2 - atan2, inspired by libm.

Definition:ISDOpcodes.h:999

llvm::ISD::SUBC

@ SUBC

Definition:ISDOpcodes.h:277

llvm::ISD::FNEARBYINT

@ FNEARBYINT

Definition:ISDOpcodes.h:1015

llvm::ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS

@ ATOMIC_CMP_SWAP_WITH_SUCCESS

Val, Success, OUTCHAIN = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) N.b.

Definition:ISDOpcodes.h:1325

llvm::ISD::FCOSH

@ FCOSH

Definition:ISDOpcodes.h:992

llvm::ISD::SINT_TO_FP

@ SINT_TO_FP

[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...

Definition:ISDOpcodes.h:841

llvm::ISD::CONCAT_VECTORS

@ CONCAT_VECTORS

CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...

Definition:ISDOpcodes.h:558

llvm::ISD::VECREDUCE_FMAX

@ VECREDUCE_FMAX

FMIN/FMAX nodes can have flags, for NaN/NoNaN variants.

Definition:ISDOpcodes.h:1435

llvm::ISD::FADD

@ FADD

Simple binary floating point operators.

Definition:ISDOpcodes.h:397

llvm::ISD::VECREDUCE_FMAXIMUM

@ VECREDUCE_FMAXIMUM

FMINIMUM/FMAXIMUM nodes propatate NaNs and signed zeroes using the llvm.minimum and llvm....

Definition:ISDOpcodes.h:1439

llvm::ISD::ABS

@ ABS

ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth.

Definition:ISDOpcodes.h:717

llvm::ISD::FEXP10

@ FEXP10

Definition:ISDOpcodes.h:1011

llvm::ISD::RESET_FPMODE

@ RESET_FPMODE

Sets default dynamic floating-point control modes.

Definition:ISDOpcodes.h:1096

llvm::ISD::SIGN_EXTEND_VECTOR_INREG

@ SIGN_EXTEND_VECTOR_INREG

SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register sign-extension of the low ...

Definition:ISDOpcodes.h:871

llvm::ISD::FACOS

@ FACOS

Definition:ISDOpcodes.h:989

llvm::ISD::VECREDUCE_SMAX

@ VECREDUCE_SMAX

Definition:ISDOpcodes.h:1449

llvm::ISD::SRL

@ SRL

Definition:ISDOpcodes.h:737

llvm::ISD::FMAXIMUM

@ FMAXIMUM

Definition:ISDOpcodes.h:1051

llvm::ISD::FATAN

@ FATAN

Definition:ISDOpcodes.h:990

llvm::ISD::ATOMIC_LOAD_OR

@ ATOMIC_LOAD_OR

Definition:ISDOpcodes.h:1338

llvm::ISD::BITCAST

@ BITCAST

BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...

Definition:ISDOpcodes.h:954

llvm::ISD::ATOMIC_LOAD_XOR

@ ATOMIC_LOAD_XOR

Definition:ISDOpcodes.h:1339

llvm::ISD::FFLOOR

@ FFLOOR

Definition:ISDOpcodes.h:1018

llvm::ISD::FLDEXP

@ FLDEXP

FLDEXP - ldexp, inspired by libm (op0 * 2**op1).

Definition:ISDOpcodes.h:997

llvm::ISD::SDIVFIX

@ SDIVFIX

RESULT = [US]DIVFIX(LHS, RHS, SCALE) - Perform fixed point division on 2 integers with the same width...

Definition:ISDOpcodes.h:387

llvm::ISD::BUILTIN_OP_END

@ BUILTIN_OP_END

BUILTIN_OP_END - This must be the last enum value in this list.

Definition:ISDOpcodes.h:1494

llvm::ISD::UCMP

@ UCMP

Definition:ISDOpcodes.h:706

llvm::ISD::SRA

@ SRA

Definition:ISDOpcodes.h:736

llvm::ISD::LLROUND

@ LLROUND

Definition:ISDOpcodes.h:1020

llvm::ISD::USUBO

@ USUBO

Definition:ISDOpcodes.h:335

llvm::ISD::AVGFLOORU

@ AVGFLOORU

Definition:ISDOpcodes.h:681

llvm::ISD::SIGN_EXTEND

@ SIGN_EXTEND

Conversion operators.

Definition:ISDOpcodes.h:805

llvm::ISD::FLOG2

@ FLOG2

Definition:ISDOpcodes.h:1007

llvm::ISD::AVGCEILS

@ AVGCEILS

AVGCEILS/AVGCEILU - Rounding averaging add - Add two integers using an integer of type i[N+2],...

Definition:ISDOpcodes.h:685

llvm::ISD::READSTEADYCOUNTER

@ READSTEADYCOUNTER

READSTEADYCOUNTER - This corresponds to the readfixedcounter intrinsic.

Definition:ISDOpcodes.h:1259

llvm::ISD::USHLSAT

@ USHLSAT

Definition:ISDOpcodes.h:367

llvm::ISD::UDIVFIXSAT

@ UDIVFIXSAT

Definition:ISDOpcodes.h:394

llvm::ISD::VECREDUCE_FADD

@ VECREDUCE_FADD

These reductions have relaxed evaluation order semantics, and have a single vector operand.

Definition:ISDOpcodes.h:1432

llvm::ISD::UADDSAT

@ UADDSAT

Definition:ISDOpcodes.h:348

llvm::ISD::CTTZ_ZERO_UNDEF

@ CTTZ_ZERO_UNDEF

Bit counting operators with an undefined result for zero inputs.

Definition:ISDOpcodes.h:752

llvm::ISD::FASIN

@ FASIN

Definition:ISDOpcodes.h:988

llvm::ISD::FMAXNUM

@ FMAXNUM

Definition:ISDOpcodes.h:1032

llvm::ISD::FPOWI

@ FPOWI

Definition:ISDOpcodes.h:995

llvm::ISD::FRINT

@ FRINT

Definition:ISDOpcodes.h:1014

llvm::ISD::PREFETCH

@ PREFETCH

PREFETCH - This corresponds to a prefetch intrinsic.

Definition:ISDOpcodes.h:1292

llvm::ISD::TRUNCATE_SSAT_U

@ TRUNCATE_SSAT_U

Definition:ISDOpcodes.h:834

llvm::ISD::VECREDUCE_FMIN

@ VECREDUCE_FMIN

Definition:ISDOpcodes.h:1436

llvm::ISD::FSINCOS

@ FSINCOS

FSINCOS - Compute both fsin and fcos as a single operation.

Definition:ISDOpcodes.h:1059

llvm::ISD::SETCCCARRY

@ SETCCCARRY

Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but op #2 is a boolean indicating ...

Definition:ISDOpcodes.h:788

llvm::ISD::FNEG

@ FNEG

Perform various unary floating-point operations inspired by libm.

Definition:ISDOpcodes.h:981

llvm::ISD::SSUBO

@ SSUBO

Same for subtraction.

Definition:ISDOpcodes.h:334

llvm::ISD::ATOMIC_LOAD_MIN

@ ATOMIC_LOAD_MIN

Definition:ISDOpcodes.h:1341

llvm::ISD::FP_TO_UINT

@ FP_TO_UINT

Definition:ISDOpcodes.h:888

llvm::ISD::OR

@ OR

Definition:ISDOpcodes.h:710

llvm::ISD::IS_FPCLASS

@ IS_FPCLASS

Performs a check of floating point class property, defined by IEEE-754.

Definition:ISDOpcodes.h:522

llvm::ISD::SSUBSAT

@ SSUBSAT

RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2 integers with the same bit width ...

Definition:ISDOpcodes.h:356

llvm::ISD::UMULO

@ UMULO

Definition:ISDOpcodes.h:339

llvm::ISD::SELECT

@ SELECT

Select(COND, TRUEVAL, FALSEVAL).

Definition:ISDOpcodes.h:757

llvm::ISD::VECREDUCE_UMAX

@ VECREDUCE_UMAX

Definition:ISDOpcodes.h:1451

llvm::ISD::FTANH

@ FTANH

Definition:ISDOpcodes.h:993

llvm::ISD::SPLAT_VECTOR

@ SPLAT_VECTOR

SPLAT_VECTOR(VAL) - Returns a vector with the scalar value VAL duplicated in all lanes.

Definition:ISDOpcodes.h:642

llvm::ISD::FSHL

@ FSHL

Definition:ISDOpcodes.h:740

llvm::ISD::AVGCEILU

@ AVGCEILU

Definition:ISDOpcodes.h:686

llvm::ISD::FCBRT

@ FCBRT

Definition:ISDOpcodes.h:984

llvm::ISD::SADDO

@ SADDO

RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.

Definition:ISDOpcodes.h:330

llvm::ISD::FSHR

@ FSHR

Definition:ISDOpcodes.h:741

llvm::ISD::FROUND

@ FROUND

Definition:ISDOpcodes.h:1016

llvm::ISD::USUBSAT

@ USUBSAT

Definition:ISDOpcodes.h:357

llvm::ISD::VECREDUCE_ADD

@ VECREDUCE_ADD

Integer reductions may have a result type larger than the vector element type.

Definition:ISDOpcodes.h:1444

llvm::ISD::GET_FPMODE

@ GET_FPMODE

Reads the current dynamic floating-point control modes.

Definition:ISDOpcodes.h:1087

llvm::ISD::GET_FPENV

@ GET_FPENV

Gets the current floating-point environment.

Definition:ISDOpcodes.h:1064

llvm::ISD::SHL

@ SHL

Shift and rotation operations.

Definition:ISDOpcodes.h:735

llvm::ISD::ATOMIC_LOAD_CLR

@ ATOMIC_LOAD_CLR

Definition:ISDOpcodes.h:1337

llvm::ISD::VECTOR_SHUFFLE

@ VECTOR_SHUFFLE

VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.

Definition:ISDOpcodes.h:615

llvm::ISD::ATOMIC_LOAD_AND

@ ATOMIC_LOAD_AND

Definition:ISDOpcodes.h:1336

llvm::ISD::FMINNUM_IEEE

@ FMINNUM_IEEE

FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimumNumber or maximumNumber on two values,...

Definition:ISDOpcodes.h:1044

llvm::ISD::XOR

@ XOR

Definition:ISDOpcodes.h:711

llvm::ISD::EXTRACT_VECTOR_ELT

@ EXTRACT_VECTOR_ELT

EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...

Definition:ISDOpcodes.h:550

llvm::ISD::ZERO_EXTEND

@ ZERO_EXTEND

ZERO_EXTEND - Used for integer types, zeroing the new bits.

Definition:ISDOpcodes.h:811

llvm::ISD::DEBUGTRAP

@ DEBUGTRAP

DEBUGTRAP - Trap intended to get the attention of a debugger.

Definition:ISDOpcodes.h:1282

llvm::ISD::FP_TO_UINT_SAT

@ FP_TO_UINT_SAT

Definition:ISDOpcodes.h:907

llvm::ISD::FMUL

@ FMUL

Definition:ISDOpcodes.h:399

llvm::ISD::VECREDUCE_XOR

@ VECREDUCE_XOR

Definition:ISDOpcodes.h:1448

llvm::ISD::ATOMIC_CMP_SWAP

@ ATOMIC_CMP_SWAP

Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo,...

Definition:ISDOpcodes.h:1319

llvm::ISD::ATOMIC_LOAD_UMAX

@ ATOMIC_LOAD_UMAX

Definition:ISDOpcodes.h:1344

llvm::ISD::FTAN

@ FTAN

Definition:ISDOpcodes.h:987

llvm::ISD::FMINNUM

@ FMINNUM

FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.

Definition:ISDOpcodes.h:1031

llvm::ISD::SUB

@ SUB

Definition:ISDOpcodes.h:247

llvm::ISD::UBSANTRAP

@ UBSANTRAP

UBSANTRAP - Trap with an immediate describing the kind of sanitizer failure.

Definition:ISDOpcodes.h:1286

llvm::ISD::SSHLSAT

@ SSHLSAT

RESULT = [US]SHLSAT(LHS, RHS) - Perform saturation left shift.

Definition:ISDOpcodes.h:366

llvm::ISD::SMULO

@ SMULO

Same for multiplication.

Definition:ISDOpcodes.h:338

llvm::ISD::PARITY

@ PARITY

Definition:ISDOpcodes.h:749

llvm::ISD::VECREDUCE_AND

@ VECREDUCE_AND

Definition:ISDOpcodes.h:1446

llvm::ISD::ANY_EXTEND_VECTOR_INREG

@ ANY_EXTEND_VECTOR_INREG

ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register any-extension of the low la...

Definition:ISDOpcodes.h:860

llvm::ISD::SIGN_EXTEND_INREG

@ SIGN_EXTEND_INREG

SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...

Definition:ISDOpcodes.h:849

llvm::ISD::UDIVFIX

@ UDIVFIX

Definition:ISDOpcodes.h:388

llvm::ISD::UMULFIXSAT

@ UMULFIXSAT

Definition:ISDOpcodes.h:381

llvm::ISD::SMIN

@ SMIN

[US]{MIN/MAX} - Binary minimum or maximum of signed or unsigned integers.

Definition:ISDOpcodes.h:697

llvm::ISD::SDIVFIXSAT

@ SDIVFIXSAT

Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...

Definition:ISDOpcodes.h:393

llvm::ISD::FP_EXTEND

@ FP_EXTEND

X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.

Definition:ISDOpcodes.h:939

llvm::ISD::VECREDUCE_OR

@ VECREDUCE_OR

Definition:ISDOpcodes.h:1447

llvm::ISD::UADDO_CARRY

@ UADDO_CARRY

Carry-using nodes for multiple precision addition and subtraction.

Definition:ISDOpcodes.h:310

llvm::ISD::FROUNDEVEN

@ FROUNDEVEN

Definition:ISDOpcodes.h:1017

llvm::ISD::VECREDUCE_MUL

@ VECREDUCE_MUL

Definition:ISDOpcodes.h:1445

llvm::ISD::VECREDUCE_UMIN

@ VECREDUCE_UMIN

Definition:ISDOpcodes.h:1452

llvm::ISD::FDIV

@ FDIV

Definition:ISDOpcodes.h:400

llvm::ISD::FREM

@ FREM

Definition:ISDOpcodes.h:401

llvm::ISD::ATOMIC_LOAD_ADD

@ ATOMIC_LOAD_ADD

Definition:ISDOpcodes.h:1334

llvm::ISD::FMINIMUM

@ FMINIMUM

FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0....

Definition:ISDOpcodes.h:1050

llvm::ISD::ATOMIC_LOAD_SUB

@ ATOMIC_LOAD_SUB

Definition:ISDOpcodes.h:1335

llvm::ISD::FP_TO_SINT

@ FP_TO_SINT

FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.

Definition:ISDOpcodes.h:887

llvm::ISD::READCYCLECOUNTER

@ READCYCLECOUNTER

READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.

Definition:ISDOpcodes.h:1253

llvm::ISD::AND

@ AND

Bitwise operators - logical and, logical or, logical xor.

Definition:ISDOpcodes.h:709

llvm::ISD::TRAP

@ TRAP

TRAP - Trapping instruction.

Definition:ISDOpcodes.h:1279

llvm::ISD::GET_FPENV_MEM

@ GET_FPENV_MEM

Gets the current floating-point environment.

Definition:ISDOpcodes.h:1078

llvm::ISD::USUBO_CARRY

@ USUBO_CARRY

Definition:ISDOpcodes.h:311

llvm::ISD::FLOG

@ FLOG

Definition:ISDOpcodes.h:1006

llvm::ISD::SUBE

@ SUBE

Definition:ISDOpcodes.h:287

llvm::ISD::SCMP

@ SCMP

[US]CMP - 3-way comparison of signed or unsigned integers.

Definition:ISDOpcodes.h:705

llvm::ISD::AVGFLOORS

@ AVGFLOORS

AVGFLOORS/AVGFLOORU - Averaging add - Add two integers using an integer of type i[N+1],...

Definition:ISDOpcodes.h:680

llvm::ISD::VECREDUCE_FMUL

@ VECREDUCE_FMUL

Definition:ISDOpcodes.h:1433

llvm::ISD::ADDE

@ ADDE

Carry-using nodes for multiple precision addition and subtraction.

Definition:ISDOpcodes.h:286

llvm::ISD::UREM

@ UREM

Definition:ISDOpcodes.h:252

llvm::ISD::FREEZE

@ FREEZE

FREEZE - FREEZE(VAL) returns an arbitrary value if VAL is UNDEF (or is evaluated to UNDEF),...

Definition:ISDOpcodes.h:223

llvm::ISD::INSERT_VECTOR_ELT

@ INSERT_VECTOR_ELT

INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL.

Definition:ISDOpcodes.h:539

llvm::ISD::FEXP

@ FEXP

Definition:ISDOpcodes.h:1009

llvm::ISD::VECTOR_SPLICE

@ VECTOR_SPLICE

VECTOR_SPLICE(VEC1, VEC2, IMM) - Returns a subvector of the same type as VEC1/VEC2 from CONCAT_VECTOR...

Definition:ISDOpcodes.h:627

llvm::ISD::FCEIL

@ FCEIL

Definition:ISDOpcodes.h:1012

llvm::ISD::ATOMIC_SWAP

@ ATOMIC_SWAP

Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN,...

Definition:ISDOpcodes.h:1333

llvm::ISD::MUL

@ MUL

Definition:ISDOpcodes.h:248

llvm::ISD::FSINH

@ FSINH

Definition:ISDOpcodes.h:991

llvm::ISD::FFREXP

@ FFREXP

FFREXP - frexp, extract fractional and exponent component of a floating-point value.

Definition:ISDOpcodes.h:1004

llvm::ISD::FP_ROUND

@ FP_ROUND

X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...

Definition:ISDOpcodes.h:920

llvm::ISD::VECTOR_COMPRESS

@ VECTOR_COMPRESS

VECTOR_COMPRESS(Vec, Mask, Passthru) consecutively place vector elements based on mask e....

Definition:ISDOpcodes.h:669

llvm::ISD::LROUND

@ LROUND

Definition:ISDOpcodes.h:1019

llvm::ISD::FMAXIMUMNUM

@ FMAXIMUMNUM

Definition:ISDOpcodes.h:1056

llvm::ISD::CLEAR_CACHE

@ CLEAR_CACHE

Definition:ISDOpcodes.h:1490

llvm::ISD::ZERO_EXTEND_VECTOR_INREG

@ ZERO_EXTEND_VECTOR_INREG

ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register zero-extension of the low ...

Definition:ISDOpcodes.h:882

llvm::ISD::ADDRSPACECAST

@ ADDRSPACECAST

ADDRSPACECAST - This operator converts between pointers of different address spaces.

Definition:ISDOpcodes.h:958

llvm::ISD::FP_TO_SINT_SAT

@ FP_TO_SINT_SAT

FP_TO_[US]INT_SAT - Convert floating point value in operand 0 to a signed or unsigned scalar integer ...

Definition:ISDOpcodes.h:906

llvm::ISD::VECREDUCE_FMINIMUM

@ VECREDUCE_FMINIMUM

Definition:ISDOpcodes.h:1440

llvm::ISD::TRUNCATE

@ TRUNCATE

TRUNCATE - Completely drop the high bits.

Definition:ISDOpcodes.h:817

llvm::ISD::VECREDUCE_SEQ_FMUL

@ VECREDUCE_SEQ_FMUL

Definition:ISDOpcodes.h:1418

llvm::ISD::BITREVERSE

@ BITREVERSE

Definition:ISDOpcodes.h:748

llvm::ISD::FCOPYSIGN

@ FCOPYSIGN

FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.

Definition:ISDOpcodes.h:508

llvm::ISD::SADDSAT

@ SADDSAT

RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 integers with the same bit width (W)...

Definition:ISDOpcodes.h:347

llvm::ISD::FEXP2

@ FEXP2

Definition:ISDOpcodes.h:1010

llvm::ISD::SMAX

@ SMAX

Definition:ISDOpcodes.h:698

llvm::ISD::GET_DYNAMIC_AREA_OFFSET

@ GET_DYNAMIC_AREA_OFFSET

GET_DYNAMIC_AREA_OFFSET - get offset from native SP to the address of the most recent dynamic alloca.

Definition:ISDOpcodes.h:1398

llvm::ISD::UMAX

@ UMAX

Definition:ISDOpcodes.h:700

llvm::ISD::SET_FPENV_MEM

@ SET_FPENV_MEM

Sets the current floating point environment.

Definition:ISDOpcodes.h:1083

llvm::ISD::FMINIMUMNUM

@ FMINIMUMNUM

FMINIMUMNUM/FMAXIMUMNUM - minimumnum/maximumnum that is same with FMINNUM_IEEE and FMAXNUM_IEEE besid...

Definition:ISDOpcodes.h:1055

llvm::ISD::TRUNCATE_SSAT_S

@ TRUNCATE_SSAT_S

TRUNCATE_[SU]SAT_[SU] - Truncate for saturated operand [SU] located in middle, prefix for SAT means i...

Definition:ISDOpcodes.h:832

llvm::ISD::ABDS

@ ABDS

ABDS/ABDU - Absolute difference - Return the absolute difference between two numbers interpreted as s...

Definition:ISDOpcodes.h:692

llvm::ISD::TRUNCATE_USAT_U

@ TRUNCATE_USAT_U

Definition:ISDOpcodes.h:836

llvm::ISD::SADDO_CARRY

@ SADDO_CARRY

Carry-using overflow-aware nodes for multiple precision addition and subtraction.

Definition:ISDOpcodes.h:320

llvm::ISD::ABDU

@ ABDU

Definition:ISDOpcodes.h:693

llvm::ISD::PRE_INC

@ PRE_INC

Definition:ISDOpcodes.h:1559

llvm::ISD::CondCode

CondCode

ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...

Definition:ISDOpcodes.h:1610

llvm::ISD::SETNE

@ SETNE

Definition:ISDOpcodes.h:1635

llvm::ISD::SETGT

@ SETGT

Definition:ISDOpcodes.h:1631

llvm::ISD::SETLT

@ SETLT

Definition:ISDOpcodes.h:1633

llvm::ISD::SETGE

@ SETGE

Definition:ISDOpcodes.h:1632

llvm::ISD::SETLE

@ SETLE

Definition:ISDOpcodes.h:1634

llvm::ISD::SETEQ

@ SETEQ

Definition:ISDOpcodes.h:1630

llvm::ISD::SETCC_INVALID

@ SETCC_INVALID

Definition:ISDOpcodes.h:1638

llvm::ISD::SEXTLOAD

@ SEXTLOAD

Definition:ISDOpcodes.h:1590

llvm::ISD::ZEXTLOAD

@ ZEXTLOAD

Definition:ISDOpcodes.h:1590

llvm::ISD::EXTLOAD

@ EXTLOAD

Definition:ISDOpcodes.h:1590

llvm::ISD::LAST_INDEXED_MODE

static const int LAST_INDEXED_MODE

Definition:ISDOpcodes.h:1561

llvm::RTLIB::getFSINCOS

Libcall getFSINCOS(EVT RetVT)

getFSINCOS - Return the FSINCOS_* value for the given types, or UNKNOWN_LIBCALL if there is none.

Definition:TargetLoweringBase.cpp:405

llvm::RTLIB::getPOWI

Libcall getPOWI(EVT RetVT)

getPOWI - Return the POWI_* value for the given types, or UNKNOWN_LIBCALL if there is none.

Definition:TargetLoweringBase.cpp:390

llvm::RTLIB::getSINTTOFP

Libcall getSINTTOFP(EVT OpVT, EVT RetVT)

getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.

Definition:TargetLoweringBase.cpp:300

llvm::RTLIB::initCmpLibcallCCs

void initCmpLibcallCCs(ISD::CondCode *CmpLibcallCCs)

Initialize the default condition code on the libcalls.

Definition:TargetLoweringBase.cpp:586

llvm::RTLIB::getSYNC

Libcall getSYNC(unsigned Opc, MVT VT)

Return the SYNC_FETCH_AND_* value for the given opcode and type, or UNKNOWN_LIBCALL if there is none.

Definition:TargetLoweringBase.cpp:497

llvm::RTLIB::getLDEXP

Libcall getLDEXP(EVT RetVT)

getLDEXP - Return the LDEXP_* value for the given types, or UNKNOWN_LIBCALL if there is none.

Definition:TargetLoweringBase.cpp:395

llvm::RTLIB::getUINTTOFP

Libcall getUINTTOFP(EVT OpVT, EVT RetVT)

getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.

Definition:TargetLoweringBase.cpp:346

llvm::RTLIB::getFREXP

Libcall getFREXP(EVT RetVT)

getFREXP - Return the FREXP_* value for the given types, or UNKNOWN_LIBCALL if there is none.

Definition:TargetLoweringBase.cpp:400

llvm::RTLIB::Libcall

Libcall

RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit.

Definition:RuntimeLibcalls.h:33

llvm::RTLIB::getMEMCPY_ELEMENT_UNORDERED_ATOMIC

Libcall getMEMCPY_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)

getMEMCPY_ELEMENT_UNORDERED_ATOMIC - Return MEMCPY_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...

Definition:TargetLoweringBase.cpp:535

llvm::RTLIB::getFPTOUINT

Libcall getFPTOUINT(EVT OpVT, EVT RetVT)

getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.

Definition:TargetLoweringBase.cpp:251

llvm::RTLIB::getFPTOSINT

Libcall getFPTOSINT(EVT OpVT, EVT RetVT)

getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.

Definition:TargetLoweringBase.cpp:202

llvm::RTLIB::getOUTLINE_ATOMIC

Libcall getOUTLINE_ATOMIC(unsigned Opc, AtomicOrdering Order, MVT VT)

Return the outline atomics value for the given opcode, atomic ordering and type, or UNKNOWN_LIBCALL i...

Definition:TargetLoweringBase.cpp:455

llvm::RTLIB::getFPEXT

Libcall getFPEXT(EVT OpVT, EVT RetVT)

getFPEXT - Return the FPEXT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.

Definition:TargetLoweringBase.cpp:120

llvm::RTLIB::getFPROUND

Libcall getFPROUND(EVT OpVT, EVT RetVT)

getFPROUND - Return the FPROUND_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.

Definition:TargetLoweringBase.cpp:155

llvm::RTLIB::getMEMSET_ELEMENT_UNORDERED_ATOMIC

Libcall getMEMSET_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)

getMEMSET_ELEMENT_UNORDERED_ATOMIC - Return MEMSET_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...

Definition:TargetLoweringBase.cpp:569

llvm::RTLIB::getOutlineAtomicHelper

Libcall getOutlineAtomicHelper(const Libcall(&LC)[5][4], AtomicOrdering Order, uint64_t MemSize)

Return the outline atomics value for the given atomic ordering, access size and set of libcalls for a...

Definition:TargetLoweringBase.cpp:410

llvm::RTLIB::getFPLibCall

Libcall getFPLibCall(EVT VT, Libcall Call_F32, Libcall Call_F64, Libcall Call_F80, Libcall Call_F128, Libcall Call_PPCF128)

GetFPLibCall - Helper to return the right libcall for the given floating point type,...

Definition:TargetLoweringBase.cpp:103

llvm::RTLIB::getMEMMOVE_ELEMENT_UNORDERED_ATOMIC

Libcall getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)

getMEMMOVE_ELEMENT_UNORDERED_ATOMIC - Return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_* value for the given e...

Definition:TargetLoweringBase.cpp:552

llvm::Reloc::Static

@ Static

Definition:CodeGen.h:25

llvm::Sched::ILP

@ ILP

Definition:TargetLowering.h:105

llvm::cl::Hidden

@ Hidden

Definition:CommandLine.h:137

llvm::cl::init

initializer< Ty > init(const Ty &Val)

Definition:CommandLine.h:443

llvm

This is an optimization pass for GlobalISel generic memory operations.

Definition:AddressRanges.h:18

llvm::Log2_32_Ceil

unsigned Log2_32_Ceil(uint32_t Value)

Return the ceil log base 2 of the specified value, 32 if the value is zero.

Definition:MathExtras.h:354

llvm::GetReturnInfo

void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)

Given an LLVM IR type and return type attributes, compute the return value EVTs and flags,...

Definition:TargetLoweringBase.cpp:1661

llvm::BuildMI

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

Definition:MachineInstrBuilder.h:373

llvm::enum_seq

auto enum_seq(EnumT Begin, EnumT End)

Iterate over an enum type from Begin up to - but not including - End.

Definition:Sequence.h:337

llvm::isDereferenceableAndAlignedPointer

bool isDereferenceableAndAlignedPointer(const Value *V, Type *Ty, Align Alignment, const DataLayout &DL, const Instruction *CtxI=nullptr, AssumptionCache *AC=nullptr, const DominatorTree *DT=nullptr, const TargetLibraryInfo *TLI=nullptr)

Returns true if V is always a dereferenceable pointer with alignment greater or equal than requested.

Definition:Loads.cpp:217

llvm::shouldOptimizeForSize

bool shouldOptimizeForSize(const MachineFunction *MF, ProfileSummaryInfo *PSI, const MachineBlockFrequencyInfo *BFI, PGSOQueryType QueryType=PGSOQueryType::Other)

Returns true if machine function MF is suggested to be size-optimized based on the profile.

Definition:MachineSizeOpts.cpp:27

llvm::force_iteration_on_noniterable_enum

constexpr force_iteration_on_noniterable_enum_t force_iteration_on_noniterable_enum

Definition:Sequence.h:108

llvm::bit_ceil

T bit_ceil(T Value)

Returns the smallest integral power of two no smaller than Value if Value is nonzero.

Definition:bit.h:342

llvm::isReleaseOrStronger

bool isReleaseOrStronger(AtomicOrdering AO)

Definition:AtomicOrdering.h:133

llvm::isPowerOf2_32

constexpr bool isPowerOf2_32(uint32_t Value)

Return true if the argument is a power of two > 0.

Definition:MathExtras.h:292

llvm::none_of

bool none_of(R &&Range, UnaryPredicate P)

Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.

Definition:STLExtras.h:1753

llvm::report_fatal_error

void report_fatal_error(Error Err, bool gen_crash_diag=true)

Report a serious error, calling any installed error handler.

Definition:Error.cpp:167

llvm::AtomicOrdering

AtomicOrdering

Atomic ordering for LLVM's memory model.

Definition:AtomicOrdering.h:56

llvm::getApproximateEVTForLLT

EVT getApproximateEVTForLLT(LLT Ty, LLVMContext &Ctx)

Definition:LowLevelTypeUtils.cpp:57

llvm::divideCeil

constexpr T divideCeil(U Numerator, V Denominator)

Returns the integer ceil(Numerator / Denominator).

Definition:MathExtras.h:404

llvm::RecurKind::Or

@ Or

Bitwise or logical OR of integers.

llvm::RecurKind::Mul

@ Mul

Product of integers.

llvm::RecurKind::Xor

@ Xor

Bitwise or logical XOR of integers.

llvm::RecurKind::FMul

@ FMul

Product of floats.

llvm::RecurKind::And

@ And

Bitwise or logical AND of integers.

llvm::RecurKind::Add

@ Add

Sum of integers.

llvm::RecurKind::FAdd

@ FAdd

Sum of floats.

llvm::ComputeValueVTs

void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< EVT > *MemVTs, SmallVectorImpl< TypeSize > *Offsets=nullptr, TypeSize StartingOffset=TypeSize::getZero())

ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...

Definition:Analysis.cpp:79

llvm::isAcquireOrStronger

bool isAcquireOrStronger(AtomicOrdering AO)

Definition:AtomicOrdering.h:129

llvm::Cost

InstructionCost Cost

Definition:FunctionSpecialization.h:102

llvm::Align

This struct is a compact representation of a valid (non-zero power of two) alignment.

Definition:Alignment.h:39

llvm::EVT

Extended Value Type.

Definition:ValueTypes.h:35

llvm::EVT::getPow2VectorType

EVT getPow2VectorType(LLVMContext &Context) const

Widens the length of the given vector EVT up to the nearest power of 2 and returns that type.

Definition:ValueTypes.h:472

llvm::EVT::isSimple

bool isSimple() const

Test if the given EVT is simple (as opposed to being extended).

Definition:ValueTypes.h:137

llvm::EVT::getVectorVT

static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)

Returns the EVT that represents a vector NumElements in length, where each element is of type VT.

Definition:ValueTypes.h:74

llvm::EVT::getVectorElementCount

ElementCount getVectorElementCount() const

Definition:ValueTypes.h:345

llvm::EVT::getSizeInBits

TypeSize getSizeInBits() const

Return the size of the specified value type in bits.

Definition:ValueTypes.h:368

llvm::EVT::isPow2VectorType

bool isPow2VectorType() const

Returns true if the given vector is a power of 2.

Definition:ValueTypes.h:465

llvm::EVT::getSimpleVT

MVT getSimpleVT() const

Return the SimpleValueType held in the specified simple EVT.

Definition:ValueTypes.h:311

llvm::EVT::getIntegerVT

static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)

Returns the EVT that represents an integer with the given number of bits.

Definition:ValueTypes.h:65

llvm::EVT::isFixedLengthVector

bool isFixedLengthVector() const

Definition:ValueTypes.h:181

llvm::EVT::getRoundIntegerType

EVT getRoundIntegerType(LLVMContext &Context) const

Rounds the bit-width of the given integer EVT up to the nearest power of two (and at least to eight),...

Definition:ValueTypes.h:414

llvm::EVT::isVector

bool isVector() const

Return true if this is a vector value type.

Definition:ValueTypes.h:168

llvm::EVT::getScalarType

EVT getScalarType() const

If this is a vector type, return the element type, otherwise return this.

Definition:ValueTypes.h:318

llvm::EVT::getTypeForEVT

Type * getTypeForEVT(LLVMContext &Context) const

This method returns an LLVM type corresponding to the specified EVT.

Definition:ValueTypes.cpp:210

llvm::EVT::getVectorElementType

EVT getVectorElementType() const

Given a vector type, return the type of each element.

Definition:ValueTypes.h:323

llvm::EVT::getVectorNumElements

unsigned getVectorNumElements() const

Given a vector type, return the number of elements it contains.

Definition:ValueTypes.h:331

llvm::EVT::isZeroSized

bool isZeroSized() const

Test if the given EVT has zero size, this will fail if called on a scalable type.

Definition:ValueTypes.h:132

llvm::EVT::getHalfNumVectorElementsVT

EVT getHalfNumVectorElementsVT(LLVMContext &Context) const

Definition:ValueTypes.h:448

llvm::EVT::isInteger

bool isInteger() const

Return true if this is an integer or a vector integer type.

Definition:ValueTypes.h:152

llvm::ISD::ArgFlagsTy

Definition:TargetCallingConv.h:27

llvm::ISD::OutputArg

OutputArg - This struct carries flags and a value for a single outgoing (actual) argument or outgoing...

Definition:TargetCallingConv.h:237

llvm::MachinePointerInfo::getFixedStack

static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)

Return a MachinePointerInfo record that refers to the specified FrameIndex.

Definition:MachineOperand.cpp:1072

llvm::TargetLoweringBase::AddrMode

This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg + ScalableOffset*...

Definition:TargetLowering.h:2816

llvm::TargetLoweringBase::AddrMode::BaseOffs

int64_t BaseOffs

Definition:TargetLowering.h:2818

llvm::TargetLoweringBase::AddrMode::BaseGV

GlobalValue * BaseGV

Definition:TargetLowering.h:2817

llvm::TargetLoweringBase::AddrMode::HasBaseReg

bool HasBaseReg

Definition:TargetLowering.h:2819

llvm::TargetLoweringBase::AddrMode::Scale

int64_t Scale

Definition:TargetLowering.h:2820

llvm::TargetLoweringBase::AddrMode::ScalableOffset

int64_t ScalableOffset

Definition:TargetLowering.h:2821

llvm::cl::desc

Definition:CommandLine.h:409