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1//===-- SparcISelDAGToDAG.cpp - A dag to dag inst selector for Sparc ------===//

2//

3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.

4// See https://llvm.org/LICENSE.txt for license information.

5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception

6//

7//===----------------------------------------------------------------------===//

8//

9// This file defines an instruction selector for the SPARC target.

10//

11//===----------------------------------------------------------------------===//

13#include "SparcTargetMachine.h"

14#include "llvm/CodeGen/MachineRegisterInfo.h"

15#include "llvm/CodeGen/SelectionDAGISel.h"

16#include "llvm/Support/ErrorHandling.h"

17using namespacellvm;

19#define DEBUG_TYPE "sparc-isel"

20#define PASS_NAME "SPARC DAG->DAG Pattern Instruction Selection"

22//===----------------------------------------------------------------------===//

23// Instruction Selector Implementation

24//===----------------------------------------------------------------------===//

26//===--------------------------------------------------------------------===//

27/// SparcDAGToDAGISel - SPARC specific code to select SPARC machine

28/// instructions for SelectionDAG operations.

29///

30namespace{

31classSparcDAGToDAGISel :publicSelectionDAGISel {

32 /// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can

33 /// make the right decision when generating code for different targets.

34constSparcSubtarget *Subtarget =nullptr;

36public:

37 SparcDAGToDAGISel() =delete;

39explicit SparcDAGToDAGISel(SparcTargetMachine &tm) :SelectionDAGISel(tm) {}

41boolrunOnMachineFunction(MachineFunction &MF) override{

42 Subtarget = &MF.getSubtarget<SparcSubtarget>();

43returnSelectionDAGISel::runOnMachineFunction(MF);

44 }

46voidSelect(SDNode *N)override;

48// Complex Pattern Selectors.

49bool SelectADDRrr(SDValue N,SDValue &R1,SDValue &R2);

50bool SelectADDRri(SDValue N,SDValue &Base,SDValue &Offset);

52 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for

53 /// inline asm expressions.

54boolSelectInlineAsmMemoryOperand(constSDValue &Op,

55InlineAsm::ConstraintCode ConstraintID,

56 std::vector<SDValue> &OutOps)override;

58// Include the pieces autogenerated from the target description.

59#include "SparcGenDAGISel.inc"

61private:

62SDNode* getGlobalBaseReg();

63bool tryInlineAsm(SDNode *N);

64};

66classSparcDAGToDAGISelLegacy :publicSelectionDAGISelLegacy {

67public:

68staticcharID;

69explicit SparcDAGToDAGISelLegacy(SparcTargetMachine &tm)

70 :SelectionDAGISelLegacy(ID, std::make_unique<SparcDAGToDAGISel>(tm)) {}

71};

72}// end anonymous namespace

74char SparcDAGToDAGISelLegacy::ID = 0;

76INITIALIZE_PASS(SparcDAGToDAGISelLegacy,DEBUG_TYPE,PASS_NAME,false,false)

78SDNode* SparcDAGToDAGISel::getGlobalBaseReg() {

79Register GlobalBaseReg = Subtarget->getInstrInfo()->getGlobalBaseReg(MF);

80return CurDAG->getRegister(GlobalBaseReg,

81 TLI->getPointerTy(CurDAG->getDataLayout()))

82 .getNode();

83}

85bool SparcDAGToDAGISel::SelectADDRri(SDValue Addr,

86SDValue &Base,SDValue &Offset) {

87if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {

88Base = CurDAG->getTargetFrameIndex(

89 FIN->getIndex(), TLI->getPointerTy(CurDAG->getDataLayout()));

90Offset = CurDAG->getTargetConstant(0,SDLoc(Addr), MVT::i32);

91returntrue;

92 }

93if (Addr.getOpcode() ==ISD::TargetExternalSymbol ||

94Addr.getOpcode() ==ISD::TargetGlobalAddress ||

95Addr.getOpcode() ==ISD::TargetGlobalTLSAddress)

96returnfalse;// direct calls.

98if (Addr.getOpcode() ==ISD::ADD) {

99if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {

100if (isInt<13>(CN->getSExtValue())) {

101if (FrameIndexSDNode *FIN =

102 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {

103// Constant offset from frame ref.

104Base = CurDAG->getTargetFrameIndex(

105 FIN->getIndex(), TLI->getPointerTy(CurDAG->getDataLayout()));

106 }else {

107Base =Addr.getOperand(0);

108 }

109Offset = CurDAG->getSignedTargetConstant(CN->getSExtValue(),

110SDLoc(Addr), MVT::i32);

111returntrue;

112 }

113 }

114if (Addr.getOperand(0).getOpcode() ==SPISD::Lo) {

115Base =Addr.getOperand(1);

116Offset =Addr.getOperand(0).getOperand(0);

117returntrue;

118 }

119if (Addr.getOperand(1).getOpcode() ==SPISD::Lo) {

120Base =Addr.getOperand(0);

121Offset =Addr.getOperand(1).getOperand(0);

122returntrue;

123 }

124 }

125Base =Addr;

126Offset = CurDAG->getTargetConstant(0,SDLoc(Addr), MVT::i32);

127returntrue;

128}

129

130bool SparcDAGToDAGISel::SelectADDRrr(SDValue Addr,SDValue &R1,SDValue &R2) {

131if (Addr.getOpcode() ==ISD::FrameIndex)returnfalse;

132if (Addr.getOpcode() ==ISD::TargetExternalSymbol ||

133Addr.getOpcode() ==ISD::TargetGlobalAddress ||

134Addr.getOpcode() ==ISD::TargetGlobalTLSAddress)

135returnfalse;// direct calls.

136

137if (Addr.getOpcode() ==ISD::ADD) {

138if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))

139if (isInt<13>(CN->getSExtValue()))

140returnfalse;// Let the reg+imm pattern catch this!

141if (Addr.getOperand(0).getOpcode() ==SPISD::Lo ||

142Addr.getOperand(1).getOpcode() ==SPISD::Lo)

143returnfalse;// Let the reg+imm pattern catch this!

144 R1 =Addr.getOperand(0);

145R2 =Addr.getOperand(1);

146returntrue;

147 }

148

149 R1 =Addr;

150R2 = CurDAG->getRegister(SP::G0, TLI->getPointerTy(CurDAG->getDataLayout()));

151returntrue;

152}

153

154

155// Re-assemble i64 arguments split up in SelectionDAGBuilder's

156// visitInlineAsm / GetRegistersForValue functions.

157//

158// Note: This function was copied from, and is essentially identical

159// to ARMISelDAGToDAG::SelectInlineAsm. It is very unfortunate that

160// such hacking-up is necessary; a rethink of how inline asm operands

161// are handled may be in order to make doing this more sane.

162//

163// TODO: fix inline asm support so I can simply tell it that 'i64'

164// inputs to asm need to be allocated to the IntPair register type,

165// and have that work. Then, delete this function.

166bool SparcDAGToDAGISel::tryInlineAsm(SDNode *N){

167 std::vector<SDValue> AsmNodeOperands;

168InlineAsm::Flag Flag;

169bool Changed =false;

170unsigned NumOps =N->getNumOperands();

171

172// Normally, i64 data is bounded to two arbitrary GPRs for "%r"

173// constraint. However, some instructions (e.g. ldd/std) require

174// (even/even+1) GPRs.

175

176// So, here, we check for this case, and mutate the inlineasm to use

177// a single IntPair register instead, which guarantees such even/odd

178// placement.

179

180SDLoc dl(N);

181SDValue Glue =N->getGluedNode() ?N->getOperand(NumOps - 1) :SDValue();

182

183SmallVector<bool, 8> OpChanged;

184// Glue node will be appended late.

185for(unsigned i = 0, e =N->getGluedNode() ? NumOps - 1 : NumOps; i < e; ++i) {

186SDValue op =N->getOperand(i);

187 AsmNodeOperands.push_back(op);

188

189if (i <InlineAsm::Op_FirstOperand)

190continue;

191

192if (constauto *C = dyn_cast<ConstantSDNode>(N->getOperand(i)))

193Flag =InlineAsm::Flag(C->getZExtValue());

194else

195continue;

196

197// Immediate operands to inline asm in the SelectionDAG are modeled with

198// two operands. The first is a constant of value InlineAsm::Kind::Imm, and

199// the second is a constant with the value of the immediate. If we get here

200// and we have a Kind::Imm, skip the next operand, and continue.

201if (Flag.isImmKind()) {

202SDValue op =N->getOperand(++i);

203 AsmNodeOperands.push_back(op);

204continue;

205 }

206

207constunsigned NumRegs =Flag.getNumOperandRegisters();

208if (NumRegs)

209 OpChanged.push_back(false);

210

211unsigned DefIdx = 0;

212bool IsTiedToChangedOp =false;

213// If it's a use that is tied with a previous def, it has no

214// reg class constraint.

215if (Changed &&Flag.isUseOperandTiedToDef(DefIdx))

216 IsTiedToChangedOp = OpChanged[DefIdx];

217

218if (!Flag.isRegUseKind() && !Flag.isRegDefKind() &&

219 !Flag.isRegDefEarlyClobberKind())

220continue;

221

222unsigned RC;

223constbool HasRC =Flag.hasRegClassConstraint(RC);

224if ((!IsTiedToChangedOp && (!HasRC || RC != SP::IntRegsRegClassID))

225 || NumRegs != 2)

226continue;

227

228assert((i+2 < NumOps) &&"Invalid number of operands in inline asm");

229SDValue V0 =N->getOperand(i+1);

230SDValue V1 =N->getOperand(i+2);

231Register Reg0 = cast<RegisterSDNode>(V0)->getReg();

232Register Reg1 = cast<RegisterSDNode>(V1)->getReg();

233SDValue PairedReg;

234MachineRegisterInfo &MRI = MF->getRegInfo();

235

236if (Flag.isRegDefKind() ||Flag.isRegDefEarlyClobberKind()) {

237// Replace the two GPRs with 1 GPRPair and copy values from GPRPair to

238// the original GPRs.

239

240Register GPVR =MRI.createVirtualRegister(&SP::IntPairRegClass);

241 PairedReg = CurDAG->getRegister(GPVR, MVT::v2i32);

242SDValue Chain =SDValue(N,0);

243

244SDNode *GU =N->getGluedUser();

245SDValue RegCopy = CurDAG->getCopyFromReg(Chain, dl, GPVR, MVT::v2i32,

246 Chain.getValue(1));

247

248// Extract values from a GPRPair reg and copy to the original GPR reg.

249SDValue Sub0 = CurDAG->getTargetExtractSubreg(SP::sub_even, dl, MVT::i32,

250 RegCopy);

251SDValue Sub1 = CurDAG->getTargetExtractSubreg(SP::sub_odd, dl, MVT::i32,

252 RegCopy);

253SDValue T0 = CurDAG->getCopyToReg(Sub0, dl, Reg0, Sub0,

254 RegCopy.getValue(1));

255SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1));

256

257// Update the original glue user.

258 std::vector<SDValue> Ops(GU->op_begin(), GU->op_end()-1);

259 Ops.push_back(T1.getValue(1));

260 CurDAG->UpdateNodeOperands(GU, Ops);

261 }else {

262// For Kind == InlineAsm::Kind::RegUse, we first copy two GPRs into a

263// GPRPair and then pass the GPRPair to the inline asm.

264SDValue Chain = AsmNodeOperands[InlineAsm::Op_InputChain];

265

266// As REG_SEQ doesn't take RegisterSDNode, we copy them first.

267SDValue T0 = CurDAG->getCopyFromReg(Chain, dl, Reg0, MVT::i32,

268 Chain.getValue(1));

269SDValue T1 = CurDAG->getCopyFromReg(Chain, dl, Reg1, MVT::i32,

270 T0.getValue(1));

271SDValue Pair =SDValue(

272 CurDAG->getMachineNode(

273 TargetOpcode::REG_SEQUENCE, dl, MVT::v2i32,

274 {

275 CurDAG->getTargetConstant(SP::IntPairRegClassID, dl,

276 MVT::i32),

277 T0,

278 CurDAG->getTargetConstant(SP::sub_even, dl, MVT::i32),

279 T1,

280 CurDAG->getTargetConstant(SP::sub_odd, dl, MVT::i32),

281 }),

282 0);

283

284// Copy REG_SEQ into a GPRPair-typed VR and replace the original two

285// i32 VRs of inline asm with it.

286Register GPVR =MRI.createVirtualRegister(&SP::IntPairRegClass);

287 PairedReg = CurDAG->getRegister(GPVR, MVT::v2i32);

288 Chain = CurDAG->getCopyToReg(T1, dl, GPVR, Pair,T1.getValue(1));

289

290 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;

291 Glue = Chain.getValue(1);

292 }

293

294 Changed =true;

295

296if(PairedReg.getNode()) {

297 OpChanged[OpChanged.size() -1 ] =true;

298Flag =InlineAsm::Flag(Flag.getKind(), 1/* RegNum*/);

299if (IsTiedToChangedOp)

300Flag.setMatchingOp(DefIdx);

301else

302Flag.setRegClass(SP::IntPairRegClassID);

303// Replace the current flag.

304 AsmNodeOperands[AsmNodeOperands.size() -1] = CurDAG->getTargetConstant(

305 Flag, dl, MVT::i32);

306// Add the new register node and skip the original two GPRs.

307 AsmNodeOperands.push_back(PairedReg);

308// Skip the next two GPRs.

309 i += 2;

310 }

311 }

312

313if (Glue.getNode())

314 AsmNodeOperands.push_back(Glue);

315if (!Changed)

316returnfalse;

317

318 SelectInlineAsmMemoryOperands(AsmNodeOperands,SDLoc(N));

319

320SDValue New = CurDAG->getNode(N->getOpcode(),SDLoc(N),

321 CurDAG->getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);

322New->setNodeId(-1);

323 ReplaceNode(N,New.getNode());

324returntrue;

325}

326

327void SparcDAGToDAGISel::Select(SDNode *N) {

328SDLoc dl(N);

329if (N->isMachineOpcode()) {

330N->setNodeId(-1);

331return;// Already selected.

332 }

333

334switch (N->getOpcode()) {

335default:break;

336caseISD::INLINEASM:

337caseISD::INLINEASM_BR: {

338if (tryInlineAsm(N))

339return;

340break;

341 }

342caseSPISD::GLOBAL_BASE_REG:

343 ReplaceNode(N, getGlobalBaseReg());

344return;

345

346caseISD::SDIV:

347caseISD::UDIV: {

348// sdivx / udivx handle 64-bit divides.

349if (N->getValueType(0) == MVT::i64)

350break;

351// FIXME: should use a custom expander to expose the SRA to the dag.

352SDValue DivLHS =N->getOperand(0);

353SDValue DivRHS =N->getOperand(1);

354

355// Set the Y register to the high-part.

356SDValue TopPart;

357if (N->getOpcode() ==ISD::SDIV) {

358 TopPart =SDValue(CurDAG->getMachineNode(SP::SRAri, dl, MVT::i32, DivLHS,

359 CurDAG->getTargetConstant(31, dl, MVT::i32)),

360 0);

361 }else {

362 TopPart = CurDAG->getRegister(SP::G0, MVT::i32);

363 }

364 TopPart = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, SP::Y, TopPart,

365SDValue())

366 .getValue(1);

367

368// FIXME: Handle div by immediate.

369unsigned Opcode =N->getOpcode() ==ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;

370 CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart);

371return;

372 }

373 }

374

375 SelectCode(N);

376}

377

378

379/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for

380/// inline asm expressions.

381bool SparcDAGToDAGISel::SelectInlineAsmMemoryOperand(

382constSDValue &Op,InlineAsm::ConstraintCode ConstraintID,

383 std::vector<SDValue> &OutOps) {

384SDValue Op0, Op1;

385switch (ConstraintID) {

386default:returntrue;

387case InlineAsm::ConstraintCode::o:

388case InlineAsm::ConstraintCode::m:// memory

389if (!SelectADDRrr(Op, Op0, Op1))

390 SelectADDRri(Op, Op0, Op1);

391break;

392 }

393

394 OutOps.push_back(Op0);

395 OutOps.push_back(Op1);

396returnfalse;

397}

398

399/// createSparcISelDag - This pass converts a legalized DAG into a

400/// SPARC-specific DAG, ready for instruction scheduling.

401///

402FunctionPass *llvm::createSparcISelDag(SparcTargetMachine &TM) {

403returnnew SparcDAGToDAGISelLegacy(TM);

404}

MRI

unsigned const MachineRegisterInfo * MRI

Definition:AArch64AdvSIMDScalarPass.cpp:105

Select

AMDGPU Register Bank Select

Definition:AMDGPURegBankSelect.cpp:71

Addr

uint64_t Addr

Definition:ELFObjHandler.cpp:79

#define op(i)

MachineRegisterInfo.h

#define R2(n)

#define T1

Definition:Mips16ISelLowering.cpp:340

INITIALIZE_PASS

#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)

Definition:PassSupport.h:38

assert

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

SelectionDAGISel.h

PASS_NAME

#define PASS_NAME

Definition:SparcISelDAGToDAG.cpp:20

DEBUG_TYPE

#define DEBUG_TYPE

Definition:SparcISelDAGToDAG.cpp:19

SparcTargetMachine.h

llvm::ConstantSDNode

Definition:SelectionDAGNodes.h:1684

llvm::DWARFExpression::Operation

This class represents an Operation in the Expression.

Definition:DWARFExpression.h:32

llvm::FrameIndexSDNode

Definition:SelectionDAGNodes.h:1904

llvm::FunctionPass

FunctionPass class - This class is used to implement most global optimizations.

Definition:Pass.h:310

llvm::InlineAsm::Flag

Definition:InlineAsm.h:303

llvm::InlineAsm::Op_InputChain

@ Op_InputChain

Definition:InlineAsm.h:202

llvm::InlineAsm::Op_FirstOperand

@ Op_FirstOperand

Definition:InlineAsm.h:206

llvm::InlineAsm::ConstraintCode

ConstraintCode

Definition:InlineAsm.h:239

llvm::MachineFunction

Definition:MachineFunction.h:267

llvm::MachineFunction::getSubtarget

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

Definition:MachineFunction.h:733

llvm::MachineRegisterInfo

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

Definition:MachineRegisterInfo.h:51

llvm::Register

Wrapper class representing virtual and physical registers.

Definition:Register.h:19

llvm::SDLoc

Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...

Definition:SelectionDAGNodes.h:1182

llvm::SDNode

Represents one node in the SelectionDAG.

Definition:SelectionDAGNodes.h:496

llvm::SDNode::op_end

op_iterator op_end() const

Definition:SelectionDAGNodes.h:1000

llvm::SDNode::op_begin

op_iterator op_begin() const

Definition:SelectionDAGNodes.h:999

llvm::SDValue

Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.

Definition:SelectionDAGNodes.h:145

llvm::SDValue::getNode

SDNode * getNode() const

get the SDNode which holds the desired result

Definition:SelectionDAGNodes.h:159

llvm::SDValue::getValue

SDValue getValue(unsigned R) const

Definition:SelectionDAGNodes.h:179

llvm::SelectionDAGISelLegacy

Definition:SelectionDAGISel.h:539

llvm::SelectionDAGISel

SelectionDAGISel - This is the common base class used for SelectionDAG-based pattern-matching instruc...

Definition:SelectionDAGISel.h:45

llvm::SelectionDAGISel::SelectInlineAsmMemoryOperand

virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, InlineAsm::ConstraintCode ConstraintID, std::vector< SDValue > &OutOps)

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode,...

Definition:SelectionDAGISel.h:118

llvm::SelectionDAGISel::runOnMachineFunction

virtual bool runOnMachineFunction(MachineFunction &mf)

Definition:SelectionDAGISel.cpp:574

llvm::SmallVectorBase::size

size_t size() const

Definition:SmallVector.h:78

llvm::SmallVectorTemplateBase::push_back

void push_back(const T &Elt)

Definition:SmallVector.h:413

llvm::SmallVector

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

Definition:SmallVector.h:1196

llvm::SparcSubtarget

Definition:SparcSubtarget.h:33

llvm::SparcTargetMachine

Definition:SparcTargetMachine.h:24

unsigned

ErrorHandling.h

llvm::CallingConv::C

@ C

The default llvm calling convention, compatible with C.

Definition:CallingConv.h:34

llvm::CallingConv::ID

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

Definition:CallingConv.h:24

llvm::ISD::UDIV

@ UDIV

Definition:ISDOpcodes.h:250

llvm::ISD::SDIV

@ SDIV

Definition:ISDOpcodes.h:249

llvm::ISD::ADD

@ ADD

Simple integer binary arithmetic operators.

Definition:ISDOpcodes.h:246

llvm::ISD::FrameIndex

@ FrameIndex

Definition:ISDOpcodes.h:80

llvm::ISD::TargetExternalSymbol

@ TargetExternalSymbol

Definition:ISDOpcodes.h:175

llvm::ISD::TargetGlobalAddress

@ TargetGlobalAddress

TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or anything else with this node...

Definition:ISDOpcodes.h:170

llvm::ISD::INLINEASM_BR

@ INLINEASM_BR

INLINEASM_BR - Branching version of inline asm. Used by asm-goto.

Definition:ISDOpcodes.h:1168

llvm::ISD::INLINEASM

@ INLINEASM

INLINEASM - Represents an inline asm block.

Definition:ISDOpcodes.h:1165

llvm::ISD::TargetGlobalTLSAddress

@ TargetGlobalTLSAddress

Definition:ISDOpcodes.h:171

llvm::MCID::Flag

Flag

These should be considered private to the implementation of the MCInstrDesc class.

Definition:MCInstrDesc.h:148

llvm::PPCISD::GlobalBaseReg

@ GlobalBaseReg

The result of the mflr at function entry, used for PIC code.

Definition:PPCISelLowering.h:151

llvm::SPISD::Lo

@ Lo

Definition:SparcISelLowering.h:42

llvm::SPISD::GLOBAL_BASE_REG

@ GLOBAL_BASE_REG

Definition:SparcISelLowering.h:51

llvm::ms_demangle::IntrinsicFunctionKind::New

@ New

llvm::sampleprof::Base

@ Base

Definition:Discriminator.h:58

llvm

This is an optimization pass for GlobalISel generic memory operations.

Definition:AddressRanges.h:18

llvm::Offset

@ Offset

Definition:DWP.cpp:480

llvm::createSparcISelDag

FunctionPass * createSparcISelDag(SparcTargetMachine &TM)

createSparcISelDag - This pass converts a legalized DAG into a SPARC-specific DAG,...

Definition:SparcISelDAGToDAG.cpp:402

#define N