1//===-- SPIRVPostLegalizer.cpp - ammend info after legalization -*- C++ -*-===// 3// which may appear after the legalizer pass 5// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 6// See https://llvm.org/LICENSE.txt for license information. 7// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 9//===----------------------------------------------------------------------===// 11// The pass partially apply pre-legalization logic to new instructions inserted 12// as a result of legalization: 13// - assigns SPIR-V types to registers for new instructions. 15//===----------------------------------------------------------------------===// 26#include "llvm/IR/IntrinsicsSPIRV.h" 30#define DEBUG_TYPE "spirv-postlegalizer" 45// Defined in SPIRVLegalizerInfo.cpp. 49// Defined in SPIRVPreLegalizer.cpp. 60case TargetOpcode::G_SMAX:
61case TargetOpcode::G_UMAX:
62case TargetOpcode::G_SMIN:
63case TargetOpcode::G_UMIN:
64case TargetOpcode::G_FMINNUM:
65case TargetOpcode::G_FMINIMUM:
66case TargetOpcode::G_FMAXNUM:
67case TargetOpcode::G_FMAXIMUM:
80constunsigned Opcode =
I.getOpcode();
81if (Opcode == TargetOpcode::G_UNMERGE_VALUES) {
82unsigned ArgI =
I.getNumOperands() - 1;
83Register SrcReg =
I.getOperand(ArgI).isReg()
84 ?
I.getOperand(ArgI).getReg()
88if (!DefType || DefType->
getOpcode() != SPIRV::OpTypeVector)
90"cannot select G_UNMERGE_VALUES with a non-vector argument");
93for (
unsigned i = 0; i <
I.getNumDefs(); ++i) {
94Register ResVReg =
I.getOperand(i).getReg();
97// There was no "assign type" actions, let's fix this now 103I.getNumOperands() > 1 &&
I.getOperand(1).isReg()) {
104// Legalizer may have added a new instructions and introduced new 105// registers, we must decorate them as if they were introduced in a 107Register ResVReg =
I.getOperand(0).getReg();
108// Check if the register defined by the instruction is newly generated 109// or already processed 110if (
MRI.getRegClassOrNull(ResVReg))
113// Check if we have type defined for operands of the new instruction 119// If this is a simple operation that is to be reduced by TableGen 120// definition we must apply some of pre-legalizer rules here 130// Do a preorder traversal of the CFG starting from the BB |Start|. 131// point. Calls |op| on each basic block encountered during the traversal. 134 std::stack<MachineBasicBlock *> ToVisit;
137 ToVisit.push(&Start);
138 Seen.
insert(ToVisit.top());
139while (ToVisit.size() != 0) {
154// Do a preorder traversal of the CFG starting from the given function's entry 155// point. Calls |op| on each basic block encountered during the traversal. 161// Initialize the type registry. 164 GR->setCurrentFunc(MF);
175char SPIRVPostLegalizer::
ID = 0;
178returnnew SPIRVPostLegalizer();
unsigned const MachineRegisterInfo * MRI
This file contains the simple types necessary to represent the attributes associated with functions a...
This file contains the declarations for the subclasses of Constant, which represent the different fla...
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
This file builds on the ADT/GraphTraits.h file to build a generic graph post order iterator.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void visit(MachineFunction &MF, MachineBasicBlock &Start, std::function< void(MachineBasicBlock *)> op)
bool isTypeFoldingSupported(unsigned Opcode)
static bool mayBeInserted(unsigned Opcode)
static void processNewInstrs(MachineFunction &MF, SPIRVGlobalRegistry *GR, MachineIRBuilder MIB)
FunctionPass class - This class is used to implement most global optimizations.
iterator_range< succ_iterator > successors()
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Helper class to build MachineInstr.
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
const MachineOperand & getOperand(unsigned i) const
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Wrapper class representing virtual and physical registers.
constexpr bool isValid() const
SPIRVType * getSPIRVTypeForVReg(Register VReg, const MachineFunction *MF=nullptr) const
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
bool contains(ConstPtrType Ptr) const
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
The instances of the Type class are immutable: once they are created, they are never changed.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
This is an optimization pass for GlobalISel generic memory operations.
Register insertAssignInstr(Register Reg, Type *Ty, SPIRVType *SpirvTy, SPIRVGlobalRegistry *GR, MachineIRBuilder &MIB, MachineRegisterInfo &MRI)
Helper external function for inserting ASSIGN_TYPE instuction between Reg and its definition,...
FunctionPass * createSPIRVPostLegalizerPass()
void setRegClassType(Register Reg, SPIRVType *SpvType, SPIRVGlobalRegistry *GR, MachineRegisterInfo *MRI, const MachineFunction &MF, bool Force)
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
void initializeSPIRVPostLegalizerPass(PassRegistry &)
void processInstr(MachineInstr &MI, MachineIRBuilder &MIB, MachineRegisterInfo &MRI, SPIRVGlobalRegistry *GR)
