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1//===-- SIOptimizeExecMaskingPreRA.cpp ------------------------------------===//

2//

3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.

4// See https://llvm.org/LICENSE.txt for license information.

5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception

6//

7//===----------------------------------------------------------------------===//

8//

9/// \file

10/// This pass performs exec mask handling peephole optimizations which needs

11/// to be done before register allocation to reduce register pressure.

12///

13//===----------------------------------------------------------------------===//

15#include "AMDGPU.h"

16#include "GCNSubtarget.h"

17#include "MCTargetDesc/AMDGPUMCTargetDesc.h"

18#include "llvm/CodeGen/LiveIntervals.h"

19#include "llvm/CodeGen/MachineFunctionPass.h"

20#include "llvm/InitializePasses.h"

22using namespacellvm;

24#define DEBUG_TYPE "si-optimize-exec-masking-pre-ra"

26namespace{

28classSIOptimizeExecMaskingPreRA :publicMachineFunctionPass {

29private:

30constSIRegisterInfo *TRI;

31constSIInstrInfo *TII;

32MachineRegisterInfo *MRI;

33LiveIntervals *LIS;

35unsigned AndOpc;

36unsigned Andn2Opc;

37unsigned OrSaveExecOpc;

38unsigned XorTermrOpc;

39MCRegister CondReg;

40MCRegister ExecReg;

42bool optimizeVcndVcmpPair(MachineBasicBlock &MBB);

43bool optimizeElseBranch(MachineBasicBlock &MBB);

45public:

46staticcharID;

48 SIOptimizeExecMaskingPreRA() :MachineFunctionPass(ID) {

49initializeSIOptimizeExecMaskingPreRAPass(*PassRegistry::getPassRegistry());

50 }

52boolrunOnMachineFunction(MachineFunction &MF)override;

54StringRef getPassName() const override{

55return"SI optimize exec mask operations pre-RA";

56 }

58voidgetAnalysisUsage(AnalysisUsage &AU) const override{

59 AU.addRequired<LiveIntervalsWrapperPass>();

60 AU.setPreservesAll();

61MachineFunctionPass::getAnalysisUsage(AU);

62 }

63};

65}// End anonymous namespace.

67INITIALIZE_PASS_BEGIN(SIOptimizeExecMaskingPreRA,DEBUG_TYPE,

68"SI optimize exec mask operations pre-RA",false,false)

69INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)

70INITIALIZE_PASS_END(SIOptimizeExecMaskingPreRA,DEBUG_TYPE,

71 "SI optimize exec maskoperations pre-RA",false,false)

73char SIOptimizeExecMaskingPreRA::ID = 0;

75char &llvm::SIOptimizeExecMaskingPreRAID = SIOptimizeExecMaskingPreRA::ID;

77FunctionPass *llvm::createSIOptimizeExecMaskingPreRAPass() {

78returnnew SIOptimizeExecMaskingPreRA();

79}

81// See if there is a def between \p AndIdx and \p SelIdx that needs to live

82// beyond \p AndIdx.

83staticboolisDefBetween(constLiveRange &LR,SlotIndex AndIdx,

84SlotIndex SelIdx) {

85LiveQueryResult AndLRQ = LR.Query(AndIdx);

86return (!AndLRQ.isKill() && AndLRQ.valueIn() != LR.Query(SelIdx).valueOut());

87}

89// FIXME: Why do we bother trying to handle physical registers here?

90staticboolisDefBetween(constSIRegisterInfo &TRI,

91LiveIntervals *LIS,Register Reg,

92constMachineInstr &Sel,constMachineInstr &And) {

93SlotIndex AndIdx = LIS->getInstructionIndex(And).getRegSlot();

94SlotIndex SelIdx = LIS->getInstructionIndex(Sel).getRegSlot();

96if (Reg.isVirtual())

97returnisDefBetween(LIS->getInterval(Reg), AndIdx, SelIdx);

99for (MCRegUnit Unit :TRI.regunits(Reg.asMCReg())) {

100if (isDefBetween(LIS->getRegUnit(Unit), AndIdx, SelIdx))

101returntrue;

102 }

103

104returnfalse;

105}

106

107// Optimize sequence

108// %sel = V_CNDMASK_B32_e64 0, 1, %cc

109// %cmp = V_CMP_NE_U32 1, %sel

110// $vcc = S_AND_B64 $exec, %cmp

111// S_CBRANCH_VCC[N]Z

112// =>

113// $vcc = S_ANDN2_B64 $exec, %cc

114// S_CBRANCH_VCC[N]Z

115//

116// It is the negation pattern inserted by DAGCombiner::visitBRCOND() in the

117// rebuildSetCC(). We start with S_CBRANCH to avoid exhaustive search, but

118// only 3 first instructions are really needed. S_AND_B64 with exec is a

119// required part of the pattern since V_CNDMASK_B32 writes zeroes for inactive

120// lanes.

121//

122// Returns true on success.

123bool SIOptimizeExecMaskingPreRA::optimizeVcndVcmpPair(MachineBasicBlock &MBB) {

124autoI =llvm::find_if(MBB.terminators(), [](constMachineInstr &MI) {

125 unsigned Opc = MI.getOpcode();

126 return Opc == AMDGPU::S_CBRANCH_VCCZ ||

127 Opc == AMDGPU::S_CBRANCH_VCCNZ; });

128if (I ==MBB.terminators().end())

129returnfalse;

130

131auto *And =

132TRI->findReachingDef(CondReg, AMDGPU::NoSubRegister, *I, *MRI, LIS);

133if (!And ||And->getOpcode() != AndOpc ||

134 !And->getOperand(1).isReg() || !And->getOperand(2).isReg())

135returnfalse;

136

137MachineOperand *AndCC = &And->getOperand(1);

138Register CmpReg = AndCC->getReg();

139unsigned CmpSubReg = AndCC->getSubReg();

140if (CmpReg ==Register(ExecReg)) {

141 AndCC = &And->getOperand(2);

142 CmpReg = AndCC->getReg();

143 CmpSubReg = AndCC->getSubReg();

144 }elseif (And->getOperand(2).getReg() !=Register(ExecReg)) {

145returnfalse;

146 }

147

148auto *Cmp =TRI->findReachingDef(CmpReg, CmpSubReg, *And, *MRI, LIS);

149if (!Cmp || !(Cmp->getOpcode() == AMDGPU::V_CMP_NE_U32_e32 ||

150Cmp->getOpcode() == AMDGPU::V_CMP_NE_U32_e64) ||

151Cmp->getParent() !=And->getParent())

152returnfalse;

153

154MachineOperand *Op1 =TII->getNamedOperand(*Cmp, AMDGPU::OpName::src0);

155MachineOperand *Op2 =TII->getNamedOperand(*Cmp, AMDGPU::OpName::src1);

156if (Op1->isImm() && Op2->isReg())

157std::swap(Op1, Op2);

158if (!Op1->isReg() || !Op2->isImm() || Op2->getImm() != 1)

159returnfalse;

160

161Register SelReg = Op1->getReg();

162if (SelReg.isPhysical())

163returnfalse;

164

165auto *Sel =TRI->findReachingDef(SelReg, Op1->getSubReg(), *Cmp, *MRI, LIS);

166if (!Sel || Sel->getOpcode() != AMDGPU::V_CNDMASK_B32_e64)

167returnfalse;

168

169if (TII->hasModifiersSet(*Sel, AMDGPU::OpName::src0_modifiers) ||

170TII->hasModifiersSet(*Sel, AMDGPU::OpName::src1_modifiers))

171returnfalse;

172

173 Op1 =TII->getNamedOperand(*Sel, AMDGPU::OpName::src0);

174 Op2 =TII->getNamedOperand(*Sel, AMDGPU::OpName::src1);

175MachineOperand *CC =TII->getNamedOperand(*Sel, AMDGPU::OpName::src2);

176if (!Op1->isImm() || !Op2->isImm() || !CC->isReg() ||

177 Op1->getImm() != 0 || Op2->getImm() != 1)

178returnfalse;

179

180Register CCReg =CC->getReg();

181

182// If there was a def between the select and the and, we would need to move it

183// to fold this.

184if (isDefBetween(*TRI, LIS, CCReg, *Sel, *And))

185returnfalse;

186

187// Cannot safely mirror live intervals with PHI nodes, so check for these

188// before optimization.

189SlotIndex SelIdx = LIS->getInstructionIndex(*Sel);

190LiveInterval *SelLI = &LIS->getInterval(SelReg);

191if (llvm::any_of(SelLI->vnis(),

192 [](constVNInfo *VNI) {

193 return VNI->isPHIDef();

194 }))

195returnfalse;

196

197// TODO: Guard against implicit def operands?

198LLVM_DEBUG(dbgs() <<"Folding sequence:\n\t" << *Sel <<'\t' << *Cmp <<'\t'

199 << *And);

200

201MachineInstr *Andn2 =

202BuildMI(MBB, *And,And->getDebugLoc(),TII->get(Andn2Opc),

203And->getOperand(0).getReg())

204 .addReg(ExecReg)

205 .addReg(CCReg,getUndefRegState(CC->isUndef()),CC->getSubReg());

206MachineOperand &AndSCC =And->getOperand(3);

207assert(AndSCC.getReg() == AMDGPU::SCC);

208MachineOperand &Andn2SCC = Andn2->getOperand(3);

209assert(Andn2SCC.getReg() == AMDGPU::SCC);

210 Andn2SCC.setIsDead(AndSCC.isDead());

211

212SlotIndex AndIdx = LIS->ReplaceMachineInstrInMaps(*And, *Andn2);

213And->eraseFromParent();

214

215LLVM_DEBUG(dbgs() <<"=>\n\t" << *Andn2 <<'\n');

216

217// Update live intervals for CCReg before potentially removing CmpReg/SelReg,

218// and their associated liveness information.

219SlotIndex CmpIdx = LIS->getInstructionIndex(*Cmp);

220if (CCReg.isVirtual()) {

221LiveInterval &CCLI = LIS->getInterval(CCReg);

222auto CCQ = CCLI.Query(SelIdx.getRegSlot());

223if (CCQ.valueIn()) {

224 LIS->removeInterval(CCReg);

225 LIS->createAndComputeVirtRegInterval(CCReg);

226 }

227 }else

228 LIS->removeAllRegUnitsForPhysReg(CCReg);

229

230// Try to remove compare. Cmp value should not used in between of cmp

231// and s_and_b64 if VCC or just unused if any other register.

232LiveInterval *CmpLI = CmpReg.isVirtual() ? &LIS->getInterval(CmpReg) :nullptr;

233if ((CmpLI && CmpLI->Query(AndIdx.getRegSlot()).isKill()) ||

234 (CmpReg ==Register(CondReg) &&

235 std::none_of(std::next(Cmp->getIterator()), Andn2->getIterator(),

236 [&](constMachineInstr &MI) {

237 return MI.readsRegister(CondReg, TRI);

238 }))) {

239LLVM_DEBUG(dbgs() <<"Erasing: " << *Cmp <<'\n');

240if (CmpLI)

241 LIS->removeVRegDefAt(*CmpLI, CmpIdx.getRegSlot());

242 LIS->RemoveMachineInstrFromMaps(*Cmp);

243Cmp->eraseFromParent();

244

245// Try to remove v_cndmask_b32.

246// Kill status must be checked before shrinking the live range.

247bool IsKill = SelLI->Query(CmpIdx.getRegSlot()).isKill();

248 LIS->shrinkToUses(SelLI);

249boolIsDead = SelLI->Query(SelIdx.getRegSlot()).isDeadDef();

250if (MRI->use_nodbg_empty(SelReg) && (IsKill ||IsDead)) {

251LLVM_DEBUG(dbgs() <<"Erasing: " << *Sel <<'\n');

252

253 LIS->removeVRegDefAt(*SelLI, SelIdx.getRegSlot());

254 LIS->RemoveMachineInstrFromMaps(*Sel);

255bool ShrinkSel = Sel->getOperand(0).readsReg();

256 Sel->eraseFromParent();

257if (ShrinkSel) {

258// The result of the V_CNDMASK was a subreg def which counted as a read

259// from the other parts of the reg. Shrink their live ranges.

260 LIS->shrinkToUses(SelLI);

261 }

262 }

263 }

264

265returntrue;

266}

267

268// Optimize sequence

269// %dst = S_OR_SAVEEXEC %src

270// ... instructions not modifying exec ...

271// %tmp = S_AND $exec, %dst

272// $exec = S_XOR_term $exec, %tmp

273// =>

274// %dst = S_OR_SAVEEXEC %src

275// ... instructions not modifying exec ...

276// $exec = S_XOR_term $exec, %dst

277//

278// Clean up potentially unnecessary code added for safety during

279// control flow lowering.

280//

281// Return whether any changes were made to MBB.

282bool SIOptimizeExecMaskingPreRA::optimizeElseBranch(MachineBasicBlock &MBB) {

283if (MBB.empty())

284returnfalse;

285

286// Check this is an else block.

287autoFirst =MBB.begin();

288MachineInstr &SaveExecMI = *First;

289if (SaveExecMI.getOpcode() != OrSaveExecOpc)

290returnfalse;

291

292autoI =llvm::find_if(MBB.terminators(), [this](constMachineInstr &MI) {

293 return MI.getOpcode() == XorTermrOpc;

294 });

295if (I ==MBB.terminators().end())

296returnfalse;

297

298MachineInstr &XorTermMI = *I;

299if (XorTermMI.getOperand(1).getReg() !=Register(ExecReg))

300returnfalse;

301

302Register SavedExecReg = SaveExecMI.getOperand(0).getReg();

303Register DstReg = XorTermMI.getOperand(2).getReg();

304

305// Find potentially unnecessary S_AND

306MachineInstr *AndExecMI =nullptr;

307I--;

308while (I !=First && !AndExecMI) {

309if (I->getOpcode() == AndOpc &&I->getOperand(0).getReg() == DstReg &&

310I->getOperand(1).getReg() ==Register(ExecReg))

311 AndExecMI = &*I;

312I--;

313 }

314if (!AndExecMI)

315returnfalse;

316

317// Check for exec modifying instructions.

318// Note: exec defs do not create live ranges beyond the

319// instruction so isDefBetween cannot be used.

320// Instead just check that the def segments are adjacent.

321SlotIndex StartIdx = LIS->getInstructionIndex(SaveExecMI);

322SlotIndex EndIdx = LIS->getInstructionIndex(*AndExecMI);

323for (MCRegUnit Unit :TRI->regunits(ExecReg)) {

324LiveRange &RegUnit = LIS->getRegUnit(Unit);

325if (RegUnit.find(StartIdx) != std::prev(RegUnit.find(EndIdx)))

326returnfalse;

327 }

328

329// Remove unnecessary S_AND

330 LIS->removeInterval(SavedExecReg);

331 LIS->removeInterval(DstReg);

332

333 SaveExecMI.getOperand(0).setReg(DstReg);

334

335 LIS->RemoveMachineInstrFromMaps(*AndExecMI);

336 AndExecMI->eraseFromParent();

337

338 LIS->createAndComputeVirtRegInterval(DstReg);

339

340returntrue;

341}

342

343bool SIOptimizeExecMaskingPreRA::runOnMachineFunction(MachineFunction &MF) {

344if (skipFunction(MF.getFunction()))

345returnfalse;

346

347constGCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();

348TRI =ST.getRegisterInfo();

349TII =ST.getInstrInfo();

350MRI = &MF.getRegInfo();

351 LIS = &getAnalysis<LiveIntervalsWrapperPass>().getLIS();

352

353constboolWave32 =ST.isWave32();

354 AndOpc =Wave32 ? AMDGPU::S_AND_B32 : AMDGPU::S_AND_B64;

355 Andn2Opc =Wave32 ? AMDGPU::S_ANDN2_B32 : AMDGPU::S_ANDN2_B64;

356 OrSaveExecOpc =

357Wave32 ? AMDGPU::S_OR_SAVEEXEC_B32 : AMDGPU::S_OR_SAVEEXEC_B64;

358 XorTermrOpc =Wave32 ? AMDGPU::S_XOR_B32_term : AMDGPU::S_XOR_B64_term;

359 CondReg =MCRegister::from(Wave32 ? AMDGPU::VCC_LO : AMDGPU::VCC);

360 ExecReg =MCRegister::from(Wave32 ? AMDGPU::EXEC_LO : AMDGPU::EXEC);

361

362DenseSet<Register> RecalcRegs({AMDGPU::EXEC_LO, AMDGPU::EXEC_HI});

363bool Changed =false;

364

365for (MachineBasicBlock &MBB : MF) {

366

367if (optimizeElseBranch(MBB)) {

368 RecalcRegs.insert(AMDGPU::SCC);

369 Changed =true;

370 }

371

372if (optimizeVcndVcmpPair(MBB)) {

373 RecalcRegs.insert(AMDGPU::VCC_LO);

374 RecalcRegs.insert(AMDGPU::VCC_HI);

375 RecalcRegs.insert(AMDGPU::SCC);

376 Changed =true;

377 }

378

379// Try to remove unneeded instructions before s_endpgm.

380if (MBB.succ_empty()) {

381if (MBB.empty())

382continue;

383

384// Skip this if the endpgm has any implicit uses, otherwise we would need

385// to be careful to update / remove them.

386// S_ENDPGM always has a single imm operand that is not used other than to

387// end up in the encoding

388MachineInstr &Term =MBB.back();

389if (Term.getOpcode() != AMDGPU::S_ENDPGM ||Term.getNumOperands() != 1)

390continue;

391

392SmallVector<MachineBasicBlock*, 4>Blocks({&MBB});

393

394while (!Blocks.empty()) {

395auto *CurBB =Blocks.pop_back_val();

396autoI = CurBB->rbegin(), E = CurBB->rend();

397if (I != E) {

398if (I->isUnconditionalBranch() ||I->getOpcode() == AMDGPU::S_ENDPGM)

399 ++I;

400elseif (I->isBranch())

401continue;

402 }

403

404while (I != E) {

405if (I->isDebugInstr()) {

406I = std::next(I);

407continue;

408 }

409

410if (I->mayStore() ||I->isBarrier() ||I->isCall() ||

411I->hasUnmodeledSideEffects() ||I->hasOrderedMemoryRef())

412break;

413

414LLVM_DEBUG(dbgs()

415 <<"Removing no effect instruction: " << *I <<'\n');

416

417for (auto &Op :I->operands()) {

418if (Op.isReg())

419 RecalcRegs.insert(Op.getReg());

420 }

421

422auto Next = std::next(I);

423 LIS->RemoveMachineInstrFromMaps(*I);

424I->eraseFromParent();

425I = Next;

426

427 Changed =true;

428 }

429

430if (I != E)

431continue;

432

433// Try to ascend predecessors.

434for (auto *Pred : CurBB->predecessors()) {

435if (Pred->succ_size() == 1)

436Blocks.push_back(Pred);

437 }

438 }

439continue;

440 }

441

442// If the only user of a logical operation is move to exec, fold it now

443// to prevent forming of saveexec. I.e.:

444//

445// %0:sreg_64 = COPY $exec

446// %1:sreg_64 = S_AND_B64 %0:sreg_64, %2:sreg_64

447// =>

448// %1 = S_AND_B64 $exec, %2:sreg_64

449unsigned ScanThreshold = 10;

450for (autoI =MBB.rbegin(), E =MBB.rend();I != E

451 && ScanThreshold--; ++I) {

452// Continue scanning if this is not a full exec copy

453if (!(I->isFullCopy() &&I->getOperand(1).getReg() ==Register(ExecReg)))

454continue;

455

456Register SavedExec =I->getOperand(0).getReg();

457if (SavedExec.isVirtual() &&MRI->hasOneNonDBGUse(SavedExec)) {

458MachineInstr *SingleExecUser = &*MRI->use_instr_nodbg_begin(SavedExec);

459intIdx = SingleExecUser->findRegisterUseOperandIdx(SavedExec,

460/*TRI=*/nullptr);

461assert(Idx != -1);

462if (SingleExecUser->getParent() ==I->getParent() &&

463 !SingleExecUser->getOperand(Idx).isImplicit() &&

464TII->isOperandLegal(*SingleExecUser,Idx, &I->getOperand(1))) {

465LLVM_DEBUG(dbgs() <<"Redundant EXEC COPY: " << *I <<'\n');

466 LIS->RemoveMachineInstrFromMaps(*I);

467I->eraseFromParent();

468MRI->replaceRegWith(SavedExec, ExecReg);

469 LIS->removeInterval(SavedExec);

470 Changed =true;

471 }

472 }

473break;

474 }

475 }

476

477if (Changed) {

478for (auto Reg : RecalcRegs) {

479if (Reg.isVirtual()) {

480 LIS->removeInterval(Reg);

481if (!MRI->reg_empty(Reg))

482 LIS->createAndComputeVirtRegInterval(Reg);

483 }else {

484 LIS->removeAllRegUnitsForPhysReg(Reg);

485 }

486 }

487 }

488

489return Changed;

490}

MRI

unsigned const MachineRegisterInfo * MRI

Definition:AArch64AdvSIMDScalarPass.cpp:105

AMDGPUMCTargetDesc.h

Provides AMDGPU specific target descriptions.

AMDGPU.h

MBB

MachineBasicBlock & MBB

Definition:ARMSLSHardening.cpp:71

Idx

Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx

Definition:DeadArgumentElimination.cpp:353

LLVM_DEBUG

#define LLVM_DEBUG(...)

Definition:Debug.h:106

Blocks

DenseMap< Block *, BlockRelaxAux > Blocks

Definition:ELF_riscv.cpp:507

GCNSubtarget.h

AMD GCN specific subclass of TargetSubtarget.

TII

const HexagonInstrInfo * TII

Definition:HexagonCopyToCombine.cpp:125

IRTranslator LLVM IR MI

Definition:IRTranslator.cpp:112

InitializePasses.h

LiveIntervals.h

#define I(x, y, z)

Definition:MD5.cpp:58

MachineFunctionPass.h

TRI

unsigned const TargetRegisterInfo * TRI

Definition:MachineSink.cpp:2029

INITIALIZE_PASS_DEPENDENCY

#define INITIALIZE_PASS_DEPENDENCY(depName)

Definition:PassSupport.h:55

INITIALIZE_PASS_END

#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)

Definition:PassSupport.h:57

INITIALIZE_PASS_BEGIN

#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)

Definition:PassSupport.h:52

auto CC

Definition:RISCVRedundantCopyElimination.cpp:79

assert

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

IsDead

bool IsDead

Definition:SILowerControlFlow.cpp:176

SI optimize exec mask operations pre RA

Definition:SIOptimizeExecMaskingPreRA.cpp:71

isDefBetween

static bool isDefBetween(const LiveRange &LR, SlotIndex AndIdx, SlotIndex SelIdx)

Definition:SIOptimizeExecMaskingPreRA.cpp:83

DEBUG_TYPE

#define DEBUG_TYPE

Definition:SIOptimizeExecMaskingPreRA.cpp:24

operations

SI optimize exec mask operations

Definition:SIOptimizeExecMasking.cpp:108

llvm::AnalysisUsage

Represent the analysis usage information of a pass.

Definition:PassAnalysisSupport.h:47

llvm::AnalysisUsage::addRequired

AnalysisUsage & addRequired()

Definition:PassAnalysisSupport.h:75

llvm::AnalysisUsage::setPreservesAll

void setPreservesAll()

Set by analyses that do not transform their input at all.

Definition:PassAnalysisSupport.h:130

llvm::DWARFExpression::Operation

This class represents an Operation in the Expression.

Definition:DWARFExpression.h:32

llvm::DenseSet

Implements a dense probed hash-table based set.

Definition:DenseSet.h:278

llvm::FunctionPass

FunctionPass class - This class is used to implement most global optimizations.

Definition:Pass.h:310

llvm::GCNSubtarget

Definition:GCNSubtarget.h:34

llvm::LiveInterval

LiveInterval - This class represents the liveness of a register, or stack slot.

Definition:LiveInterval.h:687

llvm::LiveIntervalsWrapperPass

Definition:LiveIntervals.h:527

llvm::LiveIntervals

Definition:LiveIntervals.h:55

llvm::LiveIntervals::getInstructionIndex

SlotIndex getInstructionIndex(const MachineInstr &Instr) const

Returns the base index of the given instruction.

Definition:LiveIntervals.h:245

llvm::LiveIntervals::getRegUnit

LiveRange & getRegUnit(unsigned Unit)

Return the live range for register unit Unit.

Definition:LiveIntervals.h:412

llvm::LiveIntervals::getInterval

LiveInterval & getInterval(Register Reg)

Definition:LiveIntervals.h:133

llvm::LiveQueryResult

Result of a LiveRange query.

Definition:LiveInterval.h:90

llvm::LiveQueryResult::isDeadDef

bool isDeadDef() const

Return true if this instruction has a dead def.

Definition:LiveInterval.h:117

llvm::LiveQueryResult::valueIn

VNInfo * valueIn() const

Return the value that is live-in to the instruction.

Definition:LiveInterval.h:105

llvm::LiveQueryResult::valueOut

VNInfo * valueOut() const

Return the value leaving the instruction, if any.

Definition:LiveInterval.h:123

llvm::LiveQueryResult::isKill

bool isKill() const

Return true if the live-in value is killed by this instruction.

Definition:LiveInterval.h:112

llvm::LiveRange

This class represents the liveness of a register, stack slot, etc.

Definition:LiveInterval.h:157

llvm::LiveRange::vnis

iterator_range< vni_iterator > vnis()

Definition:LiveInterval.h:230

llvm::LiveRange::Query

LiveQueryResult Query(SlotIndex Idx) const

Query Liveness at Idx.

Definition:LiveInterval.h:542

llvm::LiveRange::find

iterator find(SlotIndex Pos)

find - Return an iterator pointing to the first segment that ends after Pos, or end().

Definition:LiveInterval.cpp:350

llvm::MCRegister

Wrapper class representing physical registers. Should be passed by value.

Definition:MCRegister.h:33

llvm::MCRegister::from

static MCRegister from(unsigned Val)

Check the provided unsigned value is a valid MCRegister.

Definition:MCRegister.h:78

llvm::MachineBasicBlock

Definition:MachineBasicBlock.h:125

llvm::MachineBasicBlock::empty

bool empty() const

Definition:MachineBasicBlock.h:327

llvm::MachineBasicBlock::rend

reverse_iterator rend()

Definition:MachineBasicBlock.h:365

llvm::MachineBasicBlock::succ_empty

bool succ_empty() const

Definition:MachineBasicBlock.h:436

llvm::MachineBasicBlock::begin

iterator begin()

Definition:MachineBasicBlock.h:355

llvm::MachineBasicBlock::back

MachineInstr & back()

Definition:MachineBasicBlock.h:335

llvm::MachineBasicBlock::terminators

iterator_range< iterator > terminators()

Definition:MachineBasicBlock.h:375

llvm::MachineBasicBlock::rbegin

reverse_iterator rbegin()

Definition:MachineBasicBlock.h:359

llvm::MachineFunctionPass

MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...

Definition:MachineFunctionPass.h:30

llvm::MachineFunctionPass::getAnalysisUsage

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

Definition:MachineFunctionPass.cpp:169

llvm::MachineFunctionPass::runOnMachineFunction

virtual bool runOnMachineFunction(MachineFunction &MF)=0

runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...

llvm::MachineFunction

Definition:MachineFunction.h:267

llvm::MachineFunction::getSubtarget

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

Definition:MachineFunction.h:733

llvm::MachineFunction::getRegInfo

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

Definition:MachineFunction.h:743

llvm::MachineFunction::getFunction

Function & getFunction()

Return the LLVM function that this machine code represents.

Definition:MachineFunction.h:704

llvm::MachineInstrBuilder::addReg

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

Definition:MachineInstrBuilder.h:99

llvm::MachineInstr

Representation of each machine instruction.

Definition:MachineInstr.h:71

llvm::MachineInstr::getOpcode

unsigned getOpcode() const

Returns the opcode of this MachineInstr.

Definition:MachineInstr.h:577

llvm::MachineInstr::getParent

const MachineBasicBlock * getParent() const

Definition:MachineInstr.h:349

llvm::MachineInstr::findRegisterUseOperandIdx

int findRegisterUseOperandIdx(Register Reg, const TargetRegisterInfo *TRI, bool isKill=false) const

Returns the operand index that is a use of the specific register or -1 if it is not found.

Definition:MachineInstr.cpp:1060

llvm::MachineInstr::eraseFromParent

void eraseFromParent()

Unlink 'this' from the containing basic block and delete it.

Definition:MachineInstr.cpp:767

llvm::MachineInstr::getOperand

const MachineOperand & getOperand(unsigned i) const

Definition:MachineInstr.h:587

llvm::MachineOperand

MachineOperand class - Representation of each machine instruction operand.

Definition:MachineOperand.h:48

llvm::MachineOperand::getSubReg

unsigned getSubReg() const

Definition:MachineOperand.h:374

llvm::MachineOperand::getImm

int64_t getImm() const

Definition:MachineOperand.h:556

llvm::MachineOperand::isImplicit

bool isImplicit() const

Definition:MachineOperand.h:389

llvm::MachineOperand::isReg

bool isReg() const

isReg - Tests if this is a MO_Register operand.

Definition:MachineOperand.h:329

llvm::MachineOperand::setIsDead

void setIsDead(bool Val=true)

Definition:MachineOperand.h:525

llvm::MachineOperand::setReg

void setReg(Register Reg)

Change the register this operand corresponds to.

Definition:MachineOperand.cpp:61

llvm::MachineOperand::isImm

bool isImm() const

isImm - Tests if this is a MO_Immediate operand.

Definition:MachineOperand.h:331

llvm::MachineOperand::isDead

bool isDead() const

Definition:MachineOperand.h:394

llvm::MachineOperand::getReg

getReg - Returns the register number.

Definition:MachineOperand.h:369

llvm::MachineRegisterInfo

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

Definition:MachineRegisterInfo.h:51

llvm::PassRegistry::getPassRegistry

static PassRegistry * getPassRegistry()

getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...

Definition:PassRegistry.cpp:24

llvm::Pass::getPassName

virtual StringRef getPassName() const

getPassName - Return a nice clean name for a pass.

Definition:Pass.cpp:81

llvm::Register

Wrapper class representing virtual and physical registers.

Definition:Register.h:19

llvm::Register::isVirtual

constexpr bool isVirtual() const

Return true if the specified register number is in the virtual register namespace.

Definition:Register.h:91

llvm::Register::isPhysical

constexpr bool isPhysical() const

Return true if the specified register number is in the physical register namespace.

Definition:Register.h:95

llvm::SIInstrInfo

Definition:SIInstrInfo.h:85

llvm::SIRegisterInfo

Definition:SIRegisterInfo.h:32

llvm::SlotIndex

SlotIndex - An opaque wrapper around machine indexes.

Definition:SlotIndexes.h:65

llvm::SlotIndex::getRegSlot

SlotIndex getRegSlot(bool EC=false) const

Returns the register use/def slot in the current instruction for a normal or early-clobber def.

Definition:SlotIndexes.h:237

llvm::SmallVector

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

Definition:SmallVector.h:1196

llvm::StringRef

StringRef - Represent a constant reference to a string, i.e.

Definition:StringRef.h:51

llvm::VNInfo

VNInfo - Value Number Information.

Definition:LiveInterval.h:53

llvm::detail::DenseSetImpl::insert

std::pair< iterator, bool > insert(const ValueT &V)

Definition:DenseSet.h:213

llvm::ilist_node_impl::getIterator

self_iterator getIterator()

Definition:ilist_node.h:132

unsigned

false

Definition:StackSlotColoring.cpp:193

llvm::ARM_MB::ST

@ ST

Definition:ARMBaseInfo.h:73

llvm::CallingConv::ID

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

Definition:CallingConv.h:24

llvm::M68kBeads::Term

@ Term

Definition:M68kBaseInfo.h:116

llvm::X86Disassembler::Reg

Reg

All possible values of the reg field in the ModR/M byte.

Definition:X86DisassemblerDecoder.h:621

llvm::X86::FirstMacroFusionInstKind::Cmp

@ Cmp

llvm

This is an optimization pass for GlobalISel generic memory operations.

Definition:AddressRanges.h:18

llvm::BuildMI

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

Definition:MachineInstrBuilder.h:373

llvm::any_of

bool any_of(R &&range, UnaryPredicate P)

Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.

Definition:STLExtras.h:1746

llvm::dbgs

raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

Definition:Debug.cpp:163

llvm::SIOptimizeExecMaskingPreRAID

char & SIOptimizeExecMaskingPreRAID

Definition:SIOptimizeExecMaskingPreRA.cpp:75

llvm::IRMemLocation::First

@ First

Helpers to iterate all locations in the MemoryEffectsBase class.

llvm::getUndefRegState

unsigned getUndefRegState(bool B)

Definition:MachineInstrBuilder.h:561

llvm::RecurKind::And

@ And

Bitwise or logical AND of integers.

llvm::initializeSIOptimizeExecMaskingPreRAPass

void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry &)

llvm::find_if

auto find_if(R &&Range, UnaryPredicate P)

Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.

Definition:STLExtras.h:1766

llvm::createSIOptimizeExecMaskingPreRAPass

FunctionPass * createSIOptimizeExecMaskingPreRAPass()

Definition:SIOptimizeExecMaskingPreRA.cpp:77

llvm::Wave32

@ Wave32

Definition:AMDGPUMCTargetDesc.h:32

std::swap

void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)

Implement std::swap in terms of BitVector swap.

Definition:BitVector.h:860