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1//===-- SILowerControlFlow.cpp - Use predicates for control flow ----------===//

2//

3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.

4// See https://llvm.org/LICENSE.txt for license information.

5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception

6//

7//===----------------------------------------------------------------------===//

8//

9/// \file

10/// This pass lowers the pseudo control flow instructions to real

11/// machine instructions.

12///

13/// All control flow is handled using predicated instructions and

14/// a predicate stack. Each Scalar ALU controls the operations of 64 Vector

15/// ALUs. The Scalar ALU can update the predicate for any of the Vector ALUs

16/// by writing to the 64-bit EXEC register (each bit corresponds to a

17/// single vector ALU). Typically, for predicates, a vector ALU will write

18/// to its bit of the VCC register (like EXEC VCC is 64-bits, one for each

19/// Vector ALU) and then the ScalarALU will AND the VCC register with the

20/// EXEC to update the predicates.

21///

22/// For example:

23/// %vcc = V_CMP_GT_F32 %vgpr1, %vgpr2

24/// %sgpr0 = SI_IF %vcc

25/// %vgpr0 = V_ADD_F32 %vgpr0, %vgpr0

26/// %sgpr0 = SI_ELSE %sgpr0

27/// %vgpr0 = V_SUB_F32 %vgpr0, %vgpr0

28/// SI_END_CF %sgpr0

29///

30/// becomes:

31///

32/// %sgpr0 = S_AND_SAVEEXEC_B64 %vcc // Save and update the exec mask

33/// %sgpr0 = S_XOR_B64 %sgpr0, %exec // Clear live bits from saved exec mask

34/// S_CBRANCH_EXECZ label0 // This instruction is an optional

35/// // optimization which allows us to

36/// // branch if all the bits of

37/// // EXEC are zero.

38/// %vgpr0 = V_ADD_F32 %vgpr0, %vgpr0 // Do the IF block of the branch

39///

40/// label0:

41/// %sgpr0 = S_OR_SAVEEXEC_B64 %sgpr0 // Restore the exec mask for the Then

42/// // block

43/// %exec = S_XOR_B64 %sgpr0, %exec // Update the exec mask

44/// S_CBRANCH_EXECZ label1 // Use our branch optimization

45/// // instruction again.

46/// %vgpr0 = V_SUB_F32 %vgpr0, %vgpr // Do the ELSE block

47/// label1:

48/// %exec = S_OR_B64 %exec, %sgpr0 // Re-enable saved exec mask bits

49//===----------------------------------------------------------------------===//

51#include "SILowerControlFlow.h"

52#include "AMDGPU.h"

53#include "GCNSubtarget.h"

54#include "MCTargetDesc/AMDGPUMCTargetDesc.h"

55#include "llvm/ADT/SmallSet.h"

56#include "llvm/CodeGen/LiveIntervals.h"

57#include "llvm/CodeGen/LiveVariables.h"

58#include "llvm/CodeGen/MachineDominators.h"

59#include "llvm/CodeGen/MachineFunctionPass.h"

60#include "llvm/Target/TargetMachine.h"

62using namespacellvm;

64#define DEBUG_TYPE "si-lower-control-flow"

66staticcl::opt<bool>

67RemoveRedundantEndcf("amdgpu-remove-redundant-endcf",

68cl::init(true),cl::ReallyHidden);

70namespace{

72classSILowerControlFlow {

73private:

74constSIRegisterInfo *TRI =nullptr;

75constSIInstrInfo *TII =nullptr;

76LiveIntervals *LIS =nullptr;

77LiveVariables *LV =nullptr;

78MachineDominatorTree *MDT =nullptr;

79MachineRegisterInfo *MRI =nullptr;

80SetVector<MachineInstr*> LoweredEndCf;

81DenseSet<Register> LoweredIf;

82SmallSet<MachineBasicBlock *, 4> KillBlocks;

83SmallSet<Register, 8> RecomputeRegs;

85constTargetRegisterClass *BoolRC =nullptr;

86unsigned AndOpc;

87unsigned OrOpc;

88unsigned XorOpc;

89unsigned MovTermOpc;

90unsigned Andn2TermOpc;

91unsigned XorTermrOpc;

92unsigned OrTermrOpc;

93unsigned OrSaveExecOpc;

94unsigned Exec;

96bool EnableOptimizeEndCf =false;

98bool hasKill(constMachineBasicBlock *Begin,constMachineBasicBlock *End);

100void emitIf(MachineInstr &MI);

101void emitElse(MachineInstr &MI);

102void emitIfBreak(MachineInstr &MI);

103void emitLoop(MachineInstr &MI);

104

105MachineBasicBlock *emitEndCf(MachineInstr &MI);

106

107void findMaskOperands(MachineInstr &MI,unsigned OpNo,

108SmallVectorImpl<MachineOperand> &Src)const;

109

110void combineMasks(MachineInstr &MI);

111

112bool removeMBBifRedundant(MachineBasicBlock &MBB);

113

114MachineBasicBlock *process(MachineInstr &MI);

115

116// Skip to the next instruction, ignoring debug instructions, and trivial

117// block boundaries (blocks that have one (typically fallthrough) successor,

118// and the successor has one predecessor.

119MachineBasicBlock::iterator

120 skipIgnoreExecInstsTrivialSucc(MachineBasicBlock &MBB,

121MachineBasicBlock::iterator It)const;

122

123 /// Find the insertion point for a new conditional branch.

124MachineBasicBlock::iterator

125 skipToUncondBrOrEnd(MachineBasicBlock &MBB,

126MachineBasicBlock::iterator I) const{

127assert(I->isTerminator());

128

129// FIXME: What if we had multiple pre-existing conditional branches?

130MachineBasicBlock::iterator End =MBB.end();

131while (I !=End && !I->isUnconditionalBranch())

132 ++I;

133returnI;

134 }

135

136// Remove redundant SI_END_CF instructions.

137void optimizeEndCf();

138

139public:

140 SILowerControlFlow(LiveIntervals *LIS,LiveVariables *LV,

141MachineDominatorTree *MDT)

142 : LIS(LIS), LV(LV), MDT(MDT) {}

143boolrun(MachineFunction &MF);

144};

145

146classSILowerControlFlowLegacy :publicMachineFunctionPass {

147public:

148staticcharID;

149

150 SILowerControlFlowLegacy() :MachineFunctionPass(ID) {}

151

152boolrunOnMachineFunction(MachineFunction &MF)override;

153

154StringRef getPassName() const override{

155return"SI Lower control flow pseudo instructions";

156 }

157

158voidgetAnalysisUsage(AnalysisUsage &AU) const override{

159 AU.addUsedIfAvailable<LiveIntervalsWrapperPass>();

160// Should preserve the same set that TwoAddressInstructions does.

161 AU.addPreserved<MachineDominatorTreeWrapperPass>();

162 AU.addPreserved<SlotIndexesWrapperPass>();

163 AU.addPreserved<LiveIntervalsWrapperPass>();

164 AU.addPreserved<LiveVariablesWrapperPass>();

165MachineFunctionPass::getAnalysisUsage(AU);

166 }

167};

168

169}// end anonymous namespace

170

171char SILowerControlFlowLegacy::ID = 0;

172

173INITIALIZE_PASS(SILowerControlFlowLegacy,DEBUG_TYPE,"SI lower control flow",

174false,false)

175

176staticvoid setImpSCCDefDead(MachineInstr &MI,boolIsDead) {

177MachineOperand &ImpDefSCC =MI.getOperand(3);

178assert(ImpDefSCC.getReg() == AMDGPU::SCC && ImpDefSCC.isDef());

179

180 ImpDefSCC.setIsDead(IsDead);

181}

182

183char &llvm::SILowerControlFlowLegacyID = SILowerControlFlowLegacy::ID;

184

185bool SILowerControlFlow::hasKill(constMachineBasicBlock *Begin,

186constMachineBasicBlock *End) {

187DenseSet<const MachineBasicBlock*> Visited;

188SmallVector<MachineBasicBlock *, 4> Worklist(Begin->successors());

189

190while (!Worklist.empty()) {

191MachineBasicBlock *MBB = Worklist.pop_back_val();

192

193if (MBB ==End || !Visited.insert(MBB).second)

194continue;

195if (KillBlocks.contains(MBB))

196returntrue;

197

198 Worklist.append(MBB->succ_begin(),MBB->succ_end());

199 }

200

201returnfalse;

202}

203

204staticboolisSimpleIf(constMachineInstr &MI,constMachineRegisterInfo *MRI) {

205Register SaveExecReg =MI.getOperand(0).getReg();

206auto U =MRI->use_instr_nodbg_begin(SaveExecReg);

207

208if (U ==MRI->use_instr_nodbg_end() ||

209 std::next(U) !=MRI->use_instr_nodbg_end() ||

210 U->getOpcode() != AMDGPU::SI_END_CF)

211returnfalse;

212

213returntrue;

214}

215

216void SILowerControlFlow::emitIf(MachineInstr &MI) {

217MachineBasicBlock &MBB = *MI.getParent();

218constDebugLoc &DL =MI.getDebugLoc();

219MachineBasicBlock::iterator I(&MI);

220Register SaveExecReg =MI.getOperand(0).getReg();

221MachineOperand&Cond =MI.getOperand(1);

222assert(Cond.getSubReg() == AMDGPU::NoSubRegister);

223

224MachineOperand &ImpDefSCC =MI.getOperand(4);

225assert(ImpDefSCC.getReg() == AMDGPU::SCC && ImpDefSCC.isDef());

226

227// If there is only one use of save exec register and that use is SI_END_CF,

228// we can optimize SI_IF by returning the full saved exec mask instead of

229// just cleared bits.

230bool SimpleIf =isSimpleIf(MI,MRI);

231

232if (SimpleIf) {

233// Check for SI_KILL_*_TERMINATOR on path from if to endif.

234// if there is any such terminator simplifications are not safe.

235autoUseMI =MRI->use_instr_nodbg_begin(SaveExecReg);

236 SimpleIf = !hasKill(MI.getParent(),UseMI->getParent());

237 }

238

239// Add an implicit def of exec to discourage scheduling VALU after this which

240// will interfere with trying to form s_and_saveexec_b64 later.

241Register CopyReg = SimpleIf ? SaveExecReg

242 :MRI->createVirtualRegister(BoolRC);

243MachineInstr *CopyExec =

244BuildMI(MBB,I,DL,TII->get(AMDGPU::COPY), CopyReg)

245 .addReg(Exec)

246 .addReg(Exec,RegState::ImplicitDefine);

247 LoweredIf.insert(CopyReg);

248

249Register Tmp =MRI->createVirtualRegister(BoolRC);

250

251MachineInstr *And =

252BuildMI(MBB,I,DL,TII->get(AndOpc), Tmp)

253 .addReg(CopyReg)

254 .add(Cond);

255if (LV)

256 LV->replaceKillInstruction(Cond.getReg(),MI, *And);

257

258 setImpSCCDefDead(*And,true);

259

260MachineInstr *Xor =nullptr;

261if (!SimpleIf) {

262Xor =

263BuildMI(MBB,I,DL,TII->get(XorOpc), SaveExecReg)

264 .addReg(Tmp)

265 .addReg(CopyReg);

266 setImpSCCDefDead(*Xor, ImpDefSCC.isDead());

267 }

268

269// Use a copy that is a terminator to get correct spill code placement it with

270// fast regalloc.

271MachineInstr *SetExec =

272BuildMI(MBB,I,DL,TII->get(MovTermOpc), Exec)

273 .addReg(Tmp,RegState::Kill);

274if (LV)

275 LV->getVarInfo(Tmp).Kills.push_back(SetExec);

276

277// Skip ahead to the unconditional branch in case there are other terminators

278// present.

279I = skipToUncondBrOrEnd(MBB,I);

280

281// Insert the S_CBRANCH_EXECZ instruction which will be optimized later

282// during SIPreEmitPeephole.

283MachineInstr *NewBr =BuildMI(MBB,I,DL,TII->get(AMDGPU::S_CBRANCH_EXECZ))

284 .add(MI.getOperand(2));

285

286if (!LIS) {

287MI.eraseFromParent();

288return;

289 }

290

291 LIS->InsertMachineInstrInMaps(*CopyExec);

292

293// Replace with and so we don't need to fix the live interval for condition

294// register.

295 LIS->ReplaceMachineInstrInMaps(MI, *And);

296

297if (!SimpleIf)

298 LIS->InsertMachineInstrInMaps(*Xor);

299 LIS->InsertMachineInstrInMaps(*SetExec);

300 LIS->InsertMachineInstrInMaps(*NewBr);

301

302 LIS->removeAllRegUnitsForPhysReg(AMDGPU::EXEC);

303MI.eraseFromParent();

304

305// FIXME: Is there a better way of adjusting the liveness? It shouldn't be

306// hard to add another def here but I'm not sure how to correctly update the

307// valno.

308 RecomputeRegs.insert(SaveExecReg);

309 LIS->createAndComputeVirtRegInterval(Tmp);

310if (!SimpleIf)

311 LIS->createAndComputeVirtRegInterval(CopyReg);

312}

313

314void SILowerControlFlow::emitElse(MachineInstr &MI) {

315MachineBasicBlock &MBB = *MI.getParent();

316constDebugLoc &DL =MI.getDebugLoc();

317

318Register DstReg =MI.getOperand(0).getReg();

319Register SrcReg =MI.getOperand(1).getReg();

320

321MachineBasicBlock::iterator Start =MBB.begin();

322

323// This must be inserted before phis and any spill code inserted before the

324// else.

325Register SaveReg =MRI->createVirtualRegister(BoolRC);

326MachineInstr *OrSaveExec =

327BuildMI(MBB, Start,DL,TII->get(OrSaveExecOpc), SaveReg)

328 .add(MI.getOperand(1));// Saved EXEC

329if (LV)

330 LV->replaceKillInstruction(SrcReg,MI, *OrSaveExec);

331

332MachineBasicBlock *DestBB =MI.getOperand(2).getMBB();

333

334MachineBasicBlock::iterator ElsePt(MI);

335

336// This accounts for any modification of the EXEC mask within the block and

337// can be optimized out pre-RA when not required.

338MachineInstr *And =BuildMI(MBB, ElsePt,DL,TII->get(AndOpc), DstReg)

339 .addReg(Exec)

340 .addReg(SaveReg);

341

342MachineInstr *Xor =

343BuildMI(MBB, ElsePt,DL,TII->get(XorTermrOpc), Exec)

344 .addReg(Exec)

345 .addReg(DstReg);

346

347// Skip ahead to the unconditional branch in case there are other terminators

348// present.

349 ElsePt = skipToUncondBrOrEnd(MBB, ElsePt);

350

351MachineInstr *Branch =

352BuildMI(MBB, ElsePt,DL,TII->get(AMDGPU::S_CBRANCH_EXECZ))

353 .addMBB(DestBB);

354

355if (!LIS) {

356MI.eraseFromParent();

357return;

358 }

359

360 LIS->RemoveMachineInstrFromMaps(MI);

361MI.eraseFromParent();

362

363 LIS->InsertMachineInstrInMaps(*OrSaveExec);

364 LIS->InsertMachineInstrInMaps(*And);

365

366 LIS->InsertMachineInstrInMaps(*Xor);

367 LIS->InsertMachineInstrInMaps(*Branch);

368

369 RecomputeRegs.insert(SrcReg);

370 RecomputeRegs.insert(DstReg);

371 LIS->createAndComputeVirtRegInterval(SaveReg);

372

373// Let this be recomputed.

374 LIS->removeAllRegUnitsForPhysReg(AMDGPU::EXEC);

375}

376

377void SILowerControlFlow::emitIfBreak(MachineInstr &MI) {

378MachineBasicBlock &MBB = *MI.getParent();

379constDebugLoc &DL =MI.getDebugLoc();

380auto Dst =MI.getOperand(0).getReg();

381

382// Skip ANDing with exec if the break condition is already masked by exec

383// because it is a V_CMP in the same basic block. (We know the break

384// condition operand was an i1 in IR, so if it is a VALU instruction it must

385// be one with a carry-out.)

386bool SkipAnding =false;

387if (MI.getOperand(1).isReg()) {

388if (MachineInstr *Def =MRI->getUniqueVRegDef(MI.getOperand(1).getReg())) {

389 SkipAnding =Def->getParent() ==MI.getParent()

390 &&SIInstrInfo::isVALU(*Def);

391 }

392 }

393

394// AND the break condition operand with exec, then OR that into the "loop

395// exit" mask.

396MachineInstr *And =nullptr, *Or =nullptr;

397Register AndReg;

398if (!SkipAnding) {

399 AndReg =MRI->createVirtualRegister(BoolRC);

400And =BuildMI(MBB, &MI,DL,TII->get(AndOpc), AndReg)

401 .addReg(Exec)

402 .add(MI.getOperand(1));

403if (LV)

404 LV->replaceKillInstruction(MI.getOperand(1).getReg(),MI, *And);

405Or =BuildMI(MBB, &MI,DL,TII->get(OrOpc), Dst)

406 .addReg(AndReg)

407 .add(MI.getOperand(2));

408 }else {

409Or =BuildMI(MBB, &MI,DL,TII->get(OrOpc), Dst)

410 .add(MI.getOperand(1))

411 .add(MI.getOperand(2));

412if (LV)

413 LV->replaceKillInstruction(MI.getOperand(1).getReg(),MI, *Or);

414 }

415if (LV)

416 LV->replaceKillInstruction(MI.getOperand(2).getReg(),MI, *Or);

417

418if (LIS) {

419 LIS->ReplaceMachineInstrInMaps(MI, *Or);

420if (And) {

421// Read of original operand 1 is on And now not Or.

422 RecomputeRegs.insert(And->getOperand(2).getReg());

423 LIS->InsertMachineInstrInMaps(*And);

424 LIS->createAndComputeVirtRegInterval(AndReg);

425 }

426 }

427

428MI.eraseFromParent();

429}

430

431void SILowerControlFlow::emitLoop(MachineInstr &MI) {

432MachineBasicBlock &MBB = *MI.getParent();

433constDebugLoc &DL =MI.getDebugLoc();

434

435MachineInstr *AndN2 =

436BuildMI(MBB, &MI,DL,TII->get(Andn2TermOpc), Exec)

437 .addReg(Exec)

438 .add(MI.getOperand(0));

439if (LV)

440 LV->replaceKillInstruction(MI.getOperand(0).getReg(),MI, *AndN2);

441

442auto BranchPt = skipToUncondBrOrEnd(MBB,MI.getIterator());

443MachineInstr *Branch =

444BuildMI(MBB, BranchPt,DL,TII->get(AMDGPU::S_CBRANCH_EXECNZ))

445 .add(MI.getOperand(1));

446

447if (LIS) {

448 RecomputeRegs.insert(MI.getOperand(0).getReg());

449 LIS->ReplaceMachineInstrInMaps(MI, *AndN2);

450 LIS->InsertMachineInstrInMaps(*Branch);

451 }

452

453MI.eraseFromParent();

454}

455

456MachineBasicBlock::iterator

457SILowerControlFlow::skipIgnoreExecInstsTrivialSucc(

458MachineBasicBlock &MBB,MachineBasicBlock::iterator It) const{

459

460SmallSet<const MachineBasicBlock *, 4> Visited;

461MachineBasicBlock *B = &MBB;

462do {

463if (!Visited.insert(B).second)

464returnMBB.end();

465

466auto E =B->end();

467for ( ; It != E; ++It) {

468if (TII->mayReadEXEC(*MRI, *It))

469break;

470 }

471

472if (It != E)

473return It;

474

475if (B->succ_size() != 1)

476returnMBB.end();

477

478// If there is one trivial successor, advance to the next block.

479MachineBasicBlock *Succ = *B->succ_begin();

480

481 It = Succ->begin();

482B = Succ;

483 }while (true);

484}

485

486MachineBasicBlock *SILowerControlFlow::emitEndCf(MachineInstr &MI) {

487MachineBasicBlock &MBB = *MI.getParent();

488constDebugLoc &DL =MI.getDebugLoc();

489

490MachineBasicBlock::iterator InsPt =MBB.begin();

491

492// If we have instructions that aren't prolog instructions, split the block

493// and emit a terminator instruction. This ensures correct spill placement.

494// FIXME: We should unconditionally split the block here.

495bool NeedBlockSplit =false;

496Register DataReg =MI.getOperand(0).getReg();

497for (MachineBasicBlock::iterator I = InsPt, E =MI.getIterator();

498I != E; ++I) {

499if (I->modifiesRegister(DataReg,TRI)) {

500 NeedBlockSplit =true;

501break;

502 }

503 }

504

505unsigned Opcode = OrOpc;

506MachineBasicBlock *SplitBB = &MBB;

507if (NeedBlockSplit) {

508 SplitBB =MBB.splitAt(MI,/*UpdateLiveIns*/true, LIS);

509if (MDT && SplitBB != &MBB) {

510MachineDomTreeNode *MBBNode = (*MDT)[&MBB];

511SmallVector<MachineDomTreeNode *>Children(MBBNode->begin(),

512 MBBNode->end());

513MachineDomTreeNode *SplitBBNode = MDT->addNewBlock(SplitBB, &MBB);

514for (MachineDomTreeNode *Child : Children)

515 MDT->changeImmediateDominator(Child, SplitBBNode);

516 }

517 Opcode = OrTermrOpc;

518 InsPt =MI;

519 }

520

521MachineInstr *NewMI =

522BuildMI(MBB, InsPt,DL,TII->get(Opcode), Exec)

523 .addReg(Exec)

524 .add(MI.getOperand(0));

525if (LV) {

526 LV->replaceKillInstruction(DataReg,MI, *NewMI);

527

528if (SplitBB != &MBB) {

529// Track the set of registers defined in the original block so we don't

530// accidentally add the original block to AliveBlocks. AliveBlocks only

531// includes blocks which are live through, which excludes live outs and

532// local defs.

533DenseSet<Register> DefInOrigBlock;

534

535for (MachineBasicBlock *BlockPiece : {&MBB, SplitBB}) {

536for (MachineInstr &X : *BlockPiece) {

537for (MachineOperand &Op :X.all_defs()) {

538if (Op.getReg().isVirtual())

539 DefInOrigBlock.insert(Op.getReg());

540 }

541 }

542 }

543

544for (unsigned i = 0, e =MRI->getNumVirtRegs(); i != e; ++i) {

545Register Reg =Register::index2VirtReg(i);

546LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);

547

548if (VI.AliveBlocks.test(MBB.getNumber()))

549VI.AliveBlocks.set(SplitBB->getNumber());

550else {

551for (MachineInstr *Kill :VI.Kills) {

552if (Kill->getParent() == SplitBB && !DefInOrigBlock.contains(Reg))

553VI.AliveBlocks.set(MBB.getNumber());

554 }

555 }

556 }

557 }

558 }

559

560 LoweredEndCf.insert(NewMI);

561

562if (LIS)

563 LIS->ReplaceMachineInstrInMaps(MI, *NewMI);

564

565MI.eraseFromParent();

566

567if (LIS)

568 LIS->handleMove(*NewMI);

569return SplitBB;

570}

571

572// Returns replace operands for a logical operation, either single result

573// for exec or two operands if source was another equivalent operation.

574void SILowerControlFlow::findMaskOperands(MachineInstr &MI,unsigned OpNo,

575SmallVectorImpl<MachineOperand> &Src) const{

576MachineOperand &Op =MI.getOperand(OpNo);

577if (!Op.isReg() || !Op.getReg().isVirtual()) {

578 Src.push_back(Op);

579return;

580 }

581

582MachineInstr *Def =MRI->getUniqueVRegDef(Op.getReg());

583if (!Def ||Def->getParent() !=MI.getParent() ||

584 !(Def->isFullCopy() || (Def->getOpcode() ==MI.getOpcode())))

585return;

586

587// Make sure we do not modify exec between def and use.

588// A copy with implicitly defined exec inserted earlier is an exclusion, it

589// does not really modify exec.

590for (autoI =Def->getIterator();I !=MI.getIterator(); ++I)

591if (I->modifiesRegister(AMDGPU::EXEC,TRI) &&

592 !(I->isCopy() &&I->getOperand(0).getReg() != Exec))

593return;

594

595for (constauto &SrcOp :Def->explicit_operands())

596if (SrcOp.isReg() &&SrcOp.isUse() &&

597 (SrcOp.getReg().isVirtual() ||SrcOp.getReg() == Exec))

598 Src.push_back(SrcOp);

599}

600

601// Search and combine pairs of equivalent instructions, like

602// S_AND_B64 x, (S_AND_B64 x, y) => S_AND_B64 x, y

603// S_OR_B64 x, (S_OR_B64 x, y) => S_OR_B64 x, y

604// One of the operands is exec mask.

605void SILowerControlFlow::combineMasks(MachineInstr &MI) {

606assert(MI.getNumExplicitOperands() == 3);

607SmallVector<MachineOperand, 4> Ops;

608unsigned OpToReplace = 1;

609 findMaskOperands(MI, 1, Ops);

610if (Ops.size() == 1) OpToReplace = 2;// First operand can be exec or its copy

611 findMaskOperands(MI, 2, Ops);

612if (Ops.size() != 3)return;

613

614unsigned UniqueOpndIdx;

615if (Ops[0].isIdenticalTo(Ops[1])) UniqueOpndIdx = 2;

616elseif (Ops[0].isIdenticalTo(Ops[2])) UniqueOpndIdx = 1;

617elseif (Ops[1].isIdenticalTo(Ops[2])) UniqueOpndIdx = 1;

618elsereturn;

619

620Register Reg =MI.getOperand(OpToReplace).getReg();

621MI.removeOperand(OpToReplace);

622MI.addOperand(Ops[UniqueOpndIdx]);

623if (MRI->use_empty(Reg))

624MRI->getUniqueVRegDef(Reg)->eraseFromParent();

625}

626

627void SILowerControlFlow::optimizeEndCf() {

628// If the only instruction immediately following this END_CF is another

629// END_CF in the only successor we can avoid emitting exec mask restore here.

630if (!EnableOptimizeEndCf)

631return;

632

633for (MachineInstr *MI :reverse(LoweredEndCf)) {

634MachineBasicBlock &MBB = *MI->getParent();

635auto Next =

636 skipIgnoreExecInstsTrivialSucc(MBB, std::next(MI->getIterator()));

637if (Next ==MBB.end() || !LoweredEndCf.count(&*Next))

638continue;

639// Only skip inner END_CF if outer ENDCF belongs to SI_IF.

640// If that belongs to SI_ELSE then saved mask has an inverted value.

641Register SavedExec

642 =TII->getNamedOperand(*Next, AMDGPU::OpName::src1)->getReg();

643assert(SavedExec.isVirtual() &&"Expected saved exec to be src1!");

644

645constMachineInstr *Def =MRI->getUniqueVRegDef(SavedExec);

646if (Def && LoweredIf.count(SavedExec)) {

647LLVM_DEBUG(dbgs() <<"Skip redundant ";MI->dump());

648if (LIS)

649 LIS->RemoveMachineInstrFromMaps(*MI);

650Register Reg;

651if (LV)

652Reg =TII->getNamedOperand(*MI, AMDGPU::OpName::src1)->getReg();

653MI->eraseFromParent();

654if (LV)

655 LV->recomputeForSingleDefVirtReg(Reg);

656 removeMBBifRedundant(MBB);

657 }

658 }

659}

660

661MachineBasicBlock *SILowerControlFlow::process(MachineInstr &MI) {

662MachineBasicBlock &MBB = *MI.getParent();

663MachineBasicBlock::iterator I(MI);

664MachineInstr *Prev = (I !=MBB.begin()) ? &*(std::prev(I)) :nullptr;

665

666MachineBasicBlock *SplitBB = &MBB;

667

668switch (MI.getOpcode()) {

669case AMDGPU::SI_IF:

670 emitIf(MI);

671break;

672

673case AMDGPU::SI_ELSE:

674 emitElse(MI);

675break;

676

677case AMDGPU::SI_IF_BREAK:

678 emitIfBreak(MI);

679break;

680

681case AMDGPU::SI_LOOP:

682 emitLoop(MI);

683break;

684

685case AMDGPU::SI_WATERFALL_LOOP:

686MI.setDesc(TII->get(AMDGPU::S_CBRANCH_EXECNZ));

687break;

688

689case AMDGPU::SI_END_CF:

690 SplitBB = emitEndCf(MI);

691break;

692

693default:

694assert(false &&"Attempt to process unsupported instruction");

695break;

696 }

697

698MachineBasicBlock::iterator Next;

699for (I = Prev ? Prev->getIterator() :MBB.begin();I !=MBB.end();I = Next) {

700 Next = std::next(I);

701MachineInstr &MaskMI = *I;

702switch (MaskMI.getOpcode()) {

703case AMDGPU::S_AND_B64:

704case AMDGPU::S_OR_B64:

705case AMDGPU::S_AND_B32:

706case AMDGPU::S_OR_B32:

707// Cleanup bit manipulations on exec mask

708 combineMasks(MaskMI);

709break;

710default:

711I =MBB.end();

712break;

713 }

714 }

715

716return SplitBB;

717}

718

719bool SILowerControlFlow::removeMBBifRedundant(MachineBasicBlock &MBB) {

720for (auto &I :MBB.instrs()) {

721if (!I.isDebugInstr() && !I.isUnconditionalBranch())

722returnfalse;

723 }

724

725assert(MBB.succ_size() == 1 &&"MBB has more than one successor");

726

727MachineBasicBlock *Succ = *MBB.succ_begin();

728MachineBasicBlock *FallThrough =nullptr;

729

730while (!MBB.predecessors().empty()) {

731MachineBasicBlock *P = *MBB.pred_begin();

732if (P->getFallThrough(false) == &MBB)

733 FallThrough =P;

734P->ReplaceUsesOfBlockWith(&MBB, Succ);

735 }

736MBB.removeSuccessor(Succ);

737if (LIS) {

738for (auto &I :MBB.instrs())

739 LIS->RemoveMachineInstrFromMaps(I);

740 }

741if (MDT) {

742// If Succ, the single successor of MBB, is dominated by MBB, MDT needs

743// updating by changing Succ's idom to the one of MBB; otherwise, MBB must

744// be a leaf node in MDT and could be erased directly.

745if (MDT->dominates(&MBB, Succ))

746 MDT->changeImmediateDominator(MDT->getNode(Succ),

747 MDT->getNode(&MBB)->getIDom());

748 MDT->eraseNode(&MBB);

749 }

750MBB.clear();

751MBB.eraseFromParent();

752if (FallThrough && !FallThrough->isLayoutSuccessor(Succ)) {

753// Note: we cannot update block layout and preserve live intervals;

754// hence we must insert a branch.

755MachineInstr *BranchMI =BuildMI(*FallThrough, FallThrough->end(),

756 FallThrough->findBranchDebugLoc(),TII->get(AMDGPU::S_BRANCH))

757 .addMBB(Succ);

758if (LIS)

759 LIS->InsertMachineInstrInMaps(*BranchMI);

760 }

761

762returntrue;

763}

764

765bool SILowerControlFlow::run(MachineFunction &MF) {

766constGCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();

767TII =ST.getInstrInfo();

768TRI = &TII->getRegisterInfo();

769 EnableOptimizeEndCf =RemoveRedundantEndcf &&

770 MF.getTarget().getOptLevel() > CodeGenOptLevel::None;

771

772MRI = &MF.getRegInfo();

773 BoolRC =TRI->getBoolRC();

774

775if (ST.isWave32()) {

776 AndOpc = AMDGPU::S_AND_B32;

777 OrOpc = AMDGPU::S_OR_B32;

778 XorOpc = AMDGPU::S_XOR_B32;

779 MovTermOpc = AMDGPU::S_MOV_B32_term;

780 Andn2TermOpc = AMDGPU::S_ANDN2_B32_term;

781 XorTermrOpc = AMDGPU::S_XOR_B32_term;

782 OrTermrOpc = AMDGPU::S_OR_B32_term;

783 OrSaveExecOpc = AMDGPU::S_OR_SAVEEXEC_B32;

784Exec = AMDGPU::EXEC_LO;

785 }else {

786 AndOpc = AMDGPU::S_AND_B64;

787 OrOpc = AMDGPU::S_OR_B64;

788 XorOpc = AMDGPU::S_XOR_B64;

789 MovTermOpc = AMDGPU::S_MOV_B64_term;

790 Andn2TermOpc = AMDGPU::S_ANDN2_B64_term;

791 XorTermrOpc = AMDGPU::S_XOR_B64_term;

792 OrTermrOpc = AMDGPU::S_OR_B64_term;

793 OrSaveExecOpc = AMDGPU::S_OR_SAVEEXEC_B64;

794Exec = AMDGPU::EXEC;

795 }

796

797// Compute set of blocks with kills

798constbool CanDemote =

799 MF.getFunction().getCallingConv() ==CallingConv::AMDGPU_PS;

800for (auto &MBB : MF) {

801bool IsKillBlock =false;

802for (auto &Term :MBB.terminators()) {

803if (TII->isKillTerminator(Term.getOpcode())) {

804 KillBlocks.insert(&MBB);

805 IsKillBlock =true;

806break;

807 }

808 }

809if (CanDemote && !IsKillBlock) {

810for (auto &MI :MBB) {

811if (MI.getOpcode() == AMDGPU::SI_DEMOTE_I1) {

812 KillBlocks.insert(&MBB);

813break;

814 }

815 }

816 }

817 }

818

819bool Changed =false;

820MachineFunction::iterator NextBB;

821for (MachineFunction::iterator BI = MF.begin();

822 BI != MF.end(); BI = NextBB) {

823 NextBB = std::next(BI);

824MachineBasicBlock *MBB = &*BI;

825

826MachineBasicBlock::iterator I, E, Next;

827 E =MBB->end();

828for (I =MBB->begin();I != E;I = Next) {

829 Next = std::next(I);

830MachineInstr &MI = *I;

831MachineBasicBlock *SplitMBB =MBB;

832

833switch (MI.getOpcode()) {

834case AMDGPU::SI_IF:

835case AMDGPU::SI_ELSE:

836case AMDGPU::SI_IF_BREAK:

837case AMDGPU::SI_WATERFALL_LOOP:

838case AMDGPU::SI_LOOP:

839case AMDGPU::SI_END_CF:

840 SplitMBB = process(MI);

841 Changed =true;

842break;

843 }

844

845if (SplitMBB !=MBB) {

846MBB = Next->getParent();

847 E =MBB->end();

848 }

849 }

850 }

851

852 optimizeEndCf();

853

854if (LIS) {

855for (Register Reg : RecomputeRegs) {

856 LIS->removeInterval(Reg);

857 LIS->createAndComputeVirtRegInterval(Reg);

858 }

859 }

860

861 RecomputeRegs.clear();

862 LoweredEndCf.clear();

863 LoweredIf.clear();

864 KillBlocks.clear();

865

866return Changed;

867}

868

869bool SILowerControlFlowLegacy::runOnMachineFunction(MachineFunction &MF) {

870// This doesn't actually need LiveIntervals, but we can preserve them.

871auto *LISWrapper = getAnalysisIfAvailable<LiveIntervalsWrapperPass>();

872LiveIntervals *LIS = LISWrapper ? &LISWrapper->getLIS() :nullptr;

873// This doesn't actually need LiveVariables, but we can preserve them.

874auto *LVWrapper = getAnalysisIfAvailable<LiveVariablesWrapperPass>();

875LiveVariables *LV = LVWrapper ? &LVWrapper->getLV() :nullptr;

876auto *MDTWrapper = getAnalysisIfAvailable<MachineDominatorTreeWrapperPass>();

877MachineDominatorTree *MDT = MDTWrapper ? &MDTWrapper->getDomTree() :nullptr;

878return SILowerControlFlow(LIS, LV, MDT).run(MF);

879}

880

881PreservedAnalyses

882SILowerControlFlowPass::run(MachineFunction &MF,

883MachineFunctionAnalysisManager &MFAM) {

884LiveIntervals *LIS = MFAM.getCachedResult<LiveIntervalsAnalysis>(MF);

885LiveVariables *LV = MFAM.getCachedResult<LiveVariablesAnalysis>(MF);

886MachineDominatorTree *MDT =

887 MFAM.getCachedResult<MachineDominatorTreeAnalysis>(MF);

888

889bool Changed = SILowerControlFlow(LIS, LV, MDT).run(MF);

890if (!Changed)

891returnPreservedAnalyses::all();

892

893auto PA =getMachineFunctionPassPreservedAnalyses();

894 PA.preserve<MachineDominatorTreeAnalysis>();

895 PA.preserve<SlotIndexesAnalysis>();

896 PA.preserve<LiveIntervalsAnalysis>();

897 PA.preserve<LiveVariablesAnalysis>();

898return PA;

899}

MRI

unsigned const MachineRegisterInfo * MRI

Definition:AArch64AdvSIMDScalarPass.cpp:105

UseMI

MachineInstrBuilder & UseMI

Definition:AArch64ExpandPseudoInsts.cpp:112

AMDGPUMCTargetDesc.h

Provides AMDGPU specific target descriptions.

AMDGPU.h

MBB

MachineBasicBlock & MBB

Definition:ARMSLSHardening.cpp:71

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

Definition:ARMSLSHardening.cpp:73

static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")

LLVM_DEBUG

#define LLVM_DEBUG(...)

Definition:Debug.h:106

End

bool End

Definition:ELF_riscv.cpp:480

static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")

GCNSubtarget.h

AMD GCN specific subclass of TargetSubtarget.

TII

const HexagonInstrInfo * TII

Definition:HexagonCopyToCombine.cpp:125

IRTranslator LLVM IR MI

Definition:IRTranslator.cpp:112

LiveIntervals.h

LiveVariables.h

#define I(x, y, z)

Definition:MD5.cpp:58

MachineDominators.h

MachineFunctionPass.h

TRI

unsigned const TargetRegisterInfo * TRI

Definition:MachineSink.cpp:2029

#define P(N)

INITIALIZE_PASS

#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)

Definition:PassSupport.h:38

Cond

const SmallVectorImpl< MachineOperand > & Cond

Definition:RISCVRedundantCopyElimination.cpp:75

RemoveRedundantEndcf

static cl::opt< bool > RemoveRedundantEndcf("amdgpu-remove-redundant-endcf", cl::init(true), cl::ReallyHidden)

assert

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

IsDead

bool IsDead

Definition:SILowerControlFlow.cpp:176

isSimpleIf

static bool isSimpleIf(const MachineInstr &MI, const MachineRegisterInfo *MRI)

Definition:SILowerControlFlow.cpp:204

DEBUG_TYPE

#define DEBUG_TYPE

Definition:SILowerControlFlow.cpp:64

SILowerControlFlow.h

SmallSet.h

This file defines the SmallSet class.

llvm::AnalysisManager

A container for analyses that lazily runs them and caches their results.

Definition:PassManager.h:253

llvm::AnalysisManager::getCachedResult

PassT::Result * getCachedResult(IRUnitT &IR) const

Get the cached result of an analysis pass for a given IR unit.

Definition:PassManager.h:429

llvm::AnalysisUsage

Represent the analysis usage information of a pass.

Definition:PassAnalysisSupport.h:47

llvm::AnalysisUsage::addUsedIfAvailable

AnalysisUsage & addUsedIfAvailable()

Add the specified Pass class to the set of analyses used by this pass.

Definition:PassAnalysisSupport.h:117

llvm::AnalysisUsage::addPreserved

AnalysisUsage & addPreserved()

Add the specified Pass class to the set of analyses preserved by this pass.

Definition:PassAnalysisSupport.h:98

llvm::DWARFExpression::Operation

This class represents an Operation in the Expression.

Definition:DWARFExpression.h:32

llvm::DebugLoc

A debug info location.

Definition:DebugLoc.h:33

llvm::DenseSet

Implements a dense probed hash-table based set.

Definition:DenseSet.h:278

llvm::DomTreeNodeBase

Base class for the actual dominator tree node.

Definition:GenericDomTree.h:54

llvm::DomTreeNodeBase::begin

iterator begin()

Definition:GenericDomTree.h:76

llvm::DomTreeNodeBase::end

iterator end()

Definition:GenericDomTree.h:77

llvm::DominatorTreeBase::changeImmediateDominator

void changeImmediateDominator(DomTreeNodeBase< NodeT > *N, DomTreeNodeBase< NodeT > *NewIDom)

changeImmediateDominator - This method is used to update the dominator tree information when a node's...

Definition:GenericDomTree.h:723

llvm::DominatorTreeBase::addNewBlock

DomTreeNodeBase< NodeT > * addNewBlock(NodeT *BB, NodeT *DomBB)

Add a new node to the dominator tree information.

Definition:GenericDomTree.h:687

llvm::DominatorTreeBase::eraseNode

void eraseNode(NodeT *BB)

eraseNode - Removes a node from the dominator tree.

Definition:GenericDomTree.h:737

llvm::DominatorTreeBase::getNode

DomTreeNodeBase< NodeT > * getNode(const NodeT *BB) const

getNode - return the (Post)DominatorTree node for the specified basic block.

Definition:GenericDomTree.h:401

llvm::Function::getCallingConv

CallingConv::ID getCallingConv() const

getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...

Definition:Function.h:277

llvm::GCNSubtarget

Definition:GCNSubtarget.h:34

llvm::LiveIntervalsAnalysis

Definition:LiveIntervals.h:507

llvm::LiveIntervalsWrapperPass

Definition:LiveIntervals.h:527

llvm::LiveIntervals

Definition:LiveIntervals.h:55

llvm::LiveIntervals::removeAllRegUnitsForPhysReg

void removeAllRegUnitsForPhysReg(MCRegister Reg)

Remove associated live ranges for the register units associated with Reg.

Definition:LiveIntervals.h:442

llvm::LiveIntervals::InsertMachineInstrInMaps

SlotIndex InsertMachineInstrInMaps(MachineInstr &MI)

Definition:LiveIntervals.h:283

llvm::LiveIntervals::handleMove

void handleMove(MachineInstr &MI, bool UpdateFlags=false)

Call this method to notify LiveIntervals that instruction MI has been moved within a basic block.

Definition:LiveIntervals.cpp:1559

llvm::LiveIntervals::RemoveMachineInstrFromMaps

void RemoveMachineInstrFromMaps(MachineInstr &MI)

Definition:LiveIntervals.h:293

llvm::LiveIntervals::removeInterval

void removeInterval(Register Reg)

Interval removal.

Definition:LiveIntervals.h:170

llvm::LiveIntervals::createAndComputeVirtRegInterval

LiveInterval & createAndComputeVirtRegInterval(Register Reg)

Definition:LiveIntervals.h:156

llvm::LiveIntervals::ReplaceMachineInstrInMaps

SlotIndex ReplaceMachineInstrInMaps(MachineInstr &MI, MachineInstr &NewMI)

Definition:LiveIntervals.h:297

llvm::LiveRange::clear

void clear()

Definition:LiveInterval.h:300

llvm::LiveVariablesAnalysis

Definition:LiveVariables.h:304

llvm::LiveVariablesWrapperPass

Definition:LiveVariables.h:324

llvm::LiveVariables

Definition:LiveVariables.h:48

llvm::LiveVariables::replaceKillInstruction

void replaceKillInstruction(Register Reg, MachineInstr &OldMI, MachineInstr &NewMI)

replaceKillInstruction - Update register kill info by replacing a kill instruction with a new one.

Definition:LiveVariables.cpp:770

llvm::LiveVariables::recomputeForSingleDefVirtReg

void recomputeForSingleDefVirtReg(Register Reg)

Recompute liveness from scratch for a virtual register Reg that is known to have a single def that do...

Definition:LiveVariables.cpp:684

llvm::LiveVariables::getVarInfo

VarInfo & getVarInfo(Register Reg)

getVarInfo - Return the VarInfo structure for the specified VIRTUAL register.

Definition:LiveVariables.cpp:114

llvm::MachineBasicBlock

Definition:MachineBasicBlock.h:125

llvm::MachineBasicBlock::clear

void clear()

Definition:MachineBasicBlock.h:1101

llvm::MachineBasicBlock::getNumber

int getNumber() const

MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...

Definition:MachineBasicBlock.h:1217

llvm::MachineBasicBlock::succ_end

succ_iterator succ_end()

Definition:MachineBasicBlock.h:423

llvm::MachineBasicBlock::instrs

instr_range instrs()

Definition:MachineBasicBlock.h:350

llvm::MachineBasicBlock::succ_begin

succ_iterator succ_begin()

Definition:MachineBasicBlock.h:421

llvm::MachineBasicBlock::succ_size

unsigned succ_size() const

Definition:MachineBasicBlock.h:433

llvm::MachineBasicBlock::removeSuccessor

void removeSuccessor(MachineBasicBlock *Succ, bool NormalizeSuccProbs=false)

Remove successor from the successors list of this MachineBasicBlock.

Definition:MachineBasicBlock.cpp:836

llvm::MachineBasicBlock::begin

iterator begin()

Definition:MachineBasicBlock.h:355

llvm::MachineBasicBlock::pred_begin

pred_iterator pred_begin()

Definition:MachineBasicBlock.h:405

llvm::MachineBasicBlock::isLayoutSuccessor

bool isLayoutSuccessor(const MachineBasicBlock *MBB) const

Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...

Definition:MachineBasicBlock.cpp:964

llvm::MachineBasicBlock::splitAt

MachineBasicBlock * splitAt(MachineInstr &SplitInst, bool UpdateLiveIns=true, LiveIntervals *LIS=nullptr)

Split a basic block into 2 pieces at SplitPoint.

Definition:MachineBasicBlock.cpp:1025

llvm::MachineBasicBlock::eraseFromParent

void eraseFromParent()

This method unlinks 'this' from the containing function and deletes it.

Definition:MachineBasicBlock.cpp:1476

llvm::MachineBasicBlock::end

iterator end()

Definition:MachineBasicBlock.h:357

llvm::MachineBasicBlock::terminators

iterator_range< iterator > terminators()

Definition:MachineBasicBlock.h:375

llvm::MachineBasicBlock::findBranchDebugLoc

DebugLoc findBranchDebugLoc()

Find and return the merged DebugLoc of the branch instructions of the block.

Definition:MachineBasicBlock.cpp:1559

llvm::MachineBasicBlock::successors

iterator_range< succ_iterator > successors()

Definition:MachineBasicBlock.h:444

llvm::MachineBasicBlock::predecessors

iterator_range< pred_iterator > predecessors()

Definition:MachineBasicBlock.h:438

llvm::MachineDominatorTreeAnalysis

Analysis pass which computes a MachineDominatorTree.

Definition:MachineDominators.h:107

llvm::MachineDominatorTreeWrapperPass

Analysis pass which computes a MachineDominatorTree.

Definition:MachineDominators.h:131

llvm::MachineDominatorTree

DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...

Definition:MachineDominators.h:75

llvm::MachineDominatorTree::dominates

bool dominates(const MachineInstr *A, const MachineInstr *B) const

Definition:MachineDominators.h:91

llvm::MachineFunctionPass

MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...

Definition:MachineFunctionPass.h:30

llvm::MachineFunctionPass::getAnalysisUsage

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

Definition:MachineFunctionPass.cpp:169

llvm::MachineFunctionPass::runOnMachineFunction

virtual bool runOnMachineFunction(MachineFunction &MF)=0

runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...

llvm::MachineFunction

Definition:MachineFunction.h:267

llvm::MachineFunction::getSubtarget

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

Definition:MachineFunction.h:733

llvm::MachineFunction::getRegInfo

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

Definition:MachineFunction.h:743

llvm::MachineFunction::getFunction

Function & getFunction()

Return the LLVM function that this machine code represents.

Definition:MachineFunction.h:704

llvm::MachineFunction::getTarget

const TargetMachine & getTarget() const

getTarget - Return the target machine this machine code is compiled with

Definition:MachineFunction.h:729

llvm::MachineInstrBuilder::add

const MachineInstrBuilder & add(const MachineOperand &MO) const

Definition:MachineInstrBuilder.h:226

llvm::MachineInstrBuilder::addReg

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

Definition:MachineInstrBuilder.h:99

llvm::MachineInstrBuilder::addMBB

const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const

Definition:MachineInstrBuilder.h:148

llvm::MachineInstrBundleIterator< MachineInstr >

llvm::MachineInstr

Representation of each machine instruction.

Definition:MachineInstr.h:71

llvm::MachineInstr::getOpcode

unsigned getOpcode() const

Returns the opcode of this MachineInstr.

Definition:MachineInstr.h:577

llvm::MachineInstr::getParent

const MachineBasicBlock * getParent() const

Definition:MachineInstr.h:349

llvm::MachineOperand

MachineOperand class - Representation of each machine instruction operand.

Definition:MachineOperand.h:48

llvm::MachineOperand::setIsDead

void setIsDead(bool Val=true)

Definition:MachineOperand.h:525

llvm::MachineOperand::isDef

bool isDef() const

Definition:MachineOperand.h:384

llvm::MachineOperand::isDead

bool isDead() const

Definition:MachineOperand.h:394

llvm::MachineOperand::getReg

getReg - Returns the register number.

Definition:MachineOperand.h:369

llvm::MachineRegisterInfo

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

Definition:MachineRegisterInfo.h:51

llvm::Pass::dump

void dump() const

Definition:Pass.cpp:136

llvm::Pass::getPassName

virtual StringRef getPassName() const

getPassName - Return a nice clean name for a pass.

Definition:Pass.cpp:81

llvm::PreservedAnalyses

A set of analyses that are preserved following a run of a transformation pass.

Definition:Analysis.h:111

llvm::PreservedAnalyses::all

static PreservedAnalyses all()

Construct a special preserved set that preserves all passes.

Definition:Analysis.h:117

llvm::Register

Wrapper class representing virtual and physical registers.

Definition:Register.h:19

llvm::Register::index2VirtReg

static Register index2VirtReg(unsigned Index)

Convert a 0-based index to a virtual register number.

Definition:Register.h:84

llvm::Register::isVirtual

constexpr bool isVirtual() const

Return true if the specified register number is in the virtual register namespace.

Definition:Register.h:91

llvm::SIInstrInfo

Definition:SIInstrInfo.h:85

llvm::SIInstrInfo::isVALU

static bool isVALU(const MachineInstr &MI)

Definition:SIInstrInfo.h:425

llvm::SILowerControlFlowPass::run

PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM)

Definition:SILowerControlFlow.cpp:882

llvm::SIRegisterInfo

Definition:SIRegisterInfo.h:32

llvm::SetVector

A vector that has set insertion semantics.

Definition:SetVector.h:57

llvm::SetVector::clear

void clear()

Completely clear the SetVector.

Definition:SetVector.h:273

llvm::SetVector::count

size_type count(const key_type &key) const

Count the number of elements of a given key in the SetVector.

Definition:SetVector.h:264

llvm::SetVector::insert

bool insert(const value_type &X)

Insert a new element into the SetVector.

Definition:SetVector.h:162

llvm::SlotIndexesAnalysis

Definition:SlotIndexes.h:644

llvm::SlotIndexesWrapperPass

Definition:SlotIndexes.h:663

llvm::SmallSet

SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...

Definition:SmallSet.h:132

llvm::SmallSet::clear

void clear()

Definition:SmallSet.h:204

llvm::SmallSet::contains

bool contains(const T &V) const

Check if the SmallSet contains the given element.

Definition:SmallSet.h:222

llvm::SmallSet::insert

std::pair< const_iterator, bool > insert(const T &V)

insert - Insert an element into the set if it isn't already there.

Definition:SmallSet.h:181

llvm::SmallVectorBase::empty

bool empty() const

Definition:SmallVector.h:81

llvm::SmallVectorBase::size

size_t size() const

Definition:SmallVector.h:78

llvm::SmallVectorImpl

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

Definition:SmallVector.h:573

llvm::SmallVectorImpl::pop_back_val

T pop_back_val()

Definition:SmallVector.h:673

llvm::SmallVectorImpl::append

void append(ItTy in_start, ItTy in_end)

Add the specified range to the end of the SmallVector.

Definition:SmallVector.h:683

llvm::SmallVector

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

Definition:SmallVector.h:1196

llvm::SrcOp

Definition:MachineIRBuilder.h:142

llvm::SrcOp::getReg

Definition:MachineIRBuilder.h:194

llvm::StringRef

StringRef - Represent a constant reference to a string, i.e.

Definition:StringRef.h:51

llvm::TargetMachine::getOptLevel

CodeGenOptLevel getOptLevel() const

Returns the optimization level: None, Less, Default, or Aggressive.

Definition:TargetMachine.h:257

llvm::TargetRegisterClass

Definition:TargetRegisterInfo.h:44

llvm::cl::opt

Definition:CommandLine.h:1423

llvm::detail::DenseSetImpl::insert

std::pair< iterator, bool > insert(const ValueT &V)

Definition:DenseSet.h:213

llvm::detail::DenseSetImpl::clear

void clear()

Definition:DenseSet.h:92

llvm::detail::DenseSetImpl::contains

bool contains(const_arg_type_t< ValueT > V) const

Check if the set contains the given element.

Definition:DenseSet.h:193

llvm::detail::DenseSetImpl::count

size_type count(const_arg_type_t< ValueT > V) const

Return 1 if the specified key is in the set, 0 otherwise.

Definition:DenseSet.h:95

llvm::ilist_node_impl::getIterator

self_iterator getIterator()

Definition:ilist_node.h:132

unsigned

TargetMachine.h

llvm::ARM_MB::ST

@ ST

Definition:ARMBaseInfo.h:73

llvm::CallingConv::AMDGPU_PS

@ AMDGPU_PS

Used for Mesa/AMDPAL pixel shaders.

Definition:CallingConv.h:194

llvm::CallingConv::ID

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

Definition:CallingConv.h:24

llvm::M68kBeads::Term

@ Term

Definition:M68kBaseInfo.h:116

llvm::MCID::Branch

@ Branch

Definition:MCInstrDesc.h:159

llvm::RegState::ImplicitDefine

@ ImplicitDefine

Definition:MachineInstrBuilder.h:65

llvm::RegState::Kill

@ Kill

The last use of a register.

Definition:MachineInstrBuilder.h:50

llvm::SIEncodingFamily::VI

@ VI

Definition:SIDefines.h:37

llvm::X86Disassembler::Reg

Reg

All possible values of the reg field in the ModR/M byte.

Definition:X86DisassemblerDecoder.h:621

llvm::cl::ReallyHidden

@ ReallyHidden

Definition:CommandLine.h:138

llvm::cl::init

initializer< Ty > init(const Ty &Val)

Definition:CommandLine.h:443

llvm::dxil::PointerTypeAnalysis::run

PointerTypeMap run(const Module &M)

Compute the PointerTypeMap for the module M.

Definition:PointerTypeAnalysis.cpp:191

llvm::logicalview::LVReportKind::Children

@ Children

llvm::orc::MemProt::Exec

@ Exec

llvm::rdf::Def

NodeAddr< DefNode * > Def

Definition:RDFGraph.h:384

llvm

This is an optimization pass for GlobalISel generic memory operations.

Definition:AddressRanges.h:18

llvm::BuildMI

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

Definition:MachineInstrBuilder.h:373

llvm::getMachineFunctionPassPreservedAnalyses

PreservedAnalyses getMachineFunctionPassPreservedAnalyses()

Returns the minimum set of Analyses that all machine function passes must preserve.

Definition:MachinePassManager.cpp:158

llvm::reverse

auto reverse(ContainerTy &&C)

Definition:STLExtras.h:420

llvm::dbgs

raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

Definition:Debug.cpp:163

llvm::SILowerControlFlowLegacyID

char & SILowerControlFlowLegacyID

Definition:SILowerControlFlow.cpp:183

llvm::RecurKind::Or

@ Or

Bitwise or logical OR of integers.

llvm::RecurKind::Xor

@ Xor

Bitwise or logical XOR of integers.

llvm::RecurKind::And

@ And

Bitwise or logical AND of integers.

llvm::LiveVariables::VarInfo

VarInfo - This represents the regions where a virtual register is live in the program.

Definition:LiveVariables.h:78

llvm::LiveVariables::VarInfo::Kills

std::vector< MachineInstr * > Kills

Kills - List of MachineInstruction's which are the last use of this virtual register (kill it) in the...

Definition:LiveVariables.h:88