1//===-- RISCVTargetParser.cpp - Parser for target features ------*- C++ -*-===// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7//===----------------------------------------------------------------------===// 9// This file implements a target parser to recognise hardware features 12//===----------------------------------------------------------------------===// 23#define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN, \ 24 FAST_VECTOR_UNALIGN, MVENDORID, MARCHID, MIMPID) \ 26#define TUNE_PROC(ENUM, NAME) CK_##ENUM, 27#include "llvm/TargetParser/RISCVTargetParserDef.inc" 31#define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN, \ 32 FAST_VECTOR_UNALIGN, MVENDORID, MARCHID, MIMPID) \ 36 FAST_SCALAR_UNALIGN, \ 37 FAST_VECTOR_UNALIGN, \ 38 {MVENDORID, MARCHID, MIMPID}, \ 40#include "llvm/TargetParser/RISCVTargetParserDef.inc" 52returnInfo &&
Info->FastScalarUnalignedAccess;
57returnInfo &&
Info->FastVectorUnalignedAccess;
62return Model.MVendorID != 0 && Model.MArchID != 0 && Model.MImpID != 0;
77returnInfo->is64Bit() == IsRV64;
81 std::optional<CPUKind> Kind =
84 #include "llvm/TargetParser/RISCVTargetParserDef.inc" 85 .Default(std::nullopt);
90// Fallback to parsing as a CPU. 98returnInfo->DefaultMarch;
103if (IsRV64 ==
C.is64Bit())
110if (IsRV64 ==
C.is64Bit())
113#define TUNE_PROC(ENUM, NAME) Values.emplace_back(StringRef(NAME)); 114#include "llvm/TargetParser/RISCVTargetParserDef.inc" 117// This function is currently used by IREE, so it's not dead code. 122if (MarchFromCPU ==
"")
125 EnabledFeatures.
clear();
127 MarchFromCPU,
/* EnableExperimentalExtension */true);
132 std::vector<std::string> FeatStrings =
133 (*RII)->toFeatures(
/* AddAllExtensions */false);
134for (
constauto &
F : FeatStrings)
141namespaceRISCVExtensionBitmaskTable {
142#define GET_RISCVExtensionBitmaskTable_IMPL 143#include "llvm/TargetParser/RISCVTargetParserDef.inc" 145}
// namespace RISCVExtensionBitmaskTable 149bool operator()(
const RISCVExtensionBitmaskTable::RISCVExtensionBitmask &
LHS,
151return StringRef(
LHS.Name) <
RHS;
159// Encode VTYPE into the binary format used by the the VSETVLI instruction which 160// is used by our MC layer representation. 162// Bits | Name | Description 163// -----+------------+------------------------------------------------ 164// 7 | vma | Vector mask agnostic 165// 6 | vta | Vector tail agnostic 166// 5:3 | vsew[2:0] | Standard element width (SEW) setting 167// 2:0 | vlmul[2:0] | Vector register group multiplier (LMUL) setting 171unsigned VLMULBits =
static_cast<unsigned>(VLMUL);
173unsigned VTypeI = (VSEWBits << 3) | (VLMULBits & 0x7);
190return std::make_pair(1 <<
static_cast<unsigned>(VLMUL),
false);
194return std::make_pair(1 << (8 -
static_cast<unsigned>(VLMUL)),
true);
199unsigned Sew =
getSEW(VType);
228// Convert LMul to a fixed point value with 3 fractional bits. 229 LMul = Fractional ? (8 / LMul) : (LMul * 8);
231assert(SEW >= 8 &&
"Unexpected SEW value");
232return (SEW * 8) / LMul;
235std::optional<RISCVII::VLMUL>
238unsigned EMULFixedPoint = (EEW * 8) / Ratio;
239bool Fractional = EMULFixedPoint < 8;
240unsigned EMUL = Fractional ? 8 / EMULFixedPoint : EMULFixedPoint / 8;
246}
// namespace RISCVVType Analysis containing CSE Info
#define TUNE_PROC(ENUM, NAME)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
static llvm::Expected< std::unique_ptr< RISCVISAInfo > > parseArchString(StringRef Arch, bool EnableExperimentalExtension, bool ExperimentalExtensionVersionCheck=true)
Parse RISC-V ISA info from arch string.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
reference emplace_back(ArgTypes &&... Args)
void push_back(const T &Elt)
StringRef - Represent a constant reference to a string, i.e.
A switch()-like statement whose cases are string literals.
This class implements an extremely fast bulk output stream that can only output to a stream.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
static bool isTailAgnostic(unsigned VType)
static RISCVII::VLMUL getVLMUL(unsigned VType)
std::pair< unsigned, bool > decodeVLMUL(RISCVII::VLMUL VLMUL)
unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul)
static bool isValidLMUL(unsigned LMUL, bool Fractional)
static RISCVII::VLMUL encodeLMUL(unsigned LMUL, bool Fractional)
static bool isMaskAgnostic(unsigned VType)
static unsigned encodeSEW(unsigned SEW)
static bool isValidSEW(unsigned SEW)
void printVType(unsigned VType, raw_ostream &OS)
unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic, bool MaskAgnostic)
static unsigned getSEW(unsigned VType)
std::optional< RISCVII::VLMUL > getSameRatioLMUL(unsigned SEW, RISCVII::VLMUL VLMUL, unsigned EEW)
bool hasFastVectorUnalignedAccess(StringRef CPU)
void getFeaturesForCPU(StringRef CPU, SmallVectorImpl< std::string > &EnabledFeatures, bool NeedPlus=false)
void fillValidTuneCPUArchList(SmallVectorImpl< StringRef > &Values, bool IsRV64)
static const CPUInfo * getCPUInfoByName(StringRef CPU)
constexpr CPUInfo RISCVCPUInfo[]
CPUModel getCPUModel(StringRef CPU)
StringRef getMArchFromMcpu(StringRef CPU)
bool parseCPU(StringRef CPU, bool IsRV64)
bool hasFastScalarUnalignedAccess(StringRef CPU)
bool hasValidCPUModel(StringRef CPU)
bool parseTuneCPU(StringRef CPU, bool IsRV64)
void fillValidCPUArchList(SmallVectorImpl< StringRef > &Values, bool IsRV64)
This is an optimization pass for GlobalISel generic memory operations.
bool errorToBool(Error Err)
Helper for converting an Error to a bool.
