1//===-- RISCVSubtarget.cpp - RISC-V Subtarget Information -----------------===// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7//===----------------------------------------------------------------------===// 9// This file implements the RISC-V specific subclass of TargetSubtargetInfo. 11//===----------------------------------------------------------------------===// 27#define DEBUG_TYPE "riscv-subtarget" 29#define GET_SUBTARGETINFO_TARGET_DESC 30#define GET_SUBTARGETINFO_CTOR 31#include "RISCVGenSubtargetInfo.inc" 33#define GET_RISCV_MACRO_FUSION_PRED_IMPL 34#include "RISCVGenMacroFusion.inc" 38#define GET_RISCVTuneInfoTable_IMPL 39#include "RISCVGenSearchableTables.inc" 40}
// namespace llvm::RISCVTuneInfoTable 43"riscv-v-fixed-length-vector-lmul-max",
44cl::desc(
"The maximum LMUL value to use for fixed length vectors. " 45"Fractional LMUL values are not supported."),
49"riscv-disable-using-constant-pool-for-large-ints",
50cl::desc(
"Disable using constant pool for large integers."),
54"riscv-max-build-ints-cost",
59cl::desc(
"Enable the use of AA during codegen."));
63cl::desc(
"Set minimum number of entries to use a jump table on RISCV"));
67cl::desc(
"RISCV: Optimize for load-store bonding"),
74void RISCVSubtarget::anchor() {}
77RISCVSubtarget::initializeSubtargetDependencies(
constTriple &TT,
StringRef CPU,
80// Determine default and user-specified characteristics 81bool Is64Bit =
TT.isArch64Bit();
82if (CPU.
empty() || CPU ==
"generic")
83 CPU = Is64Bit ?
"generic-rv64" :
"generic-rv32";
88 TuneInfo = RISCVTuneInfoTable::getRISCVTuneInfo(TuneCPU);
89// If there is no TuneInfo for this CPU, we fail back to generic. 91 TuneInfo = RISCVTuneInfoTable::getRISCVTuneInfo(
"generic");
92assert(TuneInfo &&
"TuneInfo shouldn't be nullptr!");
102StringRef ABIName,
unsigned RVVVectorBitsMin,
103unsigned RVVVectorBitsMax,
106 RVVVectorBitsMin(RVVVectorBitsMin), RVVVectorBitsMax(RVVVectorBitsMax),
108 initializeSubtargetDependencies(TT, CPU, TuneCPU, FS, ABIName)),
109 InstrInfo(*this), RegInfo(getHwMode()), TLInfo(TM, *this) {
110TSInfo = std::make_unique<RISCVSelectionDAGInfo>();
151// Loading integer from constant pool needs two instructions (the reason why 152// the minimum cost is 2): an address calculation instruction and a load 153// instruction. Usually, address calculation and instructions used for 154// building integers (addi, slli, etc.) can be done in one cycle, so here we 155// set the default cost to (LoadLatency + 1) if no threshold is provided. 157 ? getSchedModel().LoadLatency + 1
163"Tried to get vector length without Zve or V extension support!");
165// ZvlLen specifies the minimum required vlen. The upper bound provided by 166// riscv-v-vector-bits-max should be no less than it. 167if (RVVVectorBitsMax != 0 && RVVVectorBitsMax < ZvlLen)
169"than the Zvl*b limitation");
171return RVVVectorBitsMax;
176"Tried to get vector length without Zve or V extension support!");
178if (RVVVectorBitsMin == -1U)
181// ZvlLen specifies the minimum required vlen. The lower bound provided by 182// riscv-v-vector-bits-min should be no less than it. 183if (RVVVectorBitsMin != 0 && RVVVectorBitsMin < ZvlLen)
185"than the Zvl*b limitation");
187return RVVVectorBitsMin;
192"Tried to get vector length without Zve or V extension support!");
195"V extension requires a LMUL to be at most 8 and a power of 2!");
207return getSchedModel().hasInstrSchedModel();
210 /// Enable use of alias analysis during code generation (during MI 211 /// scheduling, DAGCombine, etc.). 221unsigned NumRegionInstrs)
const{
222// Do bidirectional scheduling since it provides a more balanced scheduling 223// leading to better performance. This will increase compile time. 227// Disabling the latency heuristic can reduce the number of spills/reloads but 228// will cause some regressions on some cores. 231// Spilling is generally expensive on all RISC-V cores, so always enable 232// register-pressure tracking. This will increase compile time. 237unsigned NumRegionInstrs)
const{
static cl::opt< bool > UseAA("aarch64-use-aa", cl::init(true), cl::desc("Enable the use of AA during codegen."))
This file describes how to lower LLVM calls to machine code calls.
This file declares the targeting of the Machinelegalizer class for RISC-V.
static cl::opt< unsigned > RVVVectorLMULMax("riscv-v-fixed-length-vector-lmul-max", cl::desc("The maximum LMUL value to use for fixed length vectors. " "Fractional LMUL values are not supported."), cl::init(8), cl::Hidden)
static cl::opt< bool > UseAA("riscv-use-aa", cl::init(true), cl::desc("Enable the use of AA during codegen."))
static cl::opt< unsigned > RISCVMinimumJumpTableEntries("riscv-min-jump-table-entries", cl::Hidden, cl::desc("Set minimum number of entries to use a jump table on RISCV"))
static cl::opt< bool > UseMIPSLoadStorePairsOpt("mips-riscv-load-store-pairs", cl::desc("RISCV: Optimize for load-store bonding"), cl::init(false), cl::Hidden)
static cl::opt< bool > UseCCMovInsn("riscv-ccmov", cl::desc("RISCV: Use 'mips.ccmov' instruction"), cl::init(true), cl::Hidden)
static cl::opt< bool > RISCVDisableUsingConstantPoolForLargeInts("riscv-disable-using-constant-pool-for-large-ints", cl::desc("Disable using constant pool for large integers."), cl::init(false), cl::Hidden)
static cl::opt< unsigned > RISCVMaxBuildIntsCost("riscv-max-build-ints-cost", cl::desc("The maximum cost used for building integers."), cl::init(0), cl::Hidden)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This class provides the information for the target register banks.
unsigned getMinimumJumpTableEntries() const
const LegalizerInfo * getLegalizerInfo() const override
unsigned getMaxLMULForFixedLengthVectors() const
bool useRVVForFixedLengthVectors() const
MISched::Direction getPostRASchedDirection() const
unsigned getMinRVVVectorSizeInBits() const
std::unique_ptr< InstructionSelector > InstSelector
RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, StringRef ABIName, unsigned RVVVectorBitsMin, unsigned RVVVectorLMULMax, const TargetMachine &TM)
const RISCVRegisterBankInfo * getRegBankInfo() const override
void overridePostRASchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override
const CallLowering * getCallLowering() const override
InstructionSelector * getInstructionSelector() const override
unsigned getMaxBuildIntsCost() const
bool useCCMovInsn() const
void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override
std::unique_ptr< const SelectionDAGTargetInfo > TSInfo
bool hasVInstructions() const
bool useAA() const override
Enable use of alias analysis during code generation (during MI scheduling, DAGCombine,...
bool enableMachinePipeliner() const override
bool useConstantPoolForLargeInts() const
~RISCVSubtarget() override
unsigned getMaxRVVVectorSizeInBits() const
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
std::unique_ptr< RISCVRegisterBankInfo > RegBankInfo
std::unique_ptr< CallLowering > CallLoweringInfo
const RISCVTargetLowering * getTargetLowering() const override
bool enableSubRegLiveness() const override
const SelectionDAGTargetInfo * getSelectionDAGInfo() const override
Targets can subclass this to parameterize the SelectionDAG lowering and instruction selection process...
StringRef - Represent a constant reference to a string, i.e.
constexpr bool empty() const
empty - Check if the string is empty.
const TargetMachine & getTargetMachine() const
Primary interface to the complete machine description for the target machine.
Triple - Helper class for working with autoconf configuration names.
ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits, StringRef ABIName)
void validate(const Triple &TT, const FeatureBitset &FeatureBits)
static constexpr unsigned RVVBitsPerBlock
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
InstructionSelector * createRISCVInstructionSelector(const RISCVTargetMachine &TM, const RISCVSubtarget &Subtarget, const RISCVRegisterBankInfo &RBI)
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
T bit_floor(T Value)
Returns the largest integral power of two no greater than Value if Value is nonzero.
Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.
bool DisableLatencyHeuristic
unsigned MinimumJumpTableEntries
