1//=- RISCVMachineFunctionInfo.h - RISC-V machine function info ----*- C++ -*-=// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7//===----------------------------------------------------------------------===// 9// This file declares RISCV-specific per-machine-function information. 11//===----------------------------------------------------------------------===// 13#ifndef LLVM_LIB_TARGET_RISCV_RISCVMACHINEFUNCTIONINFO_H 14#define LLVM_LIB_TARGET_RISCV_RISCVMACHINEFUNCTIONINFO_H 23classRISCVMachineFunctionInfo;
45/// RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo 46/// and contains private RISCV-specific information for each MachineFunction. 49 /// FrameIndex for start of varargs area 50int VarArgsFrameIndex = 0;
51 /// Size of the save area used for varargs 52int VarArgsSaveSize = 0;
53 /// FrameIndex used for transferring values between 64-bit FPRs and a pair 54 /// of 32-bit GPRs via the stack. 55int MoveF64FrameIndex = -1;
56 /// FrameIndex of the spill slot for the scratch register in BranchRelaxation. 57int BranchRelaxationScratchFrameIndex = -1;
58 /// Size of any opaque stack adjustment due to save/restore libcalls. 59unsigned LibCallStackSize = 0;
60 /// Size of RVV stack. 62 /// Alignment of RVV stack. 64 /// Padding required to keep RVV stack aligned within the main stack. 66 /// Size of stack frame to save callee saved registers 67unsigned CalleeSavedStackSize = 0;
68 /// Is there any vector argument or return? 69bool IsVectorCall =
false;
71 /// Registers that have been sign extended from i32. 74 /// Size of stack frame for Zcmp PUSH/POP 75unsigned RVPushStackSize = 0;
76unsigned RVPushRegs = 0;
79 int64_t StackProbeSize = 0;
81 /// Does it probe the stack for a dynamic allocation? 82bool HasDynamicAllocation =
false;
99if (MoveF64FrameIndex == -1)
102return MoveF64FrameIndex;
106return BranchRelaxationScratchFrameIndex;
109 BranchRelaxationScratchFrameIndex =
Index;
113return LibCallStackSize + RVPushStackSize;
120// We cannot use fixed locations for the callee saved spill slots if the 121// function uses a varargs save area, or is an interrupt handler. 141// We cannot use fixed locations for the callee saved spill slots if the 142// function uses a varargs save area. 143// TODO: Use a separate placement for vararg registers to enable Zcmp. 146 VarArgsSaveSize == 0;
170}
// end namespace llvm 172#endif// LLVM_LIB_TARGET_RISCV_RISCVMACHINEFUNCTIONINFO_H Allocate memory in an ever growing pool, as if by bump-pointer.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
bool hasTailCall() const
Returns true if the function contains a tail call.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Function & getFunction()
Return the LLVM function that this machine code represents.
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo and contains private RISCV-...
void setLibCallStackSize(unsigned Size)
bool isPushable(const MachineFunction &MF) const
void initializeBaseYamlFields(const yaml::RISCVMachineFunctionInfo &YamlMFI)
bool hasDynamicAllocation() const
void setRVPushStackSize(unsigned Size)
bool isSExt32Register(Register Reg) const
int getRVPushRlist() const
MachineFunctionInfo * clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF, const DenseMap< MachineBasicBlock *, MachineBasicBlock * > &Src2DstMBB) const override
Make a functionally equivalent copy of this MachineFunctionInfo in MF.
void setCalleeSavedStackSize(unsigned Size)
void setRVVPadding(uint64_t Padding)
unsigned getLibCallStackSize() const
uint64_t getRVVPadding() const
void setVarArgsFrameIndex(int Index)
unsigned getRVPushStackSize() const
int getVarArgsFrameIndex() const
unsigned getReservedSpillsSize() const
void setBranchRelaxationScratchFrameIndex(int Index)
unsigned getRVPushRegs() const
bool isVectorCall() const
bool useSaveRestoreLibCalls(const MachineFunction &MF) const
void setRVVStackSize(uint64_t Size)
uint64_t getRVVStackSize() const
void setVarArgsSaveSize(int Size)
Align getRVVStackAlign() const
int getBranchRelaxationScratchFrameIndex() const
unsigned getVarArgsSaveSize() const
void setRVPushRlist(int Rlist)
void setDynamicAllocation()
int getMoveF64FrameIndex(MachineFunction &MF)
void setRVVStackAlign(Align StackAlign)
unsigned getCalleeSavedStackSize() const
void addSExt32Register(Register Reg)
void setRVPushRegs(unsigned Regs)
Wrapper class representing virtual and physical registers.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
This is an optimization pass for GlobalISel generic memory operations.
This struct is a compact representation of a valid (non-zero power of two) alignment.
MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...
Targets should override this in a way that mirrors the implementation of llvm::MachineFunctionInfo.
static void mapping(IO &YamlIO, RISCVMachineFunctionInfo &MFI)
void mappingImpl(yaml::IO &YamlIO) override
RISCVMachineFunctionInfo()=default
~RISCVMachineFunctionInfo()=default
