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LLVM 20.0.0git
RISCVMCCodeEmitter.cpp
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1//===-- RISCVMCCodeEmitter.cpp - Convert RISC-V code to machine code ------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the RISCVMCCodeEmitter class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "MCTargetDesc/RISCVBaseInfo.h"
14#include "MCTargetDesc/RISCVFixupKinds.h"
15#include "MCTargetDesc/RISCVMCExpr.h"
16#include "MCTargetDesc/RISCVMCTargetDesc.h"
17#include "llvm/ADT/Statistic.h"
18#include "llvm/MC/MCAsmInfo.h"
19#include "llvm/MC/MCCodeEmitter.h"
20#include "llvm/MC/MCContext.h"
21#include "llvm/MC/MCExpr.h"
22#include "llvm/MC/MCInst.h"
23#include "llvm/MC/MCInstBuilder.h"
24#include "llvm/MC/MCInstrInfo.h"
25#include "llvm/MC/MCRegisterInfo.h"
26#include "llvm/MC/MCSubtargetInfo.h"
27#include "llvm/MC/MCSymbol.h"
28#include "llvm/Support/Casting.h"
29#include "llvm/Support/EndianStream.h"
30
31using namespacellvm;
32
33#define DEBUG_TYPE "mccodeemitter"
34
35STATISTIC(MCNumEmitted,"Number of MC instructions emitted");
36STATISTIC(MCNumFixups,"Number of MC fixups created");
37
38namespace{
39classRISCVMCCodeEmitter :publicMCCodeEmitter {
40 RISCVMCCodeEmitter(const RISCVMCCodeEmitter &) =delete;
41voidoperator=(const RISCVMCCodeEmitter &) =delete;
42MCContext &Ctx;
43MCInstrInfoconst &MCII;
44
45public:
46 RISCVMCCodeEmitter(MCContext &ctx,MCInstrInfoconst &MCII)
47 : Ctx(ctx), MCII(MCII) {}
48
49 ~RISCVMCCodeEmitter()override =default;
50
51voidencodeInstruction(constMCInst &MI,SmallVectorImpl<char> &CB,
52SmallVectorImpl<MCFixup> &Fixups,
53constMCSubtargetInfo &STI)const override;
54
55void expandFunctionCall(constMCInst &MI,SmallVectorImpl<char> &CB,
56SmallVectorImpl<MCFixup> &Fixups,
57constMCSubtargetInfo &STI)const;
58
59void expandTLSDESCCall(constMCInst &MI,SmallVectorImpl<char> &CB,
60SmallVectorImpl<MCFixup> &Fixups,
61constMCSubtargetInfo &STI)const;
62
63void expandAddTPRel(constMCInst &MI,SmallVectorImpl<char> &CB,
64SmallVectorImpl<MCFixup> &Fixups,
65constMCSubtargetInfo &STI)const;
66
67void expandLongCondBr(constMCInst &MI,SmallVectorImpl<char> &CB,
68SmallVectorImpl<MCFixup> &Fixups,
69constMCSubtargetInfo &STI)const;
70
71 /// TableGen'erated function for getting the binary encoding for an
72 /// instruction.
73uint64_t getBinaryCodeForInstr(constMCInst &MI,
74SmallVectorImpl<MCFixup> &Fixups,
75constMCSubtargetInfo &STI)const;
76
77 /// Return binary encoding of operand. If the machine operand requires
78 /// relocation, record the relocation and return zero.
79uint64_t getMachineOpValue(constMCInst &MI,constMCOperand &MO,
80SmallVectorImpl<MCFixup> &Fixups,
81constMCSubtargetInfo &STI)const;
82
83uint64_t getImmOpValueAsr1(constMCInst &MI,unsigned OpNo,
84SmallVectorImpl<MCFixup> &Fixups,
85constMCSubtargetInfo &STI)const;
86
87uint64_t getImmOpValue(constMCInst &MI,unsigned OpNo,
88SmallVectorImpl<MCFixup> &Fixups,
89constMCSubtargetInfo &STI)const;
90
91unsigned getVMaskReg(constMCInst &MI,unsigned OpNo,
92SmallVectorImpl<MCFixup> &Fixups,
93constMCSubtargetInfo &STI)const;
94
95unsigned getRlistOpValue(constMCInst &MI,unsigned OpNo,
96SmallVectorImpl<MCFixup> &Fixups,
97constMCSubtargetInfo &STI)const;
98
99unsigned getRegReg(constMCInst &MI,unsigned OpNo,
100SmallVectorImpl<MCFixup> &Fixups,
101constMCSubtargetInfo &STI)const;
102};
103}// end anonymous namespace
104
105MCCodeEmitter *llvm::createRISCVMCCodeEmitter(constMCInstrInfo &MCII,
106MCContext &Ctx) {
107returnnew RISCVMCCodeEmitter(Ctx, MCII);
108}
109
110// Expand PseudoCALL(Reg), PseudoTAIL and PseudoJump to AUIPC and JALR with
111// relocation types. We expand those pseudo-instructions while encoding them,
112// meaning AUIPC and JALR won't go through RISC-V MC to MC compressed
113// instruction transformation. This is acceptable because AUIPC has no 16-bit
114// form and C_JALR has no immediate operand field. We let linker relaxation
115// deal with it. When linker relaxation is enabled, AUIPC and JALR have a
116// chance to relax to JAL.
117// If the C extension is enabled, JAL has a chance relax to C_JAL.
118void RISCVMCCodeEmitter::expandFunctionCall(constMCInst &MI,
119SmallVectorImpl<char> &CB,
120SmallVectorImpl<MCFixup> &Fixups,
121constMCSubtargetInfo &STI) const{
122MCInst TmpInst;
123MCOperand Func;
124MCRegister Ra;
125if (MI.getOpcode() == RISCV::PseudoTAIL) {
126 Func =MI.getOperand(0);
127 Ra =RISCVII::getTailExpandUseRegNo(STI.getFeatureBits());
128 }elseif (MI.getOpcode() == RISCV::PseudoCALLReg) {
129Func =MI.getOperand(1);
130 Ra =MI.getOperand(0).getReg();
131 }elseif (MI.getOpcode() == RISCV::PseudoCALL) {
132Func =MI.getOperand(0);
133 Ra = RISCV::X1;
134 }elseif (MI.getOpcode() == RISCV::PseudoJump) {
135Func =MI.getOperand(1);
136 Ra =MI.getOperand(0).getReg();
137 }
138uint32_tBinary;
139
140assert(Func.isExpr() &&"Expected expression");
141
142constMCExpr *CallExpr =Func.getExpr();
143
144// Emit AUIPC Ra, Func with R_RISCV_CALL relocation type.
145 TmpInst =MCInstBuilder(RISCV::AUIPC).addReg(Ra).addExpr(CallExpr);
146Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
147support::endian::write(CB, Binary,llvm::endianness::little);
148
149if (MI.getOpcode() == RISCV::PseudoTAIL ||
150MI.getOpcode() == RISCV::PseudoJump)
151// Emit JALR X0, Ra, 0
152 TmpInst =MCInstBuilder(RISCV::JALR).addReg(RISCV::X0).addReg(Ra).addImm(0);
153else
154// Emit JALR Ra, Ra, 0
155 TmpInst =MCInstBuilder(RISCV::JALR).addReg(Ra).addReg(Ra).addImm(0);
156Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
157support::endian::write(CB, Binary,llvm::endianness::little);
158}
159
160void RISCVMCCodeEmitter::expandTLSDESCCall(constMCInst &MI,
161SmallVectorImpl<char> &CB,
162SmallVectorImpl<MCFixup> &Fixups,
163constMCSubtargetInfo &STI) const{
164MCOperand SrcSymbol =MI.getOperand(3);
165assert(SrcSymbol.isExpr() &&
166"Expected expression as first input to TLSDESCCALL");
167constRISCVMCExpr *Expr = dyn_cast<RISCVMCExpr>(SrcSymbol.getExpr());
168MCRegisterLink =MI.getOperand(0).getReg();
169MCRegister Dest =MI.getOperand(1).getReg();
170 int64_tImm =MI.getOperand(2).getImm();
171Fixups.push_back(MCFixup::create(
172 0, Expr,MCFixupKind(RISCV::fixup_riscv_tlsdesc_call),MI.getLoc()));
173MCInstCall =
174MCInstBuilder(RISCV::JALR).addReg(Link).addReg(Dest).addImm(Imm);
175
176uint32_tBinary = getBinaryCodeForInstr(Call, Fixups, STI);
177support::endian::write(CB, Binary,llvm::endianness::little);
178}
179
180// Expand PseudoAddTPRel to a simple ADD with the correct relocation.
181void RISCVMCCodeEmitter::expandAddTPRel(constMCInst &MI,
182SmallVectorImpl<char> &CB,
183SmallVectorImpl<MCFixup> &Fixups,
184constMCSubtargetInfo &STI) const{
185MCOperand DestReg =MI.getOperand(0);
186MCOperand SrcReg =MI.getOperand(1);
187MCOperand TPReg =MI.getOperand(2);
188assert(TPReg.isReg() && TPReg.getReg() == RISCV::X4 &&
189"Expected thread pointer as second input to TP-relative add");
190
191MCOperand SrcSymbol =MI.getOperand(3);
192assert(SrcSymbol.isExpr() &&
193"Expected expression as third input to TP-relative add");
194
195constRISCVMCExpr *Expr = dyn_cast<RISCVMCExpr>(SrcSymbol.getExpr());
196assert(Expr && Expr->getKind() ==RISCVMCExpr::VK_RISCV_TPREL_ADD &&
197"Expected tprel_add relocation on TP-relative symbol");
198
199// Emit the correct tprel_add relocation for the symbol.
200Fixups.push_back(MCFixup::create(
201 0, Expr,MCFixupKind(RISCV::fixup_riscv_tprel_add),MI.getLoc()));
202
203// Emit fixup_riscv_relax for tprel_add where the relax feature is enabled.
204if (STI.hasFeature(RISCV::FeatureRelax)) {
205constMCConstantExpr *Dummy =MCConstantExpr::create(0, Ctx);
206Fixups.push_back(MCFixup::create(
207 0, Dummy,MCFixupKind(RISCV::fixup_riscv_relax),MI.getLoc()));
208 }
209
210// Emit a normal ADD instruction with the given operands.
211MCInst TmpInst =MCInstBuilder(RISCV::ADD)
212 .addOperand(DestReg)
213 .addOperand(SrcReg)
214 .addOperand(TPReg);
215uint32_tBinary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
216support::endian::write(CB, Binary,llvm::endianness::little);
217}
218
219staticunsignedgetInvertedBranchOp(unsigned BrOp) {
220switch (BrOp) {
221default:
222llvm_unreachable("Unexpected branch opcode!");
223case RISCV::PseudoLongBEQ:
224return RISCV::BNE;
225case RISCV::PseudoLongBNE:
226return RISCV::BEQ;
227case RISCV::PseudoLongBLT:
228return RISCV::BGE;
229case RISCV::PseudoLongBGE:
230return RISCV::BLT;
231case RISCV::PseudoLongBLTU:
232return RISCV::BGEU;
233case RISCV::PseudoLongBGEU:
234return RISCV::BLTU;
235 }
236}
237
238// Expand PseudoLongBxx to an inverted conditional branch and an unconditional
239// jump.
240void RISCVMCCodeEmitter::expandLongCondBr(constMCInst &MI,
241SmallVectorImpl<char> &CB,
242SmallVectorImpl<MCFixup> &Fixups,
243constMCSubtargetInfo &STI) const{
244MCRegister SrcReg1 =MI.getOperand(0).getReg();
245MCRegister SrcReg2 =MI.getOperand(1).getReg();
246MCOperand SrcSymbol =MI.getOperand(2);
247unsigned Opcode =MI.getOpcode();
248bool IsEqTest =
249 Opcode == RISCV::PseudoLongBNE || Opcode == RISCV::PseudoLongBEQ;
250
251bool UseCompressedBr =false;
252if (IsEqTest && (STI.hasFeature(RISCV::FeatureStdExtC) ||
253 STI.hasFeature(RISCV::FeatureStdExtZca))) {
254if (RISCV::X8 <= SrcReg1.id() && SrcReg1.id() <= RISCV::X15 &&
255 SrcReg2.id() == RISCV::X0) {
256 UseCompressedBr =true;
257 }elseif (RISCV::X8 <= SrcReg2.id() && SrcReg2.id() <= RISCV::X15 &&
258 SrcReg1.id() == RISCV::X0) {
259std::swap(SrcReg1, SrcReg2);
260 UseCompressedBr =true;
261 }
262 }
263
264uint32_tOffset;
265if (UseCompressedBr) {
266unsigned InvOpc =
267 Opcode == RISCV::PseudoLongBNE ? RISCV::C_BEQZ : RISCV::C_BNEZ;
268MCInst TmpInst =MCInstBuilder(InvOpc).addReg(SrcReg1).addImm(6);
269uint16_tBinary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
270 support::endian::write<uint16_t>(CB, Binary,llvm::endianness::little);
271Offset = 2;
272 }else {
273unsigned InvOpc =getInvertedBranchOp(Opcode);
274MCInst TmpInst =
275MCInstBuilder(InvOpc).addReg(SrcReg1).addReg(SrcReg2).addImm(8);
276uint32_tBinary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
277support::endian::write(CB, Binary,llvm::endianness::little);
278Offset = 4;
279 }
280
281// Save the number fixups.
282size_t FixupStartIndex =Fixups.size();
283
284// Emit an unconditional jump to the destination.
285MCInst TmpInst =
286MCInstBuilder(RISCV::JAL).addReg(RISCV::X0).addOperand(SrcSymbol);
287uint32_tBinary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
288support::endian::write(CB, Binary,llvm::endianness::little);
289
290// Drop any fixup added so we can add the correct one.
291Fixups.resize(FixupStartIndex);
292
293if (SrcSymbol.isExpr()) {
294Fixups.push_back(MCFixup::create(Offset, SrcSymbol.getExpr(),
295MCFixupKind(RISCV::fixup_riscv_jal),
296MI.getLoc()));
297 }
298}
299
300void RISCVMCCodeEmitter::encodeInstruction(constMCInst &MI,
301SmallVectorImpl<char> &CB,
302SmallVectorImpl<MCFixup> &Fixups,
303constMCSubtargetInfo &STI) const{
304constMCInstrDesc &Desc = MCII.get(MI.getOpcode());
305// Get byte count of instruction.
306unsignedSize =Desc.getSize();
307
308// RISCVInstrInfo::getInstSizeInBytes expects that the total size of the
309// expanded instructions for each pseudo is correct in the Size field of the
310// tablegen definition for the pseudo.
311switch (MI.getOpcode()) {
312default:
313break;
314case RISCV::PseudoCALLReg:
315case RISCV::PseudoCALL:
316case RISCV::PseudoTAIL:
317case RISCV::PseudoJump:
318 expandFunctionCall(MI, CB, Fixups, STI);
319 MCNumEmitted += 2;
320return;
321case RISCV::PseudoAddTPRel:
322 expandAddTPRel(MI, CB, Fixups, STI);
323 MCNumEmitted += 1;
324return;
325case RISCV::PseudoLongBEQ:
326case RISCV::PseudoLongBNE:
327case RISCV::PseudoLongBLT:
328case RISCV::PseudoLongBGE:
329case RISCV::PseudoLongBLTU:
330case RISCV::PseudoLongBGEU:
331 expandLongCondBr(MI, CB, Fixups, STI);
332 MCNumEmitted += 2;
333return;
334case RISCV::PseudoTLSDESCCall:
335 expandTLSDESCCall(MI, CB, Fixups, STI);
336 MCNumEmitted += 1;
337return;
338 }
339
340switch (Size) {
341default:
342llvm_unreachable("Unhandled encodeInstruction length!");
343case 2: {
344uint16_tBits = getBinaryCodeForInstr(MI, Fixups, STI);
345 support::endian::write<uint16_t>(CB, Bits,llvm::endianness::little);
346break;
347 }
348case 4: {
349uint32_tBits = getBinaryCodeForInstr(MI, Fixups, STI);
350support::endian::write(CB, Bits,llvm::endianness::little);
351break;
352 }
353case 6: {
354uint64_tBits = getBinaryCodeForInstr(MI, Fixups, STI) & 0xffff'ffff'ffffu;
355SmallVector<char, 8> Encoding;
356support::endian::write(Encoding, Bits,llvm::endianness::little);
357assert(Encoding[6] == 0 && Encoding[7] == 0 &&
358"Unexpected encoding for 48-bit instruction");
359 Encoding.truncate(6);
360 CB.append(Encoding);
361break;
362 }
363case 8: {
364uint64_tBits = getBinaryCodeForInstr(MI, Fixups, STI);
365support::endian::write(CB, Bits,llvm::endianness::little);
366break;
367 }
368 }
369
370 ++MCNumEmitted;// Keep track of the # of mi's emitted.
371}
372
373uint64_t
374RISCVMCCodeEmitter::getMachineOpValue(constMCInst &MI,constMCOperand &MO,
375SmallVectorImpl<MCFixup> &Fixups,
376constMCSubtargetInfo &STI) const{
377
378if (MO.isReg())
379return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
380
381if (MO.isImm())
382return MO.getImm();
383
384llvm_unreachable("Unhandled expression!");
385return 0;
386}
387
388uint64_t
389RISCVMCCodeEmitter::getImmOpValueAsr1(constMCInst &MI,unsigned OpNo,
390SmallVectorImpl<MCFixup> &Fixups,
391constMCSubtargetInfo &STI) const{
392constMCOperand &MO =MI.getOperand(OpNo);
393
394if (MO.isImm()) {
395uint64_t Res = MO.getImm();
396assert((Res & 1) == 0 &&"LSB is non-zero");
397return Res >> 1;
398 }
399
400return getImmOpValue(MI, OpNo, Fixups, STI);
401}
402
403uint64_t RISCVMCCodeEmitter::getImmOpValue(constMCInst &MI,unsigned OpNo,
404SmallVectorImpl<MCFixup> &Fixups,
405constMCSubtargetInfo &STI) const{
406bool EnableRelax = STI.hasFeature(RISCV::FeatureRelax);
407constMCOperand &MO =MI.getOperand(OpNo);
408
409MCInstrDescconst &Desc = MCII.get(MI.getOpcode());
410unsigned MIFrm =RISCVII::getFormat(Desc.TSFlags);
411
412// If the destination is an immediate, there is nothing to do.
413if (MO.isImm())
414return MO.getImm();
415
416assert(MO.isExpr() &&
417"getImmOpValue expects only expressions or immediates");
418constMCExpr *Expr = MO.getExpr();
419MCExpr::ExprKindKind = Expr->getKind();
420RISCV::FixupsFixupKind =RISCV::fixup_riscv_invalid;
421bool RelaxCandidate =false;
422if (Kind ==MCExpr::Target) {
423constRISCVMCExpr *RVExpr = cast<RISCVMCExpr>(Expr);
424
425switch (RVExpr->getKind()) {
426caseRISCVMCExpr::VK_RISCV_None:
427caseRISCVMCExpr::VK_RISCV_Invalid:
428caseRISCVMCExpr::VK_RISCV_32_PCREL:
429llvm_unreachable("Unhandled fixup kind!");
430caseRISCVMCExpr::VK_RISCV_TPREL_ADD:
431// tprel_add is only used to indicate that a relocation should be emitted
432// for an add instruction used in TP-relative addressing. It should not be
433// expanded as if representing an actual instruction operand and so to
434// encounter it here is an error.
435llvm_unreachable(
436"VK_RISCV_TPREL_ADD should not represent an instruction operand");
437caseRISCVMCExpr::VK_RISCV_LO:
438if (MIFrm ==RISCVII::InstFormatI)
439FixupKind =RISCV::fixup_riscv_lo12_i;
440elseif (MIFrm ==RISCVII::InstFormatS)
441FixupKind =RISCV::fixup_riscv_lo12_s;
442else
443llvm_unreachable("VK_RISCV_LO used with unexpected instruction format");
444 RelaxCandidate =true;
445break;
446caseRISCVMCExpr::VK_RISCV_HI:
447FixupKind =RISCV::fixup_riscv_hi20;
448 RelaxCandidate =true;
449break;
450caseRISCVMCExpr::VK_RISCV_PCREL_LO:
451if (MIFrm ==RISCVII::InstFormatI)
452FixupKind =RISCV::fixup_riscv_pcrel_lo12_i;
453elseif (MIFrm ==RISCVII::InstFormatS)
454FixupKind =RISCV::fixup_riscv_pcrel_lo12_s;
455else
456llvm_unreachable(
457"VK_RISCV_PCREL_LO used with unexpected instruction format");
458 RelaxCandidate =true;
459break;
460caseRISCVMCExpr::VK_RISCV_PCREL_HI:
461FixupKind =RISCV::fixup_riscv_pcrel_hi20;
462 RelaxCandidate =true;
463break;
464caseRISCVMCExpr::VK_RISCV_GOT_HI:
465FixupKind =RISCV::fixup_riscv_got_hi20;
466break;
467caseRISCVMCExpr::VK_RISCV_TPREL_LO:
468if (MIFrm ==RISCVII::InstFormatI)
469FixupKind =RISCV::fixup_riscv_tprel_lo12_i;
470elseif (MIFrm ==RISCVII::InstFormatS)
471FixupKind =RISCV::fixup_riscv_tprel_lo12_s;
472else
473llvm_unreachable(
474"VK_RISCV_TPREL_LO used with unexpected instruction format");
475 RelaxCandidate =true;
476break;
477caseRISCVMCExpr::VK_RISCV_TPREL_HI:
478FixupKind =RISCV::fixup_riscv_tprel_hi20;
479 RelaxCandidate =true;
480break;
481caseRISCVMCExpr::VK_RISCV_TLS_GOT_HI:
482FixupKind =RISCV::fixup_riscv_tls_got_hi20;
483break;
484caseRISCVMCExpr::VK_RISCV_TLS_GD_HI:
485FixupKind =RISCV::fixup_riscv_tls_gd_hi20;
486break;
487caseRISCVMCExpr::VK_RISCV_CALL:
488FixupKind =RISCV::fixup_riscv_call;
489 RelaxCandidate =true;
490break;
491caseRISCVMCExpr::VK_RISCV_CALL_PLT:
492FixupKind =RISCV::fixup_riscv_call_plt;
493 RelaxCandidate =true;
494break;
495caseRISCVMCExpr::VK_RISCV_TLSDESC_HI:
496FixupKind =RISCV::fixup_riscv_tlsdesc_hi20;
497break;
498caseRISCVMCExpr::VK_RISCV_TLSDESC_LOAD_LO:
499FixupKind =RISCV::fixup_riscv_tlsdesc_load_lo12;
500break;
501caseRISCVMCExpr::VK_RISCV_TLSDESC_ADD_LO:
502FixupKind =RISCV::fixup_riscv_tlsdesc_add_lo12;
503break;
504caseRISCVMCExpr::VK_RISCV_TLSDESC_CALL:
505FixupKind =RISCV::fixup_riscv_tlsdesc_call;
506break;
507 }
508 }elseif ((Kind ==MCExpr::SymbolRef &&
509 cast<MCSymbolRefExpr>(Expr)->getKind() ==
510MCSymbolRefExpr::VK_None) ||
511 Kind ==MCExpr::Binary) {
512// FIXME: Sub kind binary exprs have chance of underflow.
513if (MIFrm ==RISCVII::InstFormatJ) {
514FixupKind =RISCV::fixup_riscv_jal;
515 }elseif (MIFrm ==RISCVII::InstFormatB) {
516FixupKind =RISCV::fixup_riscv_branch;
517 }elseif (MIFrm ==RISCVII::InstFormatCJ) {
518FixupKind =RISCV::fixup_riscv_rvc_jump;
519 }elseif (MIFrm ==RISCVII::InstFormatCB) {
520FixupKind =RISCV::fixup_riscv_rvc_branch;
521 }elseif (MIFrm ==RISCVII::InstFormatI) {
522FixupKind =RISCV::fixup_riscv_12_i;
523 }
524 }
525
526assert(FixupKind !=RISCV::fixup_riscv_invalid &&"Unhandled expression!");
527
528Fixups.push_back(
529MCFixup::create(0, Expr,MCFixupKind(FixupKind),MI.getLoc()));
530 ++MCNumFixups;
531
532// Ensure an R_RISCV_RELAX relocation will be emitted if linker relaxation is
533// enabled and the current fixup will result in a relocation that may be
534// relaxed.
535if (EnableRelax && RelaxCandidate) {
536constMCConstantExpr *Dummy =MCConstantExpr::create(0, Ctx);
537Fixups.push_back(
538MCFixup::create(0, Dummy,MCFixupKind(RISCV::fixup_riscv_relax),
539MI.getLoc()));
540 ++MCNumFixups;
541 }
542
543return 0;
544}
545
546unsigned RISCVMCCodeEmitter::getVMaskReg(constMCInst &MI,unsigned OpNo,
547SmallVectorImpl<MCFixup> &Fixups,
548constMCSubtargetInfo &STI) const{
549MCOperand MO =MI.getOperand(OpNo);
550assert(MO.isReg() &&"Expected a register.");
551
552switch (MO.getReg()) {
553default:
554llvm_unreachable("Invalid mask register.");
555case RISCV::V0:
556return 0;
557case RISCV::NoRegister:
558return 1;
559 }
560}
561
562unsigned RISCVMCCodeEmitter::getRlistOpValue(constMCInst &MI,unsigned OpNo,
563SmallVectorImpl<MCFixup> &Fixups,
564constMCSubtargetInfo &STI) const{
565constMCOperand &MO =MI.getOperand(OpNo);
566assert(MO.isImm() &&"Rlist operand must be immediate");
567autoImm = MO.getImm();
568assert(Imm >= 4 &&"EABI is currently not implemented");
569returnImm;
570}
571
572unsigned RISCVMCCodeEmitter::getRegReg(constMCInst &MI,unsigned OpNo,
573SmallVectorImpl<MCFixup> &Fixups,
574constMCSubtargetInfo &STI) const{
575constMCOperand &MO =MI.getOperand(OpNo);
576constMCOperand &MO1 =MI.getOperand(OpNo + 1);
577assert(MO.isReg() && MO1.isReg() &&"Expected registers.");
578
579unsignedOp = Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
580unsigned Op1 = Ctx.getRegisterInfo()->getEncodingValue(MO1.getReg());
581
582returnOp | Op1 << 5;
583}
584
585#include "RISCVGenMCCodeEmitter.inc"
Casting.h
Size
uint64_t Size
Definition:ELFObjHandler.cpp:81
EndianStream.h
MI
IRTranslator LLVM IR MI
Definition:IRTranslator.cpp:112
MCAsmInfo.h
MCCodeEmitter.h
MCContext.h
MCExpr.h
MCInstBuilder.h
MCInst.h
MCInstrInfo.h
MCRegisterInfo.h
MCSubtargetInfo.h
MCSymbol.h
RISCVBaseInfo.h
RISCVFixupKinds.h
getInvertedBranchOp
static unsigned getInvertedBranchOp(unsigned BrOp)
Definition:RISCVMCCodeEmitter.cpp:219
RISCVMCExpr.h
RISCVMCTargetDesc.h
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Statistic.h
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
STATISTIC
#define STATISTIC(VARNAME, DESC)
Definition:Statistic.h:166
CallExpr
Definition:ItaniumDemangle.h:2077
llvm::DWARFExpression::Operation
This class represents an Operation in the Expression.
Definition:DWARFExpression.h:32
llvm::MCCodeEmitter
MCCodeEmitter - Generic instruction encoding interface.
Definition:MCCodeEmitter.h:21
llvm::MCCodeEmitter::encodeInstruction
virtual void encodeInstruction(const MCInst &Inst, SmallVectorImpl< char > &CB, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const =0
Encode the given Inst to bytes and append to CB.
llvm::MCCodeEmitter::operator=
MCCodeEmitter & operator=(const MCCodeEmitter &)=delete
llvm::MCConstantExpr
Definition:MCExpr.h:144
llvm::MCConstantExpr::create
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Definition:MCExpr.cpp:222
llvm::MCContext
Context object for machine code objects.
Definition:MCContext.h:83
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition:MCExpr.h:34
llvm::MCExpr::ExprKind
ExprKind
Definition:MCExpr.h:36
llvm::MCExpr::SymbolRef
@ SymbolRef
References to labels and assigned expressions.
Definition:MCExpr.h:39
llvm::MCExpr::Target
@ Target
Target specific expression.
Definition:MCExpr.h:41
llvm::MCExpr::Binary
@ Binary
Binary expressions.
Definition:MCExpr.h:37
llvm::MCExpr::getKind
ExprKind getKind() const
Definition:MCExpr.h:78
llvm::MCFixup::create
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Definition:MCFixup.h:87
llvm::MCInstBuilder
Definition:MCInstBuilder.h:21
llvm::MCInstBuilder::addReg
MCInstBuilder & addReg(MCRegister Reg)
Add a new register operand.
Definition:MCInstBuilder.h:37
llvm::MCInstBuilder::addOperand
MCInstBuilder & addOperand(const MCOperand &Op)
Add an operand.
Definition:MCInstBuilder.h:73
llvm::MCInstBuilder::addImm
MCInstBuilder & addImm(int64_t Val)
Add a new integer immediate operand.
Definition:MCInstBuilder.h:43
llvm::MCInstBuilder::addExpr
MCInstBuilder & addExpr(const MCExpr *Val)
Add a new MCExpr operand.
Definition:MCInstBuilder.h:61
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition:MCInst.h:185
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition:MCInstrDesc.h:198
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition:MCInstrInfo.h:26
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition:MCInst.h:37
llvm::MCOperand::getImm
int64_t getImm() const
Definition:MCInst.h:81
llvm::MCOperand::isImm
bool isImm() const
Definition:MCInst.h:63
llvm::MCOperand::isReg
bool isReg() const
Definition:MCInst.h:62
llvm::MCOperand::getReg
MCRegister getReg() const
Returns the register number.
Definition:MCInst.h:70
llvm::MCOperand::getExpr
const MCExpr * getExpr() const
Definition:MCInst.h:115
llvm::MCOperand::isExpr
bool isExpr() const
Definition:MCInst.h:66
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition:MCRegister.h:33
llvm::MCRegister::id
constexpr unsigned id() const
Definition:MCRegister.h:83
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition:MCSubtargetInfo.h:76
llvm::MCSubtargetInfo::hasFeature
bool hasFeature(unsigned Feature) const
Definition:MCSubtargetInfo.h:121
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition:MCSubtargetInfo.h:114
llvm::MCSymbolRefExpr::VK_None
@ VK_None
Definition:MCExpr.h:195
llvm::RISCVMCExpr
Definition:RISCVMCExpr.h:23
llvm::RISCVMCExpr::getKind
VariantKind getKind() const
Definition:RISCVMCExpr.h:60
llvm::RISCVMCExpr::VK_RISCV_None
@ VK_RISCV_None
Definition:RISCVMCExpr.h:26
llvm::RISCVMCExpr::VK_RISCV_TLS_GOT_HI
@ VK_RISCV_TLS_GOT_HI
Definition:RISCVMCExpr.h:35
llvm::RISCVMCExpr::VK_RISCV_TPREL_LO
@ VK_RISCV_TPREL_LO
Definition:RISCVMCExpr.h:32
llvm::RISCVMCExpr::VK_RISCV_TPREL_HI
@ VK_RISCV_TPREL_HI
Definition:RISCVMCExpr.h:33
llvm::RISCVMCExpr::VK_RISCV_PCREL_HI
@ VK_RISCV_PCREL_HI
Definition:RISCVMCExpr.h:30
llvm::RISCVMCExpr::VK_RISCV_LO
@ VK_RISCV_LO
Definition:RISCVMCExpr.h:27
llvm::RISCVMCExpr::VK_RISCV_PCREL_LO
@ VK_RISCV_PCREL_LO
Definition:RISCVMCExpr.h:29
llvm::RISCVMCExpr::VK_RISCV_TLSDESC_ADD_LO
@ VK_RISCV_TLSDESC_ADD_LO
Definition:RISCVMCExpr.h:42
llvm::RISCVMCExpr::VK_RISCV_TLSDESC_LOAD_LO
@ VK_RISCV_TLSDESC_LOAD_LO
Definition:RISCVMCExpr.h:41
llvm::RISCVMCExpr::VK_RISCV_32_PCREL
@ VK_RISCV_32_PCREL
Definition:RISCVMCExpr.h:39
llvm::RISCVMCExpr::VK_RISCV_TLS_GD_HI
@ VK_RISCV_TLS_GD_HI
Definition:RISCVMCExpr.h:36
llvm::RISCVMCExpr::VK_RISCV_CALL_PLT
@ VK_RISCV_CALL_PLT
Definition:RISCVMCExpr.h:38
llvm::RISCVMCExpr::VK_RISCV_TPREL_ADD
@ VK_RISCV_TPREL_ADD
Definition:RISCVMCExpr.h:34
llvm::RISCVMCExpr::VK_RISCV_CALL
@ VK_RISCV_CALL
Definition:RISCVMCExpr.h:37
llvm::RISCVMCExpr::VK_RISCV_TLSDESC_HI
@ VK_RISCV_TLSDESC_HI
Definition:RISCVMCExpr.h:40
llvm::RISCVMCExpr::VK_RISCV_HI
@ VK_RISCV_HI
Definition:RISCVMCExpr.h:28
llvm::RISCVMCExpr::VK_RISCV_Invalid
@ VK_RISCV_Invalid
Definition:RISCVMCExpr.h:44
llvm::RISCVMCExpr::VK_RISCV_TLSDESC_CALL
@ VK_RISCV_TLSDESC_CALL
Definition:RISCVMCExpr.h:43
llvm::RISCVMCExpr::VK_RISCV_GOT_HI
@ VK_RISCV_GOT_HI
Definition:RISCVMCExpr.h:31
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition:SmallVector.h:573
llvm::SmallVectorImpl::append
void append(ItTy in_start, ItTy in_end)
Add the specified range to the end of the SmallVector.
Definition:SmallVector.h:683
llvm::SmallVectorImpl::truncate
void truncate(size_type N)
Like resize, but requires that N is less than size().
Definition:SmallVector.h:644
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition:SmallVector.h:1196
uint16_t
uint32_t
uint64_t
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition:ErrorHandling.h:143
llvm::AArch64::Fixups
Fixups
Definition:AArch64FixupKinds.h:17
llvm::AMDGPU::Imm
@ Imm
Definition:AMDGPURegBankLegalizeRules.h:105
llvm::BPF::FixupKind
FixupKind
Definition:BPFMCFixups.h:16
llvm::MCID::Call
@ Call
Definition:MCInstrDesc.h:156
llvm::NVPTXISD::Dummy
@ Dummy
Definition:NVPTXISelLowering.h:70
llvm::RISCVII::getFormat
static unsigned getFormat(uint64_t TSFlags)
Definition:RISCVBaseInfo.h:144
llvm::RISCVII::InstFormatCB
@ InstFormatCB
Definition:RISCVBaseInfo.h:47
llvm::RISCVII::InstFormatS
@ InstFormatS
Definition:RISCVBaseInfo.h:36
llvm::RISCVII::InstFormatJ
@ InstFormatJ
Definition:RISCVBaseInfo.h:39
llvm::RISCVII::InstFormatI
@ InstFormatI
Definition:RISCVBaseInfo.h:35
llvm::RISCVII::InstFormatCJ
@ InstFormatCJ
Definition:RISCVBaseInfo.h:48
llvm::RISCVII::InstFormatB
@ InstFormatB
Definition:RISCVBaseInfo.h:37
llvm::RISCVII::getTailExpandUseRegNo
static unsigned getTailExpandUseRegNo(const FeatureBitset &FeatureBits)
Definition:RISCVBaseInfo.h:211
llvm::RISCV::Fixups
Fixups
Definition:RISCVFixupKinds.h:19
llvm::RISCV::fixup_riscv_invalid
@ fixup_riscv_invalid
Definition:RISCVFixupKinds.h:82
llvm::RISCV::fixup_riscv_tprel_lo12_s
@ fixup_riscv_tprel_lo12_s
Definition:RISCVFixupKinds.h:44
llvm::RISCV::fixup_riscv_tls_got_hi20
@ fixup_riscv_tls_got_hi20
Definition:RISCVFixupKinds.h:50
llvm::RISCV::fixup_riscv_call_plt
@ fixup_riscv_call_plt
Definition:RISCVFixupKinds.h:67
llvm::RISCV::fixup_riscv_tls_gd_hi20
@ fixup_riscv_tls_gd_hi20
Definition:RISCVFixupKinds.h:53
llvm::RISCV::fixup_riscv_hi20
@ fixup_riscv_hi20
Definition:RISCVFixupKinds.h:21
llvm::RISCV::fixup_riscv_12_i
@ fixup_riscv_12_i
Definition:RISCVFixupKinds.h:25
llvm::RISCV::fixup_riscv_pcrel_lo12_i
@ fixup_riscv_pcrel_lo12_i
Definition:RISCVFixupKinds.h:31
llvm::RISCV::fixup_riscv_tlsdesc_call
@ fixup_riscv_tlsdesc_call
Definition:RISCVFixupKinds.h:79
llvm::RISCV::fixup_riscv_tprel_hi20
@ fixup_riscv_tprel_hi20
Definition:RISCVFixupKinds.h:39
llvm::RISCV::fixup_riscv_pcrel_lo12_s
@ fixup_riscv_pcrel_lo12_s
Definition:RISCVFixupKinds.h:34
llvm::RISCV::fixup_riscv_relax
@ fixup_riscv_relax
Definition:RISCVFixupKinds.h:70
llvm::RISCV::fixup_riscv_got_hi20
@ fixup_riscv_got_hi20
Definition:RISCVFixupKinds.h:37
llvm::RISCV::fixup_riscv_tprel_lo12_i
@ fixup_riscv_tprel_lo12_i
Definition:RISCVFixupKinds.h:41
llvm::RISCV::fixup_riscv_tlsdesc_load_lo12
@ fixup_riscv_tlsdesc_load_lo12
Definition:RISCVFixupKinds.h:77
llvm::RISCV::fixup_riscv_call
@ fixup_riscv_call
Definition:RISCVFixupKinds.h:64
llvm::RISCV::fixup_riscv_lo12_i
@ fixup_riscv_lo12_i
Definition:RISCVFixupKinds.h:23
llvm::RISCV::fixup_riscv_tprel_add
@ fixup_riscv_tprel_add
Definition:RISCVFixupKinds.h:47
llvm::RISCV::fixup_riscv_rvc_jump
@ fixup_riscv_rvc_jump
Definition:RISCVFixupKinds.h:59
llvm::RISCV::fixup_riscv_lo12_s
@ fixup_riscv_lo12_s
Definition:RISCVFixupKinds.h:27
llvm::RISCV::fixup_riscv_tlsdesc_hi20
@ fixup_riscv_tlsdesc_hi20
Definition:RISCVFixupKinds.h:76
llvm::RISCV::fixup_riscv_rvc_branch
@ fixup_riscv_rvc_branch
Definition:RISCVFixupKinds.h:61
llvm::RISCV::fixup_riscv_branch
@ fixup_riscv_branch
Definition:RISCVFixupKinds.h:57
llvm::RISCV::fixup_riscv_pcrel_hi20
@ fixup_riscv_pcrel_hi20
Definition:RISCVFixupKinds.h:29
llvm::RISCV::fixup_riscv_tlsdesc_add_lo12
@ fixup_riscv_tlsdesc_add_lo12
Definition:RISCVFixupKinds.h:78
llvm::RISCV::fixup_riscv_jal
@ fixup_riscv_jal
Definition:RISCVFixupKinds.h:55
llvm::codeview::Link
@ Link
Definition:CodeView.h:154
llvm::lltok::Kind
Kind
Definition:LLToken.h:18
llvm::msgpack::Type::Binary
@ Binary
llvm::rdf::Func
NodeAddr< FuncNode * > Func
Definition:RDFGraph.h:393
llvm::support::endian::write
void write(void *memory, value_type value, endianness endian)
Write a value to memory with a particular endianness.
Definition:Endian.h:92
llvm::tgtok::Bits
@ Bits
Definition:TGLexer.h:79
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition:AddressRanges.h:18
llvm::Offset
@ Offset
Definition:DWP.cpp:480
llvm::createRISCVMCCodeEmitter
MCCodeEmitter * createRISCVMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Definition:RISCVMCCodeEmitter.cpp:105
llvm::MCFixupKind
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition:MCFixup.h:21
llvm::endianness::little
@ little
std::swap
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition:BitVector.h:860
llvm::DWARFExpression::Operation::Description
Description of the encoding of one expression Op.
Definition:DWARFExpression.h:66
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