Movatterモバイル変換

Go to the documentation of this file.

1//===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===//

2//

3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.

4// See https://llvm.org/LICENSE.txt for license information.

5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception

6//

7//===----------------------------------------------------------------------===//

8//

9// This file implements the PPC specific subclass of TargetSubtargetInfo.

10//

11//===----------------------------------------------------------------------===//

13#include "PPCSubtarget.h"

14#include "GISel/PPCCallLowering.h"

15#include "GISel/PPCLegalizerInfo.h"

16#include "GISel/PPCRegisterBankInfo.h"

17#include "PPC.h"

18#include "PPCRegisterInfo.h"

19#include "PPCSelectionDAGInfo.h"

20#include "PPCTargetMachine.h"

21#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"

22#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"

23#include "llvm/CodeGen/MachineFunction.h"

24#include "llvm/CodeGen/MachineScheduler.h"

25#include "llvm/IR/GlobalAlias.h"

26#include "llvm/IR/GlobalValue.h"

27#include "llvm/IR/GlobalVariable.h"

28#include "llvm/MC/TargetRegistry.h"

29#include "llvm/Support/CommandLine.h"

30#include "llvm/Target/TargetMachine.h"

31#include "llvm/TargetParser/PPCTargetParser.h"

32#include <cstdlib>

34using namespacellvm;

36#define DEBUG_TYPE "ppc-subtarget"

38#define GET_SUBTARGETINFO_TARGET_DESC

39#define GET_SUBTARGETINFO_CTOR

40#include "PPCGenSubtargetInfo.inc"

42staticcl::opt<bool>

43EnableMachinePipeliner("ppc-enable-pipeliner",

44cl::desc("Enable Machine Pipeliner for PPC"),

45cl::init(false),cl::Hidden);

47PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU,

48StringRef TuneCPU,

49StringRef FS) {

50 initializeEnvironment();

51 initSubtargetFeatures(CPU, TuneCPU, FS);

52return *this;

53}

55PPCSubtarget::PPCSubtarget(constTriple &TT,const std::string &CPU,

56const std::string &TuneCPU,const std::string &FS,

57constPPCTargetMachine &TM)

58 :PPCGenSubtargetInfo(TT, CPU, TuneCPU, FS), TargetTriple(TT),

59 IsPPC64(TargetTriple.getArch() ==Triple::ppc64 ||

60 TargetTriple.getArch() ==Triple::ppc64le),

61 TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, TuneCPU, FS)),

62 InstrInfo(*this), TLInfo(TM, *this) {

63TSInfo = std::make_unique<PPCSelectionDAGInfo>();

65CallLoweringInfo.reset(newPPCCallLowering(*getTargetLowering()));

66Legalizer.reset(newPPCLegalizerInfo(*this));

67auto *RBI =newPPCRegisterBankInfo(*getRegisterInfo());

68RegBankInfo.reset(RBI);

70InstSelector.reset(createPPCInstructionSelector(TM, *this, *RBI));

71}

73PPCSubtarget::~PPCSubtarget() =default;

75constSelectionDAGTargetInfo *PPCSubtarget::getSelectionDAGInfo() const{

76returnTSInfo.get();

77}

79void PPCSubtarget::initializeEnvironment() {

80StackAlignment =Align(16);

81CPUDirective =PPC::DIR_NONE;

82HasPOPCNTD =POPCNTD_Unavailable;

83}

85void PPCSubtarget::initSubtargetFeatures(StringRef CPU,StringRef TuneCPU,

86StringRef FS) {

87// Determine default and user specified characteristics

88 std::string CPUName = std::string(CPU);

89if (CPUName.empty() || CPU =="generic") {

90if (TargetTriple.getSubArch() ==Triple::PPCSubArch_spe)

91 CPUName ="e500";

92else

93 CPUName = std::string(PPC::getNormalizedPPCTargetCPU(TargetTriple));

94 }

96// Determine the CPU to schedule for.

97if (TuneCPU.empty()) TuneCPU = CPUName;

99// Initialize scheduling itinerary for the specified CPU.

100InstrItins = getInstrItineraryForCPU(CPUName);

101

102// Parse features string.

103ParseSubtargetFeatures(CPUName, TuneCPU, FS);

104

105// If the user requested use of 64-bit regs, but the cpu selected doesn't

106// support it, ignore.

107if (IsPPC64 && has64BitSupport())

108 Use64BitRegs =true;

109

110if (TargetTriple.isPPC32SecurePlt())

111 IsSecurePlt =true;

112

113if (HasSPE &&IsPPC64)

114report_fatal_error("SPE is only supported for 32-bit targets.\n",false);

115if (HasSPE && (HasAltivec || HasVSX || HasFPU))

116report_fatal_error(

117"SPE and traditional floating point cannot both be enabled.\n",false);

118

119// If not SPE, set standard FPU

120if (!HasSPE)

121 HasFPU =true;

122

123StackAlignment =getPlatformStackAlignment();

124

125// Determine endianness.

126IsLittleEndian =TM.isLittleEndian();

127

128if (HasAIXSmallLocalExecTLS || HasAIXSmallLocalDynamicTLS) {

129if (!TargetTriple.isOSAIX() || !IsPPC64)

130report_fatal_error("The aix-small-local-[exec|dynamic]-tls attribute is "

131"only supported on AIX in "

132"64-bit mode.\n",

133false);

134// The aix-small-local-[exec|dynamic]-tls attribute should only be used with

135// -data-sections, as having data sections turned off with this option

136// is not ideal for performance. Moreover, the

137// small-local-[exec|dynamic]-tls region is a limited resource, and should

138// not be used for variables that may be replaced.

139if (!TM.getDataSections())

140report_fatal_error("The aix-small-local-[exec|dynamic]-tls attribute can "

141"only be specified with "

142"-data-sections.\n",

143false);

144 }

145

146if (HasAIXShLibTLSModelOpt && (!TargetTriple.isOSAIX() || !IsPPC64))

147report_fatal_error("The aix-shared-lib-tls-model-opt attribute "

148"is only supported on AIX in 64-bit mode.\n",

149false);

150}

151

152boolPPCSubtarget::enableMachineScheduler() const{returntrue; }

153

154boolPPCSubtarget::enableMachinePipeliner() const{

155return getSchedModel().hasInstrSchedModel() &&EnableMachinePipeliner;

156}

157

158boolPPCSubtarget::useDFAforSMS() const{returnfalse; }

159

160// This overrides the PostRAScheduler bit in the SchedModel for each CPU.

161boolPPCSubtarget::enablePostRAScheduler() const{returntrue; }

162

163PPCGenSubtargetInfo::AntiDepBreakModePPCSubtarget::getAntiDepBreakMode() const{

164return TargetSubtargetInfo::ANTIDEP_ALL;

165}

166

167voidPPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const{

168 CriticalPathRCs.clear();

169 CriticalPathRCs.push_back(isPPC64() ?

170 &PPC::G8RCRegClass : &PPC::GPRCRegClass);

171}

172

173voidPPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,

174unsigned NumRegionInstrs) const{

175// The GenericScheduler that we use defaults to scheduling bottom up only.

176// We want to schedule from both the top and the bottom and so we set

177// OnlyBottomUp to false.

178// We want to do bi-directional scheduling since it provides a more balanced

179// schedule leading to better performance.

180 Policy.OnlyBottomUp =false;

181// Spilling is generally expensive on all PPC cores, so always enable

182// register-pressure tracking.

183 Policy.ShouldTrackPressure =true;

184}

185

186boolPPCSubtarget::useAA() const{

187returntrue;

188}

189

190boolPPCSubtarget::enableSubRegLiveness() const{returntrue; }

191

192boolPPCSubtarget::isGVIndirectSymbol(constGlobalValue *GV) const{

193if (isAIXABI()) {

194if (constGlobalVariable *GVar = dyn_cast<GlobalVariable>(GV))

195// On AIX the only symbols that aren't indirect are toc-data.

196return !GVar->hasAttribute("toc-data");

197

198returntrue;

199 }

200

201// Large code model always uses the TOC even for local symbols.

202if (TM.getCodeModel() ==CodeModel::Large)

203returntrue;

204

205if (TM.shouldAssumeDSOLocal(GV))

206returnfalse;

207returntrue;

208}

209

210CodeModel::Model PPCSubtarget::getCodeModel(constTargetMachine &TM,

211constGlobalValue *GV) const{

212// If there isn't an attribute to override the module code model

213// this will be the effective code model.

214CodeModel::Model ModuleModel =TM.getCodeModel();

215

216// Initially support per global code model for AIX only.

217if (!isAIXABI())

218return ModuleModel;

219

220// Only GlobalVariables carry an attribute which can override the module code

221// model.

222assert(GV &&"Unexpected NULL GlobalValue");

223constGlobalVariable *GlobalVar =

224 [](constGlobalValue *GV) ->constGlobalVariable * {

225constGlobalVariable *Var = dyn_cast<GlobalVariable>(GV);

226if (Var)

227return Var;

228

229constGlobalAlias *Alias = dyn_cast<GlobalAlias>(GV);

230if (Alias)

231return dyn_cast<GlobalVariable>(Alias->getAliaseeObject());

232

233returnnullptr;

234 }(GV);

235

236if (!GlobalVar)

237return ModuleModel;

238

239 std::optional<CodeModel::Model> MaybeCodeModel = GlobalVar->getCodeModel();

240if (MaybeCodeModel) {

241CodeModel::Model CM = *MaybeCodeModel;

242assert((CM ==CodeModel::Small || CM ==CodeModel::Large) &&

243"invalid code model for AIX");

244return CM;

245 }

246

247return ModuleModel;

248}

249

250boolPPCSubtarget::isELFv2ABI() const{returnTM.isELFv2ABI(); }

251boolPPCSubtarget::isPPC64() const{returnTM.isPPC64(); }

252

253boolPPCSubtarget::isUsingPCRelativeCalls() const{

254returnisPPC64() && hasPCRelativeMemops() &&isELFv2ABI() &&

255CodeModel::Medium ==getTargetMachine().getCodeModel();

256}

257

258// GlobalISEL

259constCallLowering *PPCSubtarget::getCallLowering() const{

260returnCallLoweringInfo.get();

261}

262

263constRegisterBankInfo *PPCSubtarget::getRegBankInfo() const{

264returnRegBankInfo.get();

265}

266

267constLegalizerInfo *PPCSubtarget::getLegalizerInfo() const{

268returnLegalizer.get();

269}

270

271InstructionSelector *PPCSubtarget::getInstructionSelector() const{

272returnInstSelector.get();

273}

EnableMachinePipeliner

static cl::opt< bool > EnableMachinePipeliner("aarch64-enable-pipeliner", cl::desc("Enable Machine Pipeliner for AArch64"), cl::init(false), cl::Hidden)

InstructionSelector.h

MachineFunction.h

MachineScheduler.h

PPCCallLowering.h

This file describes how to lower LLVM calls to machine code calls.

PPCLegalizerInfo.h

This file declares the targeting of the Machinelegalizer class for PowerPC.

PPCRegisterBankInfo.h

This file declares the targeting of the RegisterBankInfo class for PowerPC.

PPCRegisterInfo.h

PPCSelectionDAGInfo.h

EnableMachinePipeliner

static cl::opt< bool > EnableMachinePipeliner("ppc-enable-pipeliner", cl::desc("Enable Machine Pipeliner for PPC"), cl::init(false), cl::Hidden)

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

TargetRegistry.h

PPCGenSubtargetInfo

llvm::CallLowering

Definition:CallLowering.h:44

llvm::GlobalAlias

Definition:GlobalAlias.h:28

llvm::GlobalAlias::getAliaseeObject

const GlobalObject * getAliaseeObject() const

Definition:Globals.cpp:595

llvm::GlobalValue

Definition:GlobalValue.h:48

llvm::GlobalVariable

Definition:GlobalVariable.h:39

llvm::InstructionSelector

Definition:InstructionSelector.h:21

llvm::LegalizerInfo

Definition:LegalizerInfo.h:1311

llvm::Legalizer

Definition:Legalizer.h:37

llvm::PPCCallLowering

Definition:PPCCallLowering.h:25

llvm::PPCLegalizerInfo

This class provides the information for the PowerPC target legalizer for GlobalISel.

Definition:PPCLegalizerInfo.h:23

llvm::PPCRegisterBankInfo

Definition:PPCRegisterBankInfo.h:64

llvm::PPCSubtarget

Definition:PPCSubtarget.h:72

llvm::PPCSubtarget::IsLittleEndian

bool IsLittleEndian

Definition:PPCSubtarget.h:100

llvm::PPCSubtarget::InstSelector

std::unique_ptr< InstructionSelector > InstSelector

Definition:PPCSubtarget.h:116

llvm::PPCSubtarget::enableMachinePipeliner

bool enableMachinePipeliner() const override

Pipeliner customization.

Definition:PPCSubtarget.cpp:154

llvm::PPCSubtarget::useDFAforSMS

bool useDFAforSMS() const override

Machine Pipeliner customization.

Definition:PPCSubtarget.cpp:158

llvm::PPCSubtarget::POPCNTD_Unavailable

@ POPCNTD_Unavailable

Definition:PPCSubtarget.h:75

llvm::PPCSubtarget::isAIXABI

bool isAIXABI() const

Definition:PPCSubtarget.h:219

llvm::PPCSubtarget::getCallLowering

const CallLowering * getCallLowering() const override

Definition:PPCSubtarget.cpp:259

llvm::PPCSubtarget::TargetTriple

Triple TargetTriple

TargetTriple - What processor and OS we're targeting.

Definition:PPCSubtarget.h:82

llvm::PPCSubtarget::getLegalizerInfo

const LegalizerInfo * getLegalizerInfo() const override

Definition:PPCSubtarget.cpp:267

llvm::PPCSubtarget::RegBankInfo

std::unique_ptr< RegisterBankInfo > RegBankInfo

Definition:PPCSubtarget.h:115

llvm::PPCSubtarget::~PPCSubtarget

~PPCSubtarget() override

llvm::PPCSubtarget::HasPOPCNTD

POPCNTDKind HasPOPCNTD

Definition:PPCSubtarget.h:102

llvm::PPCSubtarget::InstrItins

InstrItineraryData InstrItins

Selected instruction itineraries (one entry per itinerary class.)

Definition:PPCSubtarget.h:89

llvm::PPCSubtarget::StackAlignment

Align StackAlignment

stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and ...

Definition:PPCSubtarget.h:86

llvm::PPCSubtarget::overrideSchedPolicy

void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override

Definition:PPCSubtarget.cpp:173

llvm::PPCSubtarget::isPPC64

bool isPPC64() const

isPPC64 - Return true if we are generating code for 64-bit pointer mode.

Definition:PPCSubtarget.cpp:251

llvm::PPCSubtarget::getCriticalPathRCs

void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override

Definition:PPCSubtarget.cpp:167

llvm::PPCSubtarget::isUsingPCRelativeCalls

bool isUsingPCRelativeCalls() const

Definition:PPCSubtarget.cpp:253

llvm::PPCSubtarget::enableSubRegLiveness

bool enableSubRegLiveness() const override

Definition:PPCSubtarget.cpp:190

llvm::PPCSubtarget::getTargetLowering

const PPCTargetLowering * getTargetLowering() const override

Definition:PPCSubtarget.h:151

llvm::PPCSubtarget::getInstructionSelector

InstructionSelector * getInstructionSelector() const override

Definition:PPCSubtarget.cpp:271

llvm::PPCSubtarget::CPUDirective

unsigned CPUDirective

Which cpu directive was used.

Definition:PPCSubtarget.h:97

llvm::PPCSubtarget::getAntiDepBreakMode

AntiDepBreakMode getAntiDepBreakMode() const override

Definition:PPCSubtarget.cpp:163

llvm::PPCSubtarget::getSelectionDAGInfo

const SelectionDAGTargetInfo * getSelectionDAGInfo() const override

Definition:PPCSubtarget.cpp:75

llvm::PPCSubtarget::useAA

bool useAA() const override

Definition:PPCSubtarget.cpp:186

llvm::PPCSubtarget::initializeSubtargetDependencies

PPCSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef TuneCPU, StringRef FS)

initializeSubtargetDependencies - Initializes using a CPU, a TuneCPU, and feature string so that we c...

Definition:PPCSubtarget.cpp:47

llvm::PPCSubtarget::getCodeModel

CodeModel::Model getCodeModel(const TargetMachine &TM, const GlobalValue *GV) const

Calculates the effective code model for argument GV.

Definition:PPCSubtarget.cpp:210

llvm::PPCSubtarget::isELFv2ABI

bool isELFv2ABI() const

Definition:PPCSubtarget.cpp:250

llvm::PPCSubtarget::getPlatformStackAlignment

Align getPlatformStackAlignment() const

Definition:PPCSubtarget.h:193

llvm::PPCSubtarget::getTargetMachine

const PPCTargetMachine & getTargetMachine() const

Definition:PPCSubtarget.h:160

llvm::PPCSubtarget::PPCSubtarget

PPCSubtarget(const Triple &TT, const std::string &CPU, const std::string &TuneCPU, const std::string &FS, const PPCTargetMachine &TM)

This constructor initializes the data members to match that of the specified triple.

Definition:PPCSubtarget.cpp:55

llvm::PPCSubtarget::TM

const PPCTargetMachine & TM

Definition:PPCSubtarget.h:104

llvm::PPCSubtarget::TSInfo

std::unique_ptr< const SelectionDAGTargetInfo > TSInfo

Definition:PPCSubtarget.h:110

llvm::PPCSubtarget::enableMachineScheduler

bool enableMachineScheduler() const override

Scheduling customization.

Definition:PPCSubtarget.cpp:152

llvm::PPCSubtarget::getRegBankInfo

const RegisterBankInfo * getRegBankInfo() const override

Definition:PPCSubtarget.cpp:263

llvm::PPCSubtarget::getRegisterInfo

const PPCRegisterInfo * getRegisterInfo() const override

Definition:PPCSubtarget.h:157

llvm::PPCSubtarget::isGVIndirectSymbol

bool isGVIndirectSymbol(const GlobalValue *GV) const

True if the GV will be accessed via an indirect symbol.

Definition:PPCSubtarget.cpp:192

llvm::PPCSubtarget::CallLoweringInfo

std::unique_ptr< CallLowering > CallLoweringInfo

GlobalISel related APIs.

Definition:PPCSubtarget.h:113

llvm::PPCSubtarget::enablePostRAScheduler

bool enablePostRAScheduler() const override

This overrides the PostRAScheduler bit in the SchedModel for each CPU.

Definition:PPCSubtarget.cpp:161

llvm::PPCSubtarget::IsPPC64

bool IsPPC64

Definition:PPCSubtarget.h:99

llvm::PPCSubtarget::ParseSubtargetFeatures

void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)

ParseSubtargetFeatures - Parses features string setting specified subtarget options.

llvm::PPCTargetMachine

Common code between 32-bit and 64-bit PowerPC targets.

Definition:PPCTargetMachine.h:26

llvm::PPCTargetMachine::isPPC64

bool isPPC64() const

Definition:PPCTargetMachine.h:70

llvm::PPCTargetMachine::isLittleEndian

bool isLittleEndian() const

Definition:PPCTargetMachine.cpp:610

llvm::PPCTargetMachine::isELFv2ABI

bool isELFv2ABI() const

Definition:PPCTargetMachine.h:67

llvm::RegisterBankInfo

Holds all the information related to register banks.

Definition:RegisterBankInfo.h:40

llvm::SelectionDAGTargetInfo

Targets can subclass this to parameterize the SelectionDAG lowering and instruction selection process...

Definition:SelectionDAGTargetInfo.h:31

llvm::StringRef

StringRef - Represent a constant reference to a string, i.e.

Definition:StringRef.h:51

llvm::StringRef::empty

constexpr bool empty() const

empty - Check if the string is empty.

Definition:StringRef.h:147

llvm::TargetMachine

Primary interface to the complete machine description for the target machine.

Definition:TargetMachine.h:77

llvm::TargetMachine::shouldAssumeDSOLocal

bool shouldAssumeDSOLocal(const GlobalValue *GV) const

Definition:TargetMachine.cpp:178

llvm::TargetMachine::getDataSections

bool getDataSections() const

Return true if data objects should be emitted into their own section, corresponds to -fdata-sections.

Definition:TargetMachine.h:298

llvm::TargetMachine::getCodeModel

CodeModel::Model getCodeModel() const

Returns the code model.

Definition:TargetMachine.h:232

llvm::Triple

Triple - Helper class for working with autoconf configuration names.

Definition:Triple.h:44

llvm::Triple::getSubArch

SubArchType getSubArch() const

get the parsed subarchitecture type for this triple.

Definition:Triple.h:398

llvm::Triple::isOSAIX

bool isOSAIX() const

Tests whether the OS is AIX.

Definition:Triple.h:741

llvm::Triple::PPCSubArch_spe

@ PPCSubArch_spe

Definition:Triple.h:157

llvm::Triple::isPPC32SecurePlt

bool isPPC32SecurePlt() const

Tests whether the target 32-bit PowerPC uses Secure PLT.

Definition:Triple.h:1017

llvm::cl::opt

Definition:CommandLine.h:1423

TargetMachine.h

llvm::CodeModel::Model

Model

Definition:CodeGen.h:31

llvm::CodeModel::Medium

@ Medium

Definition:CodeGen.h:31

llvm::CodeModel::Large

@ Large

Definition:CodeGen.h:31

llvm::CodeModel::Small

@ Small

Definition:CodeGen.h:31

llvm::PPC::getNormalizedPPCTargetCPU

StringRef getNormalizedPPCTargetCPU(const Triple &T, StringRef CPUName="")

Definition:PPCTargetParser.cpp:91

llvm::PPC::DIR_NONE

@ DIR_NONE

Definition:PPCSubtarget.h:41

llvm::cl::Hidden

@ Hidden

Definition:CommandLine.h:137

llvm::cl::init

initializer< Ty > init(const Ty &Val)

Definition:CommandLine.h:443

llvm

This is an optimization pass for GlobalISel generic memory operations.

Definition:AddressRanges.h:18

llvm::report_fatal_error

void report_fatal_error(Error Err, bool gen_crash_diag=true)

Report a serious error, calling any installed error handler.

Definition:Error.cpp:167

llvm::createPPCInstructionSelector

InstructionSelector * createPPCInstructionSelector(const PPCTargetMachine &TM, const PPCSubtarget &Subtarget, const PPCRegisterBankInfo &RBI)

Definition:PPCInstructionSelector.cpp:784

llvm::Align

This struct is a compact representation of a valid (non-zero power of two) alignment.

Definition:Alignment.h:39

llvm::MachineSchedPolicy

Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.

Definition:MachineScheduler.h:192

llvm::MachineSchedPolicy::OnlyBottomUp

bool OnlyBottomUp

Definition:MachineScheduler.h:202

llvm::MachineSchedPolicy::ShouldTrackPressure

bool ShouldTrackPressure

Definition:MachineScheduler.h:194

llvm::cl::desc

Definition:CommandLine.h:409