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1//===---- PPCReduceCRLogicals.cpp - Reduce CR Bit Logical operations ------===//

2//

3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.

4// See https://llvm.org/LICENSE.txt for license information.

5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception

6//

7//===---------------------------------------------------------------------===//

8//

9// This pass aims to reduce the number of logical operations on bits in the CR

10// register. These instructions have a fairly high latency and only a single

11// pipeline at their disposal in modern PPC cores. Furthermore, they have a

12// tendency to occur in fairly small blocks where there's little opportunity

13// to hide the latency between the CR logical operation and its user.

14//

15//===---------------------------------------------------------------------===//

17#include "PPC.h"

18#include "PPCInstrInfo.h"

19#include "PPCTargetMachine.h"

20#include "llvm/ADT/Statistic.h"

21#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"

22#include "llvm/CodeGen/MachineDominators.h"

23#include "llvm/CodeGen/MachineFunctionPass.h"

24#include "llvm/CodeGen/MachineInstrBuilder.h"

25#include "llvm/CodeGen/MachineRegisterInfo.h"

26#include "llvm/Config/llvm-config.h"

27#include "llvm/InitializePasses.h"

28#include "llvm/Support/Debug.h"

30using namespacellvm;

32#define DEBUG_TYPE "ppc-reduce-cr-ops"

34STATISTIC(NumContainedSingleUseBinOps,

35"Number of single-use binary CR logical ops contained in a block");

36STATISTIC(NumToSplitBlocks,

37"Number of binary CR logical ops that can be used to split blocks");

38STATISTIC(TotalCRLogicals,"Number of CR logical ops.");

39STATISTIC(TotalNullaryCRLogicals,

40"Number of nullary CR logical ops (CRSET/CRUNSET).");

41STATISTIC(TotalUnaryCRLogicals,"Number of unary CR logical ops.");

42STATISTIC(TotalBinaryCRLogicals,"Number of CR logical ops.");

43STATISTIC(NumBlocksSplitOnBinaryCROp,

44"Number of blocks split on CR binary logical ops.");

45STATISTIC(NumNotSplitIdenticalOperands,

46"Number of blocks not split due to operands being identical.");

47STATISTIC(NumNotSplitChainCopies,

48"Number of blocks not split due to operands being chained copies.");

49STATISTIC(NumNotSplitWrongOpcode,

50"Number of blocks not split due to the wrong opcode.");

52/// Given a basic block \p Successor that potentially contains PHIs, this

53/// function will look for any incoming values in the PHIs that are supposed to

54/// be coming from \p OrigMBB but whose definition is actually in \p NewMBB.

55/// Any such PHIs will be updated to reflect reality.

56staticvoidupdatePHIs(MachineBasicBlock *Successor,MachineBasicBlock *OrigMBB,

57MachineBasicBlock *NewMBB,MachineRegisterInfo *MRI) {

58for (auto &MI :Successor->instrs()) {

59if (!MI.isPHI())

60continue;

61// This is a really ugly-looking loop, but it was pillaged directly from

62// MachineBasicBlock::transferSuccessorsAndUpdatePHIs().

63for (unsigned i = 2, e =MI.getNumOperands() + 1; i != e; i += 2) {

64MachineOperand &MO =MI.getOperand(i);

65if (MO.getMBB() == OrigMBB) {

66// Check if the instruction is actually defined in NewMBB.

67if (MI.getOperand(i - 1).isReg()) {

68MachineInstr *DefMI =MRI->getVRegDef(MI.getOperand(i - 1).getReg());

69if (DefMI->getParent() == NewMBB ||

70 !OrigMBB->isSuccessor(Successor)) {

71 MO.setMBB(NewMBB);

72break;

73 }

74 }

75 }

76 }

77 }

78}

80/// Given a basic block \p Successor that potentially contains PHIs, this

81/// function will look for PHIs that have an incoming value from \p OrigMBB

82/// and will add the same incoming value from \p NewMBB.

83/// NOTE: This should only be used if \p NewMBB is an immediate dominator of

84/// \p OrigMBB.

85staticvoidaddIncomingValuesToPHIs(MachineBasicBlock *Successor,

86MachineBasicBlock *OrigMBB,

87MachineBasicBlock *NewMBB,

88MachineRegisterInfo *MRI) {

89assert(OrigMBB->isSuccessor(NewMBB) &&

90"NewMBB must be a successor of OrigMBB");

91for (auto &MI :Successor->instrs()) {

92if (!MI.isPHI())

93continue;

94// This is a really ugly-looking loop, but it was pillaged directly from

95// MachineBasicBlock::transferSuccessorsAndUpdatePHIs().

96for (unsigned i = 2, e =MI.getNumOperands() + 1; i != e; i += 2) {

97MachineOperand &MO =MI.getOperand(i);

98if (MO.getMBB() == OrigMBB) {

99MachineInstrBuilder MIB(*MI.getParent()->getParent(), &MI);

100 MIB.addReg(MI.getOperand(i - 1).getReg()).addMBB(NewMBB);

101break;

102 }

103 }

104 }

105}

106

107structBlockSplitInfo {

108MachineInstr *OrigBranch;

109MachineInstr *SplitBefore;

110MachineInstr *SplitCond;

111boolInvertNewBranch;

112boolInvertOrigBranch;

113boolBranchToFallThrough;

114constMachineBranchProbabilityInfo *MBPI;

115MachineInstr *MIToDelete;

116MachineInstr *NewCond;

117boolallInstrsInSameMBB() {

118if (!OrigBranch || !SplitBefore || !SplitCond)

119returnfalse;

120MachineBasicBlock *MBB =OrigBranch->getParent();

121if (SplitBefore->getParent() !=MBB ||SplitCond->getParent() !=MBB)

122returnfalse;

123if (MIToDelete &&MIToDelete->getParent() !=MBB)

124returnfalse;

125if (NewCond &&NewCond->getParent() !=MBB)

126returnfalse;

127returntrue;

128 }

129};

130

131/// Splits a MachineBasicBlock to branch before \p SplitBefore. The original

132/// branch is \p OrigBranch. The target of the new branch can either be the same

133/// as the target of the original branch or the fallthrough successor of the

134/// original block as determined by \p BranchToFallThrough. The branch

135/// conditions will be inverted according to \p InvertNewBranch and

136/// \p InvertOrigBranch. If an instruction that previously fed the branch is to

137/// be deleted, it is provided in \p MIToDelete and \p NewCond will be used as

138/// the branch condition. The branch probabilities will be set if the

139/// MachineBranchProbabilityInfo isn't null.

140staticboolsplitMBB(BlockSplitInfo &BSI) {

141assert(BSI.allInstrsInSameMBB() &&

142"All instructions must be in the same block.");

143

144MachineBasicBlock *ThisMBB = BSI.OrigBranch->getParent();

145MachineFunction *MF = ThisMBB->getParent();

146MachineRegisterInfo *MRI = &MF->getRegInfo();

147assert(MRI->isSSA() &&"Can only do this while the function is in SSA form.");

148if (ThisMBB->succ_size() != 2) {

149LLVM_DEBUG(

150dbgs() <<"Don't know how to handle blocks that don't have exactly"

151 <<" two successors.\n");

152returnfalse;

153 }

154

155constPPCInstrInfo *TII = MF->getSubtarget<PPCSubtarget>().getInstrInfo();

156unsigned OrigBROpcode = BSI.OrigBranch->getOpcode();

157unsigned InvertedOpcode =

158 OrigBROpcode == PPC::BC

159 ? PPC::BCn

160 : OrigBROpcode == PPC::BCn

161 ? PPC::BC

162 : OrigBROpcode == PPC::BCLR ? PPC::BCLRn : PPC::BCLR;

163unsigned NewBROpcode = BSI.InvertNewBranch ? InvertedOpcode : OrigBROpcode;

164MachineBasicBlock *OrigTarget = BSI.OrigBranch->getOperand(1).getMBB();

165MachineBasicBlock *OrigFallThrough = OrigTarget == *ThisMBB->succ_begin()

166 ? *ThisMBB->succ_rbegin()

167 : *ThisMBB->succ_begin();

168MachineBasicBlock *NewBRTarget =

169 BSI.BranchToFallThrough ? OrigFallThrough : OrigTarget;

170

171// It's impossible to know the precise branch probability after the split.

172// But it still needs to be reasonable, the whole probability to original

173// targets should not be changed.

174// After split NewBRTarget will get two incoming edges. Assume P0 is the

175// original branch probability to NewBRTarget, P1 and P2 are new branch

176// probabilies to NewBRTarget after split. If the two edge frequencies are

177// same, then

178// F * P1 = F * P0 / 2 ==> P1 = P0 / 2

179// F * (1 - P1) * P2 = F * P1 ==> P2 = P1 / (1 - P1)

180BranchProbability ProbToNewTarget, ProbFallThrough;// Prob for new Br.

181BranchProbability ProbOrigTarget, ProbOrigFallThrough;// Prob for orig Br.

182 ProbToNewTarget = ProbFallThrough =BranchProbability::getUnknown();

183 ProbOrigTarget = ProbOrigFallThrough =BranchProbability::getUnknown();

184if (BSI.MBPI) {

185if (BSI.BranchToFallThrough) {

186 ProbToNewTarget = BSI.MBPI->getEdgeProbability(ThisMBB, OrigFallThrough) / 2;

187 ProbFallThrough = ProbToNewTarget.getCompl();

188 ProbOrigFallThrough = ProbToNewTarget / ProbToNewTarget.getCompl();

189 ProbOrigTarget = ProbOrigFallThrough.getCompl();

190 }else {

191 ProbToNewTarget = BSI.MBPI->getEdgeProbability(ThisMBB, OrigTarget) / 2;

192 ProbFallThrough = ProbToNewTarget.getCompl();

193 ProbOrigTarget = ProbToNewTarget / ProbToNewTarget.getCompl();

194 ProbOrigFallThrough = ProbOrigTarget.getCompl();

195 }

196 }

197

198// Create a new basic block.

199MachineBasicBlock::iterator InsertPoint = BSI.SplitBefore;

200constBasicBlock *LLVM_BB = ThisMBB->getBasicBlock();

201MachineFunction::iterator It = ThisMBB->getIterator();

202MachineBasicBlock *NewMBB = MF->CreateMachineBasicBlock(LLVM_BB);

203 MF->insert(++It, NewMBB);

204

205// Move everything after SplitBefore into the new block.

206 NewMBB->splice(NewMBB->end(), ThisMBB, InsertPoint, ThisMBB->end());

207 NewMBB->transferSuccessors(ThisMBB);

208if (!ProbOrigTarget.isUnknown()) {

209autoMBBI =find(NewMBB->successors(), OrigTarget);

210 NewMBB->setSuccProbability(MBBI, ProbOrigTarget);

211MBBI =find(NewMBB->successors(), OrigFallThrough);

212 NewMBB->setSuccProbability(MBBI, ProbOrigFallThrough);

213 }

214

215// Add the two successors to ThisMBB.

216 ThisMBB->addSuccessor(NewBRTarget, ProbToNewTarget);

217 ThisMBB->addSuccessor(NewMBB, ProbFallThrough);

218

219// Add the branches to ThisMBB.

220BuildMI(*ThisMBB, ThisMBB->end(), BSI.SplitBefore->getDebugLoc(),

221TII->get(NewBROpcode))

222 .addReg(BSI.SplitCond->getOperand(0).getReg())

223 .addMBB(NewBRTarget);

224BuildMI(*ThisMBB, ThisMBB->end(), BSI.SplitBefore->getDebugLoc(),

225TII->get(PPC::B))

226 .addMBB(NewMBB);

227if (BSI.MIToDelete)

228 BSI.MIToDelete->eraseFromParent();

229

230// Change the condition on the original branch and invert it if requested.

231auto FirstTerminator = NewMBB->getFirstTerminator();

232if (BSI.NewCond) {

233assert(FirstTerminator->getOperand(0).isReg() &&

234"Can't update condition of unconditional branch.");

235 FirstTerminator->getOperand(0).setReg(BSI.NewCond->getOperand(0).getReg());

236 }

237if (BSI.InvertOrigBranch)

238 FirstTerminator->setDesc(TII->get(InvertedOpcode));

239

240// If any of the PHIs in the successors of NewMBB reference values that

241// now come from NewMBB, they need to be updated.

242for (auto *Succ : NewMBB->successors()) {

243updatePHIs(Succ, ThisMBB, NewMBB,MRI);

244 }

245addIncomingValuesToPHIs(NewBRTarget, ThisMBB, NewMBB,MRI);

246

247LLVM_DEBUG(dbgs() <<"After splitting, ThisMBB:\n"; ThisMBB->dump());

248LLVM_DEBUG(dbgs() <<"NewMBB:\n"; NewMBB->dump());

249LLVM_DEBUG(dbgs() <<"New branch-to block:\n"; NewBRTarget->dump());

250returntrue;

251}

252

253staticboolisBinary(MachineInstr &MI) {

254returnMI.getNumOperands() == 3;

255}

256

257staticboolisNullary(MachineInstr &MI) {

258returnMI.getNumOperands() == 1;

259}

260

261/// Given a CR logical operation \p CROp, branch opcode \p BROp as well as

262/// a flag to indicate if the first operand of \p CROp is used as the

263/// SplitBefore operand, determines whether either of the branches are to be

264/// inverted as well as whether the new target should be the original

265/// fall-through block.

266staticvoid

267computeBranchTargetAndInversion(unsigned CROp,unsigned BROp,bool UsingDef1,

268bool &InvertNewBranch,bool &InvertOrigBranch,

269bool &TargetIsFallThrough) {

270// The conditions under which each of the output operands should be [un]set

271// can certainly be written much more concisely with just 3 if statements or

272// ternary expressions. However, this provides a much clearer overview to the

273// reader as to what is set for each <CROp, BROp, OpUsed> combination.

274if (BROp == PPC::BC || BROp == PPC::BCLR) {

275// Regular branches.

276switch (CROp) {

277default:

278llvm_unreachable("Don't know how to handle this CR logical.");

279case PPC::CROR:

280 InvertNewBranch =false;

281 InvertOrigBranch =false;

282 TargetIsFallThrough =false;

283return;

284case PPC::CRAND:

285 InvertNewBranch =true;

286 InvertOrigBranch =false;

287 TargetIsFallThrough =true;

288return;

289case PPC::CRNAND:

290 InvertNewBranch =true;

291 InvertOrigBranch =true;

292 TargetIsFallThrough =false;

293return;

294case PPC::CRNOR:

295 InvertNewBranch =false;

296 InvertOrigBranch =true;

297 TargetIsFallThrough =true;

298return;

299case PPC::CRORC:

300 InvertNewBranch = UsingDef1;

301 InvertOrigBranch = !UsingDef1;

302 TargetIsFallThrough =false;

303return;

304case PPC::CRANDC:

305 InvertNewBranch = !UsingDef1;

306 InvertOrigBranch = !UsingDef1;

307 TargetIsFallThrough =true;

308return;

309 }

310 }elseif (BROp == PPC::BCn || BROp == PPC::BCLRn) {

311// Negated branches.

312switch (CROp) {

313default:

314llvm_unreachable("Don't know how to handle this CR logical.");

315case PPC::CROR:

316 InvertNewBranch =true;

317 InvertOrigBranch =false;

318 TargetIsFallThrough =true;

319return;

320case PPC::CRAND:

321 InvertNewBranch =false;

322 InvertOrigBranch =false;

323 TargetIsFallThrough =false;

324return;

325case PPC::CRNAND:

326 InvertNewBranch =false;

327 InvertOrigBranch =true;

328 TargetIsFallThrough =true;

329return;

330case PPC::CRNOR:

331 InvertNewBranch =true;

332 InvertOrigBranch =true;

333 TargetIsFallThrough =false;

334return;

335case PPC::CRORC:

336 InvertNewBranch = !UsingDef1;

337 InvertOrigBranch = !UsingDef1;

338 TargetIsFallThrough =true;

339return;

340case PPC::CRANDC:

341 InvertNewBranch = UsingDef1;

342 InvertOrigBranch = !UsingDef1;

343 TargetIsFallThrough =false;

344return;

345 }

346 }else

347llvm_unreachable("Don't know how to handle this branch.");

348}

349

350namespace{

351

352classPPCReduceCRLogicals :publicMachineFunctionPass {

353

354public:

355staticcharID;

356structCRLogicalOpInfo {

357MachineInstr *MI;

358// FIXME: If chains of copies are to be handled, this should be a vector.

359 std::pair<MachineInstr*, MachineInstr*> CopyDefs;

360 std::pair<MachineInstr*, MachineInstr*> TrueDefs;

361unsigned IsBinary : 1;

362unsigned IsNullary : 1;

363unsigned ContainedInBlock : 1;

364unsigned FeedsISEL : 1;

365unsigned FeedsBR : 1;

366unsigned FeedsLogical : 1;

367unsigned SingleUse : 1;

368unsigned DefsSingleUse : 1;

369unsigned SubregDef1;

370unsigned SubregDef2;

371 CRLogicalOpInfo() :MI(nullptr), IsBinary(0), IsNullary(0),

372 ContainedInBlock(0), FeedsISEL(0), FeedsBR(0),

373 FeedsLogical(0), SingleUse(0), DefsSingleUse(1),

374 SubregDef1(0), SubregDef2(0) { }

375voiddump();

376 };

377

378private:

379constPPCInstrInfo *TII =nullptr;

380MachineFunction *MF =nullptr;

381MachineRegisterInfo *MRI =nullptr;

382constMachineBranchProbabilityInfo *MBPI =nullptr;

383

384// A vector to contain all the CR logical operations

385SmallVector<CRLogicalOpInfo, 16> AllCRLogicalOps;

386voidinitialize(MachineFunction &MFParm);

387void collectCRLogicals();

388bool handleCROp(unsignedIdx);

389bool splitBlockOnBinaryCROp(CRLogicalOpInfo &CRI);

390staticbool isCRLogical(MachineInstr &MI) {

391unsigned Opc =MI.getOpcode();

392return Opc == PPC::CRAND || Opc == PPC::CRNAND || Opc == PPC::CROR ||

393 Opc == PPC::CRXOR || Opc == PPC::CRNOR || Opc == PPC::CRNOT ||

394 Opc == PPC::CREQV || Opc == PPC::CRANDC || Opc == PPC::CRORC ||

395 Opc == PPC::CRSET || Opc == PPC::CRUNSET || Opc == PPC::CR6SET ||

396 Opc == PPC::CR6UNSET;

397 }

398bool simplifyCode() {

399bool Changed =false;

400// Not using a range-based for loop here as the vector may grow while being

401// operated on.

402for (unsigned i = 0; i < AllCRLogicalOps.size(); i++)

403 Changed |= handleCROp(i);

404return Changed;

405 }

406

407public:

408 PPCReduceCRLogicals() :MachineFunctionPass(ID) {

409initializePPCReduceCRLogicalsPass(*PassRegistry::getPassRegistry());

410 }

411

412MachineInstr *lookThroughCRCopy(unsigned Reg,unsigned &Subreg,

413MachineInstr *&CpDef);

414boolrunOnMachineFunction(MachineFunction &MF) override{

415if (skipFunction(MF.getFunction()))

416returnfalse;

417

418// If the subtarget doesn't use CR bits, there's nothing to do.

419constPPCSubtarget &STI = MF.getSubtarget<PPCSubtarget>();

420if (!STI.useCRBits())

421returnfalse;

422

423initialize(MF);

424 collectCRLogicals();

425return simplifyCode();

426 }

427 CRLogicalOpInfo createCRLogicalOpInfo(MachineInstr &MI);

428voidgetAnalysisUsage(AnalysisUsage &AU) const override{

429 AU.addRequired<MachineBranchProbabilityInfoWrapperPass>();

430 AU.addRequired<MachineDominatorTreeWrapperPass>();

431MachineFunctionPass::getAnalysisUsage(AU);

432 }

433};

434

435#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)

436LLVM_DUMP_METHODvoid PPCReduceCRLogicals::CRLogicalOpInfo::dump() {

437dbgs() <<"CRLogicalOpMI: ";

438MI->dump();

439dbgs() <<"IsBinary: " << IsBinary <<", FeedsISEL: " << FeedsISEL;

440dbgs() <<", FeedsBR: " << FeedsBR <<", FeedsLogical: ";

441dbgs() << FeedsLogical <<", SingleUse: " << SingleUse;

442dbgs() <<", DefsSingleUse: " << DefsSingleUse;

443dbgs() <<", SubregDef1: " << SubregDef1 <<", SubregDef2: ";

444dbgs() << SubregDef2 <<", ContainedInBlock: " << ContainedInBlock;

445if (!IsNullary) {

446dbgs() <<"\nDefs:\n";

447 TrueDefs.first->dump();

448 }

449if (IsBinary)

450 TrueDefs.second->dump();

451dbgs() <<"\n";

452if (CopyDefs.first) {

453dbgs() <<"CopyDef1: ";

454 CopyDefs.first->dump();

455 }

456if (CopyDefs.second) {

457dbgs() <<"CopyDef2: ";

458 CopyDefs.second->dump();

459 }

460}

461#endif

462

463PPCReduceCRLogicals::CRLogicalOpInfo

464PPCReduceCRLogicals::createCRLogicalOpInfo(MachineInstr &MIParam) {

465 CRLogicalOpInfoRet;

466Ret.MI = &MIParam;

467// Get the defs

468if (isNullary(MIParam)) {

469Ret.IsNullary = 1;

470Ret.TrueDefs = std::make_pair(nullptr,nullptr);

471Ret.CopyDefs = std::make_pair(nullptr,nullptr);

472 }else {

473MachineInstr *Def1 = lookThroughCRCopy(MIParam.getOperand(1).getReg(),

474Ret.SubregDef1,Ret.CopyDefs.first);

475assert(Def1 &&"Must be able to find a definition of operand 1.");

476Ret.DefsSingleUse &=

477MRI->hasOneNonDBGUse(Def1->getOperand(0).getReg());

478Ret.DefsSingleUse &=

479MRI->hasOneNonDBGUse(Ret.CopyDefs.first->getOperand(0).getReg());

480if (isBinary(MIParam)) {

481Ret.IsBinary = 1;

482MachineInstr *Def2 = lookThroughCRCopy(MIParam.getOperand(2).getReg(),

483Ret.SubregDef2,

484Ret.CopyDefs.second);

485assert(Def2 &&"Must be able to find a definition of operand 2.");

486Ret.DefsSingleUse &=

487MRI->hasOneNonDBGUse(Def2->getOperand(0).getReg());

488Ret.DefsSingleUse &=

489MRI->hasOneNonDBGUse(Ret.CopyDefs.second->getOperand(0).getReg());

490Ret.TrueDefs = std::make_pair(Def1, Def2);

491 }else {

492Ret.TrueDefs = std::make_pair(Def1,nullptr);

493Ret.CopyDefs.second =nullptr;

494 }

495 }

496

497Ret.ContainedInBlock = 1;

498// Get the uses

499for (MachineInstr &UseMI :

500MRI->use_nodbg_instructions(MIParam.getOperand(0).getReg())) {

501unsigned Opc =UseMI.getOpcode();

502if (Opc == PPC::ISEL || Opc == PPC::ISEL8)

503Ret.FeedsISEL = 1;

504if (Opc == PPC::BC || Opc == PPC::BCn || Opc == PPC::BCLR ||

505 Opc == PPC::BCLRn)

506Ret.FeedsBR = 1;

507Ret.FeedsLogical = isCRLogical(UseMI);

508if (UseMI.getParent() != MIParam.getParent())

509Ret.ContainedInBlock = 0;

510 }

511Ret.SingleUse =MRI->hasOneNonDBGUse(MIParam.getOperand(0).getReg()) ? 1 : 0;

512

513// We now know whether all the uses of the CR logical are in the same block.

514if (!Ret.IsNullary) {

515Ret.ContainedInBlock &=

516 (MIParam.getParent() ==Ret.TrueDefs.first->getParent());

517if (Ret.IsBinary)

518Ret.ContainedInBlock &=

519 (MIParam.getParent() ==Ret.TrueDefs.second->getParent());

520 }

521LLVM_DEBUG(Ret.dump());

522if (Ret.IsBinary &&Ret.ContainedInBlock &&Ret.SingleUse) {

523 NumContainedSingleUseBinOps++;

524if (Ret.FeedsBR &&Ret.DefsSingleUse)

525 NumToSplitBlocks++;

526 }

527returnRet;

528}

529

530/// Looks through a COPY instruction to the actual definition of the CR-bit

531/// register and returns the instruction that defines it.

532/// FIXME: This currently handles what is by-far the most common case:

533/// an instruction that defines a CR field followed by a single copy of a bit

534/// from that field into a virtual register. If chains of copies need to be

535/// handled, this should have a loop until a non-copy instruction is found.

536MachineInstr *PPCReduceCRLogicals::lookThroughCRCopy(unsigned Reg,

537unsigned &Subreg,

538MachineInstr *&CpDef) {

539 Subreg = -1;

540if (!Register::isVirtualRegister(Reg))

541returnnullptr;

542MachineInstr *Copy =MRI->getVRegDef(Reg);

543 CpDef =Copy;

544if (!Copy->isCopy())

545returnCopy;

546Register CopySrc =Copy->getOperand(1).getReg();

547 Subreg =Copy->getOperand(1).getSubReg();

548if (!CopySrc.isVirtual()) {

549constTargetRegisterInfo *TRI = &TII->getRegisterInfo();

550// Set the Subreg

551if (CopySrc == PPC::CR0EQ || CopySrc == PPC::CR6EQ)

552 Subreg = PPC::sub_eq;

553if (CopySrc == PPC::CR0LT || CopySrc == PPC::CR6LT)

554 Subreg = PPC::sub_lt;

555if (CopySrc == PPC::CR0GT || CopySrc == PPC::CR6GT)

556 Subreg = PPC::sub_gt;

557if (CopySrc == PPC::CR0UN || CopySrc == PPC::CR6UN)

558 Subreg = PPC::sub_un;

559// Loop backwards and return the first MI that modifies the physical CR Reg.

560MachineBasicBlock::iterator Me =Copy,B =Copy->getParent()->begin();

561while (Me !=B)

562if ((--Me)->modifiesRegister(CopySrc,TRI))

563return &*Me;

564returnnullptr;

565 }

566returnMRI->getVRegDef(CopySrc);

567}

568

569void PPCReduceCRLogicals::initialize(MachineFunction &MFParam) {

570 MF = &MFParam;

571MRI = &MF->getRegInfo();

572TII = MF->getSubtarget<PPCSubtarget>().getInstrInfo();

573 MBPI = &getAnalysis<MachineBranchProbabilityInfoWrapperPass>().getMBPI();

574

575 AllCRLogicalOps.clear();

576}

577

578/// Contains all the implemented transformations on CR logical operations.

579/// For example, a binary CR logical can be used to split a block on its inputs,

580/// a unary CR logical might be used to change the condition code on a

581/// comparison feeding it. A nullary CR logical might simply be removable

582/// if the user of the bit it [un]sets can be transformed.

583bool PPCReduceCRLogicals::handleCROp(unsignedIdx) {

584// We can definitely split a block on the inputs to a binary CR operation

585// whose defs and (single) use are within the same block.

586bool Changed =false;

587 CRLogicalOpInfo CRI = AllCRLogicalOps[Idx];

588if (CRI.IsBinary && CRI.ContainedInBlock && CRI.SingleUse && CRI.FeedsBR &&

589 CRI.DefsSingleUse) {

590 Changed = splitBlockOnBinaryCROp(CRI);

591if (Changed)

592 NumBlocksSplitOnBinaryCROp++;

593 }

594return Changed;

595}

596

597/// Splits a block that contains a CR-logical operation that feeds a branch

598/// and whose operands are produced within the block.

599/// Example:

600/// %vr5<def> = CMPDI %vr2, 0; CRRC:%vr5 G8RC:%vr2

601/// %vr6<def> = COPY %vr5:sub_eq; CRBITRC:%vr6 CRRC:%vr5

602/// %vr7<def> = CMPDI %vr3, 0; CRRC:%vr7 G8RC:%vr3

603/// %vr8<def> = COPY %vr7:sub_eq; CRBITRC:%vr8 CRRC:%vr7

604/// %vr9<def> = CROR %vr6<kill>, %vr8<kill>; CRBITRC:%vr9,%vr6,%vr8

605/// BC %vr9<kill>, <BB#2>; CRBITRC:%vr9

606/// Becomes:

607/// %vr5<def> = CMPDI %vr2, 0; CRRC:%vr5 G8RC:%vr2

608/// %vr6<def> = COPY %vr5:sub_eq; CRBITRC:%vr6 CRRC:%vr5

609/// BC %vr6<kill>, <BB#2>; CRBITRC:%vr6

610///

611/// %vr7<def> = CMPDI %vr3, 0; CRRC:%vr7 G8RC:%vr3

612/// %vr8<def> = COPY %vr7:sub_eq; CRBITRC:%vr8 CRRC:%vr7

613/// BC %vr9<kill>, <BB#2>; CRBITRC:%vr9

614bool PPCReduceCRLogicals::splitBlockOnBinaryCROp(CRLogicalOpInfo &CRI) {

615if (CRI.CopyDefs.first == CRI.CopyDefs.second) {

616LLVM_DEBUG(dbgs() <<"Unable to split as the two operands are the same\n");

617 NumNotSplitIdenticalOperands++;

618returnfalse;

619 }

620if (CRI.TrueDefs.first->isCopy() || CRI.TrueDefs.second->isCopy() ||

621 CRI.TrueDefs.first->isPHI() || CRI.TrueDefs.second->isPHI()) {

622LLVM_DEBUG(

623dbgs() <<"Unable to split because one of the operands is a PHI or "

624"chain of copies.\n");

625 NumNotSplitChainCopies++;

626returnfalse;

627 }

628// Note: keep in sync with computeBranchTargetAndInversion().

629if (CRI.MI->getOpcode() != PPC::CROR &&

630 CRI.MI->getOpcode() != PPC::CRAND &&

631 CRI.MI->getOpcode() != PPC::CRNOR &&

632 CRI.MI->getOpcode() != PPC::CRNAND &&

633 CRI.MI->getOpcode() != PPC::CRORC &&

634 CRI.MI->getOpcode() != PPC::CRANDC) {

635LLVM_DEBUG(dbgs() <<"Unable to split blocks on this opcode.\n");

636 NumNotSplitWrongOpcode++;

637returnfalse;

638 }

639LLVM_DEBUG(dbgs() <<"Splitting the following CR op:\n"; CRI.dump());

640MachineBasicBlock::iterator Def1It = CRI.TrueDefs.first;

641MachineBasicBlock::iterator Def2It = CRI.TrueDefs.second;

642

643bool UsingDef1 =false;

644MachineInstr *SplitBefore = &*Def2It;

645for (auto E = CRI.MI->getParent()->end(); Def2It != E; ++Def2It) {

646if (Def1It == Def2It) {// Def2 comes before Def1.

647 SplitBefore = &*Def1It;

648 UsingDef1 =true;

649break;

650 }

651 }

652

653LLVM_DEBUG(dbgs() <<"We will split the following block:\n";);

654LLVM_DEBUG(CRI.MI->getParent()->dump());

655LLVM_DEBUG(dbgs() <<"Before instruction:\n"; SplitBefore->dump());

656

657// Get the branch instruction.

658MachineInstr *Branch =

659MRI->use_nodbg_begin(CRI.MI->getOperand(0).getReg())->getParent();

660

661// We want the new block to have no code in it other than the definition

662// of the input to the CR logical and the CR logical itself. So we move

663// those to the bottom of the block (just before the branch). Then we

664// will split before the CR logical.

665MachineBasicBlock *MBB = SplitBefore->getParent();

666auto FirstTerminator =MBB->getFirstTerminator();

667MachineBasicBlock::iterator FirstInstrToMove =

668 UsingDef1 ? CRI.TrueDefs.first : CRI.TrueDefs.second;

669MachineBasicBlock::iterator SecondInstrToMove =

670 UsingDef1 ? CRI.CopyDefs.first : CRI.CopyDefs.second;

671

672// The instructions that need to be moved are not guaranteed to be

673// contiguous. Move them individually.

674// FIXME: If one of the operands is a chain of (single use) copies, they

675// can all be moved and we can still split.

676MBB->splice(FirstTerminator,MBB, FirstInstrToMove);

677if (FirstInstrToMove != SecondInstrToMove)

678MBB->splice(FirstTerminator,MBB, SecondInstrToMove);

679MBB->splice(FirstTerminator,MBB, CRI.MI);

680

681unsigned Opc = CRI.MI->getOpcode();

682bool InvertOrigBranch, InvertNewBranch, TargetIsFallThrough;

683computeBranchTargetAndInversion(Opc,Branch->getOpcode(), UsingDef1,

684 InvertNewBranch, InvertOrigBranch,

685 TargetIsFallThrough);

686MachineInstr *SplitCond =

687 UsingDef1 ? CRI.CopyDefs.second : CRI.CopyDefs.first;

688LLVM_DEBUG(dbgs() <<"We will " << (InvertNewBranch ?"invert" :"copy"));

689LLVM_DEBUG(dbgs() <<" the original branch and the target is the "

690 << (TargetIsFallThrough ?"fallthrough block\n"

691 :"orig. target block\n"));

692LLVM_DEBUG(dbgs() <<"Original branch instruction: ";Branch->dump());

693BlockSplitInfo BSI {Branch, SplitBefore, SplitCond, InvertNewBranch,

694 InvertOrigBranch, TargetIsFallThrough, MBPI, CRI.MI,

695 UsingDef1 ? CRI.CopyDefs.first : CRI.CopyDefs.second };

696bool Changed =splitMBB(BSI);

697// If we've split on a CR logical that is fed by a CR logical,

698// recompute the source CR logical as it may be usable for splitting.

699if (Changed) {

700bool Input1CRlogical =

701 CRI.TrueDefs.first && isCRLogical(*CRI.TrueDefs.first);

702bool Input2CRlogical =

703 CRI.TrueDefs.second && isCRLogical(*CRI.TrueDefs.second);

704if (Input1CRlogical)

705 AllCRLogicalOps.push_back(createCRLogicalOpInfo(*CRI.TrueDefs.first));

706if (Input2CRlogical)

707 AllCRLogicalOps.push_back(createCRLogicalOpInfo(*CRI.TrueDefs.second));

708 }

709return Changed;

710}

711

712void PPCReduceCRLogicals::collectCRLogicals() {

713for (MachineBasicBlock &MBB : *MF) {

714for (MachineInstr &MI :MBB) {

715if (isCRLogical(MI)) {

716 AllCRLogicalOps.push_back(createCRLogicalOpInfo(MI));

717 TotalCRLogicals++;

718if (AllCRLogicalOps.back().IsNullary)

719 TotalNullaryCRLogicals++;

720elseif (AllCRLogicalOps.back().IsBinary)

721 TotalBinaryCRLogicals++;

722else

723 TotalUnaryCRLogicals++;

724 }

725 }

726 }

727}

728

729}// end anonymous namespace

730

731INITIALIZE_PASS_BEGIN(PPCReduceCRLogicals,DEBUG_TYPE,

732"PowerPC Reduce CR logical Operation",false,false)

733INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)

734INITIALIZE_PASS_END(PPCReduceCRLogicals,DEBUG_TYPE,

735 "PowerPC Reduce CR logicalOperation",false,false)

736

737char PPCReduceCRLogicals::ID = 0;

738FunctionPass*

739llvm::createPPCReduceCRLogicalsPass() {returnnew PPCReduceCRLogicals(); }

MRI

unsigned const MachineRegisterInfo * MRI

Definition:AArch64AdvSIMDScalarPass.cpp:105

UseMI

MachineInstrBuilder & UseMI

Definition:AArch64ExpandPseudoInsts.cpp:112

DefMI

MachineInstrBuilder MachineInstrBuilder & DefMI

Definition:AArch64ExpandPseudoInsts.cpp:113

MBB

MachineBasicBlock & MBB

Definition:ARMSLSHardening.cpp:71

MBBI

MachineBasicBlock MachineBasicBlock::iterator MBBI

Definition:ARMSLSHardening.cpp:72

static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")

LLVM_DUMP_METHOD

#define LLVM_DUMP_METHOD

Mark debug helper function definitions like dump() that should not be stripped from debug builds.

Definition:Compiler.h:622

Idx

Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx

Definition:DeadArgumentElimination.cpp:353

Debug.h

LLVM_DEBUG

#define LLVM_DEBUG(...)

Definition:Debug.h:106

TII

const HexagonInstrInfo * TII

Definition:HexagonCopyToCombine.cpp:125

IRTranslator LLVM IR MI

Definition:IRTranslator.cpp:112

InitializePasses.h

MachineBranchProbabilityInfo.h

MachineDominators.h

MachineFunctionPass.h

MachineInstrBuilder.h

MachineRegisterInfo.h

TRI

unsigned const TargetRegisterInfo * TRI

Definition:MachineSink.cpp:2029

PPCInstrInfo.h

isBinary

static bool isBinary(MachineInstr &MI)

Definition:PPCReduceCRLogicals.cpp:253

Operation

PowerPC Reduce CR logical Operation

Definition:PPCReduceCRLogicals.cpp:735

isNullary

static bool isNullary(MachineInstr &MI)

Definition:PPCReduceCRLogicals.cpp:257

splitMBB

static bool splitMBB(BlockSplitInfo &BSI)

Splits a MachineBasicBlock to branch before SplitBefore.

Definition:PPCReduceCRLogicals.cpp:140

computeBranchTargetAndInversion

static void computeBranchTargetAndInversion(unsigned CROp, unsigned BROp, bool UsingDef1, bool &InvertNewBranch, bool &InvertOrigBranch, bool &TargetIsFallThrough)

Given a CR logical operation CROp, branch opcode BROp as well as a flag to indicate if the first oper...

Definition:PPCReduceCRLogicals.cpp:267

addIncomingValuesToPHIs

static void addIncomingValuesToPHIs(MachineBasicBlock *Successor, MachineBasicBlock *OrigMBB, MachineBasicBlock *NewMBB, MachineRegisterInfo *MRI)

Given a basic block Successor that potentially contains PHIs, this function will look for PHIs that h...

Definition:PPCReduceCRLogicals.cpp:85

updatePHIs

static void updatePHIs(MachineBasicBlock *Successor, MachineBasicBlock *OrigMBB, MachineBasicBlock *NewMBB, MachineRegisterInfo *MRI)

Given a basic block Successor that potentially contains PHIs, this function will look for any incomin...

Definition:PPCReduceCRLogicals.cpp:56

DEBUG_TYPE

#define DEBUG_TYPE

Definition:PPCReduceCRLogicals.cpp:32

PPCTargetMachine.h

PPC.h

INITIALIZE_PASS_DEPENDENCY

#define INITIALIZE_PASS_DEPENDENCY(depName)

Definition:PassSupport.h:55

INITIALIZE_PASS_END

#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)

Definition:PassSupport.h:57

INITIALIZE_PASS_BEGIN

#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)

Definition:PassSupport.h:52

assert

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

Statistic.h

This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...

STATISTIC

#define STATISTIC(VARNAME, DESC)

Definition:Statistic.h:166

initialize

static void initialize(TargetLibraryInfoImpl &TLI, const Triple &T, ArrayRef< StringLiteral > StandardNames)

Initialize the set of available library functions based on the specified target triple.

Definition:TargetLibraryInfo.cpp:917

llvm::AnalysisUsage

Represent the analysis usage information of a pass.

Definition:PassAnalysisSupport.h:47

llvm::AnalysisUsage::addRequired

AnalysisUsage & addRequired()

Definition:PassAnalysisSupport.h:75

llvm::BasicBlock

LLVM Basic Block Representation.

Definition:BasicBlock.h:61

llvm::BranchProbability

Definition:BranchProbability.h:30

llvm::BranchProbability::getUnknown

static BranchProbability getUnknown()

Definition:BranchProbability.h:51

llvm::BranchProbability::isUnknown

bool isUnknown() const

Definition:BranchProbability.h:47

llvm::BranchProbability::getCompl

BranchProbability getCompl() const

Definition:BranchProbability.h:69

llvm::FunctionPass

FunctionPass class - This class is used to implement most global optimizations.

Definition:Pass.h:310

llvm::FunctionPass::skipFunction

bool skipFunction(const Function &F) const

Optional passes call this function to check whether the pass should be skipped.

Definition:Pass.cpp:178

llvm::MachineBasicBlock

Definition:MachineBasicBlock.h:125

llvm::MachineBasicBlock::transferSuccessors

void transferSuccessors(MachineBasicBlock *FromMBB)

Transfers all the successors from MBB to this machine basic block (i.e., copies all the successors Fr...

Definition:MachineBasicBlock.cpp:917

llvm::MachineBasicBlock::getBasicBlock

const BasicBlock * getBasicBlock() const

Return the LLVM basic block that this instance corresponded to originally.

Definition:MachineBasicBlock.h:256

llvm::MachineBasicBlock::setSuccProbability

void setSuccProbability(succ_iterator I, BranchProbability Prob)

Set successor probability of a given iterator.

Definition:MachineBasicBlock.cpp:1598

llvm::MachineBasicBlock::succ_begin

succ_iterator succ_begin()

Definition:MachineBasicBlock.h:421

llvm::MachineBasicBlock::getFirstTerminator

iterator getFirstTerminator()

Returns an iterator to the first terminator instruction of this basic block.

Definition:MachineBasicBlock.cpp:244

llvm::MachineBasicBlock::succ_size

unsigned succ_size() const

Definition:MachineBasicBlock.h:433

llvm::MachineBasicBlock::dump

void dump() const

Definition:MachineBasicBlock.cpp:301

llvm::MachineBasicBlock::addSuccessor

void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())

Add Succ as a successor of this MachineBasicBlock.

Definition:MachineBasicBlock.cpp:798

llvm::MachineBasicBlock::succ_rbegin

succ_reverse_iterator succ_rbegin()

Definition:MachineBasicBlock.h:425

llvm::MachineBasicBlock::end

iterator end()

Definition:MachineBasicBlock.h:357

llvm::MachineBasicBlock::getParent

const MachineFunction * getParent() const

Return the MachineFunction containing this basic block.

Definition:MachineBasicBlock.h:311

llvm::MachineBasicBlock::successors

iterator_range< succ_iterator > successors()

Definition:MachineBasicBlock.h:444

llvm::MachineBasicBlock::isSuccessor

bool isSuccessor(const MachineBasicBlock *MBB) const

Return true if the specified MBB is a successor of this block.

Definition:MachineBasicBlock.cpp:960

llvm::MachineBasicBlock::splice

void splice(iterator Where, MachineBasicBlock *Other, iterator From)

Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...

Definition:MachineBasicBlock.h:1109

llvm::MachineBranchProbabilityInfoWrapperPass

Definition:MachineBranchProbabilityInfo.h:80

llvm::MachineBranchProbabilityInfo

Definition:MachineBranchProbabilityInfo.h:23

llvm::MachineBranchProbabilityInfo::getEdgeProbability

BranchProbability getEdgeProbability(const MachineBasicBlock *Src, const MachineBasicBlock *Dst) const

Definition:MachineBranchProbabilityInfo.cpp:88

llvm::MachineDominatorTreeWrapperPass

Analysis pass which computes a MachineDominatorTree.

Definition:MachineDominators.h:131

llvm::MachineFunctionPass

MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...

Definition:MachineFunctionPass.h:30

llvm::MachineFunctionPass::getAnalysisUsage

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

Definition:MachineFunctionPass.cpp:169

llvm::MachineFunctionPass::runOnMachineFunction

virtual bool runOnMachineFunction(MachineFunction &MF)=0

runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...

llvm::MachineFunction

Definition:MachineFunction.h:267

llvm::MachineFunction::getSubtarget

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

Definition:MachineFunction.h:733

llvm::MachineFunction::getRegInfo

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

Definition:MachineFunction.h:743

llvm::MachineFunction::getFunction

Function & getFunction()

Return the LLVM function that this machine code represents.

Definition:MachineFunction.h:704

llvm::MachineFunction::CreateMachineBasicBlock

MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *BB=nullptr, std::optional< UniqueBBID > BBID=std::nullopt)

CreateMachineBasicBlock - Allocate a new MachineBasicBlock.

Definition:MachineFunction.cpp:499

llvm::MachineFunction::insert

void insert(iterator MBBI, MachineBasicBlock *MBB)

Definition:MachineFunction.h:966

llvm::MachineInstrBuilder

Definition:MachineInstrBuilder.h:71

llvm::MachineInstrBuilder::addReg

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

Definition:MachineInstrBuilder.h:99

llvm::MachineInstrBuilder::addMBB

const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const

Definition:MachineInstrBuilder.h:148

llvm::MachineInstrBundleIterator< MachineInstr >

llvm::MachineInstr

Representation of each machine instruction.

Definition:MachineInstr.h:71

llvm::MachineInstr::getOpcode

unsigned getOpcode() const

Returns the opcode of this MachineInstr.

Definition:MachineInstr.h:577

llvm::MachineInstr::getParent

const MachineBasicBlock * getParent() const

Definition:MachineInstr.h:349

llvm::MachineInstr::getDebugLoc

const DebugLoc & getDebugLoc() const

Returns the debug location id of this MachineInstr.

Definition:MachineInstr.h:501

llvm::MachineInstr::eraseFromParent

void eraseFromParent()

Unlink 'this' from the containing basic block and delete it.

Definition:MachineInstr.cpp:767

llvm::MachineInstr::dump

void dump() const

Definition:MachineInstr.cpp:1695

llvm::MachineInstr::getOperand

const MachineOperand & getOperand(unsigned i) const

Definition:MachineInstr.h:587

llvm::MachineOperand

MachineOperand class - Representation of each machine instruction operand.

Definition:MachineOperand.h:48

llvm::MachineOperand::getMBB

MachineBasicBlock * getMBB() const

Definition:MachineOperand.h:571

llvm::MachineOperand::setMBB

void setMBB(MachineBasicBlock *MBB)

Definition:MachineOperand.h:728

llvm::MachineOperand::getReg

getReg - Returns the register number.

Definition:MachineOperand.h:369

llvm::MachineRegisterInfo

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

Definition:MachineRegisterInfo.h:51

llvm::PPCInstrInfo

Definition:PPCInstrInfo.h:175

llvm::PPCSubtarget

Definition:PPCSubtarget.h:72

llvm::PassRegistry::getPassRegistry

static PassRegistry * getPassRegistry()

getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...

Definition:PassRegistry.cpp:24

llvm::Pass::dump

void dump() const

Definition:Pass.cpp:136

llvm::Register

Wrapper class representing virtual and physical registers.

Definition:Register.h:19

llvm::Register::isVirtual

constexpr bool isVirtual() const

Return true if the specified register number is in the virtual register namespace.

Definition:Register.h:91

llvm::Register::isVirtualRegister

static constexpr bool isVirtualRegister(unsigned Reg)

Return true if the specified register number is in the virtual register namespace.

Definition:Register.h:71

llvm::SmallVectorBase::size

size_t size() const

Definition:SmallVector.h:78

llvm::SmallVectorImpl::clear

void clear()

Definition:SmallVector.h:610

llvm::SmallVectorTemplateBase::push_back

void push_back(const T &Elt)

Definition:SmallVector.h:413

llvm::SmallVectorTemplateCommon::back

reference back()

Definition:SmallVector.h:308

llvm::SmallVector

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

Definition:SmallVector.h:1196

llvm::TargetRegisterInfo

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

Definition:TargetRegisterInfo.h:235

llvm::ilist_node_impl::getIterator

self_iterator getIterator()

Definition:ilist_node.h:132

unsigned

llvm_unreachable

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

Definition:ErrorHandling.h:143

false

Definition:StackSlotColoring.cpp:193

llvm::CallingConv::ID

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

Definition:CallingConv.h:24

llvm::MCID::Branch

@ Branch

Definition:MCInstrDesc.h:159

llvm::MipsISD::Ret

@ Ret

Definition:MipsISelLowering.h:117

llvm::codeview::FrameCookieKind::Copy

@ Copy

llvm

This is an optimization pass for GlobalISel generic memory operations.

Definition:AddressRanges.h:18

llvm::dump

void dump(const SparseBitVector< ElementSize > &LHS, raw_ostream &out)

Definition:SparseBitVector.h:877

llvm::find

auto find(R &&Range, const T &Val)

Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly.

Definition:STLExtras.h:1759

llvm::BuildMI

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

Definition:MachineInstrBuilder.h:373

llvm::Successor

@ Successor

Definition:SIMachineScheduler.h:35

llvm::initializePPCReduceCRLogicalsPass

void initializePPCReduceCRLogicalsPass(PassRegistry &)

llvm::dbgs

raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

Definition:Debug.cpp:163

llvm::createPPCReduceCRLogicalsPass

FunctionPass * createPPCReduceCRLogicalsPass()

Definition:PPCReduceCRLogicals.cpp:739

BlockSplitInfo

Definition:PPCReduceCRLogicals.cpp:107

BlockSplitInfo::SplitBefore

MachineInstr * SplitBefore

Definition:PPCReduceCRLogicals.cpp:109

BlockSplitInfo::SplitCond

MachineInstr * SplitCond

Definition:PPCReduceCRLogicals.cpp:110

BlockSplitInfo::OrigBranch

MachineInstr * OrigBranch

Definition:PPCReduceCRLogicals.cpp:108

BlockSplitInfo::MIToDelete

MachineInstr * MIToDelete

Definition:PPCReduceCRLogicals.cpp:115

BlockSplitInfo::NewCond

MachineInstr * NewCond

Definition:PPCReduceCRLogicals.cpp:116

BlockSplitInfo::InvertNewBranch

bool InvertNewBranch

Definition:PPCReduceCRLogicals.cpp:111

BlockSplitInfo::allInstrsInSameMBB

bool allInstrsInSameMBB()

Definition:PPCReduceCRLogicals.cpp:117

BlockSplitInfo::InvertOrigBranch

bool InvertOrigBranch

Definition:PPCReduceCRLogicals.cpp:112

BlockSplitInfo::MBPI

const MachineBranchProbabilityInfo * MBPI

Definition:PPCReduceCRLogicals.cpp:114

BlockSplitInfo::BranchToFallThrough

bool BranchToFallThrough

Definition:PPCReduceCRLogicals.cpp:113