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1//===- PPCInstructionSelector.cpp --------------------------------*- C++ -*-==//

2//

3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.

4// See https://llvm.org/LICENSE.txt for license information.

5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception

6//

7//===----------------------------------------------------------------------===//

8/// \file

9/// This file implements the targeting of the InstructionSelector class for

10/// PowerPC.

11//===----------------------------------------------------------------------===//

13#include "PPC.h"

14#include "PPCInstrInfo.h"

15#include "PPCMachineFunctionInfo.h"

16#include "PPCRegisterBankInfo.h"

17#include "PPCSubtarget.h"

18#include "PPCTargetMachine.h"

19#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h"

20#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"

21#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"

22#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"

23#include "llvm/CodeGen/MachineConstantPool.h"

24#include "llvm/CodeGen/MachineFunction.h"

25#include "llvm/IR/IntrinsicsPowerPC.h"

26#include "llvm/Support/Debug.h"

28#define DEBUG_TYPE "ppc-gisel"

30using namespacellvm;

32namespace{

34#define GET_GLOBALISEL_PREDICATE_BITSET

35#include "PPCGenGlobalISel.inc"

36#undef GET_GLOBALISEL_PREDICATE_BITSET

38classPPCInstructionSelector :publicInstructionSelector {

39public:

40 PPCInstructionSelector(constPPCTargetMachine &TM,constPPCSubtarget &STI,

41constPPCRegisterBankInfo &RBI);

43boolselect(MachineInstr &I)override;

44staticconstchar *getName() {returnDEBUG_TYPE; }

46private:

47 /// tblgen generated 'select' implementation that is used as the initial

48 /// selector for the patterns that do not require complex C++.

49bool selectImpl(MachineInstr &I,CodeGenCoverage &CoverageInfo)const;

51bool selectFPToInt(MachineInstr &I,MachineBasicBlock &MBB,

52MachineRegisterInfo &MRI)const;

53bool selectIntToFP(MachineInstr &I,MachineBasicBlock &MBB,

54MachineRegisterInfo &MRI)const;

56bool selectZExt(MachineInstr &I,MachineBasicBlock &MBB,

57MachineRegisterInfo &MRI)const;

58bool selectConstantPool(MachineInstr &I,MachineBasicBlock &MBB,

59MachineRegisterInfo &MRI)const;

61 std::optional<bool>selectI64ImmDirect(MachineInstr &I,

62MachineBasicBlock &MBB,

63MachineRegisterInfo &MRI,Register Reg,

64uint64_t Imm)const;

65boolselectI64Imm(MachineInstr &I,MachineBasicBlock &MBB,

66MachineRegisterInfo &MRI)const;

68constPPCTargetMachine &TM;

69constPPCSubtarget &STI;

70constPPCInstrInfo &TII;

71constPPCRegisterInfo &TRI;

72constPPCRegisterBankInfo &RBI;

74#define GET_GLOBALISEL_PREDICATES_DECL

75#include "PPCGenGlobalISel.inc"

76#undef GET_GLOBALISEL_PREDICATES_DECL

78#define GET_GLOBALISEL_TEMPORARIES_DECL

79#include "PPCGenGlobalISel.inc"

80#undef GET_GLOBALISEL_TEMPORARIES_DECL

81};

83}// end anonymous namespace

85#define GET_GLOBALISEL_IMPL

86#include "PPCGenGlobalISel.inc"

87#undef GET_GLOBALISEL_IMPL

89PPCInstructionSelector::PPCInstructionSelector(constPPCTargetMachine &TM,

90constPPCSubtarget &STI,

91constPPCRegisterBankInfo &RBI)

92 : TM(TM), STI(STI),TII(*STI.getInstrInfo()),TRI(*STI.getRegisterInfo()),

93 RBI(RBI),

94#defineGET_GLOBALISEL_PREDICATES_INIT

95#include"PPCGenGlobalISel.inc"

96#undefGET_GLOBALISEL_PREDICATES_INIT

97#defineGET_GLOBALISEL_TEMPORARIES_INIT

98#include"PPCGenGlobalISel.inc"

99#undefGET_GLOBALISEL_TEMPORARIES_INIT

100{

101}

102

103staticconstTargetRegisterClass *getRegClass(LLT Ty,constRegisterBank *RB) {

104if (RB->getID() == PPC::GPRRegBankID) {

105if (Ty.getSizeInBits() == 64)

106return &PPC::G8RCRegClass;

107if (Ty.getSizeInBits() <= 32)

108return &PPC::GPRCRegClass;

109 }

110if (RB->getID() == PPC::FPRRegBankID) {

111if (Ty.getSizeInBits() == 32)

112return &PPC::F4RCRegClass;

113if (Ty.getSizeInBits() == 64)

114return &PPC::F8RCRegClass;

115 }

116if (RB->getID() == PPC::VECRegBankID) {

117if (Ty.getSizeInBits() == 128)

118return &PPC::VSRCRegClass;

119 }

120if (RB->getID() == PPC::CRRegBankID) {

121if (Ty.getSizeInBits() == 1)

122return &PPC::CRBITRCRegClass;

123if (Ty.getSizeInBits() == 4)

124return &PPC::CRRCRegClass;

125 }

126

127llvm_unreachable("Unknown RegBank!");

128}

129

130staticboolselectCopy(MachineInstr &I,constTargetInstrInfo &TII,

131MachineRegisterInfo &MRI,constTargetRegisterInfo &TRI,

132constRegisterBankInfo &RBI) {

133Register DstReg =I.getOperand(0).getReg();

134

135if (DstReg.isPhysical())

136returntrue;

137

138constRegisterBank *DstRegBank = RBI.getRegBank(DstReg,MRI,TRI);

139constTargetRegisterClass *DstRC =

140getRegClass(MRI.getType(DstReg), DstRegBank);

141

142// No need to constrain SrcReg. It will get constrained when we hit another of

143// its use or its defs.

144// Copies do not have constraints.

145if (!RBI.constrainGenericRegister(DstReg, *DstRC,MRI)) {

146LLVM_DEBUG(dbgs() <<"Failed to constrain " <<TII.getName(I.getOpcode())

147 <<" operand\n");

148returnfalse;

149 }

150

151returntrue;

152}

153

154staticunsignedselectLoadStoreOp(unsigned GenericOpc,unsigned RegBankID,

155unsigned OpSize) {

156constbool IsStore = GenericOpc == TargetOpcode::G_STORE;

157switch (RegBankID) {

158case PPC::GPRRegBankID:

159switch (OpSize) {

160case 32:

161return IsStore ? PPC::STW : PPC::LWZ;

162case 64:

163return IsStore ? PPC::STD : PPC::LD;

164default:

165llvm_unreachable("Unexpected size!");

166 }

167break;

168case PPC::FPRRegBankID:

169switch (OpSize) {

170case 32:

171return IsStore ? PPC::STFS : PPC::LFS;

172case 64:

173return IsStore ? PPC::STFD : PPC::LFD;

174default:

175llvm_unreachable("Unexpected size!");

176 }

177break;

178default:

179llvm_unreachable("Unexpected register bank!");

180 }

181return GenericOpc;

182}

183

184bool PPCInstructionSelector::selectIntToFP(MachineInstr &I,

185MachineBasicBlock &MBB,

186MachineRegisterInfo &MRI) const{

187if (!STI.hasDirectMove() || !STI.isPPC64() || !STI.hasFPCVT())

188returnfalse;

189

190constDebugLoc &DbgLoc =I.getDebugLoc();

191constRegister DstReg =I.getOperand(0).getReg();

192constRegister SrcReg =I.getOperand(1).getReg();

193

194Register MoveReg =MRI.createVirtualRegister(&PPC::VSFRCRegClass);

195

196// For now, only handle the case for 64 bit integer.

197BuildMI(MBB,I, DbgLoc,TII.get(PPC::MTVSRD), MoveReg).addReg(SrcReg);

198

199bool IsSingle =MRI.getType(DstReg).getSizeInBits() == 32;

200bool IsSigned =I.getOpcode() == TargetOpcode::G_SITOFP;

201unsigned ConvOp = IsSingle ? (IsSigned ? PPC::XSCVSXDSP : PPC::XSCVUXDSP)

202 : (IsSigned ? PPC::XSCVSXDDP : PPC::XSCVUXDDP);

203

204MachineInstr *MI =

205BuildMI(MBB,I, DbgLoc,TII.get(ConvOp), DstReg).addReg(MoveReg);

206

207I.eraseFromParent();

208returnconstrainSelectedInstRegOperands(*MI,TII,TRI, RBI);

209}

210

211bool PPCInstructionSelector::selectFPToInt(MachineInstr &I,

212MachineBasicBlock &MBB,

213MachineRegisterInfo &MRI) const{

214if (!STI.hasDirectMove() || !STI.isPPC64() || !STI.hasFPCVT())

215returnfalse;

216

217constDebugLoc &DbgLoc =I.getDebugLoc();

218constRegister DstReg =I.getOperand(0).getReg();

219constRegister SrcReg =I.getOperand(1).getReg();

220

221Register CopyReg =MRI.createVirtualRegister(&PPC::VSFRCRegClass);

222BuildMI(MBB,I, DbgLoc,TII.get(TargetOpcode::COPY), CopyReg).addReg(SrcReg);

223

224Register ConvReg =MRI.createVirtualRegister(&PPC::VSFRCRegClass);

225

226bool IsSigned =I.getOpcode() == TargetOpcode::G_FPTOSI;

227

228// single-precision is stored as double-precision on PPC in registers, so

229// always use double-precision convertions.

230unsigned ConvOp = IsSigned ? PPC::XSCVDPSXDS : PPC::XSCVDPUXDS;

231

232BuildMI(MBB,I, DbgLoc,TII.get(ConvOp), ConvReg).addReg(CopyReg);

233

234MachineInstr *MI =

235BuildMI(MBB,I, DbgLoc,TII.get(PPC::MFVSRD), DstReg).addReg(ConvReg);

236

237I.eraseFromParent();

238returnconstrainSelectedInstRegOperands(*MI,TII,TRI, RBI);

239}

240

241bool PPCInstructionSelector::selectZExt(MachineInstr &I,MachineBasicBlock &MBB,

242MachineRegisterInfo &MRI) const{

243constRegister DstReg =I.getOperand(0).getReg();

244constLLT DstTy =MRI.getType(DstReg);

245constRegisterBank *DstRegBank = RBI.getRegBank(DstReg,MRI,TRI);

246

247constRegister SrcReg =I.getOperand(1).getReg();

248

249assert(DstTy.getSizeInBits() == 64 &&"Unexpected dest size!");

250assert(MRI.getType(SrcReg).getSizeInBits() == 32 &&"Unexpected src size!");

251

252Register ImpDefReg =

253MRI.createVirtualRegister(getRegClass(DstTy, DstRegBank));

254BuildMI(MBB,I,I.getDebugLoc(),TII.get(TargetOpcode::IMPLICIT_DEF),

255 ImpDefReg);

256

257Register NewDefReg =

258MRI.createVirtualRegister(getRegClass(DstTy, DstRegBank));

259BuildMI(MBB,I,I.getDebugLoc(),TII.get(TargetOpcode::INSERT_SUBREG),

260 NewDefReg)

261 .addReg(ImpDefReg)

262 .addReg(SrcReg)

263 .addImm(PPC::sub_32);

264

265MachineInstr *MI =

266BuildMI(MBB,I,I.getDebugLoc(),TII.get(PPC::RLDICL), DstReg)

267 .addReg(NewDefReg)

268 .addImm(0)

269 .addImm(32);

270

271I.eraseFromParent();

272returnconstrainSelectedInstRegOperands(*MI,TII,TRI, RBI);

273}

274

275// For any 32 < Num < 64, check if the Imm contains at least Num consecutive

276// zeros and return the number of bits by the left of these consecutive zeros.

277staticuint32_t findContiguousZerosAtLeast(uint64_t Imm,unsigned Num) {

278uint32_t HiTZ = llvm::countr_zero<uint32_t>(Hi_32(Imm));

279uint32_t LoLZ = llvm::countl_zero<uint32_t>(Lo_32(Imm));

280if ((HiTZ + LoLZ) >= Num)

281return (32 + HiTZ);

282return 0;

283}

284

285// Direct materialization of 64-bit constants by enumerated patterns.

286// Similar to PPCISelDAGToDAG::selectI64ImmDirect().

287std::optional<bool> PPCInstructionSelector::selectI64ImmDirect(MachineInstr &I,

288MachineBasicBlock &MBB,

289MachineRegisterInfo &MRI,

290Register Reg,

291uint64_t Imm) const{

292unsigned TZ = llvm::countr_zero<uint64_t>(Imm);

293unsigned LZ = llvm::countl_zero<uint64_t>(Imm);

294unsigned TO = llvm::countr_one<uint64_t>(Imm);

295unsignedLO = llvm::countl_one<uint64_t>(Imm);

296uint32_t Hi32 =Hi_32(Imm);

297uint32_t Lo32 =Lo_32(Imm);

298uint32_t Shift = 0;

299

300// Following patterns use 1 instructions to materialize the Imm.

301

302// 1-1) Patterns : {zeros}{15-bit valve}

303// {ones}{15-bit valve}

304if (isInt<16>(Imm))

305returnBuildMI(MBB,I,I.getDebugLoc(),TII.get(PPC::LI8), Reg)

306 .addImm(Imm)

307 .constrainAllUses(TII,TRI, RBI);

308// 1-2) Patterns : {zeros}{15-bit valve}{16 zeros}

309// {ones}{15-bit valve}{16 zeros}

310if (TZ > 15 && (LZ > 32 || LO > 32))

311returnBuildMI(MBB,I,I.getDebugLoc(),TII.get(PPC::LIS8), Reg)

312 .addImm((Imm >> 16) & 0xffff)

313 .constrainAllUses(TII,TRI, RBI);

314

315// Following patterns use 2 instructions to materialize the Imm.

316

317assert(LZ < 64 &&"Unexpected leading zeros here.");

318// Count of ones follwing the leading zeros.

319unsigned FO = llvm::countl_one<uint64_t>(Imm << LZ);

320// 2-1) Patterns : {zeros}{31-bit value}

321// {ones}{31-bit value}

322if (isInt<32>(Imm)) {

323uint64_t ImmHi16 = (Imm >> 16) & 0xffff;

324unsigned Opcode = ImmHi16 ? PPC::LIS8 : PPC::LI8;

325Register TmpReg =MRI.createVirtualRegister(&PPC::G8RCRegClass);

326if (!BuildMI(MBB,I,I.getDebugLoc(),TII.get(Opcode), TmpReg)

327 .addImm((Imm >> 16) & 0xffff)

328 .constrainAllUses(TII,TRI, RBI))

329returnfalse;

330returnBuildMI(MBB,I,I.getDebugLoc(),TII.get(PPC::ORI8), Reg)

331 .addReg(TmpReg,RegState::Kill)

332 .addImm(Imm & 0xffff)

333 .constrainAllUses(TII,TRI, RBI);

334 }

335// 2-2) Patterns : {zeros}{ones}{15-bit value}{zeros}

336// {zeros}{15-bit value}{zeros}

337// {zeros}{ones}{15-bit value}

338// {ones}{15-bit value}{zeros}

339// We can take advantage of LI's sign-extension semantics to generate leading

340// ones, and then use RLDIC to mask off the ones in both sides after rotation.

341if ((LZ + FO + TZ) > 48) {

342Register TmpReg =MRI.createVirtualRegister(&PPC::G8RCRegClass);

343if (!BuildMI(MBB,I,I.getDebugLoc(),TII.get(PPC::LI8), TmpReg)

344 .addImm((Imm >> TZ) & 0xffff)

345 .constrainAllUses(TII,TRI, RBI))

346returnfalse;

347returnBuildMI(MBB,I,I.getDebugLoc(),TII.get(PPC::RLDIC), Reg)

348 .addReg(TmpReg,RegState::Kill)

349 .addImm(TZ)

350 .addImm(LZ)

351 .constrainAllUses(TII,TRI, RBI);

352 }

353// 2-3) Pattern : {zeros}{15-bit value}{ones}

354// Shift right the Imm by (48 - LZ) bits to construct a negtive 16 bits value,

355// therefore we can take advantage of LI's sign-extension semantics, and then

356// mask them off after rotation.

357//

358// +--LZ--||-15-bit-||--TO--+ +-------------|--16-bit--+

359// |00000001bbbbbbbbb1111111| -> |00000000000001bbbbbbbbb1|

360// +------------------------+ +------------------------+

361// 63 0 63 0

362// Imm (Imm >> (48 - LZ) & 0xffff)

363// +----sext-----|--16-bit--+ +clear-|-----------------+

364// |11111111111111bbbbbbbbb1| -> |00000001bbbbbbbbb1111111|

365// +------------------------+ +------------------------+

366// 63 0 63 0

367// LI8: sext many leading zeros RLDICL: rotate left (48 - LZ), clear left LZ

368if ((LZ + TO) > 48) {

369// Since the immediates with (LZ > 32) have been handled by previous

370// patterns, here we have (LZ <= 32) to make sure we will not shift right

371// the Imm by a negative value.

372assert(LZ <= 32 &&"Unexpected shift value.");

373Register TmpReg =MRI.createVirtualRegister(&PPC::G8RCRegClass);

374if (!BuildMI(MBB,I,I.getDebugLoc(),TII.get(PPC::LI8), TmpReg)

375 .addImm(Imm >> (48 - LZ) & 0xffff)

376 .constrainAllUses(TII,TRI, RBI))

377returnfalse;

378returnBuildMI(MBB,I,I.getDebugLoc(),TII.get(PPC::RLDICL), Reg)

379 .addReg(TmpReg,RegState::Kill)

380 .addImm(48 - LZ)

381 .addImm(LZ)

382 .constrainAllUses(TII,TRI, RBI);

383 }

384// 2-4) Patterns : {zeros}{ones}{15-bit value}{ones}

385// {ones}{15-bit value}{ones}

386// We can take advantage of LI's sign-extension semantics to generate leading

387// ones, and then use RLDICL to mask off the ones in left sides (if required)

388// after rotation.

389//

390// +-LZ-FO||-15-bit-||--TO--+ +-------------|--16-bit--+

391// |00011110bbbbbbbbb1111111| -> |000000000011110bbbbbbbbb|

392// +------------------------+ +------------------------+

393// 63 0 63 0

394// Imm (Imm >> TO) & 0xffff

395// +----sext-----|--16-bit--+ +LZ|---------------------+

396// |111111111111110bbbbbbbbb| -> |00011110bbbbbbbbb1111111|

397// +------------------------+ +------------------------+

398// 63 0 63 0

399// LI8: sext many leading zeros RLDICL: rotate left TO, clear left LZ

400if ((LZ + FO + TO) > 48) {

401Register TmpReg =MRI.createVirtualRegister(&PPC::G8RCRegClass);

402if (!BuildMI(MBB,I,I.getDebugLoc(),TII.get(PPC::LI8), TmpReg)

403 .addImm((Imm >> TO) & 0xffff)

404 .constrainAllUses(TII,TRI, RBI))

405returnfalse;

406returnBuildMI(MBB,I,I.getDebugLoc(),TII.get(PPC::RLDICL), Reg)

407 .addReg(TmpReg,RegState::Kill)

408 .addImm(TO)

409 .addImm(LZ)

410 .constrainAllUses(TII,TRI, RBI);

411 }

412// 2-5) Pattern : {32 zeros}{****}{0}{15-bit value}

413// If Hi32 is zero and the Lo16(in Lo32) can be presented as a positive 16 bit

414// value, we can use LI for Lo16 without generating leading ones then add the

415// Hi16(in Lo32).

416if (LZ == 32 && ((Lo32 & 0x8000) == 0)) {

417Register TmpReg =MRI.createVirtualRegister(&PPC::G8RCRegClass);

418if (!BuildMI(MBB,I,I.getDebugLoc(),TII.get(PPC::LI8), TmpReg)

419 .addImm(Lo32 & 0xffff)

420 .constrainAllUses(TII,TRI, RBI))

421returnfalse;

422returnBuildMI(MBB,I,I.getDebugLoc(),TII.get(PPC::ORIS8), Reg)

423 .addReg(TmpReg,RegState::Kill)

424 .addImm(Lo32 >> 16)

425 .constrainAllUses(TII,TRI, RBI);

426 }

427// 2-6) Patterns : {******}{49 zeros}{******}

428// {******}{49 ones}{******}

429// If the Imm contains 49 consecutive zeros/ones, it means that a total of 15

430// bits remain on both sides. Rotate right the Imm to construct an int<16>

431// value, use LI for int<16> value and then use RLDICL without mask to rotate

432// it back.

433//

434// 1) findContiguousZerosAtLeast(Imm, 49)

435// +------|--zeros-|------+ +---ones--||---15 bit--+

436// |bbbbbb0000000000aaaaaa| -> |0000000000aaaaaabbbbbb|

437// +----------------------+ +----------------------+

438// 63 0 63 0

439//

440// 2) findContiguousZerosAtLeast(~Imm, 49)

441// +------|--ones--|------+ +---ones--||---15 bit--+

442// |bbbbbb1111111111aaaaaa| -> |1111111111aaaaaabbbbbb|

443// +----------------------+ +----------------------+

444// 63 0 63 0

445if ((Shift =findContiguousZerosAtLeast(Imm, 49)) ||

446 (Shift =findContiguousZerosAtLeast(~Imm, 49))) {

447uint64_t RotImm =APInt(64, Imm).rotr(Shift).getZExtValue();

448Register TmpReg =MRI.createVirtualRegister(&PPC::G8RCRegClass);

449if (!BuildMI(MBB,I,I.getDebugLoc(),TII.get(PPC::LI8), TmpReg)

450 .addImm(RotImm & 0xffff)

451 .constrainAllUses(TII,TRI, RBI))

452returnfalse;

453returnBuildMI(MBB,I,I.getDebugLoc(),TII.get(PPC::RLDICL), Reg)

454 .addReg(TmpReg,RegState::Kill)

455 .addImm(Shift)

456 .addImm(0)

457 .constrainAllUses(TII,TRI, RBI);

458 }

459

460// Following patterns use 3 instructions to materialize the Imm.

461

462// 3-1) Patterns : {zeros}{ones}{31-bit value}{zeros}

463// {zeros}{31-bit value}{zeros}

464// {zeros}{ones}{31-bit value}

465// {ones}{31-bit value}{zeros}

466// We can take advantage of LIS's sign-extension semantics to generate leading

467// ones, add the remaining bits with ORI, and then use RLDIC to mask off the

468// ones in both sides after rotation.

469if ((LZ + FO + TZ) > 32) {

470uint64_t ImmHi16 = (Imm >> (TZ + 16)) & 0xffff;

471unsigned Opcode = ImmHi16 ? PPC::LIS8 : PPC::LI8;

472Register TmpReg =MRI.createVirtualRegister(&PPC::G8RCRegClass);

473Register Tmp2Reg =MRI.createVirtualRegister(&PPC::G8RCRegClass);

474if (!BuildMI(MBB,I,I.getDebugLoc(),TII.get(Opcode), TmpReg)

475 .addImm(ImmHi16)

476 .constrainAllUses(TII,TRI, RBI))

477returnfalse;

478if (!BuildMI(MBB,I,I.getDebugLoc(),TII.get(PPC::ORI8), Tmp2Reg)

479 .addReg(TmpReg,RegState::Kill)

480 .addImm((Imm >> TZ) & 0xffff)

481 .constrainAllUses(TII,TRI, RBI))

482returnfalse;

483returnBuildMI(MBB,I,I.getDebugLoc(),TII.get(PPC::RLDIC), Reg)

484 .addReg(Tmp2Reg,RegState::Kill)

485 .addImm(TZ)

486 .addImm(LZ)

487 .constrainAllUses(TII,TRI, RBI);

488 }

489// 3-2) Pattern : {zeros}{31-bit value}{ones}

490// Shift right the Imm by (32 - LZ) bits to construct a negative 32 bits

491// value, therefore we can take advantage of LIS's sign-extension semantics,

492// add the remaining bits with ORI, and then mask them off after rotation.

493// This is similar to Pattern 2-3, please refer to the diagram there.

494if ((LZ + TO) > 32) {

495// Since the immediates with (LZ > 32) have been handled by previous

496// patterns, here we have (LZ <= 32) to make sure we will not shift right

497// the Imm by a negative value.

498assert(LZ <= 32 &&"Unexpected shift value.");

499Register TmpReg =MRI.createVirtualRegister(&PPC::G8RCRegClass);

500Register Tmp2Reg =MRI.createVirtualRegister(&PPC::G8RCRegClass);

501if (!BuildMI(MBB,I,I.getDebugLoc(),TII.get(PPC::LIS8), TmpReg)

502 .addImm((Imm >> (48 - LZ)) & 0xffff)

503 .constrainAllUses(TII,TRI, RBI))

504returnfalse;

505if (!BuildMI(MBB,I,I.getDebugLoc(),TII.get(PPC::ORI8), Tmp2Reg)

506 .addReg(TmpReg,RegState::Kill)

507 .addImm((Imm >> (32 - LZ)) & 0xffff)

508 .constrainAllUses(TII,TRI, RBI))

509returnfalse;

510returnBuildMI(MBB,I,I.getDebugLoc(),TII.get(PPC::RLDICL), Reg)

511 .addReg(Tmp2Reg,RegState::Kill)

512 .addImm(32 - LZ)

513 .addImm(LZ)

514 .constrainAllUses(TII,TRI, RBI);

515 }

516// 3-3) Patterns : {zeros}{ones}{31-bit value}{ones}

517// {ones}{31-bit value}{ones}

518// We can take advantage of LIS's sign-extension semantics to generate leading

519// ones, add the remaining bits with ORI, and then use RLDICL to mask off the

520// ones in left sides (if required) after rotation.

521// This is similar to Pattern 2-4, please refer to the diagram there.

522if ((LZ + FO + TO) > 32) {

523Register TmpReg =MRI.createVirtualRegister(&PPC::G8RCRegClass);

524Register Tmp2Reg =MRI.createVirtualRegister(&PPC::G8RCRegClass);

525if (!BuildMI(MBB,I,I.getDebugLoc(),TII.get(PPC::LIS8), TmpReg)

526 .addImm((Imm >> (TO + 16)) & 0xffff)

527 .constrainAllUses(TII,TRI, RBI))

528returnfalse;

529if (!BuildMI(MBB,I,I.getDebugLoc(),TII.get(PPC::ORI8), Tmp2Reg)

530 .addReg(TmpReg,RegState::Kill)

531 .addImm((Imm >> TO) & 0xffff)

532 .constrainAllUses(TII,TRI, RBI))

533returnfalse;

534returnBuildMI(MBB,I,I.getDebugLoc(),TII.get(PPC::RLDICL), Reg)

535 .addReg(Tmp2Reg,RegState::Kill)

536 .addImm(TO)

537 .addImm(LZ)

538 .constrainAllUses(TII,TRI, RBI);

539 }

540// 3-4) Patterns : High word == Low word

541if (Hi32 == Lo32) {

542// Handle the first 32 bits.

543uint64_t ImmHi16 = (Lo32 >> 16) & 0xffff;

544unsigned Opcode = ImmHi16 ? PPC::LIS8 : PPC::LI8;

545Register TmpReg =MRI.createVirtualRegister(&PPC::G8RCRegClass);

546Register Tmp2Reg =MRI.createVirtualRegister(&PPC::G8RCRegClass);

547if (!BuildMI(MBB,I,I.getDebugLoc(),TII.get(Opcode), TmpReg)

548 .addImm(ImmHi16)

549 .constrainAllUses(TII,TRI, RBI))

550returnfalse;

551if (!BuildMI(MBB,I,I.getDebugLoc(),TII.get(PPC::ORI8), Tmp2Reg)

552 .addReg(TmpReg,RegState::Kill)

553 .addImm(Lo32 & 0xffff)

554 .constrainAllUses(TII,TRI, RBI))

555returnfalse;

556returnBuildMI(MBB,I,I.getDebugLoc(),TII.get(PPC::RLDIMI), Reg)

557 .addReg(Tmp2Reg)

558 .addReg(Tmp2Reg,RegState::Kill)

559 .addImm(32)

560 .addImm(0)

561 .constrainAllUses(TII,TRI, RBI);

562 }

563// 3-5) Patterns : {******}{33 zeros}{******}

564// {******}{33 ones}{******}

565// If the Imm contains 33 consecutive zeros/ones, it means that a total of 31

566// bits remain on both sides. Rotate right the Imm to construct an int<32>

567// value, use LIS + ORI for int<32> value and then use RLDICL without mask to

568// rotate it back.

569// This is similar to Pattern 2-6, please refer to the diagram there.

570if ((Shift =findContiguousZerosAtLeast(Imm, 33)) ||

571 (Shift =findContiguousZerosAtLeast(~Imm, 33))) {

572uint64_t RotImm =APInt(64, Imm).rotr(Shift).getZExtValue();

573uint64_t ImmHi16 = (RotImm >> 16) & 0xffff;

574unsigned Opcode = ImmHi16 ? PPC::LIS8 : PPC::LI8;

575Register TmpReg =MRI.createVirtualRegister(&PPC::G8RCRegClass);

576Register Tmp2Reg =MRI.createVirtualRegister(&PPC::G8RCRegClass);

577if (!BuildMI(MBB,I,I.getDebugLoc(),TII.get(Opcode), TmpReg)

578 .addImm(ImmHi16)

579 .constrainAllUses(TII,TRI, RBI))

580returnfalse;

581if (!BuildMI(MBB,I,I.getDebugLoc(),TII.get(PPC::ORI8), Tmp2Reg)

582 .addReg(TmpReg,RegState::Kill)

583 .addImm(RotImm & 0xffff)

584 .constrainAllUses(TII,TRI, RBI))

585returnfalse;

586returnBuildMI(MBB,I,I.getDebugLoc(),TII.get(PPC::RLDICL), Reg)

587 .addReg(Tmp2Reg,RegState::Kill)

588 .addImm(Shift)

589 .addImm(0)

590 .constrainAllUses(TII,TRI, RBI);

591 }

592

593// If we end up here then no instructions were inserted.

594return std::nullopt;

595}

596

597// Derived from PPCISelDAGToDAG::selectI64Imm().

598// TODO: Add support for prefixed instructions.

599bool PPCInstructionSelector::selectI64Imm(MachineInstr &I,

600MachineBasicBlock &MBB,

601MachineRegisterInfo &MRI) const{

602assert(I.getOpcode() == TargetOpcode::G_CONSTANT &&"Unexpected G code");

603

604Register DstReg =I.getOperand(0).getReg();

605 int64_tImm =I.getOperand(1).getCImm()->getValue().getZExtValue();

606// No more than 3 instructions are used if we can select the i64 immediate

607// directly.

608if (std::optional<bool> Res =selectI64ImmDirect(I,MBB,MRI, DstReg, Imm)) {

609I.eraseFromParent();

610return *Res;

611 }

612

613// Calculate the last bits as required.

614uint32_t Hi16 = (Lo_32(Imm) >> 16) & 0xffff;

615uint32_t Lo16 =Lo_32(Imm) & 0xffff;

616

617Register Reg =

618 (Hi16 || Lo16) ?MRI.createVirtualRegister(&PPC::G8RCRegClass) : DstReg;

619

620// Handle the upper 32 bit value.

621 std::optional<bool> Res =

622selectI64ImmDirect(I,MBB,MRI, Reg, Imm & 0xffffffff00000000);

623if (!Res || !*Res)

624returnfalse;

625

626// Add in the last bits as required.

627if (Hi16) {

628Register TmpReg =

629 Lo16 ?MRI.createVirtualRegister(&PPC::G8RCRegClass) : DstReg;

630if (!BuildMI(MBB,I,I.getDebugLoc(),TII.get(PPC::ORIS8), TmpReg)

631 .addReg(Reg,RegState::Kill)

632 .addImm(Hi16)

633 .constrainAllUses(TII,TRI, RBI))

634returnfalse;

635Reg = TmpReg;

636 }

637if (Lo16) {

638if (!BuildMI(MBB,I,I.getDebugLoc(),TII.get(PPC::ORI8), DstReg)

639 .addReg(Reg,RegState::Kill)

640 .addImm(Lo16)

641 .constrainAllUses(TII,TRI, RBI))

642returnfalse;

643 }

644I.eraseFromParent();

645returntrue;

646}

647

648bool PPCInstructionSelector::selectConstantPool(

649MachineInstr &I,MachineBasicBlock &MBB,MachineRegisterInfo &MRI) const{

650constDebugLoc &DbgLoc =I.getDebugLoc();

651MachineFunction *MF =MBB.getParent();

652

653// TODO: handle 32-bit.

654// TODO: Enabling floating point constant pool selection on AIX requires

655// global isel on big endian target enabled first.

656// See CallLowering::enableBigEndian().

657if (!STI.isPPC64() || !STI.isLittleEndian())

658returnfalse;

659

660 MF->getInfo<PPCFunctionInfo>()->setUsesTOCBasePtr();

661

662constRegister DstReg =I.getOperand(0).getReg();

663unsigned CPI =I.getOperand(1).getIndex();

664

665// Address stored in the TOC entry. This is related to code model and the ABI

666// we are currently using. For now we only handle 64-bit Linux LE. PowerPC

667// only supports small, medium and large code model.

668constCodeModel::Model CModel =TM.getCodeModel();

669assert(!(CModel ==CodeModel::Tiny || CModel ==CodeModel::Kernel) &&

670"PowerPC doesn't support tiny or kernel code models.");

671

672constMCRegister TOCReg = STI.getTOCPointerRegister();

673MachineMemOperand *MMO = MF->getMachineMemOperand(

674MachinePointerInfo::getGOT(*MF),MachineMemOperand::MOLoad,

675MRI.getType(DstReg), MF->getDataLayout().getPointerABIAlignment(0));

676

677MachineInstr *MI =nullptr;

678// For now we only handle 64-bit Linux.

679if (CModel ==CodeModel::Small) {

680// For small code model, generate LDtocCPT(CPI, X2).

681MI =BuildMI(MBB,I, DbgLoc,TII.get(PPC::LDtocCPT), DstReg)

682 .addConstantPoolIndex(CPI)

683 .addReg(TOCReg)

684 .addMemOperand(MMO);

685 }else {

686Register HaAddrReg =MRI.createVirtualRegister(&PPC::G8RCRegClass);

687BuildMI(MBB,I, DbgLoc,TII.get(PPC::ADDIStocHA8), HaAddrReg)

688 .addReg(TOCReg)

689 .addConstantPoolIndex(CPI);

690

691if (CModel ==CodeModel::Large)

692// For large code model, generate LDtocL(CPI, ADDIStocHA8(X2, CPI))

693MI =BuildMI(MBB,I, DbgLoc,TII.get(PPC::LDtocL), DstReg)

694 .addConstantPoolIndex(CPI)

695 .addReg(HaAddrReg)

696 .addMemOperand(MMO);

697else

698// For medium code model, generate ADDItocL8(CPI, ADDIStocHA8(X2, CPI))

699MI =BuildMI(MBB,I, DbgLoc,TII.get(PPC::ADDItocL8), DstReg)

700 .addReg(HaAddrReg)

701 .addConstantPoolIndex(CPI);

702 }

703

704I.eraseFromParent();

705returnconstrainSelectedInstRegOperands(*MI,TII,TRI, RBI);

706}

707

708bool PPCInstructionSelector::select(MachineInstr &I) {

709auto &MBB = *I.getParent();

710auto &MF = *MBB.getParent();

711auto &MRI = MF.getRegInfo();

712

713if (!isPreISelGenericOpcode(I.getOpcode())) {

714if (I.isCopy())

715returnselectCopy(I,TII,MRI,TRI, RBI);

716

717returntrue;

718 }

719

720if (selectImpl(I, *CoverageInfo))

721returntrue;

722

723unsigned Opcode =I.getOpcode();

724

725switch (Opcode) {

726default:

727returnfalse;

728case TargetOpcode::G_LOAD:

729case TargetOpcode::G_STORE: {

730GLoadStore &LdSt = cast<GLoadStore>(I);

731LLT PtrTy =MRI.getType(LdSt.getPointerReg());

732

733if (PtrTy !=LLT::pointer(0, 64)) {

734LLVM_DEBUG(dbgs() <<"Load/Store pointer has type: " << PtrTy

735 <<", expected: " <<LLT::pointer(0, 64) <<'\n');

736returnfalse;

737 }

738

739auto SelectLoadStoreAddressingMode = [&]() ->MachineInstr * {

740constunsigned NewOpc =selectLoadStoreOp(

741I.getOpcode(), RBI.getRegBank(LdSt.getReg(0),MRI,TRI)->getID(),

742 LdSt.getMemSizeInBits().getValue());

743

744if (NewOpc ==I.getOpcode())

745returnnullptr;

746

747// For now, simply use DForm with load/store addr as base and 0 as imm.

748// FIXME: optimize load/store with some specific address patterns.

749I.setDesc(TII.get(NewOpc));

750Register AddrReg =I.getOperand(1).getReg();

751bool IsKill =I.getOperand(1).isKill();

752I.getOperand(1).ChangeToImmediate(0);

753I.addOperand(*I.getParent()->getParent(),

754MachineOperand::CreateReg(AddrReg,/* isDef */false,

755/* isImp */false, IsKill));

756return &I;

757 };

758

759MachineInstr *LoadStore = SelectLoadStoreAddressingMode();

760if (!LoadStore)

761returnfalse;

762

763returnconstrainSelectedInstRegOperands(*LoadStore,TII,TRI, RBI);

764 }

765case TargetOpcode::G_SITOFP:

766case TargetOpcode::G_UITOFP:

767return selectIntToFP(I,MBB,MRI);

768case TargetOpcode::G_FPTOSI:

769case TargetOpcode::G_FPTOUI:

770return selectFPToInt(I,MBB,MRI);

771// G_SEXT will be selected in tb-gen pattern.

772case TargetOpcode::G_ZEXT:

773return selectZExt(I,MBB,MRI);

774case TargetOpcode::G_CONSTANT:

775returnselectI64Imm(I,MBB,MRI);

776case TargetOpcode::G_CONSTANT_POOL:

777return selectConstantPool(I,MBB,MRI);

778 }

779returnfalse;

780}

781

782namespacellvm {

783InstructionSelector *

784createPPCInstructionSelector(constPPCTargetMachine &TM,

785constPPCSubtarget &Subtarget,

786constPPCRegisterBankInfo &RBI) {

787returnnew PPCInstructionSelector(TM, Subtarget, RBI);

788}

789}// end namespace llvm

MRI

unsigned const MachineRegisterInfo * MRI

Definition:AArch64AdvSIMDScalarPass.cpp:105

getRegClass

static const TargetRegisterClass * getRegClass(const MachineInstr &MI, Register Reg)

Definition:AArch64InstrInfo.cpp:4575

MBB

MachineBasicBlock & MBB

Definition:ARMSLSHardening.cpp:71

Debug.h

LLVM_DEBUG

#define LLVM_DEBUG(...)

Definition:Debug.h:106

GIMatchTableExecutorImpl.h

DEBUG_TYPE

#define DEBUG_TYPE

Definition:GenericCycleImpl.h:31

GenericMachineInstrs.h

Declares convenience wrapper classes for interpreting MachineInstr instances as specific generic oper...

TII

const HexagonInstrInfo * TII

Definition:HexagonCopyToCombine.cpp:125

IRTranslator LLVM IR MI

Definition:IRTranslator.cpp:112

InstructionSelector.h

#define I(x, y, z)

Definition:MD5.cpp:58

MachineConstantPool.h

This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...

MachineFunction.h

MachineIRBuilder.h

This file declares the MachineIRBuilder class.

TRI

unsigned const TargetRegisterInfo * TRI

Definition:MachineSink.cpp:2029

selectI64ImmDirect

static SDNode * selectI64ImmDirect(SelectionDAG *CurDAG, const SDLoc &dl, uint64_t Imm, unsigned &InstCnt)

Definition:PPCISelDAGToDAG.cpp:1019

selectI64Imm

static SDNode * selectI64Imm(SelectionDAG *CurDAG, const SDLoc &dl, uint64_t Imm, unsigned *InstCnt=nullptr)

Definition:PPCISelDAGToDAG.cpp:1380

setUsesTOCBasePtr

static void setUsesTOCBasePtr(MachineFunction &MF)

Definition:PPCISelLowering.cpp:3183

PPCInstrInfo.h

GET_GLOBALISEL_PREDICATES_INIT

#define GET_GLOBALISEL_PREDICATES_INIT

GET_GLOBALISEL_TEMPORARIES_INIT

#define GET_GLOBALISEL_TEMPORARIES_INIT

selectCopy

static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)

Definition:PPCInstructionSelector.cpp:130

findContiguousZerosAtLeast

static uint32_t findContiguousZerosAtLeast(uint64_t Imm, unsigned Num)

Definition:PPCInstructionSelector.cpp:277

selectLoadStoreOp

static unsigned selectLoadStoreOp(unsigned GenericOpc, unsigned RegBankID, unsigned OpSize)

Definition:PPCInstructionSelector.cpp:154

PPCMachineFunctionInfo.h

PPCRegisterBankInfo.h

This file declares the targeting of the RegisterBankInfo class for PowerPC.

static StringRef getName(Value *V)

Definition:ProvenanceAnalysisEvaluator.cpp:20

assert

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

llvm::APInt

Class for arbitrary precision integers.

Definition:APInt.h:78

llvm::APInt::getZExtValue

uint64_t getZExtValue() const

Get zero extended value.

Definition:APInt.h:1520

llvm::APInt::rotr

APInt rotr(unsigned rotateAmt) const

Rotate right by rotateAmt.

Definition:APInt.cpp:1128

llvm::CodeGenCoverage

Definition:CodeGenCoverage.h:19

llvm::DataLayout::getPointerABIAlignment

Align getPointerABIAlignment(unsigned AS) const

Layout pointer alignment.

Definition:DataLayout.cpp:731

llvm::DebugLoc

A debug info location.

Definition:DebugLoc.h:33

llvm::GLoadStore

Represents any type of generic load or store.

Definition:GenericMachineInstrs.h:81

llvm::GLoadStore::getPointerReg

Get the source register of the pointer value.

Definition:GenericMachineInstrs.h:84

llvm::GMemOperation::getMemSizeInBits

LocationSize getMemSizeInBits() const

Returns the size in bits of the memory access.

Definition:GenericMachineInstrs.h:72

llvm::GenericMachineInstr::getReg

Access the Idx'th operand as a register and return it.

Definition:GenericMachineInstrs.h:38

llvm::InstructionSelector

Definition:InstructionSelector.h:21

llvm::InstructionSelector::select

virtual bool select(MachineInstr &I)=0

Select the (possibly generic) instruction I to only use target-specific opcodes.

llvm::LLT

Definition:LowLevelType.h:39

llvm::LLT::pointer

static constexpr LLT pointer(unsigned AddressSpace, unsigned SizeInBits)

Get a low-level pointer in the given address space.

Definition:LowLevelType.h:57

llvm::LLT::getSizeInBits

constexpr TypeSize getSizeInBits() const

Returns the total size of the type. Must only be called on sized types.

Definition:LowLevelType.h:190

llvm::LocationSize::getValue

TypeSize getValue() const

Definition:MemoryLocation.h:170

llvm::MCRegister

Wrapper class representing physical registers. Should be passed by value.

Definition:MCRegister.h:33

llvm::MachineBasicBlock

Definition:MachineBasicBlock.h:125

llvm::MachineBasicBlock::getParent

const MachineFunction * getParent() const

Return the MachineFunction containing this basic block.

Definition:MachineBasicBlock.h:311

llvm::MachineFunction

Definition:MachineFunction.h:267

llvm::MachineFunction::getMachineMemOperand

MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)

getMachineMemOperand - Allocate a new MachineMemOperand.

Definition:MachineFunction.cpp:536

llvm::MachineFunction::getRegInfo

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

Definition:MachineFunction.h:743

llvm::MachineFunction::getDataLayout

const DataLayout & getDataLayout() const

Return the DataLayout attached to the Module associated to this MF.

Definition:MachineFunction.cpp:309

llvm::MachineFunction::getInfo

Ty * getInfo()

getInfo - Keep track of various per-function pieces of information for backends that would like to do...

Definition:MachineFunction.h:831

llvm::MachineInstrBuilder::addImm

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

Definition:MachineInstrBuilder.h:133

llvm::MachineInstrBuilder::addConstantPoolIndex

const MachineInstrBuilder & addConstantPoolIndex(unsigned Idx, int Offset=0, unsigned TargetFlags=0) const

Definition:MachineInstrBuilder.h:160

llvm::MachineInstrBuilder::addReg

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

Definition:MachineInstrBuilder.h:99

llvm::MachineInstrBuilder::constrainAllUses

bool constrainAllUses(const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI) const

Definition:MachineInstrBuilder.h:339

llvm::MachineInstrBuilder::addMemOperand

const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const

Definition:MachineInstrBuilder.h:204

llvm::MachineInstr

Representation of each machine instruction.

Definition:MachineInstr.h:71

llvm::MachineMemOperand

A description of a memory reference used in the backend.

Definition:MachineMemOperand.h:129

llvm::MachineMemOperand::MOLoad

@ MOLoad

The memory access reads data.

Definition:MachineMemOperand.h:136

llvm::MachineOperand::CreateReg

static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)

Definition:MachineOperand.h:838

llvm::MachineRegisterInfo

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

Definition:MachineRegisterInfo.h:51

llvm::PPCFunctionInfo

PPCFunctionInfo - This class is derived from MachineFunction private PowerPC target-specific informat...

Definition:PPCMachineFunctionInfo.h:24

llvm::PPCInstrInfo

Definition:PPCInstrInfo.h:175

llvm::PPCRegisterBankInfo

Definition:PPCRegisterBankInfo.h:64

llvm::PPCRegisterInfo

Definition:PPCRegisterInfo.h:57

llvm::PPCSubtarget

Definition:PPCSubtarget.h:72

llvm::PPCTargetMachine

Common code between 32-bit and 64-bit PowerPC targets.

Definition:PPCTargetMachine.h:26

llvm::RegisterBankInfo

Holds all the information related to register banks.

Definition:RegisterBankInfo.h:40

llvm::RegisterBankInfo::constrainGenericRegister

static const TargetRegisterClass * constrainGenericRegister(Register Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI)

Constrain the (possibly generic) virtual register Reg to RC.

Definition:RegisterBankInfo.cpp:132

llvm::RegisterBankInfo::getRegBank

const RegisterBank & getRegBank(unsigned ID)

Get the register bank identified by ID.

Definition:RegisterBankInfo.h:440

llvm::RegisterBank

This class implements the register bank concept.

Definition:RegisterBank.h:28

llvm::RegisterBank::getID

unsigned getID() const

Get the identifier of this register bank.

Definition:RegisterBank.h:45

llvm::Register

Wrapper class representing virtual and physical registers.

Definition:Register.h:19

llvm::Register::isPhysical

constexpr bool isPhysical() const

Return true if the specified register number is in the physical register namespace.

Definition:Register.h:95

llvm::TargetInstrInfo

TargetInstrInfo - Interface to description of machine instruction set.

Definition:TargetInstrInfo.h:112

llvm::TargetRegisterClass

Definition:TargetRegisterInfo.h:44

llvm::TargetRegisterInfo

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

Definition:TargetRegisterInfo.h:235

uint32_t

uint64_t

llvm_unreachable

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

Definition:ErrorHandling.h:143

llvm::AArch64CC::LO

@ LO

Definition:AArch64BaseInfo.h:258

llvm::AMDGPU::Imm

@ Imm

Definition:AMDGPURegBankLegalizeRules.h:105

llvm::CodeModel::Model

Model

Definition:CodeGen.h:31

llvm::CodeModel::Large

@ Large

Definition:CodeGen.h:31

llvm::CodeModel::Tiny

@ Tiny

Definition:CodeGen.h:31

llvm::CodeModel::Small

@ Small

Definition:CodeGen.h:31

llvm::CodeModel::Kernel

@ Kernel

Definition:CodeGen.h:31

llvm::MCID::MoveReg

@ MoveReg

Definition:MCInstrDesc.h:163

llvm::NVPTX::LoadStore

LoadStore

Definition:NVPTX.h:107

llvm::RegState::Kill

@ Kill

The last use of a register.

Definition:MachineInstrBuilder.h:50

llvm::SystemZISD::TM

@ TM

Definition:SystemZISelLowering.h:66

llvm::X86Disassembler::Reg

Reg

All possible values of the reg field in the ModR/M byte.

Definition:X86DisassemblerDecoder.h:621

llvm

This is an optimization pass for GlobalISel generic memory operations.

Definition:AddressRanges.h:18

llvm::BuildMI

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

Definition:MachineInstrBuilder.h:373

llvm::constrainSelectedInstRegOperands

bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)

Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...

Definition:Utils.cpp:155

llvm::isPreISelGenericOpcode

bool isPreISelGenericOpcode(unsigned Opcode)

Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.

Definition:TargetOpcodes.h:30

llvm::Hi_32

constexpr uint32_t Hi_32(uint64_t Value)

Return the high 32 bits of a 64 bit value.

Definition:MathExtras.h:155

llvm::dbgs

raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

Definition:Debug.cpp:163

llvm::Lo_32

constexpr uint32_t Lo_32(uint64_t Value)

Return the low 32 bits of a 64 bit value.

Definition:MathExtras.h:160

llvm::createPPCInstructionSelector

InstructionSelector * createPPCInstructionSelector(const PPCTargetMachine &TM, const PPCSubtarget &Subtarget, const PPCRegisterBankInfo &RBI)

Definition:PPCInstructionSelector.cpp:784

llvm::MachinePointerInfo::getGOT

static MachinePointerInfo getGOT(MachineFunction &MF)

Return a MachinePointerInfo record that refers to a GOT entry.

Definition:MachineOperand.cpp:1081