1//===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7//===----------------------------------------------------------------------===// 9// This file contains the PPC implementation of TargetFrameLowering class. 11//===----------------------------------------------------------------------===// 33#define DEBUG_TYPE "framelowering" 34STATISTIC(NumPESpillVSR,
"Number of spills to vector in prologue");
35STATISTIC(NumPEReloadVSR,
"Number of reloads from vector in epilogue");
36STATISTIC(NumPrologProbed,
"Number of prologues probed");
40cl::desc(
"Enable spills in prologue to vector registers."),
57// First slot in the general register save area. 58return STI.
isPPC64() ? -8U : -4U;
70// Third slot in the general purpose register save area. 74// Second slot in the general purpose register save area. 75return STI.
isPPC64() ? -16U : -8U;
84 STI.getPlatformStackAlignment(), 0),
92// With the SVR4 ABI, callee-saved registers have fixed offsets on the stack. 94unsigned &NumEntries)
const{
96// Floating-point register save area offsets. 97#define CALLEE_SAVED_FPRS \ 117// 32-bit general purpose register save area offsets shared by ELF and 118// AIX. AIX has an extra CSR with r13. 119#define CALLEE_SAVED_GPRS32 \ 139// 64-bit general purpose register save area offsets. 140#define CALLEE_SAVED_GPRS64 \ 160// Vector register save area offsets. 161#define CALLEE_SAVED_VRS \ 175// Note that the offsets here overlap, but this is fixed up in 176// processFunctionBeforeFrameFinalized. 182// CR save area offset. We map each of the nonvolatile CR fields 183// to the slot for CR2, which is the first of the nonvolatile CR 184// fields to be assigned, so that we only allocate one save slot. 185// See PPCRegisterInfo::hasReservedSpillSlot() for more information. 188// VRSAVE save area offset. 193// SPE register save area (overlaps Vector save area). 217// VRSAVE save area offset. 224// Add AIX's extra CSR. 232 NumEntries = std::size(ELFOffsets64);
237 NumEntries = std::size(ELFOffsets32);
244 NumEntries = std::size(AIXOffsets64);
248 NumEntries = std::size(AIXOffsets32);
267/// MustSaveLR - Return true if this function requires that we save the LR 268/// register onto the stack in the prolog and restore it in the epilog of the 273// We need a save/restore of LR if there is any def of LR (which is 274// defined by calls, including the PIC setup sequence), or if there is 275// some use of the LR stack slot (e.g. for builtin_return_address). 276// (LR comes in 32 and 64 bit versions.) 281/// determineFrameLayoutAndUpdate - Determine the size of the frame and maximum 282/// call frame size. Update the MachineFunction object with the stack size. 285bool UseEstimate)
const{
286unsigned NewMaxCallFrameSize = 0;
288 &NewMaxCallFrameSize);
294/// determineFrameLayout - Determine the size of the frame and maximum call 299unsigned *NewMaxCallFrameSize)
const{
303// Get the number of bytes to allocate from the FrameInfo 307// Get stack alignments. The frame must be aligned to the greatest of these: 310Align Alignment = std::max(TargetAlign, MaxAlign);
314unsigned LR = RegInfo->getRARegister();
323// Note: for PPC32 SVR4ABI, we can still generate stackless 324// code if all local vars are reg-allocated. 327// Check whether we can skip adjusting the stack pointer (by using red zone) 328if (!DisableRedZone && CanUseRedZone && FitsInRedZone) {
333// Get the maximum call frame size of all the calls. 336// Maximum call frame needs to be at least big enough for linkage area. 338 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
340// If we have dynamic alloca then maxCallFrameSize needs to be aligned so 341// that allocations will be aligned. 343 maxCallFrameSize =
alignTo(maxCallFrameSize, Alignment);
345// Update the new max call frame size if the caller passes in a valid pointer. 346if (NewMaxCallFrameSize)
347 *NewMaxCallFrameSize = maxCallFrameSize;
349// Include call frame size in total. 350 FrameSize += maxCallFrameSize;
352// Make sure the frame is aligned. 353 FrameSize =
alignTo(FrameSize, Alignment);
358// hasFPImpl - Return true if the specified function actually has a dedicated 359// frame pointer register. 362// FIXME: This is pretty much broken by design: hasFP() might be called really 363// early, before the stack layout was calculated and thus hasFP() might return 364// true or false here depending on the time of call. 368// needsFP - Return true if the specified function should have a dedicated frame 369// pointer register. This is true if the function has variable sized allocas or 370// if frame pointer elimination is disabled. 374// Naked functions have no stack frame pushed, so we don't have a frame 387// When there is dynamic alloca in this function, we can not use the frame 388// pointer X31/R31 for the frameaddress lowering. In this case, only X1/R1 389// always points to the backchain. 391unsignedFPReg = is31 ? PPC::R31 : PPC::R1;
392unsigned FP8Reg = is31 ? PPC::X31 : PPC::X1;
397unsigned BP8Reg = HasBP ? (
unsigned) PPC::X30 : FP8Reg;
406switch (MO.getReg()) {
425/* This function will do the following: 426 - If MBB is an entry or exit block, set SR1 and SR2 to R0 and R12 427 respectively (defaults recommended by the ABI) and return true 428 - If MBB is not an entry block, initialize the register scavenger and look 429 for available registers. 430 - If the defaults (R0/R12) are available, return true 431 - If TwoUniqueRegsRequired is set to true, it looks for two unique 432 registers. Otherwise, look for a single available register. 433 - If the required registers are found, set SR1 and SR2 and return true. 434 - If the required registers are not found, set SR2 or both SR1 and SR2 to 435 PPC::NoRegister and return false. 437 Note that if both SR1 and SR2 are valid parameters and TwoUniqueRegsRequired 438 is not set, this function will attempt to find two different registers, but 439 still return true if only one register is available (and set SR1 == SR2). 444bool TwoUniqueRegsRequired,
451// Set the defaults for the two scratch registers. 456assert (SR1 &&
"Asking for the second scratch register but not the first?");
460// If MBB is an entry or exit block, use R0 and R12 as the scratch registers. 466// The scratch register will be used before the first terminator (or at the 467// end of the block if there are no terminators). 476// The scratch register will be used at the start of the block. 480// If the two registers are available, we're all good. 481// Note that we only return here if both R0 and R12 are available because 482// although the function may not require two unique registers, it may benefit 483// from having two so we should try to provide them. 487// Get the list of callee-saved registers for the target. 491// Get all the available registers in the block. 495// We shouldn't use callee-saved registers as scratch registers as they may be 496// available when looking for a candidate block for shrink wrapping but not 497// available when the actual prologue/epilogue is being emitted because they 498// were added as live-in to the prologue block by PrologueEpilogueInserter. 499for (
int i = 0; CSRegs[i]; ++i)
502// Set the first scratch register to the first available one. 505 *SR1 = FirstScratchReg == -1 ? (
unsigned)PPC::NoRegister : FirstScratchReg;
508// If there is another one available, set the second scratch register to that. 509// Otherwise, set it to either PPC::NoRegister if this function requires two 510// or to whatever SR1 is set to if this function doesn't require two. 512int SecondScratchReg = BV.
find_next(*SR1);
513if (SecondScratchReg != -1)
514 *SR2 = SecondScratchReg;
516 *SR2 = TwoUniqueRegsRequired ?
Register() : *SR1;
519// Now that we've done our best to provide both registers, double check 520// whether we were unable to provide enough. 521if (BV.
count() < (TwoUniqueRegsRequired ? 2U : 1U))
527// We need a scratch register for spilling LR and for spilling CR. By default, 528// we use two scratch registers to hide latency. However, if only one scratch 529// register is available, we can adjust for that by not overlapping the spill 530// code. However, if we need to realign the stack (i.e. have a base pointer) 531// and the stack frame is large, we need two scratch registers. 532// Also, stack probe requires two scratch registers, one for old sp, one for 533// large frame and large probe size. 538bool HasBP =
RegInfo->hasBasePointer(MF);
540int NegFrameSize = -FrameSize;
541bool IsLargeFrame = !isInt<16>(NegFrameSize);
547return ((IsLargeFrame || !HasRedZone) && HasBP && MaxAlign > 1) ||
554return findScratchRegister(TmpMBB,
false,
555 twoUniqueScratchRegsRequired(TmpMBB));
561return findScratchRegister(TmpMBB,
true);
564bool PPCFrameLowering::stackUpdateCanBeMoved(
MachineFunction &MF)
const{
568// Abort if there is no register info or function info. 572// Only move the stack update on ELFv2 ABI and PPC64. 576// Check the frame size first and return false if it does not fit the 578// We need a non-zero frame size as well as a frame that will fit in the red 579// zone. This is because by moving the stack pointer update we are now storing 580// to the red zone until the stack pointer is updated. If we get an interrupt 581// inside the prologue but before the stack update we now have a number of 582// stores to the red zone and those stores must all fit. 588// Frame pointers and base pointers complicate matters so don't do anything 589// if we have them. For example having a frame pointer will sometimes require 590// a copy of r1 into r31 and that makes keeping track of updates to r1 more 591// difficult. Similar situation exists with setjmp. 595// Calls to fast_cc functions use different rules for passing parameters on 596// the stack from the ABI and using PIC base in the function imposes 597// similar restrictions to using the base pointer. It is not generally safe 598// to move the stack pointer update in these situations. 602// Finally we can move the stack update if we do not require register 603// scavenging. Register scavenging can introduce more spills and so 604// may make the frame size larger than we have computed. 618// AIX assembler does not support cfi directives. 621constbool HasFastMFLR = Subtarget.hasFastMFLR();
623// Get processor type. 624bool isPPC64 = Subtarget.
isPPC64();
628assert((isSVR4ABI || Subtarget.
isAIXABI()) &&
"Unsupported PPC ABI.");
630// Work out frame sizes. 632 int64_t NegFrameSize = -FrameSize;
633if (!isPPC64 && (!isInt<32>(FrameSize) || !isInt<32>(NegFrameSize)))
639// Check if the link register (LR) must be saved. 644bool MustSaveCR = !MustSaveCRs.
empty();
645// Do we have a frame pointer and/or base pointer for this function? 646bool HasFP =
hasFP(MF);
648bool HasRedZone = isPPC64 || !isSVR4ABI;
649constbool HasROPProtect = Subtarget.hasROPProtect();
650bool HasPrivileged = Subtarget.hasPrivileged();
655Register LRReg = isPPC64 ? PPC::LR8 : PPC::LR;
656Register TOCReg = isPPC64 ? PPC::X2 : PPC::R2;
658Register TempReg = isPPC64 ? PPC::X12 : PPC::R12;
// another scratch reg 659// ...(R12/X12 is volatile in both Darwin & SVR4, & can't be a function arg.) 670constMCInstrDesc& SubtractCarryingInst =
TII.get(isPPC64 ? PPC::SUBFC8
672constMCInstrDesc& SubtractImmCarryingInst =
TII.get(isPPC64 ? PPC::SUBFIC8
674constMCInstrDesc &MoveFromCondRegInst =
TII.get(isPPC64 ? PPC::MFCR8
676constMCInstrDesc &StoreWordInst =
TII.get(isPPC64 ? PPC::STW8 : PPC::STW);
678TII.get(isPPC64 ? (HasPrivileged ? PPC::HASHSTP8 : PPC::HASHST8)
679 : (HasPrivileged ? PPC::HASHSTP : PPC::HASHST));
681// Regarding this assert: Even though LR is saved in the caller's frame (i.e., 682// LROffset is positive), that slot is callee-owned. Because PPC32 SVR4 has no 683// Red Zone, an asynchronous event (a form of "callee") could claim a frame & 684// overwrite it, so PPC32 SVR4 must claim at least a minimal frame to save LR. 686"FrameSize must be >0 to save/restore the FP or LR for 32-bit SVR4.");
688// Using the same bool variable as below to suppress compiler warnings. 689bool SingleScratchReg = findScratchRegister(
690 &
MBB,
false, twoUniqueScratchRegsRequired(&
MBB), &ScratchReg, &TempReg);
692"Required number of registers not available in this block");
694 SingleScratchReg = ScratchReg == TempReg;
698 int64_t FPOffset = 0;
702assert(FPIndex &&
"No Frame Pointer Save Slot!");
706 int64_t BPOffset = 0;
710assert(BPIndex &&
"No Base Pointer Save Slot!");
714 int64_t PBPOffset = 0;
718assert(PBPIndex &&
"No PIC Base Pointer Save Slot!");
722// Get stack alignments. 724if (HasBP && MaxAlign > 1)
725assert(
Log2(MaxAlign) < 16 &&
"Invalid alignment!");
727// Frames of 32KB & larger require special handling because they cannot be 728// indexed into with a simple STDU/STWU/STD/STW immediate offset operand. 729bool isLargeFrame = !isInt<16>(NegFrameSize);
731// Check if we can move the stack update instruction (stdu) down the prologue 732// past the callee saves. Hopefully this will avoid the situation where the 733// saves are waiting for the update on the store with update to complete. 735bool MovingStackUpdateDown =
false;
737// Check if we can move the stack update. 738if (stackUpdateCanBeMoved(MF)) {
741// If the callee saved register is spilled to a register instead of the 742// stack then the spill no longer uses the stack pointer. 743// This can lead to two consequences: 744// 1) We no longer need to update the stack because the function does not 745// spill any callee saved registers to stack. 746// 2) We have a situation where we still have to update the stack pointer 747// even though some registers are spilled to other registers. In 748// this case the current code moves the stack update to an incorrect 750// In either case we should abort moving the stack update operation. 751if (CSI.isSpilledToReg()) {
752 StackUpdateLoc =
MBBI;
753 MovingStackUpdateDown =
false;
757int FrIdx = CSI.getFrameIdx();
758// If the frame index is not negative the callee saved info belongs to a 759// stack object that is not a fixed stack object. We ignore non-fixed 760// stack objects because we won't move the stack update pointer past them. 766 MovingStackUpdateDown =
true;
768// We need all of the Frame Indices to meet these conditions. 769// If they do not, abort the whole operation. 770 StackUpdateLoc =
MBBI;
771 MovingStackUpdateDown =
false;
776// If the operation was not aborted then update the object offset. 777if (MovingStackUpdateDown) {
779int FrIdx = CSI.getFrameIdx();
786// Where in the prologue we move the CR fields depends on how many scratch 787// registers we have, and if we need to save the link register or not. This 788// lambda is to avoid duplicating the logic in 2 places. 789auto BuildMoveFromCR = [&]() {
790if (isELFv2ABI && MustSaveCRs.
size() == 1) {
791// In the ELFv2 ABI, we are not required to save all CR fields. 792// If only one CR field is clobbered, it is more efficient to use 793// mfocrf to selectively save just that field, because mfocrf has short 794// latency compares to mfcr. 795assert(isPPC64 &&
"V2 ABI is 64-bit only.");
802for (
unsigned CRfield : MustSaveCRs)
807// If we need to spill the CR and the LR but we don't have two separate 808// registers available, we must spill them one at a time 809if (MustSaveCR && SingleScratchReg &&
MustSaveLR) {
820if (MustSaveCR && !(SingleScratchReg &&
MustSaveLR))
841// Generate the instruction to store the LR. In the case where ROP protection 842// is required the register holding the LR should not be killed as it will be 843// used by the hash store instruction. 844auto SaveLR = [&](int64_t
Offset) {
851// Add the ROP protection Hash Store instruction. 852// NOTE: This is technically a violation of the ABI. The hash can be saved 853// up to 512 bytes into the Protected Zone. This can be outside of the 854// initial 288 byte volatile program storage region in the Protected Zone. 855// However, this restriction will be removed in an upcoming revision of the 860assert((ImmOffset <= -8 && ImmOffset >= -512) &&
861"ROP hash save offset out of range.");
862assert(((ImmOffset & 0x7) == 0) &&
863"ROP hash save offset must be 8 byte aligned.");
876assert(HasRedZone &&
"A red zone is always available on PPC64");
883// Skip the rest if this is a leaf function & all spills fit in the Red Zone. 890// Adjust stack pointer: r1 += NegFrameSize. 891// If there is a preferred stack alignment, align R1 now 893if (HasBP && HasRedZone) {
894// Save a copy of r1 as the base pointer. 900// Have we generated a STUX instruction to claim stack frame? If so, 901// the negated frame size will be placed in ScratchReg. 904 (HasBP && MaxAlign > 1) || isLargeFrame;
906// If we use STUX to update the stack pointer, we need the two scratch 907// registers TempReg and ScratchReg, we have to save LR here which is stored 909// If the offset can not be encoded into the store instruction, we also have 911// If we are using ROP Protection we need to save the LR here as we cannot 912// move the hashst instruction past the point where we get the stack frame. 914 (HasSTUX || !isInt<16>(FrameSize + LROffset) || HasROPProtect))
917// If FrameSize <= TLI.getStackProbeSize(MF), as POWER ABI requires backchain 918// pointer is always stored at SP, we will get a free probe due to an essential 919// STU(X) instruction. 921// To be consistent with other targets, a pseudo instruction is emitted and 922// will be later expanded in `inlineStackProbe`. 924TII.get(isPPC64 ? PPC::PROBED_STACKALLOC_64
925 : PPC::PROBED_STACKALLOC_32))
927 .
addDef(ScratchReg)
// ScratchReg stores the old sp. 929// FIXME: HasSTUX is only read if HasRedZone is not set, in such case, we 930// update the ScratchReg to meet the assumption that ScratchReg contains 931// the NegFrameSize. This solution is rather tricky. 938// This condition must be kept in sync with canUseAsPrologue. 939if (HasBP && MaxAlign > 1) {
956assert(!SingleScratchReg &&
"Only a single scratch reg available");
957TII.materializeImmPostRA(
MBB,
MBBI, dl, TempReg, NegFrameSize);
967 }
elseif (!isLargeFrame) {
973TII.materializeImmPostRA(
MBB,
MBBI, dl, ScratchReg, NegFrameSize);
981// Save the TOC register after the stack pointer update if a prologue TOC 982// save is required for the function. 984assert(isELFv2ABI &&
"TOC saves in the prologue only supported on ELFv2");
992assert(!isPPC64 &&
"A red zone is always available on PPC64");
994// The negated frame size is in ScratchReg, and the SPReg has been 995// decremented by the frame size: SPReg = old SPReg + ScratchReg. 996// Since FPOffset, PBPOffset, etc. are relative to the beginning of 997// the stack frame (i.e. the old SP), ideally, we would put the old 998// SP into a register and use it as the base for the stores. The 999// problem is that the only available register may be ScratchReg, 1000// which could be R0, and R0 cannot be used as a base address. 1002// First, set ScratchReg to the old SP. This may need to be modified 1008if (ScratchReg == PPC::R0) {
1009// R0 cannot be used as a base register, but it can be used as an 1010// index in a store-indexed. 1013// R0 += (FPOffset-LastOffset). 1014// Need addic, since addi treats R0 as 0. 1017 .
addImm(FPOffset-LastOffset);
1018 LastOffset = FPOffset;
1019// Store FP into *R0. 1023 .
addReg(ScratchReg);
// This will be the index (R0 is ok here). 1026// R0 += (PBPOffset-LastOffset). 1029 .
addImm(PBPOffset-LastOffset);
1030 LastOffset = PBPOffset;
1034 .
addReg(ScratchReg);
// This will be the index (R0 is ok here). 1037// R0 += (BPOffset-LastOffset). 1040 .
addImm(BPOffset-LastOffset);
1041 LastOffset = BPOffset;
1045 .
addReg(ScratchReg);
// This will be the index (R0 is ok here). 1046// BP = R0-LastOffset 1052// ScratchReg is not R0, so use it as the base register. It is 1053// already set to the old SP, so we can use the offsets directly. 1055// Now that the stack frame has been allocated, save all the necessary 1056// registers using ScratchReg as the base address. 1078// The frame size is a known 16-bit constant (fitting in the immediate 1079// field of STWU). To be here we have to be compiling for PPC32. 1080// Since the SPReg has been decreased by FrameSize, add it back to each 1085 .
addImm(FrameSize + FPOffset)
1090 .
addImm(FrameSize + PBPOffset)
1095 .
addImm(FrameSize + BPOffset)
1106 isInt<16>(FrameSize + LROffset) && !HasROPProtect)
1107 SaveLR(LROffset + FrameSize);
1109// Add Call Frame Information for the instructions we generated above. 1114// Define CFA in terms of BP. Do this in preference to using FP/SP, 1115// because if the stack needed aligning then CFA won't be at a fixed 1116// offset from FP/SP. 1117unsigned Reg =
MRI->getDwarfRegNum(BPReg,
true);
1121// Adjust the definition of CFA to account for the change in SP. 1130// Describe where FP was saved, at a fixed offset from CFA. 1131unsigned Reg =
MRI->getDwarfRegNum(
FPReg,
true);
1139// Describe where FP was saved, at a fixed offset from CFA. 1140unsigned Reg =
MRI->getDwarfRegNum(PPC::R30,
true);
1148// Describe where BP was saved, at a fixed offset from CFA. 1149unsigned Reg =
MRI->getDwarfRegNum(BPReg,
true);
1157// Describe where LR was saved, at a fixed offset from CFA. 1158unsigned Reg =
MRI->getDwarfRegNum(LRReg,
true);
1166// If there is a frame pointer, copy R1 into R31 1172if (!HasBP && needsCFI) {
1173// Change the definition of CFA from SP+offset to FP+offset, because SP 1174// will change at every alloca. 1175unsigned Reg =
MRI->getDwarfRegNum(
FPReg,
true);
1185// Describe where callee saved registers were saved, at fixed offsets from 1190if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM)
continue;
1192// This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just 1193// subregisters of CR2. We just need to emit a move of CR2. 1194if (PPC::CRBITRCRegClass.
contains(Reg))
1197if ((Reg == PPC::X2 || Reg == PPC::R2) && MustSaveTOC)
1200// For 64-bit SVR4 when we have spilled CRs, the spill location 1201// is SP+8, not a frame-relative slot. 1202if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
1203// In the ELFv1 ABI, only CR2 is noted in CFI and stands in for 1204// the whole CR word. In the ELFv2 ABI, every CR that was 1205// actually saved gets its own CFI record. 1206Register CRReg = isELFv2ABI? Reg : PPC::CR2;
1208nullptr,
MRI->getDwarfRegNum(CRReg,
true), CRSaveOffset));
1214if (
I.isSpilledToReg()) {
1215unsigned SpilledReg =
I.getDstReg();
1217nullptr,
MRI->getDwarfRegNum(Reg,
true),
1218MRI->getDwarfRegNum(SpilledReg,
true)));
1223// We have changed the object offset above but we do not want to change 1224// the actual offsets in the CFI instruction so we have to undo the 1225// offset change here. 1226if (MovingStackUpdateDown)
1230nullptr,
MRI->getDwarfRegNum(Reg,
true),
Offset));
1240bool isPPC64 = Subtarget.
isPPC64();
1245// AIX assembler does not support cfi directives. 1248int Opc =
MI.getOpcode();
1249return Opc == PPC::PROBED_STACKALLOC_64 || Opc == PPC::PROBED_STACKALLOC_32;
1251if (StackAllocMIPos == PrologMBB.
end())
1257 int64_t NegFrameSize =
MI.getOperand(2).getImm();
1259 int64_t NegProbeSize = -(int64_t)ProbeSize;
1260assert(isInt<32>(NegProbeSize) &&
"Unhandled probe size");
1261 int64_t NumBlocks = NegFrameSize / NegProbeSize;
1262 int64_t NegResidualSize = NegFrameSize % NegProbeSize;
1264Register ScratchReg =
MI.getOperand(0).getReg();
1271constMCInstrDesc &CopyInst =
TII.get(isPPC64 ? PPC::OR8 : PPC::OR);
1272// Subroutines to generate .cfi_* directives. 1275unsigned RegNum =
MRI->getDwarfRegNum(Reg,
true);
1284unsigned RegNum =
MRI->getDwarfRegNum(Reg,
true);
1290// Subroutine to determine if we can use the Imm as part of d-form. 1291auto CanUseDForm = [](int64_t Imm) {
return isInt<16>(Imm) && Imm % 4 == 0; };
1292// Subroutine to materialize the Imm into TempReg. 1296assert(isInt<32>(Imm) &&
"Unhandled imm");
1308// Subroutine to store frame pointer and decrease stack pointer by probe size. 1324// Used to probe stack when realignment is required. 1325// Note that, according to ABI's requirement, *sp must always equals the 1326// value of back-chain pointer, only st(w|d)u(x) can be used to update sp. 1327// Following is pseudo code: 1328// final_sp = (sp & align) + negframesize; 1329// neg_gap = final_sp - sp; 1330// while (neg_gap < negprobesize) { 1331// stdu fp, negprobesize(sp); 1332// neg_gap -= negprobesize; 1334// stdux fp, sp, neg_gap 1336// When HasBP & HasRedzone, back-chain pointer is already saved in BPReg 1337// before probe code, we don't need to save it, so we get one additional reg 1338// that can be used to materialize the probeside if needed to use xform. 1339// Otherwise, we can NOT materialize probeside, so we can only use Dform for 1342// The allocations are: 1343// if (HasBP && HasRedzone) { 1344// r0: materialize the probesize if needed so that we can use xform. 1347// r0: back-chain pointer 1353assert(HasBP &&
"The function is supposed to have base pointer when its " 1354"stack is realigned.");
1357// FIXME: We can eliminate this limitation if we get more infomation about 1358// which part of redzone are already used. Used redzone can be treated 1359// probed. But there might be `holes' in redzone probed, this could 1360// complicate the implementation. 1362"Probe size should be larger or equal to the size of red-zone so " 1363"that red-zone is not clobbered by probing.");
1366// FIXME: We only support NegProbeSize materializable by DForm currently. 1367// When HasBP && HasRedzone, we can use xform if we have an additional idle 1369 NegProbeSize = std::max(NegProbeSize, -((int64_t)1 << 15));
1370assert(isInt<16>(NegProbeSize) &&
1371"NegProbeSize should be materializable by DForm");
1373// Layout of output assembly kinda like: 1376// sub $scratchreg, $finalsp, r1 1377// cmpdi $scratchreg, <negprobesize> 1380// stdu <backchain>, <negprobesize>(r1) 1381// sub $scratchreg, $scratchreg, negprobesize 1382// cmpdi $scratchreg, <negprobesize> 1385// stdux <backchain>, r1, $scratchreg 1388 MF.
insert(MBBInsertPoint, ProbeLoopBodyMBB);
1390 MF.
insert(MBBInsertPoint, ProbeExitMBB);
1393Register BackChainPointer = HasRedZone ? BPReg : TempReg;
1394 allocateAndProbe(*ProbeExitMBB, ProbeExitMBB->
end(), 0, ScratchReg,
false,
1397// PROBED_STACKALLOC_64 assumes Operand(1) stores the old sp, copy BPReg 1398// to TempReg to satisfy it. 1399BuildMI(*ProbeExitMBB, ProbeExitMBB->
end(),
DL, CopyInst, TempReg)
1424Register BackChainPointer = HasRedZone ? BPReg : TempReg;
1425 allocateAndProbe(*ProbeLoopBodyMBB, ProbeLoopBodyMBB->
end(), NegProbeSize,
1426 0,
true/*UseDForm*/, BackChainPointer);
1427BuildMI(ProbeLoopBodyMBB,
DL,
TII.get(isPPC64 ? PPC::ADDI8 : PPC::ADDI),
1431BuildMI(ProbeLoopBodyMBB,
DL,
TII.get(isPPC64 ? PPC::CMPDI : PPC::CMPWI),
1438 .
addMBB(ProbeLoopBodyMBB);
1446// For case HasBP && MaxAlign > 1, we have to realign the SP by performing 1447// SP = SP - SP % MaxAlign, thus make the probe more like dynamic probe since 1448// the offset subtracted from SP is determined by SP's runtime value. 1449if (HasBP && MaxAlign > 1) {
1450// Calculate final stack pointer. 1462BuildMI(*CurrentMBB, {
MI},
DL,
TII.get(isPPC64 ? PPC::SUBF8 : PPC::SUBF),
1466 MaterializeImm(*CurrentMBB, {
MI}, NegFrameSize, ScratchReg);
1467BuildMI(*CurrentMBB, {
MI},
DL,
TII.get(isPPC64 ? PPC::ADD8 : PPC::ADD4),
1471 CurrentMBB = probeRealignedStack(*CurrentMBB, {
MI}, ScratchReg,
FPReg);
1475// Initialize current frame pointer. 1477// Use FPReg to calculate CFA. 1479 buildDefCFA(*CurrentMBB, {
MI},
FPReg, 0);
1480// Probe residual part. 1481if (NegResidualSize) {
1482bool ResidualUseDForm = CanUseDForm(NegResidualSize);
1483if (!ResidualUseDForm)
1484 MaterializeImm(*CurrentMBB, {
MI}, NegResidualSize, ScratchReg);
1485 allocateAndProbe(*CurrentMBB, {
MI}, NegResidualSize, ScratchReg,
1486 ResidualUseDForm,
FPReg);
1488bool UseDForm = CanUseDForm(NegProbeSize);
1489// If number of blocks is small, just probe them directly. 1492 MaterializeImm(*CurrentMBB, {
MI}, NegProbeSize, ScratchReg);
1493for (
int i = 0; i < NumBlocks; ++i)
1494 allocateAndProbe(*CurrentMBB, {
MI}, NegProbeSize, ScratchReg, UseDForm,
1497// Restore using SPReg to calculate CFA. 1501// Since CTR is a volatile register and current shrinkwrap implementation 1502// won't choose an MBB in a loop as the PrologMBB, it's safe to synthesize a 1503// CTR loop to probe. 1504// Calculate trip count and stores it in CTRReg. 1505 MaterializeImm(*CurrentMBB, {
MI}, NumBlocks, ScratchReg);
1506BuildMI(*CurrentMBB, {
MI},
DL,
TII.get(isPPC64 ? PPC::MTCTR8 : PPC::MTCTR))
1509 MaterializeImm(*CurrentMBB, {
MI}, NegProbeSize, ScratchReg);
1510// Create MBBs of the loop. 1514 MF.
insert(MBBInsertPoint, LoopMBB);
1516 MF.
insert(MBBInsertPoint, ExitMBB);
1517// Synthesize the loop body. 1518 allocateAndProbe(*LoopMBB, LoopMBB->
end(), NegProbeSize, ScratchReg,
1520BuildMI(LoopMBB,
DL,
TII.get(isPPC64 ? PPC::BDNZ8 : PPC::BDNZ))
1524// Synthesize the exit MBB. 1525 ExitMBB->
splice(ExitMBB->
end(), CurrentMBB,
1531// Restore using SPReg to calculate CFA. 1539MI.eraseFromParent();
1548 dl =
MBBI->getDebugLoc();
1553// Get alignment info so we know how to restore the SP. 1556// Get the number of bytes allocated from the FrameInfo. 1559// Get processor type. 1560bool isPPC64 = Subtarget.
isPPC64();
1562// Check if the link register (LR) has been saved. 1566bool MustSaveCR = !MustSaveCRs.
empty();
1567// Do we have a frame pointer and/or base pointer for this function? 1568bool HasFP =
hasFP(MF);
1571bool HasROPProtect = Subtarget.hasROPProtect();
1572bool HasPrivileged = Subtarget.hasPrivileged();
1578Register TempReg = isPPC64 ? PPC::X12 : PPC::R12;
// another scratch reg 1583constMCInstrDesc& LoadImmShiftedInst =
TII.get( isPPC64 ? PPC::LIS8
1598TII.get(isPPC64 ? (HasPrivileged ? PPC::HASHCHKP8 : PPC::HASHCHK8)
1599 : (HasPrivileged ? PPC::HASHCHKP : PPC::HASHCHK));
1602 int64_t FPOffset = 0;
1604// Using the same bool variable as below to suppress compiler warnings. 1605bool SingleScratchReg = findScratchRegister(&
MBB,
true,
false, &ScratchReg,
1607assert(SingleScratchReg &&
1608"Could not find an available scratch register");
1610 SingleScratchReg = ScratchReg == TempReg;
1614assert(FPIndex &&
"No Frame Pointer Save Slot!");
1618 int64_t BPOffset = 0;
1621assert(BPIndex &&
"No Base Pointer Save Slot!");
1625 int64_t PBPOffset = 0;
1628assert(PBPIndex &&
"No PIC Base Pointer Save Slot!");
1635unsigned RetOpcode =
MBBI->getOpcode();
1636bool UsesTCRet = RetOpcode == PPC::TCRETURNri ||
1637 RetOpcode == PPC::TCRETURNdi ||
1638 RetOpcode == PPC::TCRETURNai ||
1639 RetOpcode == PPC::TCRETURNri8 ||
1640 RetOpcode == PPC::TCRETURNdi8 ||
1641 RetOpcode == PPC::TCRETURNai8;
1646assert(StackAdjust.
isImm() &&
"Expecting immediate value.");
1647// Adjust stack pointer. 1648int StackAdj = StackAdjust.
getImm();
1649int Delta = StackAdj - MaxTCRetDelta;
1650assert((Delta >= 0) &&
"Delta must be positive");
1652 FrameSize += (StackAdj +Delta);
1654 FrameSize += StackAdj;
1658// Frames of 32KB & larger require special handling because they cannot be 1659// indexed into with a simple LD/LWZ immediate offset operand. 1660bool isLargeFrame = !isInt<16>(FrameSize);
1662// On targets without red zone, the SP needs to be restored last, so that 1663// all live contents of the stack frame are upwards of the SP. This means 1664// that we cannot restore SP just now, since there may be more registers 1665// to restore from the stack frame (e.g. R31). If the frame size is not 1666// a simple immediate value, we will need a spare register to hold the 1667// restored SP. If the frame size is known and small, we can simply adjust 1668// the offsets of the registers to be restored, and still use SP to restore 1669// them. In such case, the final update of SP will be to add the frame 1671// To simplify the code, set RBReg to the base register used to restore 1672// values from the stack, and set SPAdd to the value that needs to be added 1673// to the SP at the end. The default values are as if red zone was present. 1674unsigned RBReg =
SPReg;
1677// Check if we can move the stack update instruction up the epilogue 1678// past the callee saves. This will allow the move to LR instruction 1679// to be executed before the restores of the callee saves which means 1680// that the callee saves can hide the latency from the MTLR instrcution. 1682if (stackUpdateCanBeMoved(MF)) {
1685// If the callee saved register is spilled to another register abort the 1686// stack update movement. 1687if (CSI.isSpilledToReg()) {
1688 StackUpdateLoc =
MBBI;
1691int FrIdx = CSI.getFrameIdx();
1692// If the frame index is not negative the callee saved info belongs to a 1693// stack object that is not a fixed stack object. We ignore non-fixed 1694// stack objects because we won't move the update of the stack pointer 1702// Abort the operation as we can't update all CSR restores. 1703 StackUpdateLoc =
MBBI;
1710// In the prologue, the loaded (or persistent) stack pointer value is 1711// offset by the STDU/STDUX/STWU/STWUX instruction. For targets with red 1712// zone add this offset back now. 1714// If the function has a base pointer, the stack pointer has been copied 1715// to it so we can restore it by copying in the other direction. 1716if (HasRedZone && HasBP) {
1721// If this function contained a fastcc call and GuaranteedTailCallOpt is 1722// enabled (=> hasFastCall()==true) the fastcc call might contain a tail 1723// call which invalidates the stack pointer value in SP(0). So we use the 1724// value of R31 in this case. Similar situation exists with setjmp. 1726assert(HasFP &&
"Expecting a valid frame pointer.");
1733TII.materializeImmPostRA(
MBB,
MBBI, dl, ScratchReg, FrameSize);
1745// Make sure that adding FrameSize will not overflow the max offset 1747assert(FPOffset <= 0 && BPOffset <= 0 && PBPOffset <= 0 &&
1748"Local offsets should be negative");
1750 FPOffset += FrameSize;
1751 BPOffset += FrameSize;
1752 PBPOffset += FrameSize;
1755// We don't want to use ScratchReg as a base register, because it 1756// could happen to be R0. Use FP instead, but make sure to preserve it. 1758// If FP is not saved, copy it to ScratchReg. 1770assert(RBReg != ScratchReg &&
"Should have avoided ScratchReg");
1771// If there is no red zone, ScratchReg may be needed for holding a useful 1772// value (although not the base register). Make sure it is not overwritten 1775// If we need to restore both the LR and the CR and we only have one 1776// available scratch register, we must do them one at a time. 1777if (MustSaveCR && SingleScratchReg &&
MustSaveLR) {
1778// Here TempReg == ScratchReg, and in the absence of red zone ScratchReg 1780assert(HasRedZone &&
"Expecting red zone");
1784for (
unsigned i = 0, e = MustSaveCRs.
size(); i != e; ++i)
1789// Delay restoring of the LR if ScratchReg is needed. This is ok, since 1790// LR is stored in the caller's stack frame. ScratchReg will be needed 1791// if RBReg is anything other than SP. We shouldn't use ScratchReg as 1792// a base register anyway, because it may happen to be R0. 1793bool LoadedLR =
false;
1801if (MustSaveCR && !(SingleScratchReg &&
MustSaveLR)) {
1802assert(RBReg ==
SPReg &&
"Should be using SP as a base register");
1809// If there is red zone, restore FP directly, since SP has already been 1810// restored. Otherwise, restore the value of FP into ScratchReg. 1811if (HasRedZone || RBReg ==
SPReg)
1831// There is nothing more to be loaded from the stack, so now we can 1832// restore SP: SP = RBReg + SPAdd. 1833if (RBReg !=
SPReg || SPAdd != 0) {
1834assert(!HasRedZone &&
"This should not happen with red zone");
1835// If SPAdd is 0, generate a copy. 1845assert(RBReg != ScratchReg &&
"Should be using FP or SP as base register");
1851// Now load the LR from the caller's stack frame. 1860for (
unsigned i = 0, e = MustSaveCRs.
size(); i != e; ++i)
1865// If ROP protection is required, an extra instruction is added to compute a 1866// hash and then compare it to the hash stored in the prologue. 1870assert((ImmOffset <= -8 && ImmOffset >= -512) &&
1871"ROP hash check location offset out of range.");
1872assert(((ImmOffset & 0x7) == 0) &&
1873"ROP hash check location offset must be 8 byte aligned.");
1882// Callee pop calling convention. Pop parameter/linkage area. Used for tail 1885unsigned RetOpcode =
MBBI->getOpcode();
1887 (RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8) &&
1892if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) {
1897 .
addImm(CallerAllocatedAmt >> 16);
1900 .
addImm(CallerAllocatedAmt & 0xFFFF);
1907 createTailCallBranchInstr(
MBB);
1915// If we got this far a first terminator should exist. 1921// Create branch instruction for pseudo tail call return instruction. 1922// The TCRETURNdi variants are direct calls. Valid targets for those are 1923// MO_GlobalAddress operands as well as MO_ExternalSymbol with PC-Rel 1924// since we can tail call external functions with PC-Rel (i.e. we don't need 1925// to worry about different TOC pointers). Some of the external functions will 1926// be MO_GlobalAddress while others like memcpy for example, are going to 1927// be MO_ExternalSymbol. 1928unsigned RetOpcode =
MBBI->getOpcode();
1929if (RetOpcode == PPC::TCRETURNdi) {
1940 }
elseif (RetOpcode == PPC::TCRETURNri) {
1942assert(
MBBI->getOperand(0).isReg() &&
"Expecting register operand.");
1944 }
elseif (RetOpcode == PPC::TCRETURNai) {
1948 }
elseif (RetOpcode == PPC::TCRETURNdi8) {
1959 }
elseif (RetOpcode == PPC::TCRETURNri8) {
1961assert(
MBBI->getOperand(0).isReg() &&
"Expecting register operand.");
1963 }
elseif (RetOpcode == PPC::TCRETURNai8) {
1979// Do not explicitly save the callee saved VSRp registers. 1980// The individual VSR subregisters will be saved instead. 1981 SavedRegs.
reset(PPC::VSRp26);
1982 SavedRegs.
reset(PPC::VSRp27);
1983 SavedRegs.
reset(PPC::VSRp28);
1984 SavedRegs.
reset(PPC::VSRp29);
1985 SavedRegs.
reset(PPC::VSRp30);
1986 SavedRegs.
reset(PPC::VSRp31);
1988// Save and clear the LR state. 1990unsigned LR = RegInfo->getRARegister();
1992 SavedRegs.
reset(LR);
1994// Save R31 if necessary 1996constbool isPPC64 = Subtarget.
isPPC64();
1999// If the frame pointer save index hasn't been defined yet. 2001// Find out what the fix offset of the frame pointer save area. 2003// Allocate the frame index for frame pointer save area. 2012// Allocate the frame index for the base pointer save area. 2018// Reserve stack space for the PIC Base register (R30). 2019// Only used in SVR4 32-bit. 2025// Make sure we don't explicitly spill r31, because, for example, we have 2026// some inline asm which explicitly clobbers it, when we otherwise have a 2027// frame pointer and are using r31's spill slot for the prologue/epilogue 2028// code. Same goes for the base pointer and the PIC base register. 2030 SavedRegs.
reset(isPPC64 ? PPC::X31 : PPC::R31);
2033// On AIX, when BaseRegister(R30) is used, need to spill r31 too to match 2034// AIX trackback table requirement. 2035if (!
needsFP(MF) && !SavedRegs.
test(isPPC64 ? PPC::X31 : PPC::R31) &&
2039"Invalid base register on AIX!");
2040 SavedRegs.
set(isPPC64 ? PPC::X31 : PPC::R31);
2044 SavedRegs.
reset(PPC::R30);
2046// Reserve stack space to move the linkage area to in case of a tail call. 2053// Allocate the nonvolatile CR spill slot iff the function uses CR 2, 3, or 4. 2054// For 64-bit SVR4, and all flavors of AIX we create a FixedStack 2055// object at the offset of the CR-save slot in the linkage area. The actual 2056// save and restore of the condition register will be created as part of the 2057// prologue and epilogue insertion, but the FixedStack object is needed to 2058// keep the CalleSavedInfo valid. 2059if ((SavedRegs.
test(PPC::CR2) || SavedRegs.
test(PPC::CR3) ||
2060 SavedRegs.
test(PPC::CR4))) {
2061constuint64_t SpillSize = 4;
// Condition register is always 4 bytes. 2062const int64_t SpillOffset =
2066/* IsImmutable */true,
/* IsAliased */false);
2073// Get callee saved register information. 2077// If the function is shrink-wrapped, and if the function has a tail call, the 2078// tail call might not be in the new RestoreBlock, so real branch instruction 2079// won't be generated by emitEpilogue(), because shrink-wrap has chosen new 2080// RestoreBlock. So we handle this case here. 2085 createTailCallBranchInstr(
MBB);
2089// Early exit if no callee saved registers are modified! 2090if (CSI.empty() && !
needsFP(MF)) {
2095unsigned MinGPR = PPC::R31;
2096unsigned MinG8R = PPC::X31;
2097unsigned MinFPR = PPC::F31;
2098unsigned MinVR = Subtarget.hasSPE() ? PPC::S31 : PPC::V31;
2100bool HasGPSaveArea =
false;
2101bool HasG8SaveArea =
false;
2102bool HasFPSaveArea =
false;
2103bool HasVRSaveArea =
false;
2113 (Reg != PPC::X2 && Reg != PPC::R2)) &&
2114"Not expecting to try to spill R2 in a function that must save TOC");
2115if (PPC::GPRCRegClass.
contains(Reg)) {
2116 HasGPSaveArea =
true;
2123 }
elseif (PPC::G8RCRegClass.
contains(Reg)) {
2124 HasG8SaveArea =
true;
2131 }
elseif (PPC::F8RCRegClass.
contains(Reg)) {
2132 HasFPSaveArea =
true;
2139 }
elseif (PPC::CRBITRCRegClass.
contains(Reg) ||
2141 ;
// do nothing, as we already know whether CRs are spilled 2142 }
elseif (PPC::VRRCRegClass.
contains(Reg) ||
2143 PPC::SPERCRegClass.
contains(Reg)) {
2144// Altivec and SPE are mutually exclusive, but have the same stack 2145// alignment requirements, so overload the save area for both cases. 2146 HasVRSaveArea =
true;
2161 int64_t LowerBound = 0;
2163// Take into account stack space reserved for tail calls. 2167 LowerBound = TCSPDelta;
2170// The Floating-point register save area is right below the back chain word 2171// of the previous stack frame. 2173for (
unsigned i = 0, e = FPRegs.
size(); i != e; ++i) {
2174int FI = FPRegs[i].getFrameIdx();
2179 LowerBound -= (31 -
TRI->getEncodingValue(MinFPR) + 1) * 8;
2182// Check whether the frame pointer register is allocated. If so, make sure it 2183// is spilled to the correct offset. 2186assert(FI &&
"No Frame Pointer Save Slot!");
2188// FP is R31/X31, so no need to update MinGPR/MinG8R. 2189 HasGPSaveArea =
true;
2194assert(FI &&
"No PIC Base Pointer Save Slot!");
2197 MinGPR = std::min<unsigned>(MinGPR, PPC::R30);
2198 HasGPSaveArea =
true;
2204assert(FI &&
"No Base Pointer Save Slot!");
2208if (PPC::G8RCRegClass.
contains(BP)) {
2209 MinG8R = std::min<unsigned>(MinG8R, BP);
2210 HasG8SaveArea =
true;
2211 }
elseif (PPC::GPRCRegClass.
contains(BP)) {
2212 MinGPR = std::min<unsigned>(MinGPR, BP);
2213 HasGPSaveArea =
true;
2217// General register save area starts right below the Floating-point 2218// register save area. 2219if (HasGPSaveArea || HasG8SaveArea) {
2220// Move general register save area spill slots down, taking into account 2221// the size of the Floating-point register save area. 2222for (
unsigned i = 0, e = GPRegs.
size(); i != e; ++i) {
2223if (!GPRegs[i].isSpilledToReg()) {
2224int FI = GPRegs[i].getFrameIdx();
2229// Move general register save area spill slots down, taking into account 2230// the size of the Floating-point register save area. 2231for (
unsigned i = 0, e = G8Regs.
size(); i != e; ++i) {
2232if (!G8Regs[i].isSpilledToReg()) {
2233int FI = G8Regs[i].getFrameIdx();
2239 std::min<unsigned>(
TRI->getEncodingValue(MinGPR),
2240TRI->getEncodingValue(MinG8R));
2242constunsigned GPRegSize = Subtarget.
isPPC64() ? 8 : 4;
2243 LowerBound -= (31 - MinReg + 1) * GPRegSize;
2246// For 32-bit only, the CR save area is below the general register 2247// save area. For 64-bit SVR4, the CR save area is addressed relative 2248// to the stack pointer and hence does not need an adjustment here. 2249// Only CR2 (the first nonvolatile spilled) has an associated frame 2250// index so that we have a single uniform save area. 2252// Adjust the frame index of the CR spill slot. 2253for (
constauto &CSInfo : CSI) {
2254if (CSInfo.getReg() == PPC::CR2) {
2255int FI = CSInfo.getFrameIdx();
2261 LowerBound -= 4;
// The CR save area is always 4 bytes long. 2264// Both Altivec and SPE have the same alignment and padding requirements 2265// within the stack frame. 2267// Insert alignment padding, we need 16-byte alignment. Note: for positive 2268// number the alignment formula is : y = (x + (n-1)) & (~(n-1)). But since 2269// we are using negative number here (the stack grows downward). We should 2270// use formula : y = x & (~(n-1)). Where x is the size before aligning, n 2271// is the alignment size ( n = 16 here) and y is the size after aligning. 2272assert(LowerBound <= 0 &&
"Expect LowerBound have a non-positive value!");
2273 LowerBound &= ~(15);
2275for (
unsigned i = 0, e = VRegs.
size(); i != e; ++i) {
2276int FI = VRegs[i].getFrameIdx();
2288// Reserve a slot closest to SP or frame pointer if we have a dynalloc or 2289// a large stack, which will require scavenging a register to materialize a 2292// We need to have a scavenger spill slot for spills if the frame size is 2293// large. In case there is no free register for large-offset addressing, 2294// this slot is used for the necessary emergency spill. Also, we need the 2295// slot for dynamic stack allocations. 2297// The scavenger might be invoked if the frame offset does not fit into 2298// the 16-bit immediate in case of not SPE and 8-bit in case of SPE. 2299// We don't know the complete frame size here because we've not yet computed 2300// callee-saved register spills or the needed alignment padding. 2303bool NeedSpills = Subtarget.hasSPE() ? !isInt<8>(StackSize) : !isInt<16>(StackSize);
2311unsignedSize =
TRI.getSpillSize(RC);
2312Align Alignment =
TRI.getSpillAlign(RC);
2315// Might we have over-aligned allocas? 2319// These kinds of spills might need two registers. 2325// This function checks if a callee saved gpr can be spilled to a volatile 2326// vector register. This occurs for leaf functions when the option 2327// ppc-enable-pe-vector-spills is enabled. If there are any remaining registers 2328// which were not spilled to vectors, return false so the target independent 2329// code can handle them by assigning a FrameIdx to a stack slot. 2332 std::vector<CalleeSavedInfo> &CSI)
const{
2335returntrue;
// Early exit if no callee saved registers are modified! 2341if (Subtarget.hasSPE()) {
2342// In case of SPE we only have SuperRegs and CRs 2343// in our CalleSaveInfo vector. 2345for (
auto &CalleeSaveReg : CSI) {
2348MCPhysReg Higher = RegInfo->getSubReg(Reg, 2);
2350if (
// Check only for SuperRegs. 2352// Replace Reg if only lower-32 bits modified 2353 !
MRI.isPhysRegModified(Higher))
2358// Early exit if cannot spill gprs to volatile vector registers. 2363// Build a BitVector of VSRs that can be used for spilling GPRs. 2366for (
unsigned i = 0; CSRegs[i]; ++i)
2367 BVCalleeSaved.
set(CSRegs[i]);
2369for (
unsigned Reg : BVAllocatable.
set_bits()) {
2370// Set to 0 if the register is not a volatile VSX register, or if it is 2371// used in the function. 2372if (BVCalleeSaved[Reg] || !PPC::VSRCRegClass.
contains(Reg) ||
2373MRI.isPhysRegUsed(Reg))
2374 BVAllocatable.
reset(Reg);
2377bool AllSpilledToReg =
true;
2378unsigned LastVSRUsedForSpill = 0;
2379for (
auto &CS : CSI) {
2380if (BVAllocatable.
none())
2385if (!PPC::G8RCRegClass.
contains(Reg)) {
2386 AllSpilledToReg =
false;
2390// For P9, we can reuse LastVSRUsedForSpill to spill two GPRs 2391// into one VSR using the mtvsrdd instruction. 2392if (LastVSRUsedForSpill != 0) {
2393 CS.setDstReg(LastVSRUsedForSpill);
2394 BVAllocatable.
reset(LastVSRUsedForSpill);
2395 LastVSRUsedForSpill = 0;
2399unsigned VolatileVFReg = BVAllocatable.
find_first();
2400if (VolatileVFReg < BVAllocatable.
size()) {
2401 CS.setDstReg(VolatileVFReg);
2402 LastVSRUsedForSpill = VolatileVFReg;
2404 AllSpilledToReg =
false;
2407return AllSpilledToReg;
2419bool CRSpilled =
false;
2423 VSRContainingGPRs.clear();
2425// Map each VSR to GPRs to be spilled with into it. Single VSR can contain one 2426// or two GPRs, so we need table to record information for later save/restore. 2428if (
Info.isSpilledToReg()) {
2429auto &SpilledVSR = VSRContainingGPRs[
Info.getDstReg()];
2430assert(SpilledVSR.second == 0 &&
2431"Can't spill more than two GPRs into VSR!");
2432if (SpilledVSR.first == 0)
2433 SpilledVSR.first =
Info.getReg();
2435 SpilledVSR.second =
Info.getReg();
2442// CR2 through CR4 are the nonvolatile CR fields. 2443bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4;
2445// Add the callee-saved register as live-in; it's killed at the spill. 2446// Do not do this for callee-saved registers that are live-in to the 2447// function because they will already be marked live-in and this will be 2448// adding it for a second time. It is an error to add the same register 2449// to the set more than once. 2451bool IsLiveIn =
MRI.isLiveIn(Reg);
2455if (CRSpilled && IsCRField) {
2460// The actual spill will happen in the prologue. 2461if ((Reg == PPC::X2 || Reg == PPC::R2) && MustSaveTOC)
2464// Insert the spill to the stack frame. 2468// The actual spill will happen at the start of the prologue. 2474// 32-bit: FP-relative. Note that we made sure CR2-CR4 all have 2475// the same frame index in PPCRegisterInfo::hasReservedSpillSlot. 2486if (
I.isSpilledToReg()) {
2487unsigned Dst =
I.getDstReg();
2492if (VSRContainingGPRs[Dst].second != 0) {
2493assert(Subtarget.hasP9Vector() &&
2494"mtvsrdd is unavailable on pre-P9 targets.");
2500 }
elseif (VSRContainingGPRs[Dst].second == 0) {
2501assert(Subtarget.hasP8Vector() &&
2502"Can't move GPR to VSR on pre-P8 targets.");
2506TRI->getSubReg(Dst, PPC::sub_64))
2514// Use !IsLiveIn for the kill flag. 2515// We do not want to kill registers that are live in this function 2516// before their use because they will become undefined registers. 2517// Functions without NoUnwind need to preserve the order of elements in 2518// saved vector registers. 2521TII.storeRegToStackSlotNoUpd(
MBB,
MI, Reg, !IsLiveIn,
2522I.getFrameIdx(), RC,
TRI);
2540unsigned MoveReg = PPC::R12;
2542// 32-bit: FP-relative 2545 CSI[CSIIndex].getFrameIdx()));
2547unsigned RestoreOp = PPC::MTOCRF;
2566I->getOpcode() == PPC::ADJCALLSTACKUP) {
2567// Add (actually subtract) back the amount the callee popped on return. 2568if (
int CalleeAmt =
I->getOperand(1).getImm()) {
2571unsigned StackReg =
is64Bit ? PPC::X1 : PPC::R1;
2572unsigned TmpReg =
is64Bit ? PPC::X0 : PPC::R0;
2573unsigned ADDIInstr =
is64Bit ? PPC::ADDI8 : PPC::ADDI;
2574unsigned ADDInstr =
is64Bit ? PPC::ADD8 : PPC::ADD4;
2575unsigned LISInstr =
is64Bit ? PPC::LIS8 : PPC::LIS;
2576unsigned ORIInstr =
is64Bit ? PPC::ORI8 : PPC::ORI;
2579if (isInt<16>(CalleeAmt)) {
2586 .
addImm(CalleeAmt >> 16);
2589 .
addImm(CalleeAmt & 0xFFFF);
2596// Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions. 2601return PPC::CR2 == Reg || Reg == PPC::CR3 || Reg == PPC::CR4;
2611bool CR2Spilled =
false;
2612bool CR3Spilled =
false;
2613bool CR4Spilled =
false;
2614unsigned CSIIndex = 0;
2617// Initialize insertion-point logic; we will be restoring in reverse 2625for (
unsigned i = 0, e = CSI.
size(); i != e; ++i) {
2628if ((Reg == PPC::X2 || Reg == PPC::R2) && MustSaveTOC)
2631// Restore of callee saved condition register field is handled during 2632// epilogue insertion. 2636if (Reg == PPC::CR2) {
2638// The spill slot is associated only with CR2, which is the 2639// first nonvolatile spilled. Save it here. 2642 }
elseif (Reg == PPC::CR3) {
2645 }
elseif (Reg == PPC::CR4) {
2649// On 32-bit ELF when we first encounter a non-CR register after seeing at 2650// least one CR register, restore all spilled CRs together. 2651if (CR2Spilled || CR3Spilled || CR4Spilled) {
2655 CR2Spilled = CR3Spilled = CR4Spilled =
false;
2658if (CSI[i].isSpilledToReg()) {
2660unsigned Dst = CSI[i].getDstReg();
2665if (VSRContainingGPRs[Dst].second != 0) {
2666assert(Subtarget.hasP9Vector());
2667 NumPEReloadVSR += 2;
2669 VSRContainingGPRs[Dst].second)
2672 VSRContainingGPRs[Dst].first)
2674 }
elseif (VSRContainingGPRs[Dst].second == 0) {
2675assert(Subtarget.hasP8Vector());
2678 VSRContainingGPRs[Dst].first)
2687// Default behavior for non-CR saves. 2690// Functions without NoUnwind need to preserve the order of elements in 2691// saved vector registers. 2694TII.loadRegFromStackSlotNoUpd(
MBB,
I, Reg, CSI[i].getFrameIdx(), RC,
2701"loadRegFromStackSlot didn't insert any code!");
2705// Insert in reverse order. 2714// If we haven't yet spilled the CRs, do so now. 2715if (CR2Spilled || CR3Spilled || CR4Spilled) {
2717"Only set CR[2|3|4]Spilled on 32-bit SVR4.");
2719restoreCRs(is31, CR2Spilled, CR3Spilled, CR4Spilled,
MBB,
I, CSI, CSIIndex);
2726return TOCSaveOffset;
2730return FramePointerSaveOffset;
2734return BasePointerSaveOffset;
2745// The AIX ABI uses traceback tables for EH which require that if callee-saved 2746// register N is used, all registers N-31 must be saved/restored. 2747// NOTE: The check for AIX is not actually what is relevant. Traceback tables 2748// on Linux have the same requirements. It is just that AIX is the only ABI 2749// for which we actually use traceback tables. If another ABI needs to be 2750// supported that also uses them, we can add a check such as 2751// Subtarget.usesTraceBackTables(). 2753"Function updateCalleeSaves should only be called for AIX.");
2755// If there are no callee saves then there is nothing to do. 2756if (SavedRegs.
none())
2766// Traverse the CSRs twice so as not to rely on ascending ordering of 2767// registers in the array. The first pass finds the lowest numbered 2768// register and the second pass marks all higher numbered registers 2770for (
int i = 0; CSRegs[i]; i++) {
2771// Get the lowest numbered register for each class that actually needs 2774if (!SavedRegs.
test(Cand))
2776// When R2/X2 is a CSR and not used for passing arguments, it is allocated 2777// earlier than other volatile registers. R2/X2 is not contiguous with 2778// R13/X13 to R31/X31. 2779if (Cand == PPC::X2 || Cand == PPC::R2) {
2780 SavedRegs.
set(Cand);
2784if (PPC::GPRCRegClass.
contains(Cand) && Cand < LowestGPR)
2786elseif (PPC::G8RCRegClass.
contains(Cand) && Cand < LowestG8R)
2788elseif ((PPC::F4RCRegClass.
contains(Cand) ||
2789 PPC::F8RCRegClass.
contains(Cand)) &&
2792elseif (PPC::VRRCRegClass.
contains(Cand) && Cand < LowestVR)
2796for (
int i = 0; CSRegs[i]; i++) {
2798if ((PPC::GPRCRegClass.
contains(Cand) && Cand > LowestGPR) ||
2799 (PPC::G8RCRegClass.
contains(Cand) && Cand > LowestG8R) ||
2800 ((PPC::F4RCRegClass.
contains(Cand) ||
2801 PPC::F8RCRegClass.
contains(Cand)) &&
2802 Cand > LowestFPR) ||
2803 (PPC::VRRCRegClass.
contains(Cand) && Cand > LowestVR))
2804 SavedRegs.
set(Cand);
2809// On PPC64, we use `stux r1, r1, <scratch_reg>` to extend the stack; 2810// use `add r1, r1, <scratch_reg>` to release the stack frame. 2811// Scratch register contains a signed 64-bit number, which is negative 2812// when extending the stack and is positive when releasing the stack frame. 2813// To make `stux` and `add` paired, the absolute value of the number contained 2814// in the scratch register should be the same. Thus the maximum stack size 2815// is (2^63)-1, i.e., LONG_MAX. unsigned const MachineRegisterInfo * MRI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
Analysis containing CSE Info
const HexagonInstrInfo * TII
This file implements the LivePhysRegs utility for tracking liveness of physical registers.
unsigned const TargetRegisterInfo * TRI
static bool hasSpills(const MachineFunction &MF)
static unsigned computeCRSaveOffset(const PPCSubtarget &STI)
static void restoreCRs(bool is31, bool CR2Spilled, bool CR3Spilled, bool CR4Spilled, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef< CalleeSavedInfo > CSI, unsigned CSIIndex)
static unsigned computeReturnSaveOffset(const PPCSubtarget &STI)
static bool MustSaveLR(const MachineFunction &MF, unsigned LR)
MustSaveLR - Return true if this function requires that we save the LR register onto the stack in the...
#define CALLEE_SAVED_FPRS
static cl::opt< bool > EnablePEVectorSpills("ppc-enable-pe-vector-spills", cl::desc("Enable spills in prologue to vector registers."), cl::init(false), cl::Hidden)
#define CALLEE_SAVED_GPRS32
#define CALLEE_SAVED_GPRS64
static unsigned computeLinkageSize(const PPCSubtarget &STI)
static unsigned computeFramePointerSaveOffset(const PPCSubtarget &STI)
static bool isCalleeSavedCR(unsigned Reg)
static unsigned computeTOCSaveOffset(const PPCSubtarget &STI)
static bool hasNonRISpills(const MachineFunction &MF)
static bool spillsCR(const MachineFunction &MF)
static unsigned computeBasePointerSaveOffset(const PPCSubtarget &STI)
static constexpr Register SPReg
static constexpr Register FPReg
This file declares the machine register scavenger class.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
static void buildDefCFAReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned Reg, const SystemZInstrInfo *ZII)
static bool is64Bit(const char *name)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
LLVM Basic Block Representation.
bool test(unsigned Idx) const
int find_first() const
find_first - Returns the index of the first set bit, -1 if none of the bits are set.
size_type count() const
count - Returns the number of bits which are set.
int find_next(unsigned Prev) const
find_next - Returns the index of the next set bit following the "Prev" bit.
bool none() const
none - Returns true if none of the bits are set.
iterator_range< const_set_bits_iterator > set_bits() const
size_type size() const
size - Returns the number of bits in this bitvector.
The CalleeSavedInfo class tracks the information need to locate where a callee saved register is in t...
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override
Store the specified register of the given register class to the specified stack frame index.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override
Load the specified register of the given register class from the specified stack frame index.
An instruction for reading from memory.
static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register, SMLoc Loc={})
.cfi_def_cfa_register modifies a rule for computing CFA.
static MCCFIInstruction createRegister(MCSymbol *L, unsigned Register1, unsigned Register2, SMLoc Loc={})
.cfi_register Previous value of Register1 is saved in register Register2.
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int64_t Offset, SMLoc Loc={})
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int64_t Offset, SMLoc Loc={})
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
static MCCFIInstruction cfiDefCfaOffset(MCSymbol *L, int64_t Offset, SMLoc Loc={})
.cfi_def_cfa_offset modifies a rule for computing CFA.
const MCRegisterInfo * getRegisterInfo() const
Describe properties that are true of each instruction in the target description file.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
bool isReturnBlock() const
Convenience function that returns true if the block ends in a return instruction.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any debug instructions.
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
void setMaxCallFrameSize(uint64_t S)
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
bool adjustsStack() const
Return true if this function adjusts the stack – e.g., when calling another function.
bool hasCalls() const
Return true if the current function has any function calls.
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
Align getMaxAlign() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
void setObjectOffset(int ObjectIdx, int64_t SPOffset)
Set the stack frame offset of the specified object.
uint64_t getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call.
bool hasPatchPoint() const
This method may be called any time after instruction selection is complete to determine if there is a...
MachineBasicBlock * getRestorePoint() const
int CreateSpillStackObject(uint64_t Size, Align Alignment)
Create a new statically sized stack object that represents a spill slot, returning a nonnegative iden...
uint64_t estimateStackSize(const MachineFunction &MF) const
Estimate and return the size of the stack frame.
bool hasTailCall() const
Returns true if the function contains a tail call.
bool hasStackMap() const
This method may be called any time after instruction selection is complete to determine if there is a...
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
void setStackSize(uint64_t Size)
Set the size of the stack.
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
MachineBasicBlock * getSavePoint() const
unsigned addFrameInst(const MCCFIInstruction &Inst)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
bool exposesReturnsTwice() const
exposesReturnsTwice - Returns true if the function calls setjmp or any other similar functions with a...
bool needsFrameMoves() const
True if this function needs frame moves for debug or exceptions.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MCContext & getContext() const
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MachineBasicBlock & front() const
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *BB=nullptr, std::optional< UniqueBBID > BBID=std::nullopt)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
void insert(iterator MBBI, MachineBasicBlock *MBB)
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const MachineInstrBuilder & addCFIIndex(unsigned CFIIndex) const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Representation of each machine instruction.
MachineOperand class - Representation of each machine instruction operand.
const GlobalValue * getGlobal() const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
const char * getSymbolName() const
int64_t getOffset() const
Return the offset from the symbol in this operand.
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
def_iterator def_begin(Register RegNo) const
static def_iterator def_end()
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
uint64_t getReturnSaveOffset() const
getReturnSaveOffset - Return the previous frame offset to save the return address.
bool needsFP(const MachineFunction &MF) const
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
bool canUseAsEpilogue(const MachineBasicBlock &MBB) const override
Check whether or not the given MBB can be used as a epilogue for the target.
uint64_t getStackThreshold() const override
getStackThreshold - Return the maximum stack size
void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS=nullptr) const override
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
bool hasFPImpl(const MachineFunction &MF) const override
uint64_t getFramePointerSaveOffset() const
getFramePointerSaveOffset - Return the previous frame offset to save the frame pointer.
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
unsigned getLinkageSize() const
getLinkageSize - Return the size of the PowerPC ABI linkage area.
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
const SpillSlot * getCalleeSavedSpillSlots(unsigned &NumEntries) const override
getCalleeSavedSpillSlots - This method returns a pointer to an array of pairs, that contains an entry...
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
bool canUseAsPrologue(const MachineBasicBlock &MBB) const override
Methods used by shrink wrapping to determine if MBB can be used for the function prologue/epilogue.
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, MutableArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
void replaceFPWithRealFP(MachineFunction &MF) const
bool enableShrinkWrapping(const MachineFunction &MF) const override
Returns true if the target will correctly handle shrink wrapping.
uint64_t determineFrameLayout(const MachineFunction &MF, bool UseEstimate=false, unsigned *NewMaxCallFrameSize=nullptr) const
Determine the frame layout but do not update the machine function.
void addScavengingSpillSlot(MachineFunction &MF, RegScavenger *RS) const
PPCFrameLowering(const PPCSubtarget &STI)
bool assignCalleeSavedSpillSlots(MachineFunction &MF, const TargetRegisterInfo *TRI, std::vector< CalleeSavedInfo > &CSI) const override
This function will assign callee saved gprs to volatile vector registers for prologue spills when app...
uint64_t determineFrameLayoutAndUpdate(MachineFunction &MF, bool UseEstimate=false) const
Determine the frame layout and update the machine function.
void updateCalleeSaves(const MachineFunction &MF, BitVector &SavedRegs) const
void inlineStackProbe(MachineFunction &MF, MachineBasicBlock &PrologMBB) const override
Replace a StackProbe stub (if any) with the actual probe code inline.
uint64_t getTOCSaveOffset() const
getTOCSaveOffset - Return the previous frame offset to save the TOC register – 64-bit SVR4 ABI only.
uint64_t getBasePointerSaveOffset() const
getBasePointerSaveOffset - Return the previous frame offset to save the base pointer.
PPCFunctionInfo - This class is derived from MachineFunction private PowerPC target-specific informat...
int getTailCallSPDelta() const
const SmallVectorImpl< Register > & getMustSaveCRs() const
int getPICBasePointerSaveIndex() const
bool shrinkWrapDisabled() const
int getFramePointerSaveIndex() const
void addMustSaveCR(Register Reg)
void setBasePointerSaveIndex(int Idx)
bool hasNonRISpills() const
bool isLRStoreRequired() const
void setPICBasePointerSaveIndex(int Idx)
int getROPProtectionHashSaveIndex() const
unsigned getMinReservedArea() const
void setMustSaveLR(bool U)
MustSaveLR - This is set when the prolog/epilog inserter does its initial scan of the function.
void setCRSpillFrameIndex(int idx)
int getBasePointerSaveIndex() const
void setFramePointerSaveIndex(int Idx)
bool hasBasePointer(const MachineFunction &MF) const
Register getBaseRegister(const MachineFunction &MF) const
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
bool is32BitELFABI() const
bool needsSwapsForVSXMemOps() const
bool isPPC64() const
isPPC64 - Return true if we are generating code for 64-bit pointer mode.
const PPCTargetLowering * getTargetLowering() const override
const PPCInstrInfo * getInstrInfo() const override
unsigned getRedZoneSize() const
bool is64BitELFABI() const
const PPCTargetMachine & getTargetMachine() const
const PPCRegisterInfo * getRegisterInfo() const override
bool hasInlineStackProbe(const MachineFunction &MF) const override
unsigned getStackProbeSize(const MachineFunction &MF) const
void enterBasicBlockEnd(MachineBasicBlock &MBB)
Start tracking liveness from the end of basic block MBB.
bool isRegUsed(Register Reg, bool includeReserved=true) const
Return if a specific register is currently used.
void backward()
Update internal register state and move MBB iterator backwards.
void enterBasicBlock(MachineBasicBlock &MBB)
Start tracking liveness from the begin of basic block MBB.
void addScavengingFrameIndex(int FI)
Add a scavenging frame index.
BitVector getRegsAvailable(const TargetRegisterClass *RC)
Return all available registers in the register class in Mask.
Wrapper class representing virtual and physical registers.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
An instruction for storing to memory.
Information about stack frame layout on the target.
bool hasFP(const MachineFunction &MF) const
hasFP - Return true if the specified function should have a dedicated frame pointer register.
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
virtual uint64_t getStackThreshold() const
getStackThreshold - Return the maximum stack size
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
TargetInstrInfo - Interface to description of machine instruction set.
bool isPositionIndependent() const
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
unsigned GuaranteedTailCallOpt
GuaranteedTailCallOpt - This flag is enabled when -tailcallopt is specified on the commandline.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
self_iterator getIterator()
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ Fast
Attempts to make calls as fast as possible (e.g.
@ Kill
The last use of a register.
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
constexpr bool isPowerOf2_64(uint64_t Value)
Return true if the argument is a power of two > 0 (64 bit edition.)
unsigned getKillRegState(bool B)
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
unsigned Log2(Align A)
Returns the log2 of the alignment.
void fullyRecomputeLiveIns(ArrayRef< MachineBasicBlock * > MBBs)
Convenience function for recomputing live-in's for a set of MBBs until the computation converges.
This struct is a compact representation of a valid (non-zero power of two) alignment.
