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1//===------ PPCDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===//

2//

3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.

4// See https://llvm.org/LICENSE.txt for license information.

5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception

6//

7//===----------------------------------------------------------------------===//

9#include "MCTargetDesc/PPCMCTargetDesc.h"

10#include "TargetInfo/PowerPCTargetInfo.h"

11#include "llvm/MC/MCDecoderOps.h"

12#include "llvm/MC/MCDisassembler/MCDisassembler.h"

13#include "llvm/MC/MCInst.h"

14#include "llvm/MC/MCSubtargetInfo.h"

15#include "llvm/MC/TargetRegistry.h"

16#include "llvm/Support/Endian.h"

18using namespacellvm;

20DEFINE_PPC_REGCLASSES

22#define DEBUG_TYPE "ppc-disassembler"

24typedefMCDisassembler::DecodeStatus DecodeStatus;

26namespace{

27classPPCDisassembler :publicMCDisassembler {

28bool IsLittleEndian;

30public:

31 PPCDisassembler(constMCSubtargetInfo &STI,MCContext &Ctx,

32bool IsLittleEndian)

33 :MCDisassembler(STI, Ctx), IsLittleEndian(IsLittleEndian) {}

35DecodeStatus getInstruction(MCInst &Instr,uint64_t &Size,

36ArrayRef<uint8_t> Bytes,uint64_t Address,

37raw_ostream &CStream)const override;

38};

39}// end anonymous namespace

41staticMCDisassembler *createPPCDisassembler(constTarget &T,

42constMCSubtargetInfo &STI,

43MCContext &Ctx) {

44returnnew PPCDisassembler(STI, Ctx,/*IsLittleEndian=*/false);

45}

47staticMCDisassembler *createPPCLEDisassembler(constTarget &T,

48constMCSubtargetInfo &STI,

49MCContext &Ctx) {

50returnnew PPCDisassembler(STI, Ctx,/*IsLittleEndian=*/true);

51}

53extern"C"LLVM_EXTERNAL_VISIBILITYvoidLLVMInitializePowerPCDisassembler() {

54// Register the disassembler for each target.

55TargetRegistry::RegisterMCDisassembler(getThePPC32Target(),

56createPPCDisassembler);

57TargetRegistry::RegisterMCDisassembler(getThePPC32LETarget(),

58createPPCLEDisassembler);

59TargetRegistry::RegisterMCDisassembler(getThePPC64Target(),

60createPPCDisassembler);

61TargetRegistry::RegisterMCDisassembler(getThePPC64LETarget(),

62createPPCLEDisassembler);

63}

65staticDecodeStatus decodeCondBrTarget(MCInst &Inst,unsigned Imm,

66uint64_t/*Address*/,

67constMCDisassembler */*Decoder*/) {

68 Inst.addOperand(MCOperand::createImm(SignExtend32<14>(Imm)));

69returnMCDisassembler::Success;

70}

72staticDecodeStatus decodeDirectBrTarget(MCInst &Inst,unsigned Imm,

73uint64_t/*Address*/,

74constMCDisassembler */*Decoder*/) {

75 int32_tOffset = SignExtend32<24>(Imm);

76 Inst.addOperand(MCOperand::createImm(Offset));

77returnMCDisassembler::Success;

78}

80// FIXME: These can be generated by TableGen from the existing register

81// encoding values!

83template <std::size_t N>

84staticDecodeStatus decodeRegisterClass(MCInst &Inst,uint64_t RegNo,

85constMCPhysReg (&Regs)[N]) {

86if (RegNo >=N)

87returnMCDisassembler::Fail;

88 Inst.addOperand(MCOperand::createReg(Regs[RegNo]));

89returnMCDisassembler::Success;

90}

92staticDecodeStatus DecodeCRRCRegisterClass(MCInst &Inst,uint64_t RegNo,

93uint64_t Address,

94constMCDisassembler *Decoder) {

95returndecodeRegisterClass(Inst, RegNo, CRRegs);

96}

98staticDecodeStatus DecodeCRBITRCRegisterClass(MCInst &Inst,uint64_t RegNo,

99uint64_t Address,

100constMCDisassembler *Decoder) {

101returndecodeRegisterClass(Inst, RegNo, CRBITRegs);

102}

103

104staticDecodeStatus DecodeF4RCRegisterClass(MCInst &Inst,uint64_t RegNo,

105uint64_t Address,

106constMCDisassembler *Decoder) {

107returndecodeRegisterClass(Inst, RegNo, FRegs);

108}

109

110staticDecodeStatus DecodeF8RCRegisterClass(MCInst &Inst,uint64_t RegNo,

111uint64_t Address,

112constMCDisassembler *Decoder) {

113returndecodeRegisterClass(Inst, RegNo, FRegs);

114}

115

116staticDecodeStatus DecodeFpRCRegisterClass(MCInst &Inst,uint64_t RegNo,

117uint64_t Address,

118constMCDisassembler *Decoder) {

119if (RegNo > 30 || (RegNo & 1))

120returnMCDisassembler::Fail;

121returndecodeRegisterClass(Inst, RegNo >> 1, FpRegs);

122}

123

124staticDecodeStatus DecodeVFRCRegisterClass(MCInst &Inst,uint64_t RegNo,

125uint64_t Address,

126constMCDisassembler *Decoder) {

127returndecodeRegisterClass(Inst, RegNo, VFRegs);

128}

129

130staticDecodeStatus DecodeVRRCRegisterClass(MCInst &Inst,uint64_t RegNo,

131uint64_t Address,

132constMCDisassembler *Decoder) {

133returndecodeRegisterClass(Inst, RegNo, VRegs);

134}

135

136staticDecodeStatus DecodeVSRCRegisterClass(MCInst &Inst,uint64_t RegNo,

137uint64_t Address,

138constMCDisassembler *Decoder) {

139returndecodeRegisterClass(Inst, RegNo, VSRegs);

140}

141

142staticDecodeStatus DecodeVSFRCRegisterClass(MCInst &Inst,uint64_t RegNo,

143uint64_t Address,

144constMCDisassembler *Decoder) {

145returndecodeRegisterClass(Inst, RegNo, VSFRegs);

146}

147

148staticDecodeStatus DecodeVSSRCRegisterClass(MCInst &Inst,uint64_t RegNo,

149uint64_t Address,

150constMCDisassembler *Decoder) {

151returndecodeRegisterClass(Inst, RegNo, VSSRegs);

152}

153

154staticDecodeStatus DecodeGPRCRegisterClass(MCInst &Inst,uint64_t RegNo,

155uint64_t Address,

156constMCDisassembler *Decoder) {

157returndecodeRegisterClass(Inst, RegNo, RRegs);

158}

159

160staticDecodeStatus

161DecodeGPRC_NOR0RegisterClass(MCInst &Inst,uint64_t RegNo,uint64_t Address,

162constMCDisassembler *Decoder) {

163returndecodeRegisterClass(Inst, RegNo, RRegsNoR0);

164}

165

166staticDecodeStatus DecodeG8RCRegisterClass(MCInst &Inst,uint64_t RegNo,

167uint64_t Address,

168constMCDisassembler *Decoder) {

169returndecodeRegisterClass(Inst, RegNo, XRegs);

170}

171

172staticDecodeStatus DecodeG8pRCRegisterClass(MCInst &Inst,uint64_t RegNo,

173uint64_t Address,

174constMCDisassembler *Decoder) {

175returndecodeRegisterClass(Inst, RegNo, XRegs);

176}

177

178staticDecodeStatus

179DecodeG8RC_NOX0RegisterClass(MCInst &Inst,uint64_t RegNo,uint64_t Address,

180constMCDisassembler *Decoder) {

181returndecodeRegisterClass(Inst, RegNo, XRegsNoX0);

182}

183

184#define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass

185#define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass

186

187staticDecodeStatus DecodeSPERCRegisterClass(MCInst &Inst,uint64_t RegNo,

188uint64_t Address,

189constMCDisassembler *Decoder) {

190returndecodeRegisterClass(Inst, RegNo, SPERegs);

191}

192

193staticDecodeStatus DecodeACCRCRegisterClass(MCInst &Inst,uint64_t RegNo,

194uint64_t Address,

195constMCDisassembler *Decoder) {

196returndecodeRegisterClass(Inst, RegNo, ACCRegs);

197}

198

199staticDecodeStatus DecodeWACCRCRegisterClass(MCInst &Inst,uint64_t RegNo,

200uint64_t Address,

201constvoid *Decoder) {

202returndecodeRegisterClass(Inst, RegNo, WACCRegs);

203}

204

205staticDecodeStatus DecodeWACC_HIRCRegisterClass(MCInst &Inst,uint64_t RegNo,

206uint64_t Address,

207constvoid *Decoder) {

208returndecodeRegisterClass(Inst, RegNo, WACC_HIRegs);

209}

210

211// TODO: Make this function static when the register class is used by a new

212// instruction.

213DecodeStatus DecodeDMRROWRCRegisterClass(MCInst &Inst,uint64_t RegNo,

214uint64_t Address,

215constvoid *Decoder) {

216returndecodeRegisterClass(Inst, RegNo, DMRROWRegs);

217}

218

219staticDecodeStatus DecodeDMRROWpRCRegisterClass(MCInst &Inst,uint64_t RegNo,

220uint64_t Address,

221constvoid *Decoder) {

222returndecodeRegisterClass(Inst, RegNo, DMRROWpRegs);

223}

224

225staticDecodeStatus DecodeDMRRCRegisterClass(MCInst &Inst,uint64_t RegNo,

226uint64_t Address,

227constvoid *Decoder) {

228returndecodeRegisterClass(Inst, RegNo, DMRRegs);

229}

230

231// TODO: Make this function static when the register class is used by a new

232// instruction.

233DecodeStatus DecodeDMRpRCRegisterClass(MCInst &Inst,uint64_t RegNo,

234uint64_t Address,constvoid *Decoder) {

235returndecodeRegisterClass(Inst, RegNo, DMRpRegs);

236}

237

238staticDecodeStatus DecodeVSRpRCRegisterClass(MCInst &Inst,uint64_t RegNo,

239uint64_t Address,

240constMCDisassembler *Decoder) {

241returndecodeRegisterClass(Inst, RegNo, VSRpRegs);

242}

243

244#define DecodeQSRCRegisterClass DecodeQFRCRegisterClass

245#define DecodeQBRCRegisterClass DecodeQFRCRegisterClass

246

247template <unsigned N>

248staticDecodeStatus decodeUImmOperand(MCInst &Inst,uint64_t Imm,

249 int64_t Address,

250constMCDisassembler *Decoder) {

251if (!isUInt<N>(Imm))

252returnMCDisassembler::Fail;

253 Inst.addOperand(MCOperand::createImm(Imm));

254returnMCDisassembler::Success;

255}

256

257template <unsigned N>

258staticDecodeStatus decodeSImmOperand(MCInst &Inst,uint64_t Imm,

259 int64_t Address,

260constMCDisassembler *Decoder) {

261if (!isUInt<N>(Imm))

262returnMCDisassembler::Fail;

263 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));

264returnMCDisassembler::Success;

265}

266

267staticDecodeStatus decodeImmZeroOperand(MCInst &Inst,uint64_t Imm,

268 int64_t Address,

269constMCDisassembler *Decoder) {

270if (Imm != 0)

271returnMCDisassembler::Fail;

272 Inst.addOperand(MCOperand::createImm(Imm));

273returnMCDisassembler::Success;

274}

275

276staticDecodeStatus decodeVSRpEvenOperands(MCInst &Inst,uint64_t RegNo,

277uint64_t Address,

278constMCDisassembler *Decoder) {

279if (RegNo & 1)

280returnMCDisassembler::Fail;

281 Inst.addOperand(MCOperand::createReg(VSRpRegs[RegNo >> 1]));

282returnMCDisassembler::Success;

283}

284

285staticDecodeStatus decodeDispRIXOperand(MCInst &Inst,uint64_t Imm,

286 int64_t Address,

287constMCDisassembler *Decoder) {

288// The rix displacement is an immediate shifted by 2

289 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Imm << 2)));

290returnMCDisassembler::Success;

291}

292

293staticDecodeStatus decodeDispRIHashOperand(MCInst &Inst,uint64_t Imm,

294 int64_t Address,

295constMCDisassembler *Decoder) {

296// Decode the disp field for a hash store or hash check operation.

297// The field is composed of an immediate value that is 6 bits

298// and covers the range -8 to -512. The immediate is always negative and 2s

299// complement which is why we sign extend a 7 bit value.

300const int64_t Disp = SignExtend64<7>((Imm & 0x3F) + 64) * 8;

301

302 Inst.addOperand(MCOperand::createImm(Disp));

303returnMCDisassembler::Success;

304}

305

306staticDecodeStatus decodeDispRIX16Operand(MCInst &Inst,uint64_t Imm,

307 int64_t Address,

308constMCDisassembler *Decoder) {

309// The rix16 displacement has 12-bits which are shifted by 4.

310 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Imm << 4)));

311returnMCDisassembler::Success;

312}

313

314staticDecodeStatus decodeDispSPE8Operand(MCInst &Inst,uint64_t Imm,

315 int64_t Address,

316constMCDisassembler *Decoder) {

317// Decode the dispSPE8 field, which has 5-bits, 8-byte aligned.

318

319uint64_t Disp = Imm & 0x1F;

320

321 Inst.addOperand(MCOperand::createImm(Disp << 3));

322returnMCDisassembler::Success;

323}

324

325staticDecodeStatus decodeDispSPE4Operand(MCInst &Inst,uint64_t Imm,

326 int64_t Address,

327constMCDisassembler *Decoder) {

328// Decode the dispSPE8 field, which has 5-bits, 4-byte aligned.

329

330uint64_t Disp = Imm & 0x1F;

331

332 Inst.addOperand(MCOperand::createImm(Disp << 2));

333returnMCDisassembler::Success;

334}

335

336staticDecodeStatus decodeDispSPE2Operand(MCInst &Inst,uint64_t Imm,

337 int64_t Address,

338constMCDisassembler *Decoder) {

339// Decode the dispSPE8 field, which has 5-bits, 2-byte aligned.

340

341uint64_t Disp = Imm & 0x1F;

342 Inst.addOperand(MCOperand::createImm(Disp << 1));

343returnMCDisassembler::Success;

344}

345

346staticDecodeStatus decodeCRBitMOperand(MCInst &Inst,uint64_t Imm,

347 int64_t Address,

348constMCDisassembler *Decoder) {

349// The cr bit encoding is 0x80 >> cr_reg_num.

350

351unsigned Zeros =llvm::countr_zero(Imm);

352if (Zeros >= 8)

353returnMCDisassembler::Fail;

354

355 Inst.addOperand(MCOperand::createReg(CRRegs[7 - Zeros]));

356returnMCDisassembler::Success;

357}

358

359#include "PPCGenDisassemblerTables.inc"

360

361DecodeStatus PPCDisassembler::getInstruction(MCInst &MI,uint64_t &Size,

362ArrayRef<uint8_t> Bytes,

363uint64_t Address,

364raw_ostream &CS) const{

365auto *ReadFunc = IsLittleEndian ?support::endian::read32le

366 :support::endian::read32be;

367

368// If this is an 8-byte prefixed instruction, handle it here.

369// Note: prefixed instructions aren't technically 8-byte entities - the prefix

370// appears in memory at an address 4 bytes prior to that of the base

371// instruction regardless of endianness. So we read the two pieces and

372// rebuild the 8-byte instruction.

373// TODO: In this function we call decodeInstruction several times with

374// different decoder tables. It may be possible to only call once by

375// looking at the top 6 bits of the instruction.

376if (STI.hasFeature(PPC::FeaturePrefixInstrs) && Bytes.size() >= 8) {

377uint32_t Prefix = ReadFunc(Bytes.data());

378uint32_t BaseInst = ReadFunc(Bytes.data() + 4);

379uint64_t Inst = BaseInst | (uint64_t)Prefix << 32;

380DecodeStatus result = decodeInstruction(DecoderTable64,MI, Inst, Address,

381this, STI);

382if (result !=MCDisassembler::Fail) {

383Size = 8;

384return result;

385 }

386 }

387

388// Get the four bytes of the instruction.

389Size = 4;

390if (Bytes.size() < 4) {

391Size = 0;

392returnMCDisassembler::Fail;

393 }

394

395// Read the instruction in the proper endianness.

396uint64_t Inst = ReadFunc(Bytes.data());

397

398if (STI.hasFeature(PPC::FeatureSPE)) {

399DecodeStatus result =

400 decodeInstruction(DecoderTableSPE32,MI, Inst, Address,this, STI);

401if (result !=MCDisassembler::Fail)

402return result;

403 }

404

405return decodeInstruction(DecoderTable32,MI, Inst, Address,this, STI);

406}

LLVM_EXTERNAL_VISIBILITY

#define LLVM_EXTERNAL_VISIBILITY

Definition:Compiler.h:128

Size

uint64_t Size

Definition:ELFObjHandler.cpp:81

Endian.h

IRTranslator LLVM IR MI

Definition:IRTranslator.cpp:112

static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, const MCPhysReg(&Regs)[N])

Definition:PPCDisassembler.cpp:84

decodeVSRpEvenOperands

static DecodeStatus decodeVSRpEvenOperands(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition:PPCDisassembler.cpp:276

DecodeVSFRCRegisterClass

static DecodeStatus DecodeVSFRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition:PPCDisassembler.cpp:142

decodeDispSPE4Operand

static DecodeStatus decodeDispSPE4Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)

Definition:PPCDisassembler.cpp:325

DecodeDMRRCRegisterClass

static DecodeStatus DecodeDMRRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)

Definition:PPCDisassembler.cpp:225

DecodeStatus

MCDisassembler::DecodeStatus DecodeStatus

Definition:PPCDisassembler.cpp:24

LLVMInitializePowerPCDisassembler

LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCDisassembler()

Definition:PPCDisassembler.cpp:53

decodeCRBitMOperand

static DecodeStatus decodeCRBitMOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)

Definition:PPCDisassembler.cpp:346

DecodeDMRpRCRegisterClass

DecodeStatus DecodeDMRpRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)

Definition:PPCDisassembler.cpp:233

decodeImmZeroOperand

static DecodeStatus decodeImmZeroOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)

Definition:PPCDisassembler.cpp:267

DecodeCRBITRCRegisterClass

static DecodeStatus DecodeCRBITRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition:PPCDisassembler.cpp:98

DecodeGPRC_NOR0RegisterClass

static DecodeStatus DecodeGPRC_NOR0RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition:PPCDisassembler.cpp:161

DecodeG8pRCRegisterClass

static DecodeStatus DecodeG8pRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition:PPCDisassembler.cpp:172

decodeDispRIHashOperand

static DecodeStatus decodeDispRIHashOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)

Definition:PPCDisassembler.cpp:293

DecodeGPRCRegisterClass

static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition:PPCDisassembler.cpp:154

DecodeFpRCRegisterClass

static DecodeStatus DecodeFpRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition:PPCDisassembler.cpp:116

createPPCDisassembler

static MCDisassembler * createPPCDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)

Definition:PPCDisassembler.cpp:41

decodeDispSPE2Operand

static DecodeStatus decodeDispSPE2Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)

Definition:PPCDisassembler.cpp:336

decodeSImmOperand

static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)

Definition:PPCDisassembler.cpp:258

DecodeVSRCRegisterClass

static DecodeStatus DecodeVSRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition:PPCDisassembler.cpp:136

decodeCondBrTarget

static DecodeStatus decodeCondBrTarget(MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *)

Definition:PPCDisassembler.cpp:65

decodeDispSPE8Operand

static DecodeStatus decodeDispSPE8Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)

Definition:PPCDisassembler.cpp:314

DecodeVRRCRegisterClass

static DecodeStatus DecodeVRRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition:PPCDisassembler.cpp:130

createPPCLEDisassembler

static MCDisassembler * createPPCLEDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)

Definition:PPCDisassembler.cpp:47

decodeDispRIX16Operand

static DecodeStatus decodeDispRIX16Operand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)

Definition:PPCDisassembler.cpp:306

DecodeCRRCRegisterClass

static DecodeStatus DecodeCRRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition:PPCDisassembler.cpp:92

decodeUImmOperand

static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)

Definition:PPCDisassembler.cpp:248

DecodeG8RC_NOX0RegisterClass

static DecodeStatus DecodeG8RC_NOX0RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition:PPCDisassembler.cpp:179

DecodeACCRCRegisterClass

static DecodeStatus DecodeACCRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition:PPCDisassembler.cpp:193

DecodeVSSRCRegisterClass

static DecodeStatus DecodeVSSRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition:PPCDisassembler.cpp:148

DecodeWACC_HIRCRegisterClass

static DecodeStatus DecodeWACC_HIRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)

Definition:PPCDisassembler.cpp:205

DecodeVFRCRegisterClass

static DecodeStatus DecodeVFRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition:PPCDisassembler.cpp:124

DecodeF8RCRegisterClass

static DecodeStatus DecodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition:PPCDisassembler.cpp:110

DecodeSPERCRegisterClass

static DecodeStatus DecodeSPERCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition:PPCDisassembler.cpp:187

DecodeDMRROWRCRegisterClass

DecodeStatus DecodeDMRROWRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)

Definition:PPCDisassembler.cpp:213

DecodeWACCRCRegisterClass

static DecodeStatus DecodeWACCRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)

Definition:PPCDisassembler.cpp:199

DecodeG8RCRegisterClass

static DecodeStatus DecodeG8RCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition:PPCDisassembler.cpp:166

DecodeDMRROWpRCRegisterClass

static DecodeStatus DecodeDMRROWpRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)

Definition:PPCDisassembler.cpp:219

decodeDispRIXOperand

static DecodeStatus decodeDispRIXOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const MCDisassembler *Decoder)

Definition:PPCDisassembler.cpp:285

DecodeF4RCRegisterClass

static DecodeStatus DecodeF4RCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition:PPCDisassembler.cpp:104

DecodeVSRpRCRegisterClass

static DecodeStatus DecodeVSRpRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder)

Definition:PPCDisassembler.cpp:238

decodeDirectBrTarget

static DecodeStatus decodeDirectBrTarget(MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *)

Definition:PPCDisassembler.cpp:72

PPCMCTargetDesc.h

DEFINE_PPC_REGCLASSES

#define DEFINE_PPC_REGCLASSES

Definition:PPCMCTargetDesc.h:258

PowerPCTargetInfo.h

Address

@ Address

Definition:SPIRVEmitNonSemanticDI.cpp:68

TargetRegistry.h

llvm::ArrayRef

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

Definition:ArrayRef.h:41

llvm::ArrayRef::size

size_t size() const

size - Get the array size.

Definition:ArrayRef.h:168

llvm::ArrayRef::data

const T * data() const

Definition:ArrayRef.h:165

llvm::MCContext

Context object for machine code objects.

Definition:MCContext.h:83

llvm::MCDisassembler

Superclass for all disassemblers.

Definition:MCDisassembler.h:84

llvm::MCDisassembler::DecodeStatus

DecodeStatus

Ternary decode status.

Definition:MCDisassembler.h:108

llvm::MCDisassembler::Fail

@ Fail

Definition:MCDisassembler.h:109

llvm::MCDisassembler::Success

@ Success

Definition:MCDisassembler.h:111

llvm::MCDisassembler::getInstruction

virtual DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const =0

Returns the disassembly of a single instruction.

llvm::MCInst

Instances of this class represent a single low-level machine instruction.

Definition:MCInst.h:185

llvm::MCInst::addOperand

void addOperand(const MCOperand Op)

Definition:MCInst.h:211

llvm::MCOperand::createReg

static MCOperand createReg(MCRegister Reg)

Definition:MCInst.h:135

llvm::MCOperand::createImm

static MCOperand createImm(int64_t Val)

Definition:MCInst.h:142

llvm::MCSubtargetInfo

Generic base class for all target subtargets.

Definition:MCSubtargetInfo.h:76

llvm::Target

Target - Wrapper for Target specific information.

Definition:TargetRegistry.h:144

llvm::raw_ostream

This class implements an extremely fast bulk output stream that can only output to a stream.

Definition:raw_ostream.h:52

@ Prefix

Definition:CommandLine.h:158

llvm::support::endian::read32be

uint32_t read32be(const void *P)

Definition:Endian.h:434

llvm::support::endian::read32le

uint32_t read32le(const void *P)

Definition:Endian.h:425

llvm

This is an optimization pass for GlobalISel generic memory operations.

Definition:AddressRanges.h:18

llvm::Offset

@ Offset

Definition:DWP.cpp:480

llvm::getThePPC64LETarget

Target & getThePPC64LETarget()

Definition:PowerPCTargetInfo.cpp:25

llvm::getThePPC32Target

Target & getThePPC32Target()

Definition:PowerPCTargetInfo.cpp:13

llvm::countr_zero

int countr_zero(T Val)

Count number of 0's from the least significant bit to the most stopping at the first 1.

Definition:bit.h:215

llvm::getThePPC64Target

Target & getThePPC64Target()

Definition:PowerPCTargetInfo.cpp:21

llvm::getThePPC32LETarget

Target & getThePPC32LETarget()

Definition:PowerPCTargetInfo.cpp:17

#define N

llvm::TargetRegistry::RegisterMCDisassembler

static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)

RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.

Definition:TargetRegistry.h:878