1//===-- MipsMachineFunctionInfo.cpp - Private data used for Mips ----------===// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7//===----------------------------------------------------------------------===// 24cl::desc(
"Always use $gp as the global base register."));
43if (STI.inMips16Mode())
44return Mips::CPU16RegsRegClass;
46if (STI.inMicroMipsMode())
47return Mips::GPRMM16RegClass;
49if (TM.getABI().IsN64())
50return Mips::GPR64RegClass;
52return Mips::GPR32RegClass;
82 RC = (ABI.IsN64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
91// lui $v0, %hi(%neg(%gp_rel(fname))) 93// daddiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname))) 105// Set global register to __gnu_local_gp. 107// lui $v0, %hi(__gnu_local_gp) 108// addiu $globalbasereg, $v0, %lo(__gnu_local_gp) 120// lui $v0, %hi(%neg(%gp_rel(fname))) 122// addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname))) 134// For O32 ABI, the following instruction sequence is emitted to initialize 135// the global base register: 137// 0. lui $2, %hi(_gp_disp) 138// 1. addiu $2, $2, %lo(_gp_disp) 139// 2. addu $globalbasereg, $2, $t9 141// We emit only the last instruction here. 143// GNU linker requires that the first two instructions appear at the beginning 144// of a function and no instructions be inserted before or between them. 145// The two instructions are emitted during lowering to MC layer in order to 146// avoid any reordering. 148// Register $2 (Mips::V0) is added to the list of live-in registers to ensure 149// the value instruction 1 (addiu) defines is valid when instruction 2 (addu) 159for (
int &
I : EhDataRegFI) {
162 ? Mips::GPR64RegClass
163 : Mips::GPR32RegClass;
166TRI.getSpillAlign(RC),
false);
171// ISRs require spill slots for Status & ErrorPC Coprocessor 0 registers. 172// The current implementation only supports Mips32r2+ not Mips64rX. Status 173// is always 32 bits, ErrorPC is 32 or 64 bits dependent on architecture, 174// however Mips32r2+ is the supported architecture. 178for (
int &
I : ISRDataRegFI)
180TRI.getSpillAlign(RC),
false);
184return CallsEhReturn && (FI == EhDataRegFI[0] || FI == EhDataRegFI[1]
185 || FI == EhDataRegFI[2] || FI == EhDataRegFI[3]);
189return IsISR && (FI == ISRDataRegFI[0] || FI == ISRDataRegFI[1]);
204if (MoveF64ViaSpillFI == -1) {
206TRI.getSpillSize(*RC),
TRI.getSpillAlign(*RC),
false);
208return MoveF64ViaSpillFI;
211void MipsFunctionInfo::anchor() {}
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
const HexagonInstrInfo * TII
unsigned const TargetRegisterInfo * TRI
static cl::opt< bool > FixGlobalBaseReg("mips-fix-global-base-reg", cl::Hidden, cl::init(true), cl::desc("Always use $gp as the global base register."))
static const TargetRegisterClass & getGlobalBaseRegClass(MachineFunction &MF)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Allocate memory in an ever growing pool, as if by bump-pointer.
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
PseudoSourceValueManager & getPSVManager() const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * cloneInfo(const Ty &Old)
const MachineBasicBlock & front() const
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned TargetFlags=0) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
Register getGlobalBaseRegForGlobalISel(MachineFunction &MF)
bool isISRRegFI(int FI) const
MachinePointerInfo callPtrInfo(MachineFunction &MF, const char *ES)
Create a MachinePointerInfo that has an ExternalSymbolPseudoSourceValue object representing a GOT ent...
int getMoveF64ViaSpillFI(MachineFunction &MF, const TargetRegisterClass *RC)
Register getGlobalBaseReg(MachineFunction &MF)
MachineFunctionInfo * clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF, const DenseMap< MachineBasicBlock *, MachineBasicBlock * > &Src2DstMBB) const override
Make a functionally equivalent copy of this MachineFunctionInfo in MF.
bool globalBaseRegSet() const
bool isEhDataRegFI(int FI) const
void createEhDataRegsFI(MachineFunction &MF)
void initGlobalBaseReg(MachineFunction &MF)
~MipsFunctionInfo() override
void createISRRegFI(MachineFunction &MF)
const PseudoSourceValue * getExternalSymbolCallEntry(const char *ES)
const PseudoSourceValue * getGlobalValueCallEntry(const GlobalValue *GV)
Wrapper class representing virtual and physical registers.
TargetInstrInfo - Interface to description of machine instruction set.
bool isPositionIndependent() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const TargetInstrInfo * getInstrInfo() const
@ MO_ABS_HI
MO_ABS_HI/LO - Represents the hi or low part of an absolute symbol address.
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...
This class contains a discriminated union of information about pointers in memory operands,...
