1//===- MipsISelLowering.cpp - Mips DAG Lowering Implementation ------------===// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7//===----------------------------------------------------------------------===// 9// This file defines the interfaces that Mips uses to lower LLVM code into a 12//===----------------------------------------------------------------------===// 80#define DEBUG_TYPE "mips-lower" 86cl::desc(
"MIPS: Don't trap on integer division by zero."),
92 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
93 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
96// The MIPS MSA ABI passes vector arguments in the integer register set. 97// The number of integer registers used is dependant on the ABI used. 124unsigned &NumIntermediates,
MVT &RegisterVT)
const{
129return NumIntermediates;
171N->getOffset(), Flag);
299// Mips does not have i1 type, so use i32 for 300// setcc operations results (slt, sgt, ...). 303// The cmp.cond.fmt instruction in MIPS32r6/MIPS64r6 uses 0 and -1 like MSA 304// does. Integer booleans still use 0 and 1. 309// Load extented operations for i1 types must be promoted 316// MIPS doesn't have extending float->double load/store. Set LoadExtAction 323// Set LoadExtAction for f16 vectors to Expand 335// Used by legalize types to correctly generate the setcc result. 336// Without this, every float setcc comes with a AND/OR with the result, 337// we don't want this, since the fpcmp result goes to a flag register, 338// which is used implicitly by brcond and select operations. 341// Mips Custom Operations 360// Lower fmin/fmax/fclass operations for MIPS R6. 416// Operations not directly supported by Mips. 467// Lower f16 conversion operations into library calls 480// Use the default for now 494// MIPS16 lacks MIPS32's clz and clo instructions. 529// The arguments on the stack are defined in terms of 4-byte slots on O32 530// and 8-byte slots on N32/N64. 550// Create a fast isel object. 557// We support only the standard encoding [MIPS32,MIPS32R5] ISAs. 562// Disable if either of the following is true: 563// We do not generate PIC, the ABI is not O32, XGOT is being used. 564if (!TM.isPositionIndependent() || !TM.getABI().IsO32() ||
584EVT Ty =
N->getValueType(0);
585unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64;
586unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64;
592N->getOperand(0),
N->getOperand(1));
597if (
N->hasAnyUseOfValue(0)) {
606if (
N->hasAnyUseOfValue(1)) {
641/// This function returns true if the floating point conditional branches and 642/// conditional moves which use condition code CC should be inverted. 648"Illegal Condition Code");
653// Creates and returns an FPCmp node from a setcc node. 654// Returns Op if setcc is not a floating point comparison. 656// must be a SETCC node 662if (!
LHS.getValueType().isFloatingPoint())
668// Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of 676// Creates and returns a CMovFPT/F node. 707// If the RHS (False) is 0, we swap the order of the operands 708// of ISD::SELECT (obviously also inverting the condition) so that we can 709// take advantage of conditional moves using the $0 register. 711// return (a != 0) ? x : 0; 730// If both operands are integer constants there's a possibility that we 731// can do some interesting optimizations. 738// We'll also ignore MVT::i64 operands as this optimizations proves 739// to be ineffective because of the required sign extensions as the result 740// of a SETCC operator is always MVT::i32 for non-vector types. 746// 1) (a < x) ? y : y-1 748// addiu $reg2, $reg1, y-1 752// 2) (a < x) ? y-1 : y 754// xor $reg1, $reg1, 1 755// addiu $reg2, $reg1, y-1 764// Could not optimize. 774SDValue ValueIfTrue =
N->getOperand(0), ValueIfFalse =
N->getOperand(2);
780// Since RHS (False) is 0, we swap the order of the True/False operands 781// (obviously also inverting the condition) so that we can 782// take advantage of conditional moves using the $0 register. 784// return (a != 0) ? x : 0; 790SDValue FCC =
N->getOperand(1), Glue =
N->getOperand(3);
792 ValueIfFalse, FCC, ValueIfTrue, Glue);
801SDValue FirstOperand =
N->getOperand(0);
802unsigned FirstOperandOpc = FirstOperand.
getOpcode();
804EVT ValTy =
N->getValueType(0);
808unsigned SMPos, SMSize;
813// Op's second operand must be a shifted mask. 814if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
820// $dst = and ((sra or srl) $src , pos), (2**size - 1) 821// => ext $dst, $src, pos, size 823// The second operand of the shift must be an immediate. 824if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.
getOperand(1))))
829// Return if the shifted mask does not start at bit 0 or the sum of its size 830// and Pos exceeds the word's size. 837// Pattern match CINS. 838// $dst = and (shl $src , pos), mask 839// => cins $dst, $src, pos, size 840// mask is a shifted mask with consecutive 1's, pos = shift amount, 841// size = population count. 843// The second operand of the shift must be an immediate. 844if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.
getOperand(1))))
849if (SMPos != Pos || Pos >= ValTy.
getSizeInBits() || SMSize >= 32 ||
854// SMSize is 'location' (position) in this case, not size. 859// $dst = and $src, (2**size - 1) , if size > 16 860// => ext $dst, $src, pos, size , pos = 0 862// If the mask is <= 0xffff, andi can be used instead. 866// Return if the mask doesn't start at position 0. 871 NewOperand = FirstOperand;
873return DAG.
getNode(Opc,
DL, ValTy, NewOperand,
884SDValue FirstOperand =
N->getOperand(0), SecondOperand =
N->getOperand(1);
885unsigned SMPos0, SMSize0, SMPos1, SMSize1;
889 SecondOperand.getOpcode() ==
ISD::SHL) ||
891 SecondOperand.getOpcode() ==
ISD::AND)) {
893// $dst = or (and $src1, (2**size0 - 1)), (shl $src2, size0) 894// ==> ins $src1, $src2, pos, size, pos = size0, size = 32 - pos; 896// $dst = or (shl $src2, size0), (and $src1, (2**size0 - 1)) 897// ==> ins $src1, $src2, pos, size, pos = size0, size = 32 - pos; 902 ? SecondOperand.getOperand(0)
907if (!(CN = dyn_cast<ConstantSDNode>(AndMask)) ||
912 ? SecondOperand.getOperand(1)
914if (!(CN = dyn_cast<ConstantSDNode>(ShlShift)))
918if (SMPos0 != 0 || SMSize0 != ShlShiftValue)
922EVT ValTy =
N->getValueType(0);
923 SMPos1 = ShlShiftValue;
925 SMSize1 = (ValTy == MVT::i64 ? 64 : 32) - SMPos1;
931// See if Op's first operand matches (and $src1 , mask0). 936// $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1), 937// where mask1 = (2**size - 1) << pos, mask0 = ~mask1 938// => ins $dst, $src, size, pos, $src1 939if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.
getOperand(1))) ||
943// See if Op's second operand matches (and (shl $src, pos), mask1). 944if (SecondOperand.getOpcode() ==
ISD::AND &&
945 SecondOperand.getOperand(0).getOpcode() ==
ISD::SHL) {
947if (!(CN = dyn_cast<ConstantSDNode>(SecondOperand.getOperand(1))) ||
951// The shift masks must have the same position and size. 952if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
957if (!(CN = dyn_cast<ConstantSDNode>(Shl.
getOperand(1))))
962// Return if the shift amount and the first bit position of mask are not the 964EVT ValTy =
N->getValueType(0);
965if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.
getSizeInBits()))
974// Pattern match DINS. 975// $dst = or (and $src, mask0), mask1 976// where mask0 = ((1 << SMSize0) -1) << SMPos0 977// => dins $dst, $src, pos, size 978if (~CN->
getSExtValue() == ((((int64_t)1 << SMSize0) - 1) << SMPos0) &&
979 ((SMSize0 + SMPos0 <= 64 && Subtarget.
hasMips64r2()) ||
980 (SMSize0 + SMPos0 <= 32))) {
981// Check if AND instruction has constant as argument 983if (SecondOperand.getOpcode() ==
ISD::AND) {
984if (!(CN1 = dyn_cast<ConstantSDNode>(SecondOperand->getOperand(1))))
987if (!(CN1 = dyn_cast<ConstantSDNode>(
N->getOperand(1))))
990// Don't generate INS if constant OR operand doesn't fit into bits 991// cleared by constant AND operand. 996EVT ValTy =
N->getOperand(0)->getValueType(0);
1002 SecondOperand, Const1);
1021// ROOTNode must have a multiplication as an operand for the match to be 1027// In the case where we have a multiplication as the left operand of 1028// of a subtraction, we can't combine into a MipsISD::MSub node as the 1029// the instruction definition of msub(u) places the multiplication on 1035// We don't handle vector types here. 1039// For MIPS64, madd / msub instructions are inefficent to use with 64 bit 1041// (add (mul a b) c) => 1042// let res = (madd (mthi (drotr c 32))x(mtlo c) a b) in 1043// MIPS64: (or (dsll (mfhi res) 32) (dsrl (dsll (mflo res) 32) 32) 1045// MIPS64R2: (dins (mflo res) (mfhi res) 32 32) 1047// The overhead of setting up the Hi/Lo registers and reassembling the 1048// result makes this a dubious optimzation for MIPS64. The core of the 1049// problem is that Hi/Lo contain the upper and lower 32 bits of the 1050// operand and result. 1052// It requires a chain of 4 add/mul for MIPS64R2 to get better code 1053// density than doing it naively, 5 for MIPS64. Additionally, using 1054// madd/msub on MIPS64 requires the operands actually be 32 bit sign 1055// extended operands, not true 64 bit values. 1057// FIXME: For the moment, disable this completely for MIPS64. 1069// Transform this to a MADD only if the user of this node is the add. 1070// If there are other users of the mul, this function returns here. 1071if (!Mult.hasOneUse())
1074// maddu and madd are unusual instructions in that on MIPS64 bits 63..31 1075// must be in canonical form, i.e. sign extended. For MIPS32, the operands 1076// of the multiply must have 32 or more sign bits, otherwise we cannot 1077// perform this optimization. We have to check this here as we're performing 1078// this optimization pre-legalization. 1079SDValue MultLHS = Mult->getOperand(0);
1080SDValue MultRHS = Mult->getOperand(1);
1087if (!IsSigned && !IsUnsigned)
1090// Initialize accumulator. 1093 std::tie(BottomHalf, TopHalf) =
1098// Create MipsMAdd(u) / MipsMSub(u) node. 1117// (sub v0 (mul v1, v2)) => (msub v1, v2, v0) 1132// (add v0 (mul v1, v2)) => (madd v1, v2, v0) 1141// (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt)) 1153EVT ValTy =
N->getValueType(0);
1164// Pattern match CINS. 1165// $dst = shl (and $src , imm), pos 1166// => cins $dst, $src, pos, size 1171SDValue FirstOperand =
N->getOperand(0);
1172unsigned FirstOperandOpc = FirstOperand.
getOpcode();
1173SDValue SecondOperand =
N->getOperand(1);
1174EVT ValTy =
N->getValueType(0);
1178unsigned SMPos, SMSize;
1182// The second operand of the shift must be an immediate. 1183if (!(CN = dyn_cast<ConstantSDNode>(SecondOperand)))
1194// AND's second operand must be a shifted mask. 1195if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.
getOperand(1))) ||
1199// Return if the shifted mask does not start at bit 0 or the sum of its size 1200// and Pos exceeds the word's size. 1201if (SMPos != 0 || SMSize > 32 || Pos + SMSize > ValTy.
getSizeInBits())
1205// SMSize is 'location' (position) in this case, not size. 1216unsigned Opc =
N->getOpcode();
1252// We can use ANDI+SLTIU as a bit test. Y contains the bit position. 1253// For MIPSR2 or later, we may be able to use the `ext` instruction or its' 1254// double-word variants. 1255if (
auto *
C = dyn_cast<ConstantSDNode>(
Y))
1256returnC->getAPIntValue().ule(15);
1264N->getOperand(0).getOpcode() ==
ISD::SRL) ||
1266N->getOperand(0).getOpcode() ==
ISD::SHL)) &&
1267"Expected shift-shift mask");
1269if (
N->getOperand(0).getValueType().isVector())
1284switch (
Op.getOpcode())
1299return lowerFCANONICALIZE(
Op, DAG);
1315//===----------------------------------------------------------------------===// 1316// Lower helper functions 1317//===----------------------------------------------------------------------===// 1319// addLiveIn - This helper function adds the specified physical register to the 1320// MachineFunction as a live in value. It also creates a corresponding 1321// virtual register for it. 1333bool Is64Bit,
bool IsMicroMips) {
1337// Insert instruction "teq $divisor_reg, $zero, 7". 1342TII.get(IsMicroMips ? Mips::TEQ_MM : Mips::TEQ))
1347// Use the 32-bit sub-register if this is a 64-bit division. 1351// Clear Divisor's kill flag. 1354// We would normally delete the original instruction here but in this case 1355// we only needed to inject an additional instruction rather than replace it. 1363switch (
MI.getOpcode()) {
1366case Mips::ATOMIC_LOAD_ADD_I8:
1367return emitAtomicBinaryPartword(
MI, BB, 1);
1368case Mips::ATOMIC_LOAD_ADD_I16:
1369return emitAtomicBinaryPartword(
MI, BB, 2);
1370case Mips::ATOMIC_LOAD_ADD_I32:
1371return emitAtomicBinary(
MI, BB);
1372case Mips::ATOMIC_LOAD_ADD_I64:
1373return emitAtomicBinary(
MI, BB);
1375case Mips::ATOMIC_LOAD_AND_I8:
1376return emitAtomicBinaryPartword(
MI, BB, 1);
1377case Mips::ATOMIC_LOAD_AND_I16:
1378return emitAtomicBinaryPartword(
MI, BB, 2);
1379case Mips::ATOMIC_LOAD_AND_I32:
1380return emitAtomicBinary(
MI, BB);
1381case Mips::ATOMIC_LOAD_AND_I64:
1382return emitAtomicBinary(
MI, BB);
1384case Mips::ATOMIC_LOAD_OR_I8:
1385return emitAtomicBinaryPartword(
MI, BB, 1);
1386case Mips::ATOMIC_LOAD_OR_I16:
1387return emitAtomicBinaryPartword(
MI, BB, 2);
1388case Mips::ATOMIC_LOAD_OR_I32:
1389return emitAtomicBinary(
MI, BB);
1390case Mips::ATOMIC_LOAD_OR_I64:
1391return emitAtomicBinary(
MI, BB);
1393case Mips::ATOMIC_LOAD_XOR_I8:
1394return emitAtomicBinaryPartword(
MI, BB, 1);
1395case Mips::ATOMIC_LOAD_XOR_I16:
1396return emitAtomicBinaryPartword(
MI, BB, 2);
1397case Mips::ATOMIC_LOAD_XOR_I32:
1398return emitAtomicBinary(
MI, BB);
1399case Mips::ATOMIC_LOAD_XOR_I64:
1400return emitAtomicBinary(
MI, BB);
1402case Mips::ATOMIC_LOAD_NAND_I8:
1403return emitAtomicBinaryPartword(
MI, BB, 1);
1404case Mips::ATOMIC_LOAD_NAND_I16:
1405return emitAtomicBinaryPartword(
MI, BB, 2);
1406case Mips::ATOMIC_LOAD_NAND_I32:
1407return emitAtomicBinary(
MI, BB);
1408case Mips::ATOMIC_LOAD_NAND_I64:
1409return emitAtomicBinary(
MI, BB);
1411case Mips::ATOMIC_LOAD_SUB_I8:
1412return emitAtomicBinaryPartword(
MI, BB, 1);
1413case Mips::ATOMIC_LOAD_SUB_I16:
1414return emitAtomicBinaryPartword(
MI, BB, 2);
1415case Mips::ATOMIC_LOAD_SUB_I32:
1416return emitAtomicBinary(
MI, BB);
1417case Mips::ATOMIC_LOAD_SUB_I64:
1418return emitAtomicBinary(
MI, BB);
1420case Mips::ATOMIC_SWAP_I8:
1421return emitAtomicBinaryPartword(
MI, BB, 1);
1422case Mips::ATOMIC_SWAP_I16:
1423return emitAtomicBinaryPartword(
MI, BB, 2);
1424case Mips::ATOMIC_SWAP_I32:
1425return emitAtomicBinary(
MI, BB);
1426case Mips::ATOMIC_SWAP_I64:
1427return emitAtomicBinary(
MI, BB);
1429case Mips::ATOMIC_CMP_SWAP_I8:
1430return emitAtomicCmpSwapPartword(
MI, BB, 1);
1431case Mips::ATOMIC_CMP_SWAP_I16:
1432return emitAtomicCmpSwapPartword(
MI, BB, 2);
1433case Mips::ATOMIC_CMP_SWAP_I32:
1434return emitAtomicCmpSwap(
MI, BB);
1435case Mips::ATOMIC_CMP_SWAP_I64:
1436return emitAtomicCmpSwap(
MI, BB);
1438case Mips::ATOMIC_LOAD_MIN_I8:
1439return emitAtomicBinaryPartword(
MI, BB, 1);
1440case Mips::ATOMIC_LOAD_MIN_I16:
1441return emitAtomicBinaryPartword(
MI, BB, 2);
1442case Mips::ATOMIC_LOAD_MIN_I32:
1443return emitAtomicBinary(
MI, BB);
1444case Mips::ATOMIC_LOAD_MIN_I64:
1445return emitAtomicBinary(
MI, BB);
1447case Mips::ATOMIC_LOAD_MAX_I8:
1448return emitAtomicBinaryPartword(
MI, BB, 1);
1449case Mips::ATOMIC_LOAD_MAX_I16:
1450return emitAtomicBinaryPartword(
MI, BB, 2);
1451case Mips::ATOMIC_LOAD_MAX_I32:
1452return emitAtomicBinary(
MI, BB);
1453case Mips::ATOMIC_LOAD_MAX_I64:
1454return emitAtomicBinary(
MI, BB);
1456case Mips::ATOMIC_LOAD_UMIN_I8:
1457return emitAtomicBinaryPartword(
MI, BB, 1);
1458case Mips::ATOMIC_LOAD_UMIN_I16:
1459return emitAtomicBinaryPartword(
MI, BB, 2);
1460case Mips::ATOMIC_LOAD_UMIN_I32:
1461return emitAtomicBinary(
MI, BB);
1462case Mips::ATOMIC_LOAD_UMIN_I64:
1463return emitAtomicBinary(
MI, BB);
1465case Mips::ATOMIC_LOAD_UMAX_I8:
1466return emitAtomicBinaryPartword(
MI, BB, 1);
1467case Mips::ATOMIC_LOAD_UMAX_I16:
1468return emitAtomicBinaryPartword(
MI, BB, 2);
1469case Mips::ATOMIC_LOAD_UMAX_I32:
1470return emitAtomicBinary(
MI, BB);
1471case Mips::ATOMIC_LOAD_UMAX_I64:
1472return emitAtomicBinary(
MI, BB);
1474case Mips::PseudoSDIV:
1475case Mips::PseudoUDIV:
1482case Mips::SDIV_MM_Pseudo:
1483case Mips::UDIV_MM_Pseudo:
1487case Mips::DIVU_MMR6:
1489case Mips::MODU_MMR6:
1491case Mips::PseudoDSDIV:
1492case Mips::PseudoDUDIV:
1499case Mips::PseudoSELECT_I:
1500case Mips::PseudoSELECT_I64:
1501case Mips::PseudoSELECT_S:
1502case Mips::PseudoSELECT_D32:
1503case Mips::PseudoSELECT_D64:
1504return emitPseudoSELECT(
MI, BB,
false, Mips::BNE);
1505case Mips::PseudoSELECTFP_F_I:
1506case Mips::PseudoSELECTFP_F_I64:
1507case Mips::PseudoSELECTFP_F_S:
1508case Mips::PseudoSELECTFP_F_D32:
1509case Mips::PseudoSELECTFP_F_D64:
1510return emitPseudoSELECT(
MI, BB,
true, Mips::BC1F);
1511case Mips::PseudoSELECTFP_T_I:
1512case Mips::PseudoSELECTFP_T_I64:
1513case Mips::PseudoSELECTFP_T_S:
1514case Mips::PseudoSELECTFP_T_D32:
1515case Mips::PseudoSELECTFP_T_D64:
1516return emitPseudoSELECT(
MI, BB,
true, Mips::BC1T);
1517case Mips::PseudoD_SELECT_I:
1518case Mips::PseudoD_SELECT_I64:
1519return emitPseudoD_SELECT(
MI, BB);
1521return emitLDR_W(
MI, BB);
1523return emitLDR_D(
MI, BB);
1525return emitSTR_W(
MI, BB);
1527return emitSTR_D(
MI, BB);
1531// This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and 1532// Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true) 1543bool NeedsAdditionalReg =
false;
1544switch (
MI.getOpcode()) {
1545case Mips::ATOMIC_LOAD_ADD_I32:
1546 AtomicOp = Mips::ATOMIC_LOAD_ADD_I32_POSTRA;
1548case Mips::ATOMIC_LOAD_SUB_I32:
1549 AtomicOp = Mips::ATOMIC_LOAD_SUB_I32_POSTRA;
1551case Mips::ATOMIC_LOAD_AND_I32:
1552 AtomicOp = Mips::ATOMIC_LOAD_AND_I32_POSTRA;
1554case Mips::ATOMIC_LOAD_OR_I32:
1555 AtomicOp = Mips::ATOMIC_LOAD_OR_I32_POSTRA;
1557case Mips::ATOMIC_LOAD_XOR_I32:
1558 AtomicOp = Mips::ATOMIC_LOAD_XOR_I32_POSTRA;
1560case Mips::ATOMIC_LOAD_NAND_I32:
1561 AtomicOp = Mips::ATOMIC_LOAD_NAND_I32_POSTRA;
1563case Mips::ATOMIC_SWAP_I32:
1564 AtomicOp = Mips::ATOMIC_SWAP_I32_POSTRA;
1566case Mips::ATOMIC_LOAD_ADD_I64:
1567 AtomicOp = Mips::ATOMIC_LOAD_ADD_I64_POSTRA;
1569case Mips::ATOMIC_LOAD_SUB_I64:
1570 AtomicOp = Mips::ATOMIC_LOAD_SUB_I64_POSTRA;
1572case Mips::ATOMIC_LOAD_AND_I64:
1573 AtomicOp = Mips::ATOMIC_LOAD_AND_I64_POSTRA;
1575case Mips::ATOMIC_LOAD_OR_I64:
1576 AtomicOp = Mips::ATOMIC_LOAD_OR_I64_POSTRA;
1578case Mips::ATOMIC_LOAD_XOR_I64:
1579 AtomicOp = Mips::ATOMIC_LOAD_XOR_I64_POSTRA;
1581case Mips::ATOMIC_LOAD_NAND_I64:
1582 AtomicOp = Mips::ATOMIC_LOAD_NAND_I64_POSTRA;
1584case Mips::ATOMIC_SWAP_I64:
1585 AtomicOp = Mips::ATOMIC_SWAP_I64_POSTRA;
1587case Mips::ATOMIC_LOAD_MIN_I32:
1588 AtomicOp = Mips::ATOMIC_LOAD_MIN_I32_POSTRA;
1589 NeedsAdditionalReg =
true;
1591case Mips::ATOMIC_LOAD_MAX_I32:
1592 AtomicOp = Mips::ATOMIC_LOAD_MAX_I32_POSTRA;
1593 NeedsAdditionalReg =
true;
1595case Mips::ATOMIC_LOAD_UMIN_I32:
1596 AtomicOp = Mips::ATOMIC_LOAD_UMIN_I32_POSTRA;
1597 NeedsAdditionalReg =
true;
1599case Mips::ATOMIC_LOAD_UMAX_I32:
1600 AtomicOp = Mips::ATOMIC_LOAD_UMAX_I32_POSTRA;
1601 NeedsAdditionalReg =
true;
1603case Mips::ATOMIC_LOAD_MIN_I64:
1604 AtomicOp = Mips::ATOMIC_LOAD_MIN_I64_POSTRA;
1605 NeedsAdditionalReg =
true;
1607case Mips::ATOMIC_LOAD_MAX_I64:
1608 AtomicOp = Mips::ATOMIC_LOAD_MAX_I64_POSTRA;
1609 NeedsAdditionalReg =
true;
1611case Mips::ATOMIC_LOAD_UMIN_I64:
1612 AtomicOp = Mips::ATOMIC_LOAD_UMIN_I64_POSTRA;
1613 NeedsAdditionalReg =
true;
1615case Mips::ATOMIC_LOAD_UMAX_I64:
1616 AtomicOp = Mips::ATOMIC_LOAD_UMAX_I64_POSTRA;
1617 NeedsAdditionalReg =
true;
1630// The scratch registers here with the EarlyClobber | Define | Implicit 1631// flags is used to persuade the register allocator and the machine 1632// verifier to accept the usage of this register. This has to be a real 1633// register which has an UNDEF value but is dead after the instruction which 1634// is unique among the registers chosen for the instruction. 1636// The EarlyClobber flag has the semantic properties that the operand it is 1637// attached to is clobbered before the rest of the inputs are read. Hence it 1638// must be unique among the operands to the instruction. 1639// The Define flag is needed to coerce the machine verifier that an Undef 1640// value isn't a problem. 1641// The Dead flag is needed as the value in scratch isn't used by any other 1642// instruction. Kill isn't used as Dead is more precise. 1643// The implicit flag is here due to the interaction between the other flags 1644// and the machine verifier. 1646// For correctness purpose, a new pseudo is introduced here. We need this 1647// new pseudo, so that FastRegisterAllocator does not see an ll/sc sequence 1648// that is spread over >1 basic blocks. A register allocator which 1649// introduces (or any codegen infact) a store, can violate the expectations 1652// An atomic read-modify-write sequence starts with a linked load 1653// instruction and ends with a store conditional instruction. The atomic 1654// read-modify-write sequence fails if any of the following conditions 1655// occur between the execution of ll and sc: 1656// * A coherent store is completed by another process or coherent I/O 1657// module into the block of synchronizable physical memory containing 1658// the word. The size and alignment of the block is 1659// implementation-dependent. 1660// * A coherent store is executed between an LL and SC sequence on the 1661// same processor to the block of synchornizable physical memory 1662// containing the word. 1678if (NeedsAdditionalReg) {
1685MI.eraseFromParent();
1692unsigned SrcReg)
const{
1712 int64_t ShiftImm = 32 - (
Size * 8);
1723"Unsupported size for EmitAtomicBinaryPartial.");
1750unsigned AtomicOp = 0;
1751bool NeedsAdditionalReg =
false;
1752switch (
MI.getOpcode()) {
1753case Mips::ATOMIC_LOAD_NAND_I8:
1754 AtomicOp = Mips::ATOMIC_LOAD_NAND_I8_POSTRA;
1756case Mips::ATOMIC_LOAD_NAND_I16:
1757 AtomicOp = Mips::ATOMIC_LOAD_NAND_I16_POSTRA;
1759case Mips::ATOMIC_SWAP_I8:
1760 AtomicOp = Mips::ATOMIC_SWAP_I8_POSTRA;
1762case Mips::ATOMIC_SWAP_I16:
1763 AtomicOp = Mips::ATOMIC_SWAP_I16_POSTRA;
1765case Mips::ATOMIC_LOAD_ADD_I8:
1766 AtomicOp = Mips::ATOMIC_LOAD_ADD_I8_POSTRA;
1768case Mips::ATOMIC_LOAD_ADD_I16:
1769 AtomicOp = Mips::ATOMIC_LOAD_ADD_I16_POSTRA;
1771case Mips::ATOMIC_LOAD_SUB_I8:
1772 AtomicOp = Mips::ATOMIC_LOAD_SUB_I8_POSTRA;
1774case Mips::ATOMIC_LOAD_SUB_I16:
1775 AtomicOp = Mips::ATOMIC_LOAD_SUB_I16_POSTRA;
1777case Mips::ATOMIC_LOAD_AND_I8:
1778 AtomicOp = Mips::ATOMIC_LOAD_AND_I8_POSTRA;
1780case Mips::ATOMIC_LOAD_AND_I16:
1781 AtomicOp = Mips::ATOMIC_LOAD_AND_I16_POSTRA;
1783case Mips::ATOMIC_LOAD_OR_I8:
1784 AtomicOp = Mips::ATOMIC_LOAD_OR_I8_POSTRA;
1786case Mips::ATOMIC_LOAD_OR_I16:
1787 AtomicOp = Mips::ATOMIC_LOAD_OR_I16_POSTRA;
1789case Mips::ATOMIC_LOAD_XOR_I8:
1790 AtomicOp = Mips::ATOMIC_LOAD_XOR_I8_POSTRA;
1792case Mips::ATOMIC_LOAD_XOR_I16:
1793 AtomicOp = Mips::ATOMIC_LOAD_XOR_I16_POSTRA;
1795case Mips::ATOMIC_LOAD_MIN_I8:
1796 AtomicOp = Mips::ATOMIC_LOAD_MIN_I8_POSTRA;
1797 NeedsAdditionalReg =
true;
1799case Mips::ATOMIC_LOAD_MIN_I16:
1800 AtomicOp = Mips::ATOMIC_LOAD_MIN_I16_POSTRA;
1801 NeedsAdditionalReg =
true;
1803case Mips::ATOMIC_LOAD_MAX_I8:
1804 AtomicOp = Mips::ATOMIC_LOAD_MAX_I8_POSTRA;
1805 NeedsAdditionalReg =
true;
1807case Mips::ATOMIC_LOAD_MAX_I16:
1808 AtomicOp = Mips::ATOMIC_LOAD_MAX_I16_POSTRA;
1809 NeedsAdditionalReg =
true;
1811case Mips::ATOMIC_LOAD_UMIN_I8:
1812 AtomicOp = Mips::ATOMIC_LOAD_UMIN_I8_POSTRA;
1813 NeedsAdditionalReg =
true;
1815case Mips::ATOMIC_LOAD_UMIN_I16:
1816 AtomicOp = Mips::ATOMIC_LOAD_UMIN_I16_POSTRA;
1817 NeedsAdditionalReg =
true;
1819case Mips::ATOMIC_LOAD_UMAX_I8:
1820 AtomicOp = Mips::ATOMIC_LOAD_UMAX_I8_POSTRA;
1821 NeedsAdditionalReg =
true;
1823case Mips::ATOMIC_LOAD_UMAX_I16:
1824 AtomicOp = Mips::ATOMIC_LOAD_UMAX_I16_POSTRA;
1825 NeedsAdditionalReg =
true;
1831// insert new blocks after the current block 1837// Transfer the remainder of BB and its successor edges to exitMBB. 1845// addiu masklsb2,$0,-4 # 0xfffffffc 1846// and alignedaddr,ptr,masklsb2 1847// andi ptrlsb2,ptr,3 1848// sll shiftamt,ptrlsb2,3 1849// ori maskupper,$0,255 # 0xff 1850// sll mask,maskupper,shiftamt 1852// sll incr2,incr,shiftamt 1854 int64_t MaskImm = (
Size == 1) ? 255 : 65535;
1877// The purposes of the flags on the scratch registers is explained in 1878// emitAtomicBinary. In summary, we need a scratch register which is going to 1879// be undef, that is unique among registers chosen for the instruction. 1895if (NeedsAdditionalReg) {
1901MI.eraseFromParent();
// The instruction is gone now. 1906// Lower atomic compare and swap to a pseudo instruction, taking care to 1907// define a scratch register for the pseudo instruction's expansion. The 1908// instruction is expanded after the register allocator as to prevent 1909// the insertion of stores between the linked load and the store conditional. 1915assert((
MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32 ||
1916MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I64) &&
1917"Unsupported atomic pseudo for EmitAtomicCmpSwap.");
1919constunsignedSize =
MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32 ? 4 : 8;
1927unsigned AtomicOp =
MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32
1928 ? Mips::ATOMIC_CMP_SWAP_I32_POSTRA
1929 : Mips::ATOMIC_CMP_SWAP_I64_POSTRA;
1938// We need to create copies of the various registers and kill them at the 1939// atomic pseudo. If the copies are not made, when the atomic is expanded 1940// after fast register allocation, the spills will end up outside of the 1941// blocks that their values are defined in, causing livein errors. 1944Register OldValCopy =
MRI.createVirtualRegister(
MRI.getRegClass(OldVal));
1945Register NewValCopy =
MRI.createVirtualRegister(
MRI.getRegClass(NewVal));
1951// The purposes of the flags on the scratch registers is explained in 1952// emitAtomicBinary. In summary, we need a scratch register which is going to 1953// be undef, that is unique among registers chosen for the instruction. 1963MI.eraseFromParent();
// The instruction is gone now. 1971"Unsupported size for EmitAtomicCmpSwapPartial.");
1998unsigned AtomicOp =
MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I8
1999 ? Mips::ATOMIC_CMP_SWAP_I8_POSTRA
2000 : Mips::ATOMIC_CMP_SWAP_I16_POSTRA;
2002// The scratch registers here with the EarlyClobber | Define | Dead | Implicit 2003// flags are used to coerce the register allocator and the machine verifier to 2004// accept the usage of these registers. 2005// The EarlyClobber flag has the semantic properties that the operand it is 2006// attached to is clobbered before the rest of the inputs are read. Hence it 2007// must be unique among the operands to the instruction. 2008// The Define flag is needed to coerce the machine verifier that an Undef 2009// value isn't a problem. 2010// The Dead flag is needed as the value in scratch isn't used by any other 2011// instruction. Kill isn't used as Dead is more precise. 2015// insert new blocks after the current block 2021// Transfer the remainder of BB and its successor edges to exitMBB. 2029// addiu masklsb2,$0,-4 # 0xfffffffc 2030// and alignedaddr,ptr,masklsb2 2031// andi ptrlsb2,ptr,3 2032// xori ptrlsb2,ptrlsb2,3 # Only for BE 2033// sll shiftamt,ptrlsb2,3 2034// ori maskupper,$0,255 # 0xff 2035// sll mask,maskupper,shiftamt 2037// andi maskedcmpval,cmpval,255 2038// sll shiftedcmpval,maskedcmpval,shiftamt 2039// andi maskednewval,newval,255 2040// sll shiftednewval,maskednewval,shiftamt 2041 int64_t MaskImm = (
Size == 1) ? 255 : 65535;
2042BuildMI(BB,
DL,
TII->get(ArePtrs64bit ? Mips::DADDiu : Mips::ADDiu), MaskLSB2)
2044BuildMI(BB,
DL,
TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr)
2070// The purposes of the flags on the scratch registers are explained in 2071// emitAtomicBinary. In summary, we need a scratch register which is going to 2072// be undef, that is unique among the register chosen for the instruction. 2087MI.eraseFromParent();
// The instruction is gone now. 2093// The first operand is the chain, the second is the condition, the third is 2094// the block to branch to if the condition is true. 2102// Return if flag is not set by a floating point comparison. 2112 FCC0, Dest, CondRes);
2121// Return if flag is not set by a floating point comparison. 2134"Floating point operand expected.");
2145EVT Ty =
Op.getValueType();
2151"Windows is the only supported COFF target");
2163// %gp_rel relocation 2166// %hi/%lo relocation 2168// %highest/%higher/%hi/%lo relocation 2172// Every other architecture would use shouldAssumeDSOLocal in here, but 2174// * In PIC code mips requires got loads even for local statics! 2175// * To save on got entries, for local statics the got entry contains the 2176// page and an additional add instruction takes care of the low bits. 2177// * It is legal to access a hidden symbol with a non hidden undefined, 2178// so one cannot guarantee that all access to a hidden symbol will know 2180// * Mips linkers don't support creating a page and a full got entry for 2182// * Given all that, we have to use a full got entry for hidden symbols :-( 2201EVT Ty =
Op.getValueType();
2213// If the relocation model is PIC, use the General Dynamic TLS Model or 2214// Local Dynamic TLS model, otherwise use the Initial Exec or 2215// Local Exec TLS Model. 2228// General Dynamic and Local Dynamic TLS Model. 2244Args.push_back(Entry);
2249 .setLibCallee(
CallingConv::C, PtrTy, TlsGetAddr, std::move(Args));
2250 std::pair<SDValue, SDValue> CallResult =
LowerCallTo(CLI);
2269// Initial Exec TLS Model 2277// Local Exec TLS Model 2296EVT Ty =
Op.getValueType();
2309EVT Ty =
Op.getValueType();
2318// %gp_rel relocation 2336// vastart just stores the address of the VarArgsFrameIndex slot into the 2337// memory location argument. 2338constValue *SV = cast<SrcValueSDNode>(
Op.getOperand(2))->getValue();
2350constValue *SV = cast<SrcValueSDNode>(
Node->getOperand(2))->getValue();
2358// Re-align the pointer if necessary. 2359// It should only ever be necessary for 64-bit types on O32 since the minimum 2360// argument alignment is the same as the maximum type alignment for N32/N64. 2362// FIXME: We currently align too often. The code generator doesn't notice 2363// when the pointer is still aligned from the last va_arg (or pair of 2364// va_args for the i64 on O32 case). 2375// Increment the pointer, VAList, to the next vaarg. 2377unsigned ArgSizeInBytes =
2383// Store the incremented VAList to the legalized pointer 2387// In big-endian mode we must adjust the pointer when the load size is smaller 2388// than the argument slot size. We must also reduce the known alignment to 2389// match. For example in the N64 ABI, we must add 4 bytes to the offset to get 2390// the correct half of the slot, and reduce the alignment from 8 (slot 2391// alignment) down to 4 (type alignment). 2393unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes;
2397// Load the actual argument out of the pointer VAList 2402bool HasExtractInsert) {
2403EVT TyX =
Op.getOperand(0).getValueType();
2404EVT TyY =
Op.getOperand(1).getValueType();
2410// If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it 2421if (HasExtractInsert) {
2422// ext E, Y, 31, 1 ; extract bit31 of Y 2423// ins X, E, 31, 1 ; insert extracted bit at bit31 of X 2430// sll SllY, SrlX, 31 2449bool HasExtractInsert) {
2450unsigned WidthX =
Op.getOperand(0).getValueSizeInBits();
2451unsigned WidthY =
Op.getOperand(1).getValueSizeInBits();
2456// Bitcast to integer nodes. 2460if (HasExtractInsert) {
2461// ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y 2462// ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X 2468elseif (WidthY > WidthX)
2478// (d)srl SrlX, SllX, 1 2479// (d)srl SrlY, Y, width(Y)-1 2480// (d)sll SllY, SrlX, width(Y)-1 2489elseif (WidthY > WidthX)
2507bool HasExtractInsert)
const{
2514// If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it 2519Op.getOperand(0), Const1);
2522if (HasExtractInsert)
2527// TODO: Provide DAG patterns which transform (and x, cst) 2528// back to a (shl (srl x (clz cst)) (clz cst)) sequence. 2533if (
Op.getValueType() == MVT::f32)
2536// FIXME: For mips32r2, the sequence of (BuildPairF64 (ins (ExtractElementF64 2537// Op 1), $zero, 31 1) (ExtractElementF64 Op 0)) and the Op has one use, we 2538// should be able to drop the usage of mfc1/mtc1 and rewrite the register in 2547bool HasExtractInsert)
const{
2554// Bitcast to integer node. 2558if (HasExtractInsert)
2580EVT VT =
Op.getValueType();
2594if (
Op.getConstantOperandVal(0) != 0) {
2596"return address can be determined only for current frame");
2602EVT VT =
Op.getValueType();
2615if (
Op.getConstantOperandVal(0) != 0) {
2617"return address can be determined only for current frame");
2623MVT VT =
Op.getSimpleValueType();
2624unsignedRA =
ABI.
IsN64() ? Mips::RA_64 : Mips::RA;
2627// Return RA, which contains the return address. Mark it an implicit live-in. 2632// An EH_RETURN is the result of lowering llvm.eh.return which in turn is 2633// generated from __builtin_eh_return (offset, handler) 2634// The effect of this is to adjust the stack pointer by "offset" 2635// and then branch to "handler". 2648// Store stack offset in V1, store jump target in V0. Glue CopyToReg and 2649// EH_RETURN nodes, so that instructions are emitted back-to-back. 2650unsigned OffsetReg =
ABI.
IsN64() ? Mips::V1_64 : Mips::V1;
2651unsigned AddrReg =
ABI.
IsN64() ? Mips::V0_64 : Mips::V0;
2662// FIXME: Need pseudo-fence for 'singlethread' fences 2663// FIXME: Set SType for weaker fences where supported/appropriate. 2677// if shamt < (VT.bits): 2678// lo = (shl lo, shamt) 2679// hi = (or (shl hi, shamt) (srl (srl lo, 1), (xor shamt, (VT.bits-1)))) 2682// hi = (shl lo, shamt[4:0]) 2709// if shamt < (VT.bits): 2710// lo = (or (shl (shl hi, 1), (xor shamt, (VT.bits-1))) (srl lo, shamt)) 2712// hi = (sra hi, shamt) 2714// hi = (srl hi, shamt) 2717// lo = (sra hi, shamt[4:0]) 2720// lo = (srl hi, shamt[4:0]) 2741DL, VTList,
Cond, ShiftRightHi,
2757EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT();
2758EVT BasePtrVT =
Ptr.getValueType();
2768 LD->getMemOperand());
2771// Expand an unaligned 32 or 64-bit integer load node. 2774EVT MemVT = LD->getMemoryVT();
2779// Return if load is aligned or if MemVT is neither i32 nor i64. 2780if ((LD->getAlign().value() >= (MemVT.
getSizeInBits() / 8)) ||
2781 ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
2785EVT VT =
Op.getValueType();
2789assert((VT == MVT::i32) || (VT == MVT::i64));
2792// (set dst, (i64 (load baseptr))) 2794// (set tmp, (ldl (add baseptr, 7), undef)) 2795// (set dst, (ldr baseptr, tmp)) 2809// (set dst, (i32 (load baseptr))) or 2810// (set dst, (i64 (sextload baseptr))) or 2811// (set dst, (i64 (extload baseptr))) 2813// (set tmp, (lwl (add baseptr, 3), undef)) 2814// (set dst, (lwr baseptr, tmp)) 2822// (set dst, (i64 (zextload baseptr))) 2824// (set tmp0, (lwl (add baseptr, 3), undef)) 2825// (set tmp1, (lwr baseptr, tmp0)) 2826// (set tmp2, (shl tmp1, 32)) 2827// (set dst, (srl tmp2, 32)) 2832SDValue Ops[] = { SRL, LWR.getValue(1) };
2852// Expand an unaligned 32 or 64-bit integer store node. 2859// (store val, baseptr) or 2860// (truncstore val, baseptr) 2862// (swl val, (add baseptr, 3)) 2863// (swr val, baseptr) 2873// (store val, baseptr) 2875// (sdl val, (add baseptr, 7)) 2876// (sdr val, baseptr) 2881// Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr). 2902// Lower unaligned integer stores. 2905 ((MemVT == MVT::i32) || (MemVT == MVT::i64)))
2914// Return a fixed StackObject with offset 0 which points to the old stack 2917EVT ValTy =
Op->getValueType(0);
2933//===----------------------------------------------------------------------===// 2934// Calling Convention Implementation 2935//===----------------------------------------------------------------------===// 2937//===----------------------------------------------------------------------===// 2938// TODO: Implement a generic logic using tblgen that can support this. 2939// Mips O32 ABI rules: 2941// i32 - Passed in A0, A1, A2, A3 and stack 2942// f32 - Only passed in f32 registers if no int reg has been used yet to hold 2943// an argument. Otherwise, passed in A1, A2, A3 and stack. 2944// f64 - Only passed in two aliased f32 registers if no int reg has been used 2945// yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is 2946// not used, it must be shadowed. If only A3 is available, shadow it and 2948// vXiX - Received as scalarized i32s, passed in A0 - A3 and the stack. 2949// vXf32 - Passed in either a pair of registers {A0, A1}, {A2, A3} or {A0 - A3} 2950// with the remainder spilled to the stack. 2951// vXf64 - Passed in either {A0, A1, A2, A3} or {A2, A3} and in both cases 2952// spilling the remainder to the stack. 2954// For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack. 2955//===----------------------------------------------------------------------===// 2969staticconstMCPhysReg FloatVectorIntRegs[] = { Mips::A0, Mips::A2 };
2971// Do not process byval args here. 2975// Promote i8 and i16 2977if (LocVT == MVT::i8 || LocVT == MVT::i16 || LocVT == MVT::i32) {
2981elseif (ArgFlags.
isZExt())
2988// Promote i8 and i16 2989if (LocVT == MVT::i8 || LocVT == MVT::i16) {
2993elseif (ArgFlags.
isZExt())
3001// f32 and f64 are allocated in A0, A1, A2, A3 when either of the following 3002// is true: function is vararg, argument is 3rd or higher, there is previous 3003// argument which is not f32 or f64. 3004bool AllocateFloatsInIntReg = State.
isVarArg() || ValNo > 1 ||
3007bool isI64 = (ValVT == MVT::i32 && OrigAlign ==
Align(8));
3010// The MIPS vector ABI for floats passes them in a pair of registers 3011if (ValVT == MVT::i32 && isVectorFloat) {
3012// This is the start of an vector that was scalarized into an unknown number 3013// of components. It doesn't matter how many there are. Allocate one of the 3014// notional 8 byte aligned registers which map onto the argument stack, and 3015// shadow the register lost to alignment requirements. 3023// If we're an intermediate component of the split, we can just attempt to 3024// allocate a register directly. 3027 }
elseif (ValVT == MVT::i32 ||
3028 (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
3030// If this is the first part of an i64 arg, 3031// the allocated register must be either A0 or A2. 3032if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
3035 }
elseif (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
3036// Allocate int register and shadow next int register. If first 3037// available register is Mips::A1 or Mips::A3, shadow it too. 3039if (Reg == Mips::A1 || Reg == Mips::A3)
3054// we are guaranteed to find an available float register 3055if (ValVT == MVT::f32) {
3057// Shadow int register 3061// Shadow int registers 3063if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
3082staticconstMCPhysReg F64Regs[] = { Mips::D6, Mips::D7 };
3084returnCC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
3090staticconstMCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 };
3092returnCC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
3099#include "MipsGenCallingConv.inc" 3102return CC_Mips_FixedArg;
3108//===----------------------------------------------------------------------===// 3109// Call Calling Convention Implementation 3110//===----------------------------------------------------------------------===// 3114constSDLoc &
DL,
bool IsTailCall,
3132 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
3133bool IsPICCall,
bool GlobalOrExternal,
bool InternalLinkage,
3136// Insert node "GP copy globalreg" before call to function. 3138// R_MIPS_CALL* operators (emitted when non-internal functions are called 3139// in PIC mode) allow symbols to be resolved via lazy binding. 3140// The lazy binding stub requires GP to point to the GOT. 3141// Note that we don't need GP to point to the GOT for indirect calls 3142// (when R_MIPS_CALL* is not used for the call) because Mips linker generates 3143// lazy binding stub for a function only when R_MIPS_CALL* are the only relocs 3144// used for the function (that is, Mips linker doesn't generate lazy binding 3145// stub for a function whose address is taken in the program). 3146if (IsPICCall && !InternalLinkage && IsCallReloc) {
3147unsigned GPReg =
ABI.
IsN64() ? Mips::GP_64 : Mips::GP;
3149 RegsToPass.push_back(std::make_pair(GPReg,
getGlobalReg(CLI.
DAG, Ty)));
3152// Build a sequence of copy-to-reg nodes chained together with token 3153// chain and flag operands which copy the outgoing args into registers. 3154// The InGlue in necessary since all emitted instructions must be 3158for (
auto &R : RegsToPass) {
3163// Add argument registers to the end of the list so that they are 3164// known live into the call. 3165for (
auto &R : RegsToPass)
3168// Add a register mask operand representing the call-preserved registers. 3172assert(Mask &&
"Missing call preserved mask for calling convention");
3177if (
F &&
F->hasFnAttribute(
"__Mips16RetHelper")) {
3190switch (
MI.getOpcode()) {
3194case Mips::JALRPseudo:
3196case Mips::JALR64Pseudo:
3197case Mips::JALR16_MM:
3198case Mips::JALRC16_MMR6:
3199case Mips::TAILCALLREG:
3200case Mips::TAILCALLREG64:
3201case Mips::TAILCALLR6REG:
3202case Mips::TAILCALL64R6REG:
3203case Mips::TAILCALLREG_MM:
3204case Mips::TAILCALLREG_MMR6: {
3208 Node->getNumOperands() < 1 ||
3209 Node->getOperand(0).getNumOperands() < 2) {
3212// We are after the callee address, set by LowerCall(). 3213// If added to MI, asm printer will emit .reloc R_MIPS_JALR for the 3215constSDValue TargetAddr = Node->getOperand(0).getOperand(1);
3218 dyn_cast_or_null<const GlobalAddressSDNode>(TargetAddr)) {
3219// We must not emit the R_MIPS_JALR relocation against data symbols 3220// since this will cause run-time crashes if the linker replaces the 3221// call instruction with a relative branch to the data symbol. 3222if (!isa<Function>(
G->getGlobal())) {
3224 <<
G->getGlobal()->getName() <<
"\n");
3227Sym =
G->getGlobal()->getName();
3230 dyn_cast_or_null<const ExternalSymbolSDNode>(TargetAddr)) {
3231Sym = ES->getSymbol();
3245/// LowerCall - functions arguments are copied from virtual regs to 3246/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 3267// Analyze operands of the call, assigning locations to each operand. 3274 dyn_cast_or_null<const ExternalSymbolSDNode>(Callee.getNode());
3276// There is one case where CALLSEQ_START..CALLSEQ_END can be nested, which 3277// is during the lowering of a call with a byval argument which produces 3278// a call to memcpy. For the O32 case, this causes the caller to allocate 3279// stack space for the reserved argument area for the callee, then recursively 3280// again for the memcpy call. In the NEWABI case, this doesn't occur as those 3281// ABIs mandate that the callee allocates the reserved argument area. We do 3282// still produce nested CALLSEQ_START..CALLSEQ_END with zero space though. 3284// If the callee has a byval argument and memcpy is used, we are mandated 3285// to already have produced a reserved argument area for the callee for O32. 3286// Therefore, the reserved argument area can be reused for both calls. 3288// Other cases of calling memcpy cannot have a chain with a CALLSEQ_START 3289// present, as we have yet to hook that node onto the chain. 3291// Hence, the CALLSEQ_START and CALLSEQ_END nodes can be eliminated in this 3292// case. GCC does a similar trick, in that wherever possible, it calculates 3293// the maximum out going argument area (including the reserved area), and 3294// preallocates the stack space on entrance to the caller. 3296// FIXME: We should do the same for efficiency and space. 3298// Note: The check on the calling convention below must match 3299// MipsABIInfo::GetCalleeAllocdArgSizeInBytes(). 3304// Allocate the reserved argument area. It seems strange to do this from the 3305// caller side but removing it breaks the frame size calculation. 3306unsigned ReservedArgArea =
3308 CCInfo.AllocateStack(ReservedArgArea,
Align(1));
3313// Get a count of how many bytes are to be pushed on the stack. 3314unsigned StackSize = CCInfo.getStackSize();
3316// Call site info for function parameters tracking. 3319// Check if it's really possible to do a tail call. Restrict it to functions 3320// that are part of this compilation unit. 3321bool InternalLinkage =
false;
3323 IsTailCall = isEligibleForTailCallOptimization(
3326 InternalLinkage =
G->getGlobal()->hasInternalLinkage();
3327 IsTailCall &= (InternalLinkage ||
G->getGlobal()->hasLocalLinkage() ||
3328G->getGlobal()->hasPrivateLinkage() ||
3329G->getGlobal()->hasHiddenVisibility() ||
3330G->getGlobal()->hasProtectedVisibility());
3335"site marked musttail");
3340// Chain is the output chain of the last Load/Store or CopyToReg node. 3341// ByValChain is the output chain of the last Memcpy node created for copying 3342// byval arguments to the stack. 3344 StackSize =
alignTo(StackSize, StackAlignment);
3346if (!(IsTailCall || MemcpyInByVal))
3353 std::deque<std::pair<unsigned, SDValue>> RegsToPass;
3356 CCInfo.rewindByValRegsInfo();
3358// Walk the register/memloc assignments, inserting copies/loads. 3359for (
unsigned i = 0, e = ArgLocs.
size(), OutIdx = 0; i != e; ++i, ++OutIdx) {
3364bool UseUpperBits =
false;
3367if (
Flags.isByVal()) {
3368unsigned FirstByValReg, LastByValReg;
3369unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
3370 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
3373"ByVal args of size 0 should have been ignored by front-end.");
3374assert(ByValIdx < CCInfo.getInRegsParamsCount());
3376"Do not tail-call optimize if there is a byval argument.");
3377 passByValArg(Chain,
DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
3380 CCInfo.nextInRegsParam();
3384// Promote the value if needed. 3390if ((ValVT == MVT::f32 && LocVT == MVT::i32) ||
3391 (ValVT == MVT::f64 && LocVT == MVT::i64) ||
3392 (ValVT == MVT::i64 && LocVT == MVT::f64))
3394elseif (ValVT == MVT::f64 && LocVT == MVT::i32) {
3405Register LocRegHigh = ArgLocs[++i].getLocReg();
3406 RegsToPass.
push_back(std::make_pair(LocRegLo,
Lo));
3407 RegsToPass.push_back(std::make_pair(LocRegHigh,
Hi));
3436unsigned ValSizeInBits = Outs[OutIdx].ArgVT.getSizeInBits();
3443// Arguments that can be passed on register must be kept at 3446 RegsToPass.push_back(std::make_pair(VA.
getLocReg(), Arg));
3448// If the parameter is passed through reg $D, which splits into 3449// two physical registers, avoid creating call site info. 3453// Collect CSInfo about which register passes which parameter. 3461// Register can't get to this point... 3464// emit ISD::STORE whichs stores the 3465// parameter value to a stack Location 3467 Chain, Arg,
DL, IsTailCall, DAG));
3470// Transform all store nodes into one single node because all store 3471// nodes are independent of each other. 3472if (!MemOpChains.
empty())
3475// If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 3476// direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 3477// node so that legalize doesn't hack it. 3480bool GlobalOrExternal =
false, IsCallReloc =
false;
3482// The long-calls feature is ignored in case of PIC. 3483// While we do not support -mshared / -mno-shared properly, 3484// ignore long-calls in case of -mabicalls too. 3486// If the function should be called using "long call", 3487// get its address into a register to prevent using 3488// of the `jal` instruction for the direct call. 3489if (
auto *
N = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3494 }
elseif (
auto *
N = dyn_cast<GlobalAddressSDNode>(Callee)) {
3496// If the function has long-call/far/near attribute 3497// it overrides command line switch pased to the backend. 3498if (
auto *
F = dyn_cast<Function>(
N->getGlobal())) {
3499if (
F->hasFnAttribute(
"long-call"))
3501elseif (
F->hasFnAttribute(
"short-call"))
3502 UseLongCalls =
false;
3513G->getGlobal()->hasDLLImportStorageClass()) {
3515"Windows is the only supported COFF target");
3539 GlobalOrExternal =
true;
3542constchar *
Sym = S->getSymbol();
3558 GlobalOrExternal =
true;
3564getOpndList(Ops, RegsToPass, IsPIC, GlobalOrExternal, InternalLinkage,
3565 IsCallReloc, CLI, Callee, Chain);
3579// Create the CALLSEQ_END node in the case of where it is not a call to 3581if (!(MemcpyInByVal)) {
3586// Handle result values, copying them out of physregs into vregs that we 3588return LowerCallResult(Chain, InGlue, CallConv, IsVarArg, Ins,
DL, DAG,
3592/// LowerCallResult - Lower the result values of a call into the 3593/// appropriate copies out of appropriate physical registers. 3594SDValue MipsTargetLowering::LowerCallResult(
3599// Assign locations to each value returned by this call. 3605 dyn_cast_or_null<const ExternalSymbolSDNode>(CLI.
Callee.
getNode());
3606 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips, CLI.
RetTy,
3609// Copy all of the result registers out of their specified physreg. 3610for (
unsigned i = 0; i != RVLocs.
size(); ++i) {
3615 RVLocs[i].getLocVT(), InGlue);
3620unsigned ValSizeInBits =
Ins[i].ArgVT.getSizeInBits();
3667// Shift into the upper bits if necessary. 3685// If this is an value smaller than the argument slot size (32-bit for O32, 3686// 64-bit for N32/N64), it has been promoted in some way to the argument slot 3687// size. Extract the value and insert any appropriate assertions regarding 3688// sign/zero extension. 3716//===----------------------------------------------------------------------===// 3717// Formal Arguments Calling Convention Implementation 3718//===----------------------------------------------------------------------===// 3719/// LowerFormalArguments - transform physical registers into virtual registers 3720/// and generate load operations for arguments places on the stack. 3721SDValue MipsTargetLowering::LowerFormalArguments(
3731// Used with vargs to acumulate store chains. 3732 std::vector<SDValue> OutChains;
3734// Assign locations to all of the incoming arguments. 3742if (
Func.hasFnAttribute(
"interrupt") && !
Func.arg_empty())
3744"Functions with the interrupt attribute cannot have arguments!");
3746 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FixedArg);
3748 CCInfo.getInRegsParamsCount() > 0);
3750unsigned CurArgIdx = 0;
3751 CCInfo.rewindByValRegsInfo();
3753for (
unsigned i = 0, e = ArgLocs.
size(), InsIdx = 0; i != e; ++i, ++InsIdx) {
3755if (Ins[InsIdx].isOrigArg()) {
3756 std::advance(FuncArg, Ins[InsIdx].getOrigArgIndex() - CurArgIdx);
3757 CurArgIdx =
Ins[InsIdx].getOrigArgIndex();
3763if (
Flags.isByVal()) {
3764assert(Ins[InsIdx].isOrigArg() &&
"Byval arguments cannot be implicit");
3765unsigned FirstByValReg, LastByValReg;
3766unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
3767 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
3770"ByVal args of size 0 should have been ignored by front-end.");
3771assert(ByValIdx < CCInfo.getInRegsParamsCount());
3772 copyByValRegs(Chain,
DL, OutChains, DAG, Flags, InVals, &*FuncArg,
3773 FirstByValReg, LastByValReg, VA, CCInfo);
3774 CCInfo.nextInRegsParam();
3778// Arguments stored on registers 3784// Transform the arguments stored on 3785// physical registers into virtual ones 3792// Handle floating point arguments passed in integer registers and 3793// long double arguments passed in floating point registers. 3794if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
3795 (RegVT == MVT::i64 && ValVT == MVT::f64) ||
3796 (RegVT == MVT::f64 && ValVT == MVT::i64))
3798elseif (
ABI.
IsO32() && RegVT == MVT::i32 &&
3799 ValVT == MVT::f64) {
3808 ArgValue, ArgValue2);
3812 }
else {
// VA.isRegLoc() 3817// Only arguments pased on the stack should make it here. 3820// The stack pointer offset is relative to the caller stack frame. 3824// Create load nodes to retrieve arguments from the stack 3827 LocVT,
DL, Chain, FIN,
3829 OutChains.push_back(ArgValue.
getValue(1));
3838for (
unsigned i = 0, e = ArgLocs.
size(), InsIdx = 0; i != e; ++i, ++InsIdx) {
3840if (ArgLocs[i].needsCustom()) {
3845// The mips ABIs for returning structs by value requires that we copy 3846// the sret argument into $v0 for the return. Save the argument into 3847// a virtual register so that we can access it from the return points. 3848if (Ins[InsIdx].
Flags.isSRet()) {
3862 writeVarArgRegs(OutChains, Chain,
DL, DAG, CCInfo);
3864// All stores are grouped in one node to allow the matching between 3865// the size of Ins and InVals. This only happens when on varg functions 3866if (!OutChains.empty()) {
3867 OutChains.push_back(Chain);
3874//===----------------------------------------------------------------------===// 3875// Return Value Calling Convention Implementation 3876//===----------------------------------------------------------------------===// 3884MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
3885return CCInfo.CheckCallReturn(Outs, RetCC_Mips,
RetTy);
3888bool MipsTargetLowering::shouldSignExtendTypeInLibCall(
Type *Ty,
3889bool IsSigned)
const{
3914// CCValAssign - represent the assignment of 3915// the return value to a location 3919// CCState - Info about the registers and stack slot. 3922// Analyze return values. 3923 CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
3928// Copy the result values into the output registers. 3929for (
unsigned i = 0; i != RVLocs.
size(); ++i) {
3933bool UseUpperBits =
false;
3964unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits();
3973// Guarantee that all emitted copies are stuck together with flags. 3978// The mips ABIs for returning structs by value requires that we copy 3979// the sret argument into $v0 for the return. We saved the argument into 3980// a virtual register in the entry block, so now we copy the value out 3990unsigned V0 =
ABI.
IsN64() ? Mips::V0_64 : Mips::V0;
3997 RetOps[0] = Chain;
// Update chain. 3999// Add the glue if we have it. 4003// ISRs must use "eret". 4005return LowerInterruptReturn(RetOps,
DL, DAG);
4007// Standard return on Mips is a "jr $ra" 4011//===----------------------------------------------------------------------===// 4012// Mips Inline Assembly Support 4013//===----------------------------------------------------------------------===// 4015/// getConstraintType - Given a constraint letter, return the type of 4016/// constraint it is for this target. 4018MipsTargetLowering::getConstraintType(
StringRef Constraint)
const{
4019// Mips specific constraints 4020// GCC config/mips/constraints.md 4022// 'd' : An address register. Equivalent to r 4023// unless generating MIPS16 code. 4024// 'y' : Equivalent to r; retained for 4025// backwards compatibility. 4026// 'c' : A register suitable for use in an indirect 4027// jump. This will always be $25 for -mabicalls. 4028// 'l' : The lo register. 1 word storage. 4029// 'x' : The hilo register pair. Double word storage. 4030if (Constraint.
size() == 1) {
4031switch (Constraint[0]) {
4045if (Constraint ==
"ZC")
4051/// Examine constraint type and operand type and determine a weight value. 4052/// This object must already have been set up with the operand type 4053/// and the current alternative constraint selected. 4055MipsTargetLowering::getSingleConstraintMatchWeight(
4056 AsmOperandInfo &
info,
constchar *constraint)
const{
4058Value *CallOperandVal =
info.CallOperandVal;
4059// If we don't have a value, we can't do a match, 4060// but allow it at the lowest weight. 4064// Look at the constraint type. 4065switch (*constraint) {
4074case'f':
// FPU or MSA register 4081case'c':
// $25 for indirect jumps 4082case'l':
// lo register 4083case'x':
// hilo register pair 4087case'I':
// signed 16 bit immediate 4088case'J':
// integer zero 4089case'K':
// unsigned 16 bit immediate 4090case'L':
// signed 32 bit immediate where lower 16 bits are 0 4091case'N':
// immediate in the range of -65535 to -1 (inclusive) 4092case'O':
// signed 15 bit immediate (+- 16383) 4093case'P':
// immediate in the range of 65535 to 1 (inclusive) 4094if (isa<ConstantInt>(CallOperandVal))
4104/// This is a helper function to parse a physical register string and split it 4105/// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag 4106/// that is returned indicates whether parsing was successful. The second flag 4107/// is true if the numeric part exists. 4109unsignedlonglong &Reg) {
4110if (
C.front() !=
'{' ||
C.back() !=
'}')
4111return std::make_pair(
false,
false);
4113// Search for the first numeric character. 4115I = std::find_if(
B, E, isdigit);
4119// The second flag is set to false if no numeric characters were found. 4121return std::make_pair(
true,
false);
4123// Parse the numeric characters. 4132return VT.
bitsLT(MinVT) ? MinVT : VT;
4135std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering::
4141unsignedlonglong Reg;
4146return std::make_pair(0U,
nullptr);
4148if ((Prefix ==
"hi" || Prefix ==
"lo")) {
// Parse hi/lo. 4149// No numeric characters follow "hi" or "lo". 4151return std::make_pair(0U,
nullptr);
4153 RC =
TRI->getRegClass(Prefix ==
"hi" ?
4154 Mips::HI32RegClassID : Mips::LO32RegClassID);
4155return std::make_pair(*(RC->
begin()), RC);
4156 }
elseif (Prefix.starts_with(
"$msa")) {
4157// Parse $msa(ir|csr|access|save|modify|request|map|unmap) 4159// No numeric characters follow the name. 4161return std::make_pair(0U,
nullptr);
4164 .
Case(
"$msair", Mips::MSAIR)
4165 .
Case(
"$msacsr", Mips::MSACSR)
4166 .
Case(
"$msaaccess", Mips::MSAAccess)
4167 .
Case(
"$msasave", Mips::MSASave)
4168 .
Case(
"$msamodify", Mips::MSAModify)
4169 .
Case(
"$msarequest", Mips::MSARequest)
4170 .
Case(
"$msamap", Mips::MSAMap)
4171 .
Case(
"$msaunmap", Mips::MSAUnmap)
4175return std::make_pair(0U,
nullptr);
4177 RC =
TRI->getRegClass(Mips::MSACtrlRegClassID);
4178return std::make_pair(Reg, RC);
4182return std::make_pair(0U,
nullptr);
4184if (Prefix ==
"$f") {
// Parse $f0-$f31. 4185// If the size of FP registers is 64-bit or Reg is an even number, select 4186// the 64-bit register class. Otherwise, select the 32-bit register class. 4187if (VT == MVT::Other)
4192if (RC == &Mips::AFGR64RegClass) {
4196 }
elseif (Prefix ==
"$fcc")
// Parse $fcc0-$fcc7. 4197 RC =
TRI->getRegClass(Mips::FCCRegClassID);
4198elseif (Prefix ==
"$w") {
// Parse $w0-$w31. 4200 }
else {
// Parse $0-$31. 4205assert(Reg < RC->getNumRegs());
4206return std::make_pair(*(RC->
begin() + Reg), RC);
4209/// Given a register class constraint, like 'r', if this corresponds directly 4210/// to an LLVM register class, return a register of 0 and the register class 4212std::pair<unsigned, const TargetRegisterClass *>
4216if (Constraint.
size() == 1) {
4217switch (Constraint[0]) {
4218case'd':
// Address register. Same as 'r' unless generating MIPS16 code. 4219case'y':
// Same as 'r'. Exists for compatibility. 4221if ((VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8 ||
4225return std::make_pair(0U, &Mips::CPU16RegsRegClass);
4226return std::make_pair(0U, &Mips::GPR32RegClass);
4230return std::make_pair(0U, &Mips::GPR32RegClass);
4233return std::make_pair(0U, &Mips::GPR64RegClass);
4234// This will generate an error message 4235return std::make_pair(0U,
nullptr);
4236case'f':
// FPU or MSA register 4237if (VT == MVT::v16i8)
4238return std::make_pair(0U, &Mips::MSA128BRegClass);
4239elseif (VT == MVT::v8i16 || VT == MVT::v8f16)
4240return std::make_pair(0U, &Mips::MSA128HRegClass);
4241elseif (VT == MVT::v4i32 || VT == MVT::v4f32)
4242return std::make_pair(0U, &Mips::MSA128WRegClass);
4243elseif (VT == MVT::v2i64 || VT == MVT::v2f64)
4244return std::make_pair(0U, &Mips::MSA128DRegClass);
4245elseif (VT == MVT::f32)
4246return std::make_pair(0U, &Mips::FGR32RegClass);
4249return std::make_pair(0U, &Mips::FGR64RegClass);
4250return std::make_pair(0U, &Mips::AFGR64RegClass);
4253case'c':
// register suitable for indirect jump 4255return std::make_pair((
unsigned)Mips::T9, &Mips::GPR32RegClass);
4257return std::make_pair((
unsigned)Mips::T9_64, &Mips::GPR64RegClass);
4258// This will generate an error message 4259return std::make_pair(0U,
nullptr);
4260case'l':
// use the `lo` register to store values 4261// that are no bigger than a word 4262if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8)
4263return std::make_pair((
unsigned)Mips::LO0, &Mips::LO32RegClass);
4264return std::make_pair((
unsigned)Mips::LO0_64, &Mips::LO64RegClass);
4265case'x':
// use the concatenated `hi` and `lo` registers 4266// to store doubleword values 4267// Fixme: Not triggering the use of both hi and low 4268// This will generate an error message 4269return std::make_pair(0U,
nullptr);
4273if (!Constraint.
empty()) {
4274 std::pair<unsigned, const TargetRegisterClass *>
R;
4275R = parseRegForInlineAsmConstraint(Constraint, VT);
4284/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 4285/// vector. If it is invalid, don't add anything to Ops. 4286void MipsTargetLowering::LowerAsmOperandForConstraint(
SDValueOp,
4288 std::vector<SDValue> &Ops,
4293// Only support length 1 constraints for now. 4294if (Constraint.
size() > 1)
4297char ConstraintLetter = Constraint[0];
4298switch (ConstraintLetter) {
4299default:
break;
// This will fall through to the generic implementation 4300case'I':
// Signed 16 bit constant 4301// If this fails, the parent routine will give an error 4304 int64_t Val =
C->getSExtValue();
4305if (isInt<16>(Val)) {
4311case'J':
// integer zero 4314 int64_t Val =
C->getZExtValue();
4321case'K':
// unsigned 16 bit immediate 4325if (isUInt<16>(Val)) {
4331case'L':
// signed 32 bit immediate where lower 16 bits are 0 4334 int64_t Val =
C->getSExtValue();
4335if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){
4341case'N':
// immediate in the range of -65535 to -1 (inclusive) 4344 int64_t Val =
C->getSExtValue();
4345if ((Val >= -65535) && (Val <= -1)) {
4351case'O':
// signed 15 bit immediate 4354 int64_t Val =
C->getSExtValue();
4355if ((isInt<15>(Val))) {
4361case'P':
// immediate in the range of 1 to 65535 (inclusive) 4364 int64_t Val =
C->getSExtValue();
4365if ((Val <= 65535) && (Val >= 1)) {
4374 Ops.push_back(Result);
4381bool MipsTargetLowering::isLegalAddressingMode(
constDataLayout &
DL,
4385// No global is ever allowed as a base. 4390case 0:
// "r+i" or just "i", depending on HasBaseReg. 4393if (!AM.HasBaseReg)
// allow "r+i". 4395returnfalse;
// disallow "r+r" or "r+r+i". 4405// The Mips target isn't yet aware of offsets. 4409EVT MipsTargetLowering::getOptimalMemOpType(
4417bool MipsTargetLowering::isFPImmLegal(
constAPFloat &Imm,
EVT VT,
4418bool ForCodeSize)
const{
4419if (VT != MVT::f32 && VT != MVT::f64)
4426unsigned MipsTargetLowering::getJumpTableEncoding()
const{
4428// FIXME: For space reasons this should be: EK_GPRel32BlockAddress. 4435bool MipsTargetLowering::useSoftFloat()
const{
4439void MipsTargetLowering::copyByValRegs(
4443unsigned FirstReg,
unsigned LastReg,
constCCValAssign &VA,
4448unsigned NumRegs = LastReg - FirstReg;
4449unsigned RegAreaSize = NumRegs * GPRSizeInBytes;
4450unsigned FrameObjSize = std::max(
Flags.getByValSize(), RegAreaSize);
4457 (
int)((ByValArgRegs.
size() - FirstReg) * GPRSizeInBytes);
4461// Create frame object. 4463// Make the fixed object stored to mutable so that the load instructions 4464// referencing it have their memory dependencies added. 4465// Set the frame object as isAliased which clears the underlying objects 4466// vector in ScheduleDAGInstrs::buildSchedGraph() resulting in addition of all 4467// stores as dependencies for loads referencing this fixed object. 4475// Copy arg registers. 4479for (
unsignedI = 0;
I < NumRegs; ++
I) {
4480unsigned ArgReg = ByValArgRegs[FirstReg +
I];
4481unsigned VReg =
addLiveIn(MF, ArgReg, RC);
4482unsignedOffset =
I * GPRSizeInBytes;
4487 OutChains.push_back(Store);
4491// Copy byVal arg to registers and stack. 4492void MipsTargetLowering::passByValArg(
4494 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
4499unsigned ByValSizeInBytes =
Flags.getByValSize();
4500unsigned OffsetInBytes = 0;
// From beginning of struct 4503 std::min(
Flags.getNonZeroByValAlign(),
Align(RegSizeInBytes));
4506unsigned NumRegs = LastReg - FirstReg;
4510bool LeftoverBytes = (NumRegs * RegSizeInBytes > ByValSizeInBytes);
4513// Copy words to registers. 4514for (;
I < NumRegs - LeftoverBytes; ++
I, OffsetInBytes += RegSizeInBytes) {
4520unsigned ArgReg = ArgRegs[FirstReg +
I];
4521 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal));
4524// Return if the struct has been fully copied. 4525if (ByValSizeInBytes == OffsetInBytes)
4528// Copy the remainder of the byval argument with sub-word loads and shifts. 4532for (
unsigned LoadSizeInBytes = RegSizeInBytes / 2, TotalBytesLoaded = 0;
4533 OffsetInBytes < ByValSizeInBytes; LoadSizeInBytes /= 2) {
4534unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes;
4536if (RemainingSizeInBytes < LoadSizeInBytes)
4548// Shift the loaded value. 4552 Shamt = TotalBytesLoaded * 8;
4554 Shamt = (RegSizeInBytes - (TotalBytesLoaded + LoadSizeInBytes)) * 8;
4564 OffsetInBytes += LoadSizeInBytes;
4565 TotalBytesLoaded += LoadSizeInBytes;
4566 Alignment = std::min(Alignment,
Align(LoadSizeInBytes));
4569unsigned ArgReg = ArgRegs[FirstReg +
I];
4570 RegsToPass.push_back(std::make_pair(ArgReg, Val));
4575// Copy remainder of byval arg to it with memcpy. 4576unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes;
4583Align(Alignment),
/*isVolatile=*/false,
/*AlwaysInline=*/false,
4588void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
4601// Offset of the first variable argument from stack pointer. 4609 (
int)(RegSizeInBytes * (ArgRegs.
size() -
Idx));
4612// Record the frame index of the first variable argument 4613// which is a value necessary to VASTART. 4617// Copy the integer registers that have not been used for argument passing 4618// to the argument register save area. For O32, the save area is allocated 4619// in the caller's stack frame, while for N32/64, it is allocated in the 4620// callee's stack frame. 4622 ++
I, VaArgOffset += RegSizeInBytes) {
4629 cast<StoreSDNode>(
Store.getNode())->getMemOperand()->setValue(
4631 OutChains.push_back(Store);
4636Align Alignment)
const{
4639assert(
Size &&
"Byval argument's size shouldn't be 0.");
4643unsigned FirstReg = 0;
4644unsigned NumRegs = 0;
4649// FIXME: The O32 case actually describes no shadow registers. 4653// We used to check the size as well but we can't do that anymore since 4654// CCState::HandleByVal() rounds up the size after calling this function. 4656 Alignment >=
Align(RegSizeInBytes) &&
4657"Byval argument's alignment should be a multiple of RegSizeInBytes.");
4661// If Alignment > RegSizeInBytes, the first arg register must be even. 4662// FIXME: This condition happens to do the right thing but it's not the 4663// right way to test it. We want to check that the stack frame offset 4664// of the register is aligned. 4665if ((Alignment > RegSizeInBytes) && (FirstReg % 2)) {
4666 State->
AllocateReg(IntArgRegs[FirstReg], ShadowRegs[FirstReg]);
4670// Mark the registers allocated. 4672for (
unsignedI = FirstReg;
Size > 0 && (
I < IntArgRegs.
size());
4673Size -= RegSizeInBytes, ++
I, ++NumRegs)
4685"Subtarget already supports SELECT nodes with the use of" 4686"conditional-move instructions.");
4692// To "insert" a SELECT instruction, we actually have to insert the 4693// diamond control-flow pattern. The incoming instruction knows the 4694// destination vreg to set, the condition code register to branch on, the 4695// true/false values to select between, and a branch opcode to use. 4703// bNE r1, r0, copy1MBB 4704// fallthrough --> copy0MBB 4709F->insert(It, copy0MBB);
4710F->insert(It, sinkMBB);
4712// Transfer the remainder of BB and its successor edges to sinkMBB. 4717// Next, add the true and fallthrough blocks as its successors. 4722// bc1[tf] cc, sinkMBB 4727// bne rs, $0, sinkMBB 4736// # fallthrough to sinkMBB 4739// Update machine-CFG edges 4743// %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 4753MI.eraseFromParent();
// The pseudo instruction is gone now. 4762"Subtarget already supports SELECT nodes with the use of" 4763"conditional-move instructions.");
4768// D_SELECT substitutes two SELECT nodes that goes one after another and 4769// have the same condition operand. On machines which don't have 4770// conditional-move instruction, it reduces unnecessary branch instructions 4771// which are result of using two diamond patterns that are result of two 4772// SELECT pseudo instructions. 4780// bNE r1, r0, copy1MBB 4781// fallthrough --> copy0MBB 4786F->insert(It, copy0MBB);
4787F->insert(It, sinkMBB);
4789// Transfer the remainder of BB and its successor edges to sinkMBB. 4794// Next, add the true and fallthrough blocks as its successors. 4798// bne rs, $0, sinkMBB 4806// # fallthrough to sinkMBB 4809// Update machine-CFG edges 4813// %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 4817// Use two PHI nodes to select two reults 4829MI.eraseFromParent();
// The pseudo instruction is gone now. 4834// FIXME? Maybe this could be a TableGen attribute on some registers and 4835// this table could be generated automatically from RegInfo. 4839// The Linux kernel uses $28 and sp. 4842 .
Case(
"$28", Mips::GP_64)
4843 .
Case(
"sp", Mips::SP_64)
4849 .
Case(
"$28", Mips::GP)
4850 .
Case(
"sp", Mips::SP)
4868unsigned Imm =
MI.getOperand(2).getImm();
4873// Mips release 6 can load from adress that is not naturally-aligned. 4874Register Temp =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4881// Mips release 5 needs to use instructions that can load from an unaligned 4883Register LoadHalf =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4884Register LoadFull =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4885Register Undef =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4890 .
addImm(Imm + (IsLittle ? 0 : 3))
4895 .
addImm(Imm + (IsLittle ? 3 : 0))
4900MI.eraseFromParent();
4914unsignedImm =
MI.getOperand(2).getImm();
4919// Mips release 6 can load from adress that is not naturally-aligned. 4921Register Temp =
MRI.createVirtualRegister(&Mips::GPR64RegClass);
4928Register Wtemp =
MRI.createVirtualRegister(&Mips::MSA128WRegClass);
4934 .
addImm(Imm + (IsLittle ? 0 : 4));
4938 .
addImm(Imm + (IsLittle ? 4 : 0));
4946// Mips release 5 needs to use instructions that can load from an unaligned 4948Register LoHalf =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4949Register LoFull =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4950Register LoUndef =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4951Register HiHalf =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4952Register HiFull =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4953Register HiUndef =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4954Register Wtemp =
MRI.createVirtualRegister(&Mips::MSA128WRegClass);
4959 .
addImm(Imm + (IsLittle ? 0 : 7))
4964 .
addImm(Imm + (IsLittle ? 3 : 4))
4970 .
addImm(Imm + (IsLittle ? 4 : 3))
4975 .
addImm(Imm + (IsLittle ? 7 : 0))
4984MI.eraseFromParent();
4998unsignedImm =
MI.getOperand(2).getImm();
5003// Mips release 6 can store to adress that is not naturally-aligned. 5004Register BitcastW =
MRI.createVirtualRegister(&Mips::MSA128WRegClass);
5005Register Tmp =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
5016// Mips release 5 needs to use instructions that can store to an unaligned 5018Register Tmp =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
5026 .
addImm(Imm + (IsLittle ? 0 : 3));
5030 .
addImm(Imm + (IsLittle ? 3 : 0));
5033MI.eraseFromParent();
5048unsignedImm =
MI.getOperand(2).getImm();
5053// Mips release 6 can store to adress that is not naturally-aligned. 5055Register BitcastD =
MRI.createVirtualRegister(&Mips::MSA128DRegClass);
5069Register BitcastW =
MRI.createVirtualRegister(&Mips::MSA128WRegClass);
5086 .
addImm(Imm + (IsLittle ? 0 : 4));
5090 .
addImm(Imm + (IsLittle ? 4 : 0));
5093// Mips release 5 needs to use instructions that can store to an unaligned 5110 .
addImm(Imm + (IsLittle ? 0 : 3));
5114 .
addImm(Imm + (IsLittle ? 3 : 0));
5118 .
addImm(Imm + (IsLittle ? 4 : 7));
5122 .
addImm(Imm + (IsLittle ? 7 : 4));
5125MI.eraseFromParent();
unsigned const MachineRegisterInfo * MRI
static SDValue performSHLCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG)
If the operand is a bitwise AND with a constant RHS, and the shift has a constant RHS and is the only...
static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget, const AArch64TargetLowering &TLI)
static SDValue performANDCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
This file declares a class to represent arbitrary precision floating point values and provide a varie...
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Function Alias Analysis Results
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
#define LLVM_ATTRIBUTE_UNUSED
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
const HexagonInstrInfo * TII
Module.h This file contains the declarations for the Module class.
static MachineBasicBlock * insertDivByZeroTrap(MachineInstr &MI, MachineBasicBlock *MBB)
unsigned const TargetRegisterInfo * TRI
cl::opt< bool > EmitJalrReloc
static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
static bool CC_Mips(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State) LLVM_ATTRIBUTE_UNUSED
static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, ArrayRef< MCPhysReg > F64Regs)
static SDValue performMADD_MSUBCombine(SDNode *ROOTNode, SelectionDAG &CurDAG, const MipsSubtarget &Subtarget)
static bool invertFPCondCodeUser(Mips::CondCode CC)
This function returns true if the floating point conditional branches and conditional moves which use...
static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG, bool SingleFloat)
static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static const MCPhysReg Mips64DPRegs[8]
static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG, bool IsLittle)
static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD, SDValue Chain, unsigned Offset)
static unsigned addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
static std::pair< bool, bool > parsePhysicalReg(StringRef C, StringRef &Prefix, unsigned long long &Reg)
This is a helper function to parse a physical register string and split it into non-numeric and numer...
static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD, SDValue Chain, SDValue Src, unsigned Offset)
static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool HasExtractInsert)
static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
cl::opt< bool > EmitJalrReloc
static SDValue performSUBCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op)
static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, bool HasExtractInsert)
static cl::opt< bool > NoZeroDivCheck("mno-check-zero-division", cl::Hidden, cl::desc("MIPS: Don't trap on integer division by zero."), cl::init(false))
static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static SDValue performCMovFPCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static SDValue UnpackFromArgumentSlot(SDValue Val, const CCValAssign &VA, EVT ArgVT, const SDLoc &DL, SelectionDAG &DAG)
static Mips::CondCode condCodeToFCC(ISD::CondCode CC)
static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True, SDValue False, const SDLoc &DL)
uint64_t IntrinsicInst * II
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
const SmallVectorImpl< MachineOperand > & Cond
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
SI optimize exec mask operations pre RA
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
This file defines the SmallVector class.
static const MCPhysReg IntRegs[32]
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
static const MCPhysReg F32Regs[64]
This class represents an incoming formal argument to a Function.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
LLVM Basic Block Representation.
static BranchProbability getOne()
CCState - This class holds information needed while lowering arguments and return values.
MachineFunction & getMachineFunction() const
unsigned getFirstUnallocated(ArrayRef< MCPhysReg > Regs) const
getFirstUnallocated - Return the index of the first unallocated register in the set,...
CallingConv::ID getCallingConv() const
MCRegister AllocateReg(MCPhysReg Reg)
AllocateReg - Attempt to allocate one register.
int64_t AllocateStack(unsigned Size, Align Alignment)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
uint64_t getStackSize() const
Returns the size of the currently allocated portion of the stack.
void addInRegsParamInfo(unsigned RegBegin, unsigned RegEnd)
void addLoc(const CCValAssign &V)
CCValAssign - Represent assignment of one arg/retval to a location.
Register getLocReg() const
LocInfo getLocInfo() const
static CCValAssign getReg(unsigned ValNo, MVT ValVT, MCRegister Reg, MVT LocVT, LocInfo HTP, bool IsCustom=false)
static CCValAssign getCustomReg(unsigned ValNo, MVT ValVT, MCRegister Reg, MVT LocVT, LocInfo HTP)
bool isUpperBitsInLoc() const
static CCValAssign getMem(unsigned ValNo, MVT ValVT, int64_t Offset, MVT LocVT, LocInfo HTP, bool IsCustom=false)
int64_t getLocMemOffset() const
bool isMustTailCall() const
Tests if this call site must be tail call optimized.
uint64_t getZExtValue() const
int64_t getSExtValue() const
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
TypeSize getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
const char * getSymbol() const
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
bool hasStructRetAttr() const
Determine if the function returns a structure through first or second pointer argument.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
const GlobalValue * getGlobal() const
bool hasLocalLinkage() const
bool hasDLLImportStorageClass() const
const GlobalObject * getAliaseeObject() const
bool hasInternalLinkage() const
Class to represent integer types.
This is an important class for using LLVM in a threaded context.
void emitError(const Instruction *I, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
This class is used to represent ISD::LOAD nodes.
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Wrapper class representing physical registers. Should be passed by value.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
static auto integer_valuetypes()
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
TypeSize getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
static MVT getVectorVT(MVT VT, unsigned NumElements)
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
bool isValid() const
Return true if this is a valid simple valuetype.
static MVT getIntegerVT(unsigned BitWidth)
static auto fp_valuetypes()
static auto fp_fixedlen_vector_valuetypes()
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
void setFrameAddressIsTaken(bool T)
void setHasTailCall(bool V=true)
void setReturnAddressIsTaken(bool s)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MCContext & getContext() const
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *BB=nullptr, std::optional< UniqueBBID > BBID=std::nullopt)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
void insert(iterator MBBI, MachineBasicBlock *MBB)
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Representation of each machine instruction.
const MachineOperand & getOperand(unsigned i) const
@ EK_GPRel64BlockAddress
EK_GPRel64BlockAddress - Each entry is an address of block, encoded with a relocation as gp-relative,...
@ MOVolatile
The memory access is volatile.
Flags getFlags() const
Return the raw flags of the source value,.
MachineOperand class - Representation of each machine instruction operand.
void setSubReg(unsigned subReg)
static MachineOperand CreateMCSymbol(MCSymbol *Sym, unsigned TargetFlags=0)
void setIsKill(bool Val=true)
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
const MachinePointerInfo & getPointerInfo() const
const SDValue & getChain() const
EVT getMemoryVT() const
Return the type of the in-memory value.
ArrayRef< MCPhysReg > GetVarArgRegs() const
The registers to use for the variable argument list.
bool ArePtrs64bit() const
unsigned GetCalleeAllocdArgSizeInBytes(CallingConv::ID CC) const
Obtain the size of the area allocated by the callee for arguments.
unsigned GetPtrAddiuOp() const
unsigned GetPtrAndOp() const
ArrayRef< MCPhysReg > GetByValArgRegs() const
The registers to use for byval arguments.
unsigned GetNullPtr() const
bool WasOriginalArgVectorFloat(unsigned ValNo) const
static SpecialCallingConvType getSpecialCallingConvForCallee(const SDNode *Callee, const MipsSubtarget &Subtarget)
Determine the SpecialCallingConvType for the given callee.
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
void setVarArgsFrameIndex(int Index)
unsigned getSRetReturnReg() const
int getVarArgsFrameIndex() const
MachinePointerInfo callPtrInfo(MachineFunction &MF, const char *ES)
Create a MachinePointerInfo that has an ExternalSymbolPseudoSourceValue object representing a GOT ent...
Register getGlobalBaseReg(MachineFunction &MF)
void setSRetReturnReg(unsigned Reg)
void setFormalArgInfo(unsigned Size, bool HasByval)
static const uint32_t * getMips16RetHelperMask()
bool inMicroMipsMode() const
bool useSoftFloat() const
const MipsInstrInfo * getInstrInfo() const override
bool inMips16Mode() const
bool inAbs2008Mode() const
const MipsRegisterInfo * getRegisterInfo() const override
bool systemSupportsUnalignedAccess() const
Does the system support unaligned memory access.
bool hasExtractInsert() const
Features related to the presence of specific instructions.
bool isTargetCOFF() const
bool isTargetWindows() const
bool isSingleFloat() const
bool useLongCalls() const
unsigned getGPRSizeInBytes() const
bool inMips16HardFloat() const
const TargetFrameLowering * getFrameLowering() const override
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the register type for a given MVT, ensuring vectors are treated as a series of gpr sized integ...
bool hasBitTest(SDValue X, SDValue Y) const override
Return true if the target has a bit-test instruction: (X & (1 << Y)) ==/!= 0 This knowledge can be us...
static const MipsTargetLowering * create(const MipsTargetMachine &TM, const MipsSubtarget &STI)
SDValue getAddrGPRel(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, bool IsN64) const
unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const override
Break down vectors to the correct number of gpr sized integers.
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
const char * getTargetNodeName(unsigned Opcode) const override
getTargetNodeName - This method returns the name of a target specific
SDValue getAddrNonPICSym64(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG) const
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
getSetCCResultType - get the ISD::SETCC result ValueType
SDValue getAddrGlobal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned Flag, SDValue Chain, const MachinePointerInfo &PtrInfo) const
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override
createFastISel - This method returns a target specific FastISel object, or null if the target does no...
MipsTargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
SDValue getAddrGlobalLargeGOT(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned HiFlag, unsigned LoFlag, SDValue Chain, const MachinePointerInfo &PtrInfo) const
SDValue getDllimportVariable(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, SDValue Chain, const MachinePointerInfo &PtrInfo) const
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
CCAssignFn * CCAssignFnForReturn() const
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
ReplaceNodeResults - Replace the results of node with an illegal result type with new values built ou...
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
SDValue getDllimportSymbol(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG) const
CCAssignFn * CCAssignFnForCall() const
unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the number of registers for a given MVT, ensuring vectors are treated as a series of gpr sized...
SDValue getAddrNonPIC(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG) const
SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const
void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const override
This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag.
virtual void getOpndList(SmallVectorImpl< SDValue > &Ops, std::deque< std::pair< unsigned, SDValue > > &RegsToPass, bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const
This function fills Ops, which is the list of operands that will later be used when a function call n...
EVT getTypeForExtReturn(LLVMContext &Context, EVT VT, ISD::NodeType) const override
Return the type that should be used to zero or sign extend a zeroext/signext integer return value.
bool isCheapToSpeculateCtlz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
bool isCheapToSpeculateCttz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic cttz.
bool shouldFoldConstantShiftPairToMask(const SDNode *N, CombineLevel Level) const override
Return true if it is profitable to fold a pair of shifts into a mask.
SDValue getAddrLocal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, bool IsN32OrN64) const
SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const
const MipsSubtarget & Subtarget
void HandleByVal(CCState *, unsigned &, Align) const override
Target-specific cleanup for formal ByVal parameters.
SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const
bool IsConstantInSmallSection(const DataLayout &DL, const Constant *CN, const TargetMachine &TM) const
Return true if this constant should be placed into small data section.
Wrapper class representing virtual and physical registers.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
uint64_t getAsZExtVal() const
Helper method returns the zero-extended integer value of a ConstantSDNode.
const SDValue & getOperand(unsigned Num) const
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getValue(unsigned R) const
EVT getValueType() const
Return the ValueType of the referenced return value.
TypeSize getValueSizeInBits() const
Returns the size of the value in bits.
const SDValue & getOperand(unsigned i) const
unsigned getOpcode() const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, Register Reg, SDValue N)
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond, SDValue Chain=SDValue(), bool IsSignaling=false)
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
SDValue getRegister(Register Reg, EVT VT)
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, const CallInst *CI, std::optional< bool > OverrideTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), BatchAAResults *BatchAA=nullptr)
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned TargetFlags=0)
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, Register Reg, EVT VT)
const DataLayout & getDataLayout() const
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
SDValue getSignedTargetConstant(int64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
SDValue getSignedConstant(int64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
SDValue getExternalSymbol(const char *Sym, EVT VT)
const TargetMachine & getTarget() const
SDValue getSelectCC(const SDLoc &DL, SDValue LHS, SDValue RHS, SDValue True, SDValue False, ISD::CondCode Cond)
Helper function to make it easier to build SelectCC's if you just have an ISD::CondCode instead of an...
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
SDValue getValueType(EVT)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
bool isKnownNeverNaN(SDValue Op, bool SNaN=false, unsigned Depth=0) const
Test whether the given SDValue (or all elements of it, if it is a vector) is known to never be NaN.
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned TargetFlags=0)
void ReplaceAllUsesOfValueWith(SDValue From, SDValue To)
Replace any uses of From with To, leaving uses of other values produced by From.getNode() alone.
MachineFunction & getMachineFunction() const
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
SDValue getRegisterMask(const uint32_t *RegMask)
void addCallSiteInfo(const SDNode *Node, CallSiteInfo &&CallInfo)
Set CallSiteInfo to be associated with Node.
LLVMContext * getContext() const
SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags Flags=MachineMemOperand::MOLoad|MachineMemOperand::MOStore, LocationSize Size=0, const AAMDNodes &AAInfo=AAMDNodes())
Creates a MemIntrinsicNode that may produce a result and takes a list of operands.
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
SDValue getTargetConstantPool(const Constant *C, EVT VT, MaybeAlign Align=std::nullopt, int Offset=0, unsigned TargetFlags=0)
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
std::pair< SDValue, SDValue > SplitScalar(const SDValue &N, const SDLoc &DL, const EVT &LoVT, const EVT &HiVT)
Split the scalar node with EXTRACT_ELEMENT using the provided VTs and return the low/high part.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
This class is used to represent ISD::STORE nodes.
const SDValue & getBasePtr() const
const SDValue & getValue() const
bool isTruncatingStore() const
Return true if the op does a truncation before store.
StringRef - Represent a constant reference to a string, i.e.
constexpr bool empty() const
empty - Check if the string is empty.
constexpr size_t size() const
size - Get the string size.
A switch()-like statement whose cases are string literals.
StringSwitch & Case(StringLiteral S, T Value)
Information about stack frame layout on the target.
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
TargetInstrInfo - Interface to description of machine instruction set.
Provides information about what library functions are available for the current target.
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
void setMinStackArgumentAlignment(Align Alignment)
Set the minimum stack alignment of an argument.
const TargetMachine & getTargetMachine() const
virtual unsigned getNumRegisters(LLVMContext &Context, EVT VT, std::optional< MVT > RegisterVT=std::nullopt) const
Return the number of registers that this ValueType will eventually require.
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
void setMinFunctionAlignment(Align Alignment)
Set the target's minimum function alignment.
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
@ ZeroOrOneBooleanContent
@ ZeroOrNegativeOneBooleanContent
void setStackPointerRegisterToSaveRestore(Register R)
If set to a physical register, this specifies the register that llvm.savestack/llvm....
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
void setTargetDAGCombine(ArrayRef< ISD::NodeType > NTs)
Targets should invoke this method for each target independent node that they want to provide a custom...
Align getMinStackArgumentAlignment() const
Return the minimum stack alignment of an argument.
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
std::vector< ArgListEntry > ArgListTy
unsigned MaxStoresPerMemcpy
Specify maximum number of store instructions per memcpy call.
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
virtual SDValue LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA, SelectionDAG &DAG) const
Lower TLS global address SDNode for target independent emulated TLS model.
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
bool isPositionIndependent() const
virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const
Examine constraint string and operand type and determine a weight value.
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
virtual void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
virtual unsigned getJumpTableEncoding() const
Return the entry encoding for a jump table in the current function.
virtual void LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const
This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but leg...
TLSModel::Model getTLSModel(const GlobalValue *GV) const
Returns the TLS model which should be used for the given global variable.
bool useEmulatedTLS() const
Returns true if this target uses emulated TLS.
virtual TargetLoweringObjectFile * getObjFileLowering() const
unsigned NoNaNsFPMath
NoNaNsFPMath - This flag is enabled when the -enable-no-nans-fp-math flag is specified on the command...
iterator begin() const
begin/end - Return all of the registers in this class.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
bool isVectorTy() const
True if this is an instance of VectorType.
bool isFloatTy() const
Return true if this is 'float', a 32-bit IEEE fp type.
static IntegerType * getIntNTy(LLVMContext &C, unsigned N)
bool isIntegerTy() const
True if this is an instance of IntegerType.
TypeSize getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
LLVM Value Representation.
Type * getType() const
All values are typed, get the type of this value.
constexpr ScalarTy getFixedValue() const
self_iterator getIterator()
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
@ Fast
Attempts to make calls as fast as possible (e.g.
@ C
The default llvm calling convention, compatible with C.
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
@ STACKRESTORE
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
@ STACKSAVE
STACKSAVE - STACKSAVE has one operand, an input chain.
@ BSWAP
Byte Swap and Counting operators.
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
@ ATOMIC_STORE
OUTCHAIN = ATOMIC_STORE(INCHAIN, val, ptr) This corresponds to "store atomic" instruction.
@ ADD
Simple integer binary arithmetic operators.
@ LOAD
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
@ FMA
FMA - Perform a * b + c with no intermediate rounding step.
@ FADD
Simple binary floating point operators.
@ ATOMIC_FENCE
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
@ SDIVREM
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
@ FP16_TO_FP
FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions and truncation for half-preci...
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
@ BUILD_PAIR
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
@ EH_RETURN
OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents 'eh_return' gcc dwarf builtin,...
@ SIGN_EXTEND
Conversion operators.
@ FSINCOS
FSINCOS - Compute both fsin and fcos as a single operation.
@ BR_CC
BR_CC - Conditional branch.
@ BR_JT
BR_JT - Jumptable branch.
@ FCANONICALIZE
Returns platform specific canonical encoding of a floating point number.
@ IS_FPCLASS
Performs a check of floating point class property, defined by IEEE-754.
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
@ ATOMIC_LOAD
Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) This corresponds to "load atomic" instruction.
@ VACOPY
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer,...
@ SHL
Shift and rotation operations.
@ FMINNUM_IEEE
FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimumNumber or maximumNumber on two values,...
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
@ FMINNUM
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
@ DYNAMIC_STACKALLOC
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
@ EH_DWARF_CFA
EH_DWARF_CFA - This node represents the pointer to the DWARF Canonical Frame Address (CFA),...
@ FRAMEADDR
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG.
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
@ AND
Bitwise operators - logical and, logical or, logical xor.
@ TRAP
TRAP - Trapping instruction.
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
@ VAARG
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
@ BRCOND
BRCOND - Conditional branch.
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
@ FCOPYSIGN
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
@ CALLSEQ_START
CALLSEQ_START/CALLSEQ_END - These operators mark the beginning and end of a call sequence,...
CondCode getSetCCInverse(CondCode Operation, EVT Type)
Return the operation corresponding to !(X op Y), where 'op' is a valid SetCC operation.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
@ Bitcast
Perform the operation on a different, but equivalently sized type.
Flag
These should be considered private to the implementation of the MCInstrDesc class.
@ MO_GOT_CALL
MO_GOT_CALL - Represents the offset into the global offset table at which the address of a call site ...
@ MO_TPREL_HI
MO_TPREL_HI/LO - Represents the hi and low part of the offset from.
@ MO_GOT
MO_GOT - Represents the offset into the global offset table at which the address the relocation entry...
@ MO_JALR
Helper operand used to generate R_MIPS_JALR.
@ MO_GOTTPREL
MO_GOTTPREL - Represents the offset from the thread pointer (Initial.
@ MO_GOT_HI16
MO_GOT_HI16/LO16, MO_CALL_HI16/LO16 - Relocations used for large GOTs.
@ MO_TLSLDM
MO_TLSLDM - Represents the offset into the global offset table at which.
@ MO_TLSGD
MO_TLSGD - Represents the offset into the global offset table at which.
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
@ Implicit
Not emitted register (e.g. carry, or temporary result).
@ Define
Register definition.
@ Kill
The last use of a register.
@ EarlyClobber
Register definition happens before uses.
Not(const Pred &P) -> Not< Pred >
Reg
All possible values of the reg field in the ModR/M byte.
initializer< Ty > init(const Ty &Val)
NodeAddr< FuncNode * > Func
This is an optimization pass for GlobalISel generic memory operations.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
constexpr bool isShiftedMask_64(uint64_t Value)
Return true if the argument contains a non-empty sequence of ones with the remainder zero (64 bit ver...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
constexpr T divideCeil(U Numerator, V Denominator)
Returns the integer ceil(Numerator / Denominator).
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
const MipsTargetLowering * createMips16TargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
Create MipsTargetLowering objects.
@ Or
Bitwise or logical OR of integers.
unsigned getKillRegState(bool B)
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
DWARFExpression::Operation Op
const MipsTargetLowering * createMipsSETargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
bool getAsUnsignedInteger(StringRef Str, unsigned Radix, unsigned long long &Result)
Helper functions for StringRef::getAsInteger.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
This struct is a compact representation of a valid (non-zero power of two) alignment.
uint64_t value() const
This is a hole in the type system and should not be abused.
EVT changeVectorElementTypeToInteger() const
Return a vector with the same number of elements as this vector, but with the element type converted ...
bool bitsLT(EVT VT) const
Return true if this has less bits than VT.
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
bool isPow2VectorType() const
Returns true if the given vector is a power of 2.
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
static EVT getFloatingPointVT(unsigned BitWidth)
Returns the EVT that represents a floating-point type with the given number of bits.
bool isVector() const
Return true if this is a vector value type.
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
bool isRound() const
Return true if the size is a power-of-two number of bytes.
EVT getVectorElementType() const
Given a vector type, return the type of each element.
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
bool isInteger() const
Return true if this is an integer or a vector integer type.
Align getNonZeroOrigAlign() const
SmallVector< ArgRegPair, 1 > ArgRegPairs
Vector of call argument and its forwarding register.
This class contains a discriminated union of information about pointers in memory operands,...
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Align valueOrOne() const
For convenience, returns a valid alignment or 1 if undefined.
These are IR-level optimization flags that may be propagated to SDNodes.
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
This structure contains all information that is necessary for lowering calls.
SmallVector< ISD::InputArg, 32 > Ins
SmallVector< ISD::OutputArg, 32 > Outs
SmallVector< SDValue, 32 > OutVals
bool isBeforeLegalizeOps() const
